MAX1103EUA+ [MAXIM]
8-Bit CODECs;
| 型号： | MAX1103EUA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 8-Bit CODECs |
| 文件： | 总17页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1873; Rev 1; 1/11
8-Bit CODECs
23/MAX104
General Description
Features
The MAX1102/MAX1103/MAX1104 CODECs provide
both an 8-bit analog-to-digital converter (ADC) and an
8-bit digital-to-analog converter (DAC) with a 4-wire
logic interface. The MAX1102/MAX1103 include an
onboard +2V/+4V reference, providing a well-regulat-
ed, low noise reference for both the ADC and DAC.
The MAX1104 offers ratiometric conversion, with the
o 8-Bit ADC
1LSB INL
Built-In Track-and-Hold
48dB of SINAD
o 8-Bit DAC
1LSB INL
55dB of SFDR
reference internally connected to V
.
DD
o Internal Conversion Clock
The MAX1102/MAX1103/MAX1104 are low-cost, low-
power CODECs for use with microcontrollers (µCs).
They allow for greater flexibility when selecting a µC.
Less expensive µCs without onboard converters can be
used while maintaining overall system performance.
o Single-Supply Operation
+2.7V to +3.6V (MAX1102)
+4.5V to +5.5V (MAX1103)
+2.7V to +5.5V (MAX1104)
o Low Power Consumption
The MAX1102 operates from a single +2.7V to +3.6V
supply, the MAX1103 operates from a +4.5V to +5.5V
supply, and the MAX1104 operates from a +2.7V to
+5.5V supply. The MAX1102/MAX1103 incorporate a
0.5mA at 25ksps
1µA Shutdown Mode
o 6MHz 4-Wire SPI™, QSPI™, and MICROWIRE™
V
DD
monitor in addition to AIN for power supply moni-
Compatible Interface
toring. All devices feature a low 18µA standby mode,
where both data converters are disabled while the ref-
erence remains active, and three shutdown modes:
ADC disabled, DAC disabled, and complete shutdown
(1µA). A quick 10µs wake-up time allows the
MAX1102/MAX1103/MAX1104 to cycle in and out of
shutdown even during short-duration idle times.
o Compact 8-Pin µMAX Package
o Internal Voltage Reference
+2V: MAX1102
+4V: MAX1103
o Power-Supply Monitor (MAX1102/MAX1103)
o Rail-to-rail DAC Output Buffer
The MAX1102/MAX1103/MAX1104 are available in a
®
space-saving 8-pin µMAX package.
Ordering Information
________________________Applications
TEMP
RANGE
PIN-
PACKAGE
PART
REFERENCE
Analog I/O for Microcontrollers
Analog System Signal Supervision
Voice Recording and Playback
MAX1102EUA+ -40°C to +85°C 8 µMAX
MAX1103EUA+ -40°C to +85°C 8 µMAX
MAX1104EUA+ -40°C to +85°C 8 µMAX
+Denotes a lead(Pb)-free/RoHS-compliant package.
+2V
+4V
V
DD
Functional Diagram
Pin Configuration
V
DD
V
DD/2
MAX1102
MAX1103
MAX1104
TOP VIEW
CS
SCLK
DIN
ADC
DAC
T/H
SERIAL
INTERFACE
AND
CONTROL
LOGIC
AIN
+
VOLTAGE
REFERENCE
V
1
2
3
4
8
7
6
5
DIN
DD
GND
AIN
DOUT
SCLK
CS
DAC
LATCH
MAX1102
MAX1103
MAX1104
AOUT
DOUT
OUT
µMAX
GND
µMAX is a registered trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
8-Bit CODECs
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering,10s) ..................................+300°C
Soldering Temperature (reflow) .......................................+260°C
AIN, OUT, DOUT to GND ...........................-0.3V to (V
DIN, SCLK, CS to GND ............................................-0.3V to +6V
+ 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
8-Pin µMAX (derate 4.1mW/°C above +70°C).................330mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +3.6V (MAX1102), V
= +4.5V to +5.5V (MAX1103), V
= +2.7V to +5.5V (MAX1104), f
= 6.0MHz (50% duty
DD
DD
DD
SCLK
cycle), R
= 10kΩ, C
= 100pF, T = T
to T
. Typical values are at T = +25°C, unless otherwise noted.)
MAX A
OUT
OUT
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DC ACCURACY (Note 1)
Bits
Resolution
8
Relative Accuracy
(Note 2)
INL
All codes
1/4
1/4
1
LSB
LSB
LSB
%
Differential Nonlinearity
Offset Error
DNL
Guaranteed monotonic
1
1
5
1
MAX1102/MAX1103
MAX1104
Gain Error
(Note 3)
LSB
✕
ADC DYNAMIC SPECIFICATIONS (f
= 10kHz SINE WAVE. V
= 0.9
V
)
AIN
AIN
REFp-p
Signal to Noise and Distortion
Ratio
SINAD
48
dB
23/MAX104
dB
dB
Spurious-Free Dynamic Range
Total Harmonic Distortion
Full-Power Bandwidth
SFDR
THD
59
58
MHz
2.5
ADC Wake-Up Time from
Standby
Reference enabled (MAX1102/MAX1103)
3
µs
µs
MAX1102/MAX11103
MAX1104
200
ADC Wake-Up Time from Full
Shutdown
3
ANALOG INPUT
V
Analog Input Voltage
Input Resistance
V
0
V
REF
AIN
MΩ
pF
R
10
20
IN
IN
Input Capacitance
VOLTAGE REFERENCE
C
MAX1102
2
4
Reference Voltage
V
V
REF
MAX1103
ppm/oC
Temperature Coefficient
CONVERSION RATE
Conversion Time
MAX1102/MAX1103
100
µs
µs
t
24
36
CONV
Track/Hold Acquisition Time
Internal Clock Frequency
t
3.5
ACQ
kHz
375
2
_______________________________________________________________________________________
8-Bit CODECs
23/MAX104
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +3.6V (MAX1102), V
= +4.5V to +5.5V (MAX1103), V
= +2.7V to +5.5V (MAX1104), f
= 6.0MHz (50% duty
DD
DD
DD
SCLK
cycle), R
= 10kΩ, C
= 100pF, T = T
to T
. Typical values are at T = +25°C unless otherwise noted.)
MAX A
OUT
OUT
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ksps
Throughput Rate
DAC DC ACCURACY
Resolution
ADC in continuous conversion mode
25
Bits
8
Relative Accuracy
(Note 2)
INL
1/4
1/4
1
LSB
LSB
mV
%
Differential Nonlinearity
Offset Error
DNL
Guaranteed monotonic
1
30
5
MAX1102/MAX1103
Gain Error
(Note 3)
MAX1104
30
mV
✕
DAC DYNAMIC SPECIFICATIONS (f
Spurious-Free Dynamic Range
Total Harmonic Distortion
= 1kHz SINE WAVE, V
= 0.9
V
)
OUT
OUT
REFp-p
dB
dB
SFDR
THD
55
53
1
MHz
kHz
Small-Signal Bandwidth
Full-Power Bandwidth
72
DAC Wake-Up Time from
Standby (Note 4)
Reference enabled (MAX1102/MAX1103)
10
µs
MAX1102/MAX1103
MAX1104
200
DAC Wake-Up Time from Full
Shutdown (Note 4)
µs
10
DAC OUTPUT
V
0.1
-
DD
Full-Scale Swing
MAX1104
0
V
µs
Settling Time (Note 5)
Slew Rate
Settle to within 1/2 LSB
11
Vµs
1.2
R open to 10kΩ
L
Load Regulation
0.05
LSB
0 < V
< V
- 0.1V
OUT
DD
LOGIC INPUTS AND OUTPUTS (DIN, SLCK, CS)
V
x
DD
0.7
Input High Voltage
Input Low Voltage
V
V
V
IH
V
x
DD
0.3
V
IL
µA
V
Input Current
V
= V
or V
DD
0.1
0.5
15
5
LOGIC
GND
Digital Input Hysteresis
Digital Input Capacitance
pF
V
x
DD
0.9
Output High Voltage
V
I = 1.0mA
SOURCE
V
OH
V
x
DD
0.1
Output Low Voltage
Three-State Leakage
V
I = 1.0mA
SINK
V
OL
µA
I
5.0
LEAK
_______________________________________________________________________________________
3
8-Bit CODECs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +3.6V (MAX1102), V
= +4.5V to +5.5V (MAX1103), V
= +2.7V to +5.5V (MAX1104), f
= 6.0MHz (50% duty
DD
DD
DD
SCLK
cycle), R
= 10kΩ, C
= 100pF, T = T
to T
. Typical values are at T = +25°C unless otherwise noted.)
MAX A
OUT
OUT
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY REQUIREMENTS
MAX1102
MAX1103
MAX1104
2.7
4.5
2.7
3.6
5.5
5.5
0.5
0.66
35
Supply Voltage
V
V
DD
ADC on (25ksps), DAC off
ADC off, DAC on (V = +5.5V)
0.25
0.4
18
Supply Current
I
mA
CC
DD
µA
µA
Standby Current
ADC off, DAC off, clock off, reference on
ADC off, DAC off, clock off
Full Shutdown Current
1
TIMING CHARACTERISTICS (Figures 4a and 4b)
(V
= +2.7V to +3.6V (MAX1102), V
= +4.5V to +5.5V (MAX1103), V
= +2.7V to +5.5V (MAX1104), f
= 6.0MHz (50% duty
DD
DD
DD
SCLK
cycle), R
= 10kΩ, C
= 100pF, T = T
to T
. Typical values are at T = +25°C unless otherwise noted.)
MAX A
OUT
OUT
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µs
Power Up to Reset Complete
CS Rise-to-DOUT = High-Z
CS Fall-to-DOUT Valid
CS Fall-to-SCLK Rise
t9
t10
t11
t3
40
ns
40
60
ns
R
R
= 3kΩ, C
= 50pF
= 50pF
DOUT
DOUT
DOUT
ns
15
25
10
15
23/MAX104
ns
SCLK Fall-to-CS Rise
t8
ns
DIN-to-SCLK Setup Time
DIN-to-SCLK Hold Time
SCLK Fall to DOUT Valid
SCLK Maximum Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
t4
ns
t5
ns
t6
= 3kΩ, C
78
6
DOUT
MHz
ns
f
SCLK
t
60
70
CH
ns
t
CL
Note 1: MAX1102/MAX1104 tested with V
= +3V. MAX1103 tested with V
= +5V.
DD
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset
error have been nulled.
Note 3: Gain error calculation is referenced to the ideal FS output. Gain error for the MAX1102/MAX1103 also includes reference ini-
tial accuracy error.
Note 4: Wake-up time is the time it takes for the DAC output to settle to within 1/2 LSB of the FS value after a power-up command.
Note 5: Output settling time is measured by taking the DAC from code 00hex to FFhex.
4
_______________________________________________________________________________________
8-Bit CODECs
23/MAX104
Typical Operating Characteristics
(V
= +3.0V (MAX1102), V
= +5V (MAX1103), f
= 6.0MHz (50% duty cycle), R
= 10kΩ, C
= 100pF, T = +25°C,
DD
DD
SCLK
OUT
OUT A
unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(ADC ENABLED, DAC ENABLED)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(ADC ENABLED, DAC DISABLED)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DAC ENABLED, ADC DISABLED)
500
300
250
200
150
100
50
350
300
CODE = AAhex
DAC CODE = FFhex
CODE = FFhex
450
400
250
200
150
350
300
CODE = 00hex
250
200
DAC CODE = 00hex
ADC CODE = AAhex
150
100
100
50
0
50
0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
DAC OFFSET ERROR
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT vs.
SUPPLY VOLTAGE
ADC OFFSET ERROR vs.
SUPPLY VOLTAGE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
20
15
10
5
CODE = 0Ahex
ADC and DAC OFF
REFERENCE ON
8
7
6
ADC, DAC, and
REFERENCE OFF
5
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
ADC GAIN ERROR
vs. SUPPLY VOLTAGE
ADC GAIN ERROR vs. TEMPERATURE
DAC GAIN ERROR vs. SUPPLY VOLTAGE
10
9
8
7
6
5
4
3
2
1
0
10
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
V
= 2.0V
V
= 2.0V
REF
V
= 2.0V
REF
REF
9
8
7
6
5
4
3
2
1
0
CODE = FFhex
CODE = 7Fhex
CODE = FFhex
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
8-Bit CODECs
Typical Operating Characteristics (continued)
(V
= +3.0V (MAX1102), V
= +5V (MAX1103), f
= 6.0MHz (50% duty cycle), R
= 10kΩ, C
= 100pF, T = +25°C,
OUT A
DD
DD
SCLK
OUT
unless otherwise noted.)
DAC OUTPUT HIGH VOLTAGE vs. OUTPUT
SOURCE CURRENT
DAC OUTPUT LOW VOLTAGE vs. OUTPUT
SINK CURRENT
DAC GAIN ERROR vs. TEMPERATURE
3.95
20
15
10
5
1600
1400
1200
1000
800
600
400
200
0
V
V
= +5.0V
= +2.0V
DD
REF
V
= +5.0V
DD
CODE = 00hex
3.90
3.85
3.80
3.75
3.70
3.65
3.60
3.55
CODE = FFhex
CODE = FFhex
CODE = F0hex
CODE = 0Ahex
V
V
= +5.0V
= +4.0V
DD
REF
0
-40
-15
10
35
60
85
0
2
4
6
8
10
0
2
4
6
8
10
TEMPERATURE (°C)
OUTPUT SOURCE CURRENT (mA)
OUTPUT SINK CURRENT (mA)
ADC DIFFERENTIAL NONLINEARITY
vs. CODE
DAC INTEGRAL NONLINEARITY
vs. CODE
ADC INTEGRAL NONLINEARITY vs. CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
23/MAX104
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
0
50
100
150
200
250 300
0
50
100
150
200
250 300
0
50
100
150
200
250 300
ADC OUTPUT CODE
DAC OUTPUT CODE
ADC OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. CODE
WORST-CASE 1LSB DIGITAL STEP CHANGE
WORST-CASE 1LSB DIGITAL STEP CHANGE
(POSITIVE)
(NEGATIVE)
MAX1102 toc17
MAX1102 toc18
1.00
0.75
0.50
0.25
0
3V
3V
SCLK
OUT
SCLK
OUT
0
0
-0.25
-0.50
-0.75
-1.00
20mV/div
20mV/div
0
50
100
150
200
250 300
1µs/div
1µs/div
DAC OUTPUT CODE
6
_______________________________________________________________________________________
8-Bit CODECs
23/MAX104
Typical Operating Characteristics (continued)
(V
= +3.0V (MAX1102), V
= +5V (MAX1103), f
= 6.0MHz (50% duty cycle), R
= 10kΩ, C
= 100pF, T = +25°C,
DD
DD
SCLK
OUT
OUT A
unless otherwise noted.)
CLOCK FEEDTHROUGH
POSITIVE SETTLING TIME
NEGATIVE SETTLING TIME
MAX1102 toc21
MAX1102 toc19
MAX1102 toc20
3V
0
3V
0
3V
0
SCLK
SCLK
OUT
SCLK
OUT
OUT
2mV/div
1V/div
1V/div
1µs/div
1µs/div
1µs/div
DAC FFT
ADC FFT
40
20
0
-20
V
= +4.5V
DD
V
F
= +4.5V
DD
= 24.576kHz
SAMPLE
F = 10.002kHz
L
0
-40
-20
-40
-60
-80
-100
-120
-60
-80
-100
-120
-140
0
0
1
2
3
4
5
6
7
8
9
10
2
4
6
8
10
12
14
FREQUENCY (kHz)
FREQUENCY (kHz)
_______________________________________________________________________________________
7
8-Bit CODECs
Pin Description
PIN
1
NAME
FUNCTION
V
Voltage Supply
DD
2
GND
AIN
Ground
3
ADC Analog Input
DAC Analog Voltage Output
4
OUT
CS
5
Chip Select Input. Device ignores all logic signals when CS is high.
6
SCLK
DOUT
DIN
Serial Clock Input. Data in is latched on the rising edge, data out transitions on the falling edge.
ADC Digital Output. Output is high impedance when CS is high.
7
8
DAC Digital Input. Input ignores all signals when CS is high.
shows the detailed functional diagram of the ADC
block.
Detailed Description
The MAX1102/MAX1103/MAX1104 are 8-bit CODECs in
a compact 8-pin package. These devices consist of an
8-bit ADC, an 8-bit DAC, track/hold (T/H), DAC output
buffer amplifier, internal voltage reference, input multi-
plexer (mux) and a 6MHz SPI, QSPI and MICROWIRE
compatible 4-wire serial interface. A single 8-bit word
configures the MAX1102/MAX1103/MAX1104, provid-
ing a simple interface to a microcontroller (µC).
ADC Operation
The input architecture of the ADC is illustrated in Figure
2, the equivalent input circuit, and is composed of the
T/H, input mux (MAX1102/MAX1103), input comparator,
switched capacitor DAC, and the auto-zero rail. The
switched capacitor DAC is independent of the R-2R
ladder DAC and does not provide the converted analog
output on OUT.
Analog-to-Digital Converter
The MAX1102/MAX1103/MAX1104 ADC section uses a
successive-approximation (SAR) conversion technique
and input T/H circuitry to convert an analog signal to an
8-bit digital output. No external hold capacitors are
required. The MAX1102/MAX1103 have an input multi-
plexer that directs either AIN or V /2 to the input of
DD
the T/H, allowing these devices to either convert the
analog input, or monitor the power supply. Figure 1
The T/H is in hold mode while a conversion is taking
place. Once the conversion is completed, the T/H
enters acquisition mode, and tracks the input signal
until the start of the next conversion. In single conver-
sion mode, conversion starts at the falling clock edge
corresponding to the last bit of the control word. In con-
tinuous conversion mode, the first conversion following
the control word starts on the falling clock edge of the
23/MAX104
CS
SCLK
DIN
MAX1102
MAX1103
INTERNAL
OSCILLATOR
CONTROL
LOGIC/2
SHIFT
REGISTER
SUCCESSIVE
APPROXIMATION
REGISTER
OUTPUT
DOUT
T/H
AIN
/2
ANALOG
INPUT
MUX
V
DD
CHARGE
REDISTRIBUTION
DAC
INTERNAL
OSCILLATOR
Figure 1. ADC Detailed Functional Diagram
8
_______________________________________________________________________________________
8-Bit CODECs
23/MAX104
LSB of the control word. Successive conversions are
initiated after the last bit of the previous conversion
result has been clocked out. Resultant data is only
available after conversion is complete.
Conversion Progress
The comparator’s negative input is connected to the
auto-zero rail. Since the device requires only a single
supply, the ZERO node at the input of the comparator
equals V /2. The capacitive DAC restores node ZERO
DD
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
to have no voltage difference at the comparator inputs
within the limits of an 8-bit resolution.
Input Voltage Range
Internal protection diodes that clamp the analog input
allowed between conversions. This time, t , is cal-
ACQ2
culated by the following equation:
to V
and GND allow AIN to swing from (V
DD
- 0.3V)
GND
DD
to (V
ꢀ
ꢀ
t
= (6.2
R
S
15pF) + t
ACQ
+ 0.3V) without damaging the device.
ACQ2
However, for accurate conversions, the input must not
exceed (V + 0.05V) or be less than (V - 0.05V).
where R = the source impedance of the input signal;
ACQ
Characteristics table.
S
GND
DD
t
is the T/H acquisition time from the Electrical
The valid input range for the analog input is from GND
to V . The output code is invalid (code zero) when a
REF
negative input voltage is applied, and full scale (FS)
when the input voltage exceeds the reference.
V
GND
REF
Input Bandwidth
The ADC’s input tracking circuitry has a 2.5MHz full-
power bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, low-pass filters such as the MAX7418–
MAX7426 are recommended.
MAX1102
MAX1103
MAX1104
HOLD
AIN
TRACK
15pF
5pF
ZERO
CAPACITIVE
DAC
TRACK
Digital-to-Analog Converter
The MAX1102/MAX1103/MAX1104 DAC section uses
an R-2R ladder network that converts the 8-bit digital
input into an equivalent analog output voltage propor-
tional to the applied reference voltage (Figure 3). The
DAC features a double-buffered input, and a buffered
analog output.
HOLD
V
/2
DD
Figure 2. Equivalent Input Circuit
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
REF
OUT
GND
LSB
MSB
DAC_ REGISTER
NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FFhex.
Figure 3. DAC Simplified Circuit Diagram
_______________________________________________________________________________________
9
8-Bit CODECs
Output Buffer
The MAX1102/MAX1103/MAX1104 analog output is
internally buffered by a precision unity-gain buffer that
output transition, the amplifier output typically settles to
1/2LSB in 11µs when loaded with 10kΩ in parallel with
100pF.
slews at 1.2V/µs (typ). The output swings from V
to
GND
- 0.1V to 0)
The buffer amplifier is stable with any combination of
resistive (≥ 10kΩ) or capacitive (≤ 100pF) loads.
V
DD
- 0.1V. With a 0 to V
- 0.1V (or V
DD
DD
AOUT
ADC CONVERSION CYCLE (ADC PREVIOUSLY ENABLED. DAC DISABLED)
CS
t3
t3
SCLK
DOUT
t10
t11
t4
tconv
D7
D6 D5 D4 D3 D2 D1 D0
MSB
CONVERSION RESULT
LSB
DIN
D7 D6 D5 D4 D3 D2 D1 D0
t5
AIN
MSB
CONTROL WORD
LSB
INPUT SAMPLING INSTANT
Figure 4a. Serial Interface Timing Diagram. ADC enabled and DAC disabled.
23/MAX104
VDD
AOUT
twake-up
tsettling
CS
t3
t3
SCLK
DOUT
t4
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
t5
DIN
MSB
Figure 4b. Serial Interface Timing Diagram. ADC disabled and DAC disabled.
10 ______________________________________________________________________________________
CONTROL WORD
LSB
MSB
DAC DATA
LSB
8-Bit CODECs
23/MAX104
The control word sets the mode in which the MAX1102/
MAX1103/MAX1104 operate. The enable bits, E0 to E2,
determine what sections of the device are operating by
either enabling or shutting down the two converters and
voltage reference (see Shutdown Modes). The enable
bits are independent of the address bits; for example,
the ADC need not be addressed for it to be shutdown
or powered up.
Serial Interface and Control Logic
The MAX1102/MAX1103/MAX1104 have 4-wire serial
interfaces (Figure 4). The CS, SCLK, and DIN inputs
are used to control and configure the device, while the
three-state DOUT provides access to the ADC conver-
sion result. DIN also serves as the data input to the
DAC.
The serial interface provides easy connection to µCs
with SPI, QSPI, and MICROWIRE serial interfaces at
clock rates up to 6MHz. For SPI and QSPI, set CPOL =
CPHA = 0 in the SPI control registers of the µC. Figure
4 gives detailed timing information.
C0 and C1 are the control bits. C0 sets the conversion
mode, either single or continuous (see Conversion
Modes). C1 determines whether the ADC monitors
V
DD
/2 or AIN (see Power Sense). When changing C1,
two control words must be written. The first control
word changes the state of the mux. Then wait 3.5µs for
the T/H to acquire the new input. Finally, the second
control word causes the conversion to take place. For
MAX1104 set C1 = 0.
Digital Inputs and Outputs
The logic levels of the MAX1102/MAX1103/MAX1104
digital inputs are set to accept voltage levels from both
+3V and +5V systems regardless of the supply volt-
ages.
A0 is the ADC address bit. A logic “1” on A0 addresses
the ADC. The control word configures the ADC. A logic
“0” on A0 deselects the ADC. In this state, the ADC is
still active, but does not perform any conversions.
Performing a Conversion
Configuring the MAX1102/MAX1103/MAX1104
The MAX1102/MAX1103/MAX1104 must be configured
before a conversion can occur. Following CS falling, on
each rising edge of SCLK, a bit from DIN is clocked
into the MAX1102/MAX1103/MAX1104’s internal shift
register. After CS falls, the first arriving logic “1” bit
defines the MSB of the control byte (START). Until the
START bit arrives, any number of logic “0” bits can be
clocked into DIN with no effect. Table 1 shows the con-
trol-byte format.
A1 is the DAC address bit. A logic “1” on A1 address-
es the DAC. The control word configures the DAC, and
the eight bits following the control word are read in as
DAC data. The converted analog output is available
after the eighth data bit is read into the device. A logic
“0” deselects the DAC. In this state the DAC is still
active, but ignores any digital inputs.
Both the ADC and DAC can be addresses from the
same control word, allowing both converters to operate
simultaneously.
Table 1. Control-Byte Format
BIT
NAME
DESCRIPTION
7 (MSB)
START
1 = designates a new control word. 0 = control word ignored, unless byte is DAC data.
1 = DAC addressed. Current byte configures DAC, the following byte is DAC data.
0 = DAC not addressed.
6
A1
1 = ADC addressed. Current byte configures ADC. After the 36µs conversion time, the next eight
clock cycles clock out the conversion result.
5
A0
0 = ADC not addressed.
1 = ADC input to V /2.
DD
0 = ADC input to AIN.
4
3
C1*
C0
1 = Continuous conversion. Control word not required unless the device is reconfigured.
0 = Single conversion. New control word required before next conversion.
2
1
0
E2
E1
E0
1 = Reference enabled. 0 = Reference disabled. Don’t care for MAX1104.
1 = ADC enabled. 0 = ADC disabled.
1 = DAC enabled. 0 = DAC disabled.
* Leave C1 = 0 for MAX1104.
______________________________________________________________________________________ 11
8-Bit CODECs
Configuring the ADC
In continuous conversion mode (C0 = 1), the device
maintains its configuration from a single control word,
and continuously updates the ADC conversion result,
or accepts new DAC input data.
When configuring the ADC immediately following
power-up, the first control word enables the ADC and
sets the T/H to track mode. Then wait 200µs for the
internal reference to stablize (3µs typical from standby
mode). Finally, the second control word sets the ADC
into either single or continuous mode and causes con-
version to take place.
When operating the ADC and DAC simultaneously,
both converters must be in the same conversion mode.
ADC Single Conversion Mode
Set C0 = 0 to select single conversion mode. The
falling edge of SCLK after the eighth bit of each control
word causes the ADC to switch from track to hold
mode and begin conversion. To avoid corruption of the
conversion result, SCLK must be disabled for 36µs
(Figure 6). After completing the conversion, the ADC
automatically returns to track mode, and the next eight
clock cycles shift out the result on DOUT.
Conversion Modes
The MAX1102/MAX1103/MAX1104 have two conver-
sion modes, single and continuous.
In single conversion mode (C0 = 0), a control word
must be written before an ADC conversion result can
be read, or DAC input data is accepted. Once a con-
version has occurred, the device will ignore any input
until a new control word is written. Figures 5 and 6
show the DAC and ADC single conversion mode timing
diagrams.
A minimum of 3.5µs in track mode is required for com-
plete acquisition.
CS
SCLK
DAC
S ADDR
DAC ON
DAC
S ADDR
DAC ON
DAC
S ADDR
DAC ON
DAC
S ADDR
DAC OFF
DAC
S ADDR
DAC ON
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DIN
23/MAX104
OUT
NOTE: "S" DENOTES THE BEGINNING OF A CONTROL WORD
Figure 5. DAC Single Conversion Mode Timing Diagram
CS
SCLK
ADC
S ADDR
ADC ON
ADC
S ADDR
ADC ON
ADC
S ADDR
ADC OFF
ADC
S ADDR
ADC ON
ADC
S ADDR
ADC ON
ADC
ON
ADC
ON
DIN
S
S
t
t
CONV
1
CONV
2
AIN
3
4
ACQUISITION MODE
ACQUISITION MODE
ACQUISITION
MODE
DOUT
MSB LSB
MSB LSB
MSB LSB MSB LSB
CONVERSION
RESULT FOR 1
CONVERSION
RESULT FOR 2
CONVERSION CONVERSION
RESULT FOR 3 RESULT FOR 4
Figure 6. ADC Single Conversion Mode Timing Diagram
12 ______________________________________________________________________________________
8-Bit CODECs
23/MAX104
CS
SCLK
DAC
S ADDR
DAC OFF
DAC
S ADDR
DAC ON
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DIN
OUT
Figure 7. DAC Continuous Conversion Mode Timing Diagram
CS
SCLK
ADC
ADC
ON
ADC
S ADDR
ADC ON
ADC
S ADDR
ADC ON
ADC
ON
DIN
S
S ADDR
ADC ON
S
t
CONV
2
1
4
3
AIN
5
7
6
T/MIN ACQUISITION
MODE
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
DOUT
CONVERSION CONVERSION
RESULT FOR 1 RESULT FOR 2
CONVERSION
RESULT FOR 3
CONVERSION
RESULT FOR 4
CONVERSION
RESULT FOR 5
CONVERSION
RESULT FOR 6
Figure 8. ADC Continuous Conversion Mode Timing Diagram
DAC Continuous Conversion Mode
Once the DAC is configured in continuous conversion
mode, the analog output, OUT, is updated at the rising
edge of every eighth clock pulse (Figure 7). To exit
DAC continuous conversion mode, toggle CS. The
device requires a new control word before any further
conversions take place.
OUTPUT CODE
FULL-SCALE
TRANSITION
11111111
11111110
11111101
ADC Continuous Conversion Mode
Set C0 = 1 to select continuous conversion mode. The
falling edge of SCLK after the eighth bit of the control
word causes the ADC to switch from track to hold
mode and begin conversion. To avoid corruption of the
conversion result, SCLK must be disabled for 36µs
(Figure 8). After completing the conversion, the ADC
automatically returns to track mode, and the next eight
clock cycles shift out the result on DOUT. The falling
edge of SCLK during the eighth bit of the result will
again cause the ADC to switch from track to hold mode
and begin the next conversion.
00000011
00000010
00000001
00000000
0
0.5 1.5 2.5
FS
(IN-)
INPUT VOLTAGE (LSB)
FS - 1.5LSB
Figure 9. ADC Input/Output Transfer Function
______________________________________________________________________________________ 13
8-Bit CODECs
A minimum of 3.5µs in track mode is required for com-
plete acquisition.
Reference
The full-scale range of both the ADC and DAC is set by
the internal voltage reference. The MAX1102 provides a
+2.0V reference, the MAX1103 has a +4.0V reference,
In continuous ADC-only conversion mode, a new con-
trol word (START = 1) reconfigures the device.
and the MAX1104 uses V
as the reference voltage.
DD
Interrupted Communication Results
If CS transitions from low to high during the reception of
a control word, the MAX1102/MAX1103/MAX1104
enters its power-on reset state (full shutdown mode). If
CS is toggled while receiving DAC data, the input is
ignored and any received bits are discarded. In both
cases, once CS returns low, the device requires a new
control word before further conversions can occur. If
CS goes high while data is read from the device, DOUT
enters a high-impedance state, and the serial clock is
ignored. When CS returns low, the remaining bits of the
conversion result can be clocked out.
ADC Transfer Function
Figure 9 depicts the ADC input/output transfer function.
Code transitions occur at the center of every LSB step.
Output coding is binary; with a 2.0V reference 1LSB =
(V
/256) = 7.8125mV. Full scale is achieved at V
REF
AIN
= V
- 1.5LSB. Negative input voltages are invalid
REF
and give a zero output code. Voltages greater than full
scale give an all ones output code.
Shutdown Modes
The MAX1102/MAX1103/MAX1104 feature four soft-
ware-selectable shutdown modes, helping to conserve
power by disabling any unused portion of the device.
Bits 0 through 2 of the control word select the device
shutdown mode (Table 1). Table 2 details the four
power modes with the corresponding supply current
and operating sections.
Applications Information
Power-On Reset
When power is first applied, the device enters full shut-
down mode and the DAC registers are reset to 0. To
wake up the device, the proper control word must be
written and 200µs allowed for the internal reference to
stablize. DAC data may be written to the device imme-
diately following the control word, but OUT will not finish
settling until the wake-up time has passed.
The ADC and DAC are individually controlled and can
be shutdown independently of each other. Bit 0 (E0)
controls the DAC, a logic “1” enables the DAC, a logic
“0” disables the DAC. Bit 1 (E1) controls the ADC, a
logic “1” enables the ADC, a logic “0” disables the
ADC. Either the ADC or DAC or both can be shutdown,
conserving power when one or both converters are not
in use. A fast wake-up time (3µs ADC, 10µs DAC)
allows the converters to be cycled in and out of shut-
down even during short duration idle times.
23/MAX104
Power Sense
The MAX1102/MAX1103 provide a multiplexer which
sets the T/H to either AIN or one-half of V . With C1 =
DD
1, the ADC converts the V /2 voltage, providing
DD
power sensing capability to the system. When switch-
ing the input multiplexer, two control words must be
written before any conversion takes place. The first
control word changes the multiplexer state, and the
second starts the conversion.
Data can be written to the DAC while it is in shutdown.
A control word with A1 = 1 and E0 = 0 disables the
DAC while allowing data to be written to the DAC. The
eight bits following this control word are shifted into the
DAC register. Conversion takes place once the DAC is
enabled.
Table 2. Operation Modes
SUPPLY
CURRENT
BIT
OPERATING SECTIONS
E2
0
E1
0
E0
0
REF
Off
On
On
On
On
ADC
Off
DAC
Off
1µA
1
0
0
18µA
Off
Off
1
1
0
250µA
400µA
520µA
On
Off
1
0
1
Off
On
1
1
1
On
On
14 ______________________________________________________________________________________
8-Bit CODECs
23/MAX104
Power Supply Bypassing and Layout
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another or run
digital lines underneath the device.
SYSTEM POWER SUPPLIES
GND
+3V/+5V
Figure 10 shows the recommended system-ground
connections. A single-point analog ground (star-ground
point) should be established at the device ground.
Connect all analog grounds to the star ground. No digi-
tal-system ground should be connected to this point.
The ground return to the power supply for the star
ground should be connected to this point. The ground
return to the power supply for the star ground should
be low impedance and as short as possible for noise-
free operation. High-frequency noise in the VDD power
supply may affect device performance. Bypass the
supply to the star ground with 0.1µF and 1µF capaci-
tors close to the device. Minimize capacitor lead
lengths for best supply-noise rejection. If the power
supply is very noisy, connect a 10Ω resistor in series
with VDD to form a lowpass filter.
1µF
10Ω
0.1µF
GND
V
DD
DGND
V
DD
DIGITAL
CIRCUITRY
MAX1102
MAX1103
MAX1104
Figure 10. Power-Supply Connections
Two control words are necessary to enable the ADC.
The first control word brings the ADC out of shutdown,
and sets the T/H in acquisition mode. The second con-
trol word initiates the conversion.
Bit 2 (E2) controls the reference. A logic “1” enables
the reference, a logic “0” disables the reference, further
reducing power consumption.
______________________________________________________________________________________ 15
8-Bit CODECs
Package Information
Chip Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
LAND
PACKAGE
TYPE
8 µMAX
PACKAGE
CODE
OUTLINE NO.
21-0036
PATTERN NO.
90-0092
U8+1
23/MAX104
16 ______________________________________________________________________________________
8-Bit CODECs
23/MAX104
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
12/00
1/11
Initial release
Changed spec in Timing Characteristics section
—
4
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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