MAX11045 [MAXIM]
4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs; 4- / 6 / 8通道， 16位，同时采样ADC
| 型号： | MAX11045 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs |
| 文件： | 总20页 (文件大小：2143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5036; Rev 1; 3/10
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
General Description
Features
The MAX11044/MAX11045/MAX11046† 16-bit ADCs
offer 4, 6, or 8 independent input channels. Featuring
independent track and hold (T/H) and SAR circuitry,
these parts provide simultaneous sampling at 250ksps
for each channel.
o 4-/6-/8-Channel 16-Bit ADC
o Single Analog and Digital Supply
o High-Impedance Inputs Up to 1GΩ
o On-Chip T/H Circuit for Each Channel
o Fast 3µs Conversion Time
The MAX11044/MAX11045/MAX11046 accept a 5ꢀ
input. All inputs are overrange protected with internal
20mA input clamps providing overrange protection
with a simple external resistor. Other features include a
4MHz T/H input bandwidth, internal clock, and internal
or external reference. A 20MHz, 16-bit, bidirectional,
parallel interface provides the conversion results and
accepts digital configuration inputs.
o High Throughput: 250ksps for All 8 Channels
o 16-Bit, High-Speed, Parallel Interface
o Internal Clocked Conversions
o 10ns Aperture Delay
The MAX11044/MAX11045/MAX11046 operate with a
4.75ꢀ to 5.25ꢀ analog supply and a separate flexible 2.7ꢀ
to 5.25ꢀ digital supply for interfacing with the host without a
level shifter. The MAX11044/MAX11045/MAX11046
are available in a 56-pin TQFN and 64-pin TQFP pack-
ages and operate over the extended -40°C to +85°C
temperature range.
o 100ps Channel-to-Channel T/H Matching
o Low Drift, Accurate 4.096V Internal Reference
Providing an Input Range of 5V
o External Reference Range of 3.0V to 4.25V,
Allowing Full-Scale Input Ranges of 4.0V to 5.2V
o 56-Pin (8mm x 8mm) TQFN and 64-Pin
Applications
Automatic Test Equipment
Power-Factor Monitoring and Correction
Power-Grid Protection
(10mm x 10mm) TQFP Packages
o Evaluation Kit Available
Multiphase Motor Control
ꢀibration and Waveform Analysis
Patent pending.
†
Ordering Information
Functional Diagram
PART
PIN-PACKAGE
56 TQFN-EP**
64 TQFP-EP**
56 TQFN-EP**
64 TQFP-EP**
56 TQFN-EP**
64 TQFP-EP**
CHANNELS
AVDD
DVDD
DB15
MAX11044ETN+
MAX11044ECB+*
MAX11045ETN+
MAX11045ECB+*
MAX11046ETN+
MAX11046ECB+*
4
4
6
6
8
8
CH0
16-BIT ADC
S/H
S/H
CLAMP
DB4
DB3
DB0
CH7
16-BIT ADC
CLAMP
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
**EP = Exposed pad.
CONFIGURATION
REGISTERS
WR
AGNDs
AGND
RD
MAX11044
MAX11045
MAX11046
CS
INTERFACE
AND
CONTROL
CONVST
SHDN
EOC
INT REF
EXT REF
RDC
BANDGAP
REFERENCE
REF
BUF
DGND
REFIO
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................-0.3V to +6V
DVDD to AGND and DGND .....................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
AGNDS to AGND...................................................-0.3V to +0.3V
CH0–CH7 to AGND...............................................-7.5V to +7.5V
REFIO, RDC to AGND ..................................-0.3V to the lower of
(AVDD + 0.3V) and +6V
Maximum Current into Any Pin Except AVDD, DVDD, AGND,
DGND ........................................................................... 50mA
Continuous Power Dissipation
56-Pin TQFN (derate 36mW/°C above +70°C) ..........2222mW
64-Pin TQFP (derate 43.5mW/°C above +70°C)........3478mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
EOC, WR, RD, CS, CONVST to AGND.........-0.3V to the lower of
(DVDD + 0.3V) and +6V
DB0–DB15 to AGND ....................................-0.3V to the lower of
(DVDD + 0.3V) and +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +4.75V to +5.25V, DVDD = +2.70V to +5.25V, V
= V
= V = 0V, V
DGND
= internal reference, C
= 4 x
AGNDS
AGND
REFIO
RDC
33μF, C
= 0.1μF, C
= 4 x 0.1μF || 10μF, C
= 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise
REFIO
AVDD
DVDD
noted, f
= 250ksps. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
SAMPLE
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (Note 1)
Resolution
N
16
Bits
(Note 2)
(Note 3)
(Note 4)
(Note 5)
(Note 3)
>-2
0.8
0.7
<+2
Integral Nonlinearity
INL
LSB
> -1
> -1
0.5
< +1.2
< +1.5
Differential Nonlinearity
DNL
LSB
0.7
0.45
No Missing Codes
16
Bits
%FSR
%FSR
μV/°C
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
ppm/°C
Offset Error
0.002
2.4
0.01
0.01
5/MAX1046
Channel Offset Matching
Offset Temperature Coefficient
Gain Error
0.03
0.02
0.02
0.02
0.02
0.03
Positive Full-Scale Error
Negative Full-Scale Error
Positive Full-Scale Error Matching
Negative Full-Scale Error Matching
Channel Gain-Error Matching
Gain Temperature Coefficient
DYNAMIC PERFORMANCE (Note 6)
Signal-to-Noise Ratio
Between all channels
0.8
SNR
SINAD
SFDR
THD
f
IN
f
IN
f
IN
f
IN
= 10kHz, full-scale input
= 10kHz, full-scale input
= 10kHz, full-scale input
= 10kHz, full-scale input
91
90.5
95
92.3
92
dB
dB
dB
dB
Signal-to-Noise and Distortion Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion
106
-105
-95
f
= 60Hz, full scale and ground on
IN
Channel-to-Channel Crosstalk
-126
-100
dB
adjacent channel (Note 7)
2
_______________________________________________________________________________________
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.70V to +5.25V, V
= V
= V = 0V, V
DGND
= internal reference, C
= 4 x
AGNDS
AGND
REFIO
RDC
33μF, C
= 0.1μF, C
= 4 x 0.1μF || 10μF, C
= 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise
REFIO
AVDD
DVDD
noted, f
= 250ksps. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
SAMPLE
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (CH0–CH7)
1.22 x
Input-Voltage Range
(Note 8)
V
V
REFIO
Input Leakage Current
Input Capacitance
-1
+1
μA
pF
15
Input-Clamp Protection Current
TRACK AND HOLD
Throughput Rate
Each input simultaneously
-20
+20
mA
Per channel, 8 channels in 4μs
1
1
250
ksps
μs
Acquisition Time
t
1000
ACQ
-3dB point
4
> 0.2
10
Full-Power Bandwidth
MHz
-0.1dB point
Aperture Delay
ns
ps
Aperture-Delay Matching
Aperture Jitter
100
50
ps
RMS
INTERNAL REFERENCE
REFIO Voltage
V
V
4.073
4.096
5
4.119
V
REF
REF
REFIO Temperature Coefficient
EXTERNAL REFERENCE
Input Current
ppm/°C
-10
+10
4.25
μA
V
REF Voltage-Input Range
REF Input Capacitance
3.00
15
10
pF
DIGITAL INPUTS (DB0–DB15, RD, WR, CS, CONVST)
Input Voltage High
V
V
V
= 2.7V to 5.25V
= 2.7V to 5.25V
2
V
V
IH
DVDD
DVDD
Input Voltage Low
V
0.8
10
IL
Input Capacitance
C
pF
μA
IN
Input Current
I
V
= 0V or V
DVDD
IN
IN
DIGITAL OUTPUTS (DB0–DB15, EOC)
V
-
DVDD
0.4
Output Voltage High
V
I
I
= 1.2mA
V
OH
SOURCE
Output Voltage Low
V
= 1mA
SINK
0.25
15
0.4
10
V
OL
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
DB0–DB15, V ≥ V or V ≥ V
μA
pF
RD
IH
CS
IH
DB0–DB15, V ≥ V or V ≥ V
RD
IH
CS
IH
Analog Supply Voltage
Digital Supply Voltage
AVDD
DVDD
4.75
2.70
5.25
5.25
48
V
V
MAX11046, AVDD = 5V
MAX11045, AVDD = 5V
MAX11044, AVDD = 5V
Analog Supply Current
I
42
mA
AVDD
36
_______________________________________________________________________________________
3
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.70V to +5.25V, V
= V
= V = 0V, V
DGND
= internal reference, C
= 4 x
AGNDS
AGND
REFIO
RDC
33μF, C
= 0.1μF, C
= 4 x 0.1μF || 10μF, C
= 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise
REFIO
AVDD
DVDD
noted, f
= 250ksps. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
SAMPLE
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
7.3
6.3
5.5
10
UNITS
mA
MAX11046, DVDD = 3.3V (Note 9)
MAX11045, DVDD = 3.3V (Note 9)
MAX11044, DVDD = 3.3V (Note 9)
Digital Supply Current
I
mA
DVDD
mA
I
DVDD
μA
Shutdown Current
I
12
AVDD
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS (Note 9)
CONVST Rise to EOC
Acquisition Time
PSRR
V
= 4.9V to 5.1V (Note 10)
3
LSB
AVDD
t
Conversion time (Note 11)
Sample quiet time (Note 11)
3
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CON
t
1
1000
ACQ
CS Rise to CONVST Rise
CONVST Rise to EOC Rise
EOC Fall to CONVST Fall
CONVST Low Time
t
500
Q
t
47
140
0
1
2
3
4
5
6
7
8
9
t
CONVST mode B0 = 0 only (Note 12)
CONVST mode B0 = 1 only
0
20
0
t
t
t
t
t
t
t
t
CS Fall to WR Fall
WR Low Time
20
0
CS Rise to WR Rise
Input Data Setup Time
Input Data Hold Time
CS Fall to RD Fall
10
1
0
RD Low Time
30
0
RD Rise to CS Rise
t
10
t
11
t
12
t
13
5/MAX1046
RD High Time
10
RD Fall to Data Valid
RD Rise to Data Hold Time
35
(Note 12)
5
Note 1: See the Definitions section at the end of the data sheet.
Note 2: INL is guaranteed at AVDD = 5.25V, for +25°C < T < +85°C. See the Input Range and Protection section and Typical
A
Operating Characteristics.
Note 3:
T = -40°C.
A
Note 4: DNL at code > 8192 or < 57343 (offset binary encoded), or code > -24576 or < +24575 (two’s complement), is guaranteed
at AVDD = 5.25V, for +25°C < T < +85°C. See the Input Range and Protection section and Typical Operating
A
Characteristics.
Note 5: DNL at code ≤ 8192 or ≥ 57343 (offset binary encoded), or code ≤ -24576 or ≥ +24575 (2’s complements), is guaranteed
at AVDD = 5.25V, for +25°C < T < +85°C. See the Input Range and Protection section and Typical Operating
A
Characteristics.
Note 6: AC dynamics are guaranteed at AVDD = 5.25V, for +25°C < T < +85°C. See the Input Range and Protection section and
A
Typical Operating Characteristics.
Note 7: Tested with alternating channels modulated at full scale and ground.
Note 8: See the Input Range and Protection section for more details.
Note 9:
C
LOAD
= 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. f
= 250ksps.
CONV
All data is read out.
Note 10: Defined as the change in positive full scale caused by a 2% variation in the nominal supply voltage.
Note 11: It is recommended that RD, WR, and CS are kept high for the quiet time (t ) and conversion time (t
).
CON
Q
Note 12: Guaranteed by design.
4
_______________________________________________________________________________________
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
Typical Operating Characteristics
(AVDD = 5V, DVDD = 3.3V, T = +25°C, f
A
= 250ksps, internal reference, unless otherwise noted.)
SAMPLE
INL AND DNL
vs. ANALOG SUPPLY VOLTAGE
INTEGRAL NONLINEARITY vs. CODE
DIFFERENTIAL NONLINEARITY vs. CODE
1.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
MAX INL
0.8
0.6
0.4
0.2
0
MAX DNL
MIN DNL
-0.2
-0.2
-0.4
-0.6
-0.8
-1.0
V
V
f
= 5.25V
= 3.3V
AVDD
DVDD
-0.5
-1.0
-1.5
V
V
f
= 5.25V
= 3.3V
AVDD
DVDD
-0.4
-0.6
-0.8
-1.0
V
= 3.3V
DVDD
= 250ksps
= +25°C
= 250ksps
SAMPLE
f
= 250ksps
T
= +25
°
C
SAMPLE
SAMPLE
A
MIN INL
T
A
T
A
= +25°C
= 4.096V
V
= 4.096V
RDC
V
= 4.096V
V
RDC
RDC
4.75
4.85
4.95
5.05
(V)
5.15
5.25
V
AVDD
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
INL AND DNL
vs. TEMPERATURE
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.5
1.0
0.5
0
45
40
35
30
25
T
= +25°C
A
MAX11046 CONVERTING
MAX11046 STATIC
MAX INL
f
= 250ksps
SAMPLE
MAX DNL
MAX11045 CONVERTING
MAX11045 STATIC
V
V
f
= 5.25V
= 3.3V
AVDD
DVDD
MIN DNL
= 250ksps
SAMPLE
V
RDC
= 4.096V
MAX11044 CONVERTING
-0.5
-1.0
-1.5
MIN INL
MAX11044 STATIC
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
V
AVDD
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
45
40
35
30
25
12
10
8
V
= 5.0V
= 250ksps
AVDD
MAX11046 CONVERTING
MAX11046 STATIC
T = +25°C
A
f
SAMPLE
f
= 250ksps
SAMPLE
MAX11046 CONVERTING
MAX11045 CONVERTING
MAX11045 STATIC
6
MAX11045 CONVERTING
4
MAX11044 CONVERTING
MAX11044/MAX11045/
MAX11046 STATIC
2
MAX11044 CONVERTING
MAX11044 STATIC
0
-40
-15
10
35
60
85
2.75
3.25
3.75
4.25
(V)
4.75
5.25
TEMPERATURE (°C)
V
DVDD
_______________________________________________________________________________________
5
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(AVDD = 5V, DVDD = 3.3V, T = +25°C, f
A
= 250ksps, internal reference, unless otherwise noted.)
SAMPLE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
7.2
ANALOG AND DIGITAL SHUTDOWN
CURRENT vs. SUPPLY VOLTAGE
ANALOG AND DIGITAL SHUTDOWN
CURRENT vs. TEMPERATURE
5
4
3
2
1
0
5
4
3
2
1
0
V
V
= 5.0V
= 3.3V
T
A
= +25°C
AVDD
DVDD
MAX11046 CONVERTING
6.0
4.8
I
AVDD
I
AVDD
MAX11045 CONVERTING
3.6
MAX11044
CONVERTING
2.4
V
= 3.3V
= 250ksps
= 15pF
DVDD
I
MAX11044/MAX11045/
MAX11046 STATIC
I
DVDD
DVDD
f
SAMPLE
1.2
0
C
DBxx
-40
-15
10
35
60
85
2.75
3.25
3.75
4.25
4.75
5.25
-40
-15
10
35
60
85
TEMPERATURE (°C)
AVDD AND DVDD (V)
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGES
vs. SUPPLY VOLTAGE
4.09520
4.09515
4.09510
4.09505
4.09500
4.09495
4.09490
4.112
4.108
4.104
4.100
4.096
4.092
4.088
4.084
4.080
T
= +25
°
C
V
= 5.0V
AVDD
A
UPPER TYPICAL LIMIT
LOWER TYPICAL LIMIT
V
RDC
5/MAX1046
V
REFIO
4.75
4.85
4.95
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
V
AVDD
TEMPERATURE (°C)
OFFSET ERROR AND OFFSET ERROR
MATCHING vs. TEMPERATURE
OFFSET ERROR AND OFFSET ERROR
MATCHING vs. SUPPLY VOLTAGE
0.010
0.006
0.010
0.006
V
V
= 5.0V
= 4.096V
T
= +25°C
AVDD
REFIO
A
OFFSET ERROR MATCHING
OFFSET ERROR MATCHING
0.002
0.002
-0.002
-0.006
-0.010
-0.002
-0.006
-0.010
OFFSET ERROR
OFFSET ERROR
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
V
AVDD
6
_______________________________________________________________________________________
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
Typical Operating Characteristics (continued)
(AVDD = 5V, DVDD = 3.3V, T = +25°C, f
A
= 250ksps, internal reference, unless otherwise noted.)
SAMPLE
GAIN ERROR AND GAIN ERROR
MATCHING vs. TEMPERATURE
GAIN ERROR AND GAIN ERROR
MATCHING vs. SUPPLY VOLTAGE
0.005
FFT PLOT
0.010
0
-20
T
A
= +25
°
C
V
= 5.0V
AVDD
f
f
= 10kHz
IN
= 250ksps
= +25
SAMPLE
GAIN ERROR
OFFSET ERROR
0.006
T
°C
A
0.003
0
V
AVDD
= 5.0V
-40
0.002
-0.002
-0.006
-0.010
-60
GAIN ERROR MATCHING
-80
OFFSET ERROR
MATCHING
-100
-120
-140
-0.003
-0.005
-40
-15
10
35
60
85
0
25
50
75
100
125
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
FREQUENCY (kHz)
V
AVDD
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. TEMPERATURE
TWO-TONE IMD PLOT
95
0
-20
-40
-60
-80
f
f
f
= 9838Hz
= 10235Hz
f
f
T
V
V
= 10kHz
IN1
IN2
IN
SAMPLE
= 250ksps
= +25
= 250ksps
°C
SAMPLE
94
93
92
91
90
A
T
= +25°C
= 4.096V
A
RDC
V
V
V
= 5.0V
= -0.025dB FROM FS
AVDD
IN
SNR
= 4.096V
RDC
= -0.01dBFS
IN
-100
SINAD
-120
-140
-40
-15
10
35
60
85
7.2 8.0 8.8 9.6 10.4 11.2 12.0 12.8
FREQUENCY (kHz)
TEMPERATURE (°C)
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
SNR AND SINAD
vs. ANALOG SUPPLY VOLTAGE
-102.5
-103.0
-103.5
-104.0
-104.5
-105.0
93.0
92.5
92.0
91.5
91.0
90.5
f
f
T
V
V
= 10kHz
IN
SAMPLE
= 250ksps
= +25
SNR
°C
A
= 4.096V
RDC
= -0.025dB FROM FS
IN
f
f
T
= 10kHz
IN
= 250ksps
= +25
SAMPLE
°C
A
SINAD
4.85
V
V
= 4.096V
= -0.025dB FROM FS
RDC
IN
-40
-15
10
35
60
85
4.75
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
V
AVDD
_______________________________________________________________________________________
7
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(AVDD = 5V, DVDD = 3.3V, T = +25°C, f
A
= 250ksps, internal reference, unless otherwise noted.)
SAMPLE
TOTAL HARMONIC DISTORTION
vs. ANALOG SUPPLY VOLTAGE
-99
SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. FREQUENCY
THD vs. INPUT FREQUENCY
-80
-85
96
94
92
90
88
86
84
82
f
T
V
V
= 250ksps
SAMPLE
= +25°C
A
-100
-101
-102
= 4.096V
RDC
= -0.025dB FROM FS
-90
IN
-95
-100
-105
-110
-115
f
f
T
V
V
= 10kHz
IN
SAMPLE
-103
-104
-105
f
= 250ksps
SAMPLE
= 250ksps
= +25
T
= +25°C
°
C
A
A
V
RDC
= 4.096V
= 4.096V
RDC
V
= -0.025dB FROM FS
IN
= -0.025dB FROM FS
IN
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
AVDD
OUTPUT NOISE HISTOGRAM WITH
INPUT CONNECTED TO GND
CROSSTALK vs. FREQUENCY
-90
200,000
150,000
100,000
50,000
0
f
f
T
V
V
= 60kHz
V
CHX
= 0V
IN
= 250ksps
V
f
= 5.0V
SAMPLE
AVDD
= +25°C
= 250ksps
-100
-110
-120
-130
-140
A
SAMPLE
= 4.096V
T
= +25°C
RDC
A
= -0.025dB FROM FS
INACTIVE CHANNEL AT GND
IN
5/MAX1046
0.1
1
10
100
FREQUENCY (kHz)
OUTPUT CODE (DECIMAL)
CONVERSION TIME
vs. ANALOG SUPPLY VOLTAGE
CONVERSION TIME vs. TEMPERATURE
3.00
2.99
2.98
2.97
2.96
2.95
2.94
2.93
2.92
3.00
2.99
2.98
2.97
2.96
2.95
2.94
2.93
2.92
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
V
AVDD
8
_______________________________________________________________________________________
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
Pin Description
PIN
NAME
FUNCTION
TQFP
TQFN
1
56
DB14
DB13
DB12
DB11
DB10
DB9
16-Bit Parallel Data Bus Digital Out Bit 14
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
2
1
3
2
4
3
5
4
6
5
7
8, 22, 59
9, 21, 60
10
6
DB8
7, 21, 50
DGND
DVDD
DB7
8, 20, 51
Digital Supply. Bypass to DGND with a 0.1μF capacitor at each DVDD input.
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
16-Bit Parallel Data Bus Digital I/O Bit 3
16-Bit Parallel Data Bus Digital I/O Bit 2
16-Bit Parallel Data Bus Digital I/O Bit 1
16-Bit Parallel Data Bus Digital I/O Bit 0
9
11
10
11
12
13
14
15
16
DB6
12
DB5
13
DB4
14
DB3
15
DB2
16
DB1
17
DB0
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed.
EOC goes high when a conversion is initiated.
18
19
20
17
18
19
EOC
Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on
the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST
mode = 0.
CONVST
Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current
state. Contents of the configuration register are not lost when in the shutdown state.
SHDN
AGNDS
AVDD
23, 28, 32,
38, 43, 49,
53, 58
23, 27, 33,
38, 44, 48
Signal Ground. Connect all AGND and AGNDS inputs together.
Analog Supply Input. Bypass AVDD to AGND with a 0.1μF capacitor at each AVDD input.
Analog Ground. Connect all AGND inputs together.
24, 29, 35,
46, 52, 57
24, 30,
41, 47
25, 30, 36,
45, 51, 56
25, 31,
40, 46
AGND
Reference Buffer Sense Feedback. Connect to RDC plane. Internally connected on the
56-pin TQFN parts
26, 55
—
RDC_SENSE
RDC
27, 33, 40,
48, 54
22, 28,
35, 43, 49
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at
least a 80μF total capacitance. See the Layout, Grounding, and Bypassing section.
31
34
37
39
26
29
32
34
36
CH0
CH1
Channel 0 Analog Input
Channel 1 Analog Input
CH2
Channel 2 Analog Input
CH3
Channel 3 Analog Input
External Reference Input/Internal Reference Output. Place a 0.1μF capacitor from REFIO
41
REFIO
_______________________________________________________________________________________
9
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
NAME
FUNCTION
TQFP
TQFN
42
44
47
50
37
39
42
45
CH4
CH5
CH6
CH7
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are
loaded on the rising edge of WR.
61
62
63
64
—
52
53
54
55
—
WR
CS
Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC.
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD
advances the channel output on the data bus.
RD
DB15
EP
16-Bit Parallel Data Bus Digital Out Bit 15
Exposed Pad. Internally connected to AGND. Connect to a large ground plane to
maximize thermal performance. Not intended as an electrical connection point.
sient events and measure periodic signals with band-
Detailed Description
widths exceeding the ADC’s sampling rate by using
undersampling techniques. Use anti-alias filtering to
avoid high-frequency signals being aliased into the fre-
quency band of interest.
The MAX11044/MAX11045/MAX11046 are fast, low-
power ADCs that combine 4, 6, or 8 independent ADC
channels in a single IC. Each channel includes simulta-
neously sampling independent T/H circuitry that pre-
serves relative phase information between inputs
making the MAX11044/MAX11045/MAX11046 ideal for
motor control and power monitoring. The MAX11044/
MAX11045/MAX11046 are available with 5V input
ranges that feature 20mA overrange, fault-tolerant
inputs. The MAX11044/MAX11045/MAX11046 operate
with a single 4.75V to 5.25V supply. A separate 2.7V to
5.25V supply for digital circuitry makes the devices
compatible with low-voltage processors.
Input Range and Protection
The full-scale analog input voltage is a product of the ref-
erence voltage. For the MAX11044/MAX11045/
MAX11046, the full-scale input is bipolar in the range of:
5
(V
REFIO
x
)
5/MAX1046
4.096
When in external reference mode, drive V
with a
REFIO
The MAX11044/MAX11045/MAX11046 perform conver-
sions for all channels in parallel by activating indepen-
dent ADCs. Results are available through a high-speed,
20MHz, parallel data bus after a conversion time of 3μs
following the end of a sample. The data bus is bidirec-
tional and allows for easy programming of the configu-
ration register. The MAX11044/MAX11045/MAX11046
feature a reference buffer, which is driven by an internal
3.0V to 4.25V source, resulting in an input range of
3.662V to 5.188V, respectively.
All analog inputs are fault-protected to up to 20mA.
The MAX11044/MAX11045/MAX11046 include an input
clamping circuit that activates when the input voltage at
the analog input is above (V
+ 300mV) or below
AVDD
–(V
+ 300mV). The clamp circuit remains high
AVDD
impedance while the input signal is within the range of
bandgap reference circuit (V
= 4.096V). Drive
REFIO
V
and draws little or almost no current. However,
AVDD
REFIO with an external reference or bypass with 0.1μF
capacitor to ground when using the internal reference.
when the input signal exceeds
V
, the clamps
AVDD
begin to turn on and shunt current to/from the AVDD
supply. Consequently, to obtain the highest accuracy,
Analog Inputs
ensure that the input voltage does not exceed
V
AVDD
.
Track and Hold (T/H)
To preserve phase information across all channels,
each input includes a dedicated T/H circuitry. The input
tracking circuitry provides a 4MHz small-signal band-
width, enabling the device to digitize high-speed tran-
Note that the input clamp circuit also has a small
amount of hysteresis and once triggered remains
engaged, shunting current to/from AVDD until the input
returns to within the convertible range by several hun-
dredths of a volt. This effect can cause some errors at
10 ______________________________________________________________________________________
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
the extremes of the transfer function if V is driven
IN
V
- 7V
FAULT _MAX
beyond
V
.
AVDD
R
S
=
20mA
To make use of the input clamps (see Figure 1), con-
nect a resistor (R ) between the analog input and the
S
where V
is the maximum voltage that the
FAULT_MAX
voltage source to limit the voltage at the analog input so
that the fault current into the MAX11044/MAX11045/
MAX11046 does not exceed 20mA. Note that the volt-
age at the analog input pin limits to approximately 7V
during a fault condition so the following equation can
source produces during a fault condition.
Figures 2 and 3 illustrate the clamp circuit voltage-cur-
rent characteristics for a source impedance R
=
+
S
1280Ω. While the input voltage is within the (V
AVDD
300mV) range, no current flows in the input clamps.
Once the input voltage goes beyond this voltage range,
the clamps turn on and limit the voltage at the input pin.
be used to calculate the value of R :
S
INPUT
PIN
SIGNAL
VOLTAGE
AVDD
DVDD
DB15
R
S
16-BIT ADC
CH0
S/H
S/H
CLAMP
CLAMP
SOURCE
DB4
DB3
DB0
CH7
AGNDS
AGND
16-BIT ADC
CONFIGURATION
REGISTERS
WR
RD
MAX11044
MAX11045
MAX11046
CS
INTERFACE
AND
CONTROL
CONVST
SHDN
EOC
INT REF
EXT REF
RDC
BANDGAP
REFERENCE
REF
BUF
DGND
REFIO
Figure 1. Required Setup for Clamp Circuit
30
20
30
R
V
= 1280Ω
AVDD
R
V
= 1280Ω
AVDD
S
S
= 5V
= 5V
20
10
AT CH_ INPUT
AT CH_ INPUT
10
AT SOURCE
AT SOURCE
0
0
-10
-20
-30
-10
-20
-30
-8 -6 -4 -2
0
2
4
6
8
-50
-30
-10
10
30
50
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
Figure 2. Input Clamp Characteristics
Figure 3. Input Clamp Characteristics (Zoom In)
______________________________________________________________________________________ 11
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
Applications Information
Table 1. Configuration Register
DB3
DB2
DB1
DB0
Digital Interface
The bidirectional, parallel, digital interface, DB0–DB3,
sets the 4-bit configuration register. This interface
configures the following control signals: chip select
(CS), read (RD), write (WR), end of conversion (EOC),
and convert start (CONVST). Figures 6 and 7 and the
Timing Characteristics in the Electrical Characteristics
table show the operation of the interface. DB0–DB3,
together with the output-only DB4–DB15, also output
the 16-bit conversion result. All bits are high imped-
ance when RD = 1 or CS = 1.
Int/Ext
Reference
Output
Data Format
CONVST
Mode
Reserved
Starting a Conversion
CONVST initiates conversions. The MAX11044/
MAX11045/MAX11046 provide two acquisition modes
set through the configuration register. Allow a quiet time
(t ) of 500ns prior to the start of conversion to avoid
Q
any noise interference during readout or write opera-
tions from corrupting a sample.
DB3 (Int/Ext Reference)
DB3 selects the internal or external reference. The POR
default = 0.
In default mode (DB0 = 0), drive CONVST low to place
the MAX11044/MAX11045/MAX11046 into acquisition
mode. All the input switches are closed and the internal
T/H circuits track the respective input voltage. Keep the
0 = internal reference, REFIO internally driven through a
10kΩ resistor, bypass with 0.1μF capacitor to AGND.
1 = external reference, drive REFIO with a high-quality
reference.
CONVST signal low for at least 1μs (t
) to enable
ACQ
proper settling of the sampled voltages. On the rising
edge of CONVST, the switches are opened and the
MAX11044/MAX11045/MAX11046 begin the conversion
on all the samples in parallel. EOC remains high until
the conversion is completed.
DB2 (Output Data Format)
DB2 selects the output data format. The POR default = 0.
In the second mode (DB0 = 1), the MAX11044/
MAX11045/MAX11046 enter acquisition mode as soon
as the previous conversion is completed. CONVST rising
edge initiates the next sample and conversion sequence.
CONVST needs to be low for at least 20ns to be valid.
0 = offset binary.
1 = two’s complement.
DB1 (Reserved)
Set to 0 for normal operation.
Provide adequate time for acquisition and the requisite
quiet time in both modes to achieve accurate sampling
and maximum performance of the MAX11044/
MAX11045/MAX11046.
0 = normal operation.
1 = reserved; do not use.
5/MAX1046
DB0 (CONVST Mode)
DB0 selects the acquisition mode. The POR default = 0.
Reading Conversion Results
The CS and RD are active-low, digital inputs that con-
trol the readout through the 16-bit, parallel, 20MHz data
bus (D0–D15). After EOC transitions low, read the con-
version data by driving CS and RD low. Each low peri-
od of RD presents the next channel’s result. When CS
and RD are high, the data bus is high impedance. CS
may be driven high between individual channel read-
outs or left low during the entire 8-channel readout.
0 = CONVST controls the acquisition and conversion.
Drive CONVST low to start acquisition. The rising edge
of CONVST begins the conversion.
1 = acquisition mode starts as soon as the previous
conversion is complete. The rising edge of CONVST
begins the conversion.
Programming the Configuration Register
To program the configuration register, bring the CS and
WR low and apply the required configuration data on
DB3–DB0 of the bus and then raise WR once to save
changes.
Reference
Internal Reference
The MAX11044/MAX11045/MAX11046 feature a preci-
sion, low-drift, internal bandgap reference. Bypass REFIO
with a 0.1μF capacitor to AGND to reduce noise. The
REFIO output voltage may be used as a reference for
other circuits. The output impedance of REFIO is 10kΩ.
Drive only high impedance circuits or buffer externally
when using REFIO to drive external circuitry.
12 ______________________________________________________________________________________
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
External Reference
vides the best performance. Connect DGND, AGND, and
AGNDS pins on the MAX11044/MAX11045/MAX11046 to
this ground plane. Keep the ground return to the power
supply for this ground low impedance and as short as
possible for noise-free operation.
Set the configuration register to disable the internal ref-
erence and drive REFIO with a high-quality external ref-
erence. To avoid signal degradation, ensure that the
integrated reference noise applied to REFIO is less
than 10μV in the bandwidth of up to 50kHz.
To achieve the highest performance, connect all the
RDC pins (22, 28, 36, 43, and 49) to a local RDC plane
on the PCB. A total of at least 80μF of capacitance
should be placed on this RDC plane. If two capacitors
are used, place each as close as possible to pins 22
and 49. If four capacitors are used, place each as
close as possible to pins 22, 28, 43, and 49. For exam-
ple, two 47μF, 10V X5R capacitors in 1210 case size
can be placed as close as possible to pins 22 and 49
will provide excellent performance. Alternatively, four
22μF, 10V X5R capacitors in 1210 case size placed as
close as possible to pins 22, 28, 43, and 49 will also
provide good performance. Ensure that each capacitor
is connected directly into the GND plane with an inde-
pendent via.
Reference Buffer
The MAX11044/MAX11045/MAX11046 have a built-in
reference buffer to provide a low-impedance reference
source to the SAR converters. This buffer is used in
both internal and external reference mode. The refer-
ence buffer output feeds five RDC pins. The RDC pins
should be all connected together on the PCB. The ref-
erence buffer is externally compensated and requires
at least 10μF on the RDC node. For best performance,
provide a total of at least 80μF on the RDC outputs.
Transfer Functions
Figures 8 and 9 show the transfer functions for all the
formats and devices. Code transitions occur halfway
between successive-integer LSB values.
If Y5U or Z5U ceramics are used, be aware of the high-
voltage coefficient these capacitors exhibit and select
higher voltage rating capacitors to ensure that at least
80μF of capacitance is on the RDC plane when the
plane is driven to 4.096V by the built-in reference
buffer. For example, a 22μF X5R with a 10V rating is
approximately 20μF at 4.096V, whereas, the same
capacitor in Y5U ceramic is just 13μF. However, a Y5U
22μF capacitor with a 25V rating cap is approximately
20μF at 4.096V.
Layout, Grounding, and Bypassing
For best performance use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines paral-
lel to one another (especially clock lines), and avoid run-
ning digital lines underneath the ADC package. A single
solid GND plane configuration with digital signals routed
from one direction and analog signals from the other pro-
CS
(USER SUPPLIED)
CS
t
5
(USER SUPPLIED)
t
10
t
t
t
8
9
11
t
3
t
4
RD
(USER SUPPLIED)
WR
(USER SUPPLIED)
t
13
t
12
t
7
S
S
n + 1
n
t
6
D0–D15
CONFIGURATION
REGISTER
D0–D15
(USER SUPPLIED)
Figure 5. Readout Timing Requirements
Figure 4. Programming Configuration-Register Timing
Requirements
______________________________________________________________________________________ 13
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
SAMPLE
t
t
CON
ACQ
CONVST
t
1
EOC
t
O
t
Q
CS
RD
D0–D15
S0
S1
S6
S7
Figure 6. Conversion Timing Diagram (DB0 = 0)
SAMPLE
t
t
5/MAX1046
CON
ACQ
CONVST
EOC
t
2
t
O
t
Q
CS
RD
D0–D15
S0
S1
S6
S7
Figure 7. Conversion Timing Diagram (DB0 = 1)
14 ______________________________________________________________________________________
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
Bypass AVDD and DVDD to the ground plane with
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. For these devices, the DNL of
each digital output code is measured and the worst-case
value is reported in the Electrical Characteristics table. A
DNL error specification of greater than -1 LSB guaran-
tees no missing codes and a monotonic transfer func-
tion. For example, -0.9 LSB guarantees no missing code
while -1.1 LSB results in missing code.
0.1μF ceramic chip capacitors on each pin as close as
possible to the device to minimize parasitic inductance.
Add at least one bulk 10μF decoupling capacitor to
AVDD and DVDD per PCB. Interconnect all of the
AVDD inputs and DVDD inputs using two solid power
planes. For best performance, bring the AVDD power
plane in on the analog interface side of the MAX11044/
MAX11045/MAX11046 and the DVDD power plane from
the digital interface side of the device.
Offset Error
For the MAX11044/MAX11045/MAX11046, the offset
error is defined at code transition 0x8000 to 0x8001 in
offset binary encoding and 0x0000 to 0x0001 for two’s
complement encoding. The offset code transitions
should occur with an analog input voltage of exactly 0.5
For acquisition periods near minimum (1μs) use a 1nF
C0G ceramic chip capacitor between each of the chan-
nel inputs to the ground plane as close as possible to
the MAX11044/MAX11045/MAX11046. This capacitor
reduces the inductance seen by the sampling circuitry
and reduces the voltage transient seen by the input
source circuit.
x (10/4.096) x V
/65,536 above GND. The offset error
REF
is defined as the deviation between the actual analog
input voltage required to produce the offset code transi-
tion and the ideal analog input of 0.5 x (10/4.096) x
Typical Application Circuits
Power-Grid Protection
Figure 10 shows a typical power-grid protection application.
V /65,536 above GND, expressed in LSBs.
REF
Gain Error
DSP Motor Control
Gain error is defined as the difference between the
change in analog input voltage required to produce a top
code transition minus a bottom code transition, subtract-
ed from the ideal change in analog input voltage on
Figure 11 shows a typical DSP motor control application.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For these devices, this
straight line is a line drawn between the end points of
the transfer function, once offset and gain errors have
been nullified.
(10/4.096) x V
x (65,534/65,536). For the
REF
MAX11044/MAX11045/MAX11046, top code transition is
0x7FFE to 0x7FFF in two’s complement mode and
0xFFFE to 0xFFFF in offset binary mode. The bottom code
transition is 0x8000 and 0x8001 in two’s complement
5 x V
REF
FULL-SCALE
TRANSITION
7FFF
7FFE
+FS =
5 x V
REF
4.096
FULL-SCALE
TRANSITION
4.096
FFFF
FFFE
+FS =
ZS =
ZS = 0
-FS =
-5 x V
-5 x V
REF
REF
4.096
4.096
+FS - (-FS)
65,536
0001
0000
FFFF
FFFE
+FS - (-FS)
65,536
LSB =
LSB =
8001
8000
7FFF
7FFE
V
V
x 32,768
IN
CODE =
REFIO
5
4.096
V
V
x 32,768
IN
CODE =
+ 32,768
8001
8000
REFIO
5
0001
0000
4.096
-FS
0
+FS
-FS
0
+FS
-FS + 0.5 x LSB
+FS - 1.5 x LSB
-FS + 0.5 x LSB
+FS - 1.5 x LSB
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 8. Two’s Complement Transfer Function
Figure 9. Offset-Binary Transfer Function
______________________________________________________________________________________ 15
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
VOLTAGE
TRANSFORMER
PHASE 1
OPT
ADC
ADC
OPT
CURRENT
TRANSFORMER
VN
IN
ADC
ADC
NEUTRAL
LOAD 1
MAX11046
LOAD 2
LOAD 3
I3
ADC
ADC
V3
I2
5/MAX1046
PHASE 2
V2
ADC
ADC
PHASE 3
Figure 10. Power-Grid Protection
16 ______________________________________________________________________________________
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
DSP-BASED DIGITAL
PROCESSING ENGINE
MAX11046
16-BIT
ADC
IGBT CURRENT DRIVERS
16-BIT
ADC
16-BIT
ADC
16-BIT
ADC
16-BIT
ADC
I
PHASE1
I
PHASE3
I
PHASE2
3-PHASE ELECTRIC MOTOR
POSITION
ENCODER
Figure 11. DSP Motor Control
______________________________________________________________________________________ 17
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
mode and 0x0000 and 0x0001 in offset binary mode. For
Spurious-Free Dynamic Range (SFDR)
the MAX11044/MAX11045/MAX11046, the analog input
voltage to produce these code transitions is measured
and the gain error is computed by subtracting (10/4.096)
SFDR is the ratio of the RMS amplitude of the funda-
mental (maximum signal component) to the RMS value
of the next-largest frequency component.
x V
x (65,534/65,536) from this measurement.
REF
Aperture Delay
Aperture delay (t ) is the time delay from the sampling
AD
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, SNR is the ratio of the full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization noise error only and
results directly from the ADC’s resolution (N bits):
clock edge to the instant when an actual sample is
taken.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
aperture delay.
SNR = (6.02 x N + 1.76)dB
Channel-to-Channel Isolation
Channel-to-channel isolation indicates how well each
analog input is isolated from the other channels.
Channel-to-channel isolation is measured by applying
DC to channels 1 to 7, while a -0.4dBFS sine wave at
60Hz is applied to channel 0. A 10ksps FFT is taken for
channel 0 and channel 1. Channel-to-channel isolation
is expressed in dB as the power ratio of the two 60Hz
magnitudes.
where N = 16 bits. In reality, there are other noise
sources besides quantization noise: thermal noise, ref-
erence noise, clock jitter, etc. SNR is computed by tak-
ing the ratio of the RMS signal to the RMS noise, which
includes all spectral components not including the fun-
damental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to the RMS equivalent of all the other
ADC output signals:
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in a manner that ensures that the signal’s slew
rate does not limit the ADC’s performance. The input
frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased 3dB.
⎡
⎢
⎣
⎤
⎥
⎦
Signal
(Noise +Distortion)
RMS
SINAD(dB) = 10 ×log
RMS
Effective Number of Bits (ENOB)
The ENOB indicates the global accuracy of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC,
calculate the ENOB as follows:
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as full-
power input bandwidth frequency.
5/MAX1046
SINAD −1.76
Positive Full-Scale Error
The error in the input voltage that causes the last code
transition of FFFE to FFFF (hex) (in default offset binary
mode) or 7FFE to 7FFF (hex) (in two’s complement mode)
from the ideal input voltage of 32,766.5 x (5/4.096) x
ENOB =
6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS of the first five harmonics of
the input signal to the fundamental itself. This is:
expressed as:
(V
/65,536) after correction for offset error.
REFIO
Negative Full-Scale Error
⎡
⎢
⎢
⎤
⎥
⎥
2
2
2
2
V2 + V3 + V4 + V5
The error in the input voltage that causes the first code
transition of 0000 to 0001 (hex) (in default offset binary
mode) or 8000 to 8001 (hex) (in two’s complement mode)
from the ideal input voltage of -32,767.5 x (5/4.096) x
THD = 20 ×log
V
1
⎢
⎣
⎥
⎦
where V is the fundamental amplitude and V through
V are the 2nd- through 5th-order harmonics.
1
2
(V
/65,536) after correction for offset error.
REFIO
5
Chip Information
PROCESS: BiCMOS
18 ______________________________________________________________________________________
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
5/MAX1046
Pin Configurations
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TOP VIEW
RDC
AGNDS
CH0
32
31
30
AGNDS
49
42 41 40 39 38 37 36 35 34 33 32 31 30 29
CH7 50
AGND 51
28
27
26
25
24
23
22
21
20
43
RDC
AGND
AGNDS 44
CH7 45
AGND 46
AVDD 47
AGNDS 48
RDC 49
DGND 50
DVDD 51
WR 52
AGNDS
CH0
29 AVDD
AVDD 52
AGNDS
RDC
28
27
26
25
24
23
22
21
20
19
18
AGNDS 53
RDC 54
AGND
AVDD
AGNDS
RDC
RDC_SENSE
AGND
RDC_SENSE 55
AGND 56
MAX11044
MAX11045
MAX11046
MAX11044
MAX11045
MAX11046
AVDD
AVDD 57
DGND
DVDD
AGNDS
DGND
DVDD
WR
AGNDS
DGND
58
59
60
61
62
63
19 SHDN
18 CONVST
17 EOC
DVDD
CS 53
SHDN
RD 54
CONVST
EOC
CS
*EP
DB15 55
DB14 56
16 DB0
+
*EP
RD
+
15 DB1
DB15 64
17 DB0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
TQFN
8mm x 8mm
TQFP
10mm x 10mm
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
56 TQFN-EP
PACKAGE CODE
T5688+2
DOCUMENT NO.
21-0135
64 TQFP-EP
C64E+6
21-0084
______________________________________________________________________________________ 19
4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
10/09
3/10
Initial release
Added TQFP package to data sheet
—
1, 2, 8, 9, 19
5/MAX1046
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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