MAX11068GUU+ [MAXIM]
12-Channel, High-Voltage Sensor, Smart Data-Acquisition Interface;
| 型号： | MAX11068GUU+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Channel, High-Voltage Sensor, Smart Data-Acquisition Interface |
| 文件： | 总82页 (文件大小：1955K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
General Description
Features
S 12-Cell Battery Voltage Measurement with
The MAX11068 is a programmable, highly integrated,
high-voltage, 12-channel, battery-monitoring smart data-
acquisition interface. It is optimized for use with batter-
ies used in automotive systems, hybrid electric battery
packs, electric cars, and any system that stacks long
series strings of secondary metal batteries. This highly
integrated battery sensor incorporates a simple state
machine and a high-speed I2C bus for SMBusK-laddered
serial communication.
Temperature Monitoring
Up to 12 Lithium-Ion (Li+), NiMH, or Super-Cap
Cells
Two Auxiliary Analog Inputs for Temperature
Measurement
S High-Accuracy I/Os
Excellent ±±02ꢀ% Voltage-Measurement
Accuracy
≤ ꢀmV Offset Voltage
The MAX11068 analog front-end combines a 12-channel
voltage measurement data-acquisition system with a high-
voltage switch bank input. All measurements are done
differentially across each cell. The full-scale measurement
range is from 0 to 5.0V, with full stated accuracy guaran-
teed from 0.5V to 4.7V. The input mux/switch bank allows
for differential measurement of each cell in a series stack.
A high-speed, 12-bit successive approximation (SAR) A/D
converter is used to digitize the cell voltages. All 12 cells
can be measured in less than 107Fs. The MAX11068 uses
a two-scan approach for collecting cell measurements
and correcting them for errors. The first phase of the scan
is the acquisition phase where the voltages of all 12 cells
are acquired. The second phase is the error-cancellation
phase where the ADC input is chopped to remove errors.
This two-phase approach yields excellent accuracy over
temperature and in the face of extreme noise in the sys-
tem. The MAX11068 incorporates an internal oscillator that
generates a 6.0MHz system clock with Q3.0% accuracy.
S Integrated 12-Channel Data-Acquisition System
12-Channel High-Voltage Mux to ADC
Differential Cell-Voltage Measurement
12-Bit Precision, High-Speed SAR ADC
12 Cell Voltages Measured Within 1±7µs
S Battery-Fault Detection
Overvoltage and Undervoltage Digital Threshold
Detection
Cell Sense Line Open-Circuit Detection
High/Low Temperature Digital Threshold
Detection
S 12 Integrated Cell-Equalization Switches
Support Up to 2±±mA
S Integrated 6V to 7±V Input Linear Regulator
S Integrated 2ꢀppm/NC, 20ꢀV Precision Reference
S Integrated Level-Shifted, I2C-Compliant SMBus
Ladder Interface
Supports Multiple Devices, Up to 31 SMBus-
Ladder-Connected ICs
Communications Protocol with Autoaddressing
Fault-Tolerant Hardware Handshake and Data
CRC Checking
The MAX11068 consumes less than 2.0mA from the power
supply while in data-acquisition modes. This current is
reduced to 75FA in standby mode and less than 1FA in
shutdown mode. The device is packaged in a 38-pin,
9.7mm x 4.4mm x 1.0mm TSSOP package that is lead free
and RoHS compliant and is designed to operate over the
AEC-Q100 Grade 2, -40NC to +105NC temperature range.
S Three General-Purpose Digital I/O Lines
S Ultra-Low Power Dissipation
Standby Mode Quiescent Current Drain 7ꢀµA
Shutdown Mode Leakage Current 1µA
Applications
High-Voltage, Multicell Series-Stacked-Battery
Systems
S Operating Temperature Range from -4±NC to
+1±ꢀNC (AEC-Q1±± Grade 2)
S 38-Pin, Lead-Free/RoHS-Compliant TSSOP
Electric and Hybrid Electric Vehicle (HEV)
Battery Packs
Package (907mm x 404mm)
Ordering Information
Electric Bikes
PART
TEMP RANGE PIN-PACKAGE
-40NC to +105NC 38 TSSOP
-40NC to +105NC 38 TSSOP
High-Power Battery Backup Systems
SuperCap Backup Systems
Power Tools
MAX11068GUU+
MAX11068GUU/V+
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V Denotes an automotive qualified part.
SMBus is a trademark of Intel Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-5192; Rev 0; 6/10
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
ABSOLUTE MAXIMUM RATINGS
HV, VDD , GND , DCIN to AGND ......................-0.3V to +80V
GPIO0, GPIO1, GPIO2...........................-0.3V to (VDD + 0.3V)
L
ESD Rating (HBM, Note 1)..................................................Q2kV
U
U
HV to C12................................................................-0.3V to +6V
C1–C12 to AGND......................................-0.3V to (V + 0.3V)
C0–C12, AUXIN1, AUXIN2, REF, VAA, VDD , GND ,
HV
U U
C(N+1) to C(N).....................................................-0.3V to +9.0V
C0 to AGND .........................................................-0.3V to +4.0V
SHDN to AGND.....................................................-0.3V to +60V
VAA to AGND.......................................................-0.3V to +4.0V
VDD , GND , DCIN, SHDN, CP+, CP-, HV, SCL , SDA ,
L L U U
ALRM , SCL , SDA , ALRM , GPIO0, GPIO1, GPIO2
U
L
L
L
Maximum Continuous Current into Any Pin .......................20mA
ESD Diode Maximum Average
VDD to GND .....................................................-0.3V to +4.0V
Power Dissipation for Hot Plug (Note 2) ... ..................14.4/√τ W
Continuous Power: Multilayer Board..........................1269.8mW
Continuous Power: Single-Layer Board
(derating 15.9mW/NC above +70NC).......................1095.9mW
Operating Temperature Range....................... .-40NC to +105NC
Storage Temperature Range............................ -55NC to +150NC
Junction Temperature (continuous) ................................+150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
L
L
VDD to GND ....................................................-0.3V to +6.0V
U
U
GND to GND .....................................................-0.3V to +80V
U
L
AGND to GND ....................................................-0.3V to +0.3V
L
AUXIN1, AUXIN2, THRM to AGND ......................-0.3V to +6.0V
REF to AGND ........................................... -0.3V to (VAA + 0.3V)
SCL , SDA , ALRM to GND ...............-0.3V to (VDD + 0.3V)
L
L
L
L
L
SCL , SDA , ALRM to GND .............-0.3V to (VDD + 0.3V)
U
U
U
U
U
CP+ to AGND......................... (GND - 1.0V) to (VDD + 1.0V)
U
U
CP- to AGND.........................................-0.3V to (GND + 0.3V)
U
Note 1: Human Body Model to Specification MIL-STD-883 Method 3015.7.
Note 2: Maximum average power dissipation for time period τ. Peak current must never exceed 2A. τ is one time constant (in µs) of
hot-plug current waveform through a given diode. For example, if τ is 330µs, the maximum average diode power dissipation
is 0.793W. Actual average power dissipation must be calculated from current waveform for the application circuit.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T = T
A
to T
, unless otherwise noted. V
= V
= 18V to +60V, typical values are at T = +25NC, unless otherwise
DCIN A
MIN
MAX
GNDU
specified from -40NC to +105NC per the application circuit in Figure 4.)
PARAMETER SYMBOL CONDITIONS
C±–C12 INPUTS
MIN
TYP
MAX
UNITS
Differential Cell Input-Voltage
Range
Any 2 inputs
CN+1 to CN for C12–C0 (Note 2)
VCELL
0.5
0.7
0.7
4.7
7.0
V
XIN
Input C1 referred to AGND
Inputs C2 through C[TOP] referred to
AGND
Cell Input Common-Mode Voltage
Range (Note 5)
VC
V
XIN
C[TOP] referred to AGND
C0 referred to AGND
GND
U
-0.05
-1.0
+0.05
+1.0
ADC off; C(N) to C(N+1) = 5V
ADC ON; C(N) to C(N+1) = 3V
LSB size is +1.22mV
Input-Leakage Current
ADC Resolution
I
FA
CXIN
Q10.0
ADC
12
Bits
BITS
Highest enabled input
11.34
7.66
Fs/
Channel
Channel- Conversion Time
t
S
Enabled inputs except highest
T
= +25NC (Note 4); V
= 3.0V
= 3.0V
-5
+5
A
CELL
-10NC < T < +50NC; V
(Note 3)
A
CELL
-10
+10
Channel Accuracy
mV
-40NC < T < +85NC; V
(Note 3)
= 3.0V
A
CELL
-15
-20
+15
+20
-40NC < T < +105NC; V
= 3.0V
A
CELL
2
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
ELECTRICAL CHARACTERISTICS (continued)
(T = T
A
to T
, unless otherwise noted. V
MAX
= V
= 18V to +60V, typical values are at T = +25NC, unless otherwise
DCIN A
MIN
GNDU
specified from -40NC to +105NC per the application circuit in Figure 4.)
PARAMETER
Differential Nonlinearity
Channel Offset Error
Channel Gain Error
SYMBOL
CONDITIONS
No missing codes at 12 bits
Cells 1 through 12
MIN
TYP
MAX
UNITS
LSB
mV
DNL
Q1.0
CELLV
-5
+5
OS
CELLA
Cells 1 through 12
-1.0
+1.0
%
V
R
from C(N) to C(N+1) when
SWITCH
Cell-Balancing Switch Resistance
AUXIN1, AUXIN2 INPUTS
1.5
6
20
I
enabled
AUXIN1, AUXIN2 to AGND; ADC REF =
THRM
Absolute Differential Input Range
VAUXINXIN
0
0
V
V
V
THRM
THRM
Common-Mode Input-Voltage
Range
Inputs AUXIN1/2 referred to AGND
ADC off; input voltage = 3.3V
V
Input-Leakage Current
ADC Resolution
I
-1.0
12
+1.0
FA
AUXIN
Bits
Fs/
Conversion Time
t
10
AUX_
Input
S
T
= +25NC
-0.5
-1.0
+0.5
+1.0
A
Accuracy
%
-40NC < T < +105NC
A
Differential Nonlinearity
Offset Error
DNL
AUXV
No missing codes at 12 bits
AUXIN1, AUXIN2
Q1.0
LSB
mV
%
-8
-1.0
5
+8
+1.0
28
OS
Gain Error
AUXA
AUXIN1, AUXIN2
V
THRM Switch Resistance
VOLTAGE REFERENCE
Output REF Voltage
REF Output Short-Circuit Current
R
THRM to VAA (Note 3)
18
I
THRM
REFV
T
= +25NC
A
2.45
2.50
2.55
V
OUT
REF-SC
DREF/
I
Q12.5
mA
Temperature Coefficient
Initial Drift
Q25
ppm/NC
DTEMP
Change after
1000hr burn-in
120
ppm
LOGIC INPUTS AND OUTPUTS (GPIO AND SHDN)
SHDN Voltage High
1.8
V
V
0.5
1
SHDN Voltage Low
V
V
V
3.4V
SHDN =
5.15
12.6
18
45
0.8
FA
= 30V
SHDN Input Leakage Current
SHDN
SHDN
= 56V
GPIO Input Voltage Low
GPIO Input Voltage High
I/O Leakage Current
V
V
2.4
-1
I/O pins programmed to high impedance
+2
+6.2
0.4
FA
V
GPIO Output Voltage Low
I
= 3mA
SINK
VDD -
L
0.5
GPIO Output Voltage High
I
= 3mA
V
SOURCE
Maxim Integrated
3
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
ELECTRICAL CHARACTERISTICS (continued)
(T = T
A
to T
, unless otherwise noted. V
MAX
= V
= 18V to +60V, typical values are at T = +25NC, unless otherwise
DCIN A
MIN
GNDU
specified from -40NC to +105NC per the application circuit in Figure 4.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LINEAR REGULATOR +304V (VAA)
Input Voltage Range
V
0 < I
0 < I
6V < V
< 8mA
6.0
70
V
V
DCIN
LOAD
< 8mA;
< 70V
LOAD
Output Voltage
V
3.25
3.4
3.55
VAA
DCIN
Short-Circuit Current
VAA = 0V, 6V < V
Falling VAA
< 30V
60
3.05
3.1
80
mA
V
DCIN
2.85
2.9
2.95
3.0
Power-On Reset Threshold
(Note 3)
Rising VAA
POR threshold hysteresis
Rising temperature
0.01
40
mV
NC
NC
Thermal Shutdown
+145
15
Thermal-Shutdown Hysteresis
CHARGE PUMP +304V
I
= 0 at 0.1FF CP+ to CP-
3.2
3.2
3.4
2.5
3.55
3.55
LOAD
Output Voltage
V
- V
V
%
V
VDDU
GNDU
1mA = I
at 0.1FF CP+ to CP-
LOAD
I
/I at 2.7V,
VDDU GNDU - IVDDU
VDD
Charge-Pump Efficiency
60
89
99
U - GNDU
Charge-Pump Undervoltage
Threshold
V
2.0
2.7
3.2
CPUV
INTERNAL OSCILLATORS (320768kHz, 60±MHz)
Internal 32.768kHz Oscillator
Frequency
f
32.113 32.768 33.423
kHz
WD-OSC
Internal 6.0MHz Oscillator
Frequency
f
5.82
6.0
6.18
MHz
HF-OSC
I2C LOWER PORT SCL , SDA , ALRM (Relative to GND VDD = Nominal 304V)
L
L
L
L,
L
0.3 x
SDA , SCL Input Voltage Low
V
V
V
L
L
V
VDDL
0.7 x
SDA , SCL Input Voltage High
L
L
V
VDDL
0.1 x
SDA , SCL Input Hysteresis
0.2
0.5
L
L
V
VDDL
SDA , ALRM Output Voltage Low
At sink = 3mA
0.4
1.0
3
V
L
L
SDA , SCL Leakage Current
V
= V
= 1.5V
FA
L
L
SDAL
SCLL
R
Active edge
0.5
35
1
50
1
ACTIVE_EDGE
kI
Managed passive state
Off passive state
75
SDA , Managed Resistance
L
MI
t
t
(active edge pulse)
ONE_SHOT
150
120
250
380
550
ns
ONE_SHOT
SDA rises to 70% within active edge
L
time when loaded with this capacitance
SDA 1-TAU Capacitance
C
280
pF
V
L
1_TAU
VDD -
L
0.4
ALRM Output High Voltage
At source = 3mA
L
ALRM Heaat Frequency
L
OSC = 32.768kHz Q2.0%
16,000 16,384 16,711
15
kHz
pF
Lower Port Input Capacitance
SCL , SDA , ALRM
L L L
4
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
ELECTRICAL CHARACTERISTICS (continued)
(T = T
A
to T
, unless otherwise noted. V
MAX
= V
= 18V to +60V, typical values are at T = +25NC, unless otherwise
DCIN A
MIN
GNDU
specified from -40NC to +105NC per the application circuit in Figure 4.)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
I2C UPPER PORT SCL , SDA , ALRM (Relative to GND VDD )
U
U
U
U,
U
0.3 x
SDA , ALRM Input Voltage Low
V
V
V
U
U
V
VDDU
0.7 x
SDA , ALRM Input Voltage High
U
U
V
VDDU
0.1 x
SDA , ALRM Input Hysteresis
0.05
0.4
U
U
V
VDDU
SDA , SCL Output Voltage Low
At sink = 3mA
0.4
+1
3
V
U
U
SDA , SCL Leakage Current
V
= V = 1.5V
SCLU
-1
0.5
30
Q1.0
1
FA
kI
kI
MI
ns
U
U
SDAU
Active edge
Managed passive state
Off passive state
50
1
75
SDA , Managed Resistance
U
t
t
(active edge pulse)
ONE_SHOT
150
120
250
480
550
ONE_SHOT
SDA rises to 70% within active edge
U
time when loaded with this capacitance,
i.e., choose 100pF to guarantee 3Hrising
edge
SDA 1-TAU Capacitance
280
pF
U
V
V
= VDD + 0.15V
1
1
ALRMU
ALRMU
U
ALRM Clamp Current
FA
V
U
= GND - 0.15V
U
GND
-0.49
U
250FA current pulling below GND
U
ALRM Clamp Voltage
U
VDD
+
U
250FA current pulling above VDD
SCL , SDA , ALRM
V
U
0.49
Upper Port Input Capacitance
Port-to-Port Level Delay
Interface Startup
8
3
pF
Fs
U
U
U
1
ms
From SHDN or from POR
I2C TIMING CHARACTERISTICS
I2C Clock Frequency
f
10
200
kHz
ms
I2C
Bus Timeout Period
t
t
Timeout for maximum clock low/high time
27.4
TIMEOUT
Master to slave delay from a STOP to the
next START command
Master hold time after a START
command
Bus Free Time
Bus Hold Time
t
500
350
Fs
Fs
BUF
t
HD-STA
Bus START Command Setup Time
Bus STOP Command Setup Time
t
Repeated START setup time
STOP condition setup time
Transmit
1
Fs
SU-STA
100
500
-30
400
400
ns
SU-STOP
SLAVE PORT
t
HD-DAT
Receive
SDA Data Hold Time
ns
Transmit
MASTER PORT
t
HD-DAT
Receive (Note 7)
Maxim Integrated
5
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
ELECTRICAL CHARACTERISTICS (continued)
(T = T
A
to T
, unless otherwise noted. V
MAX
= V
= 18V to +60V, typical values are at T = +25NC otherwise specified
DCIN A
MIN
GNDU
from -40NC to +105NC per the application circuit in Figure 4.)
PARAMETER
SYMBOL
CONDITIONS
Transmit (Note 7)
MIN
250
TYP
MAX
UNITS
SLAVE PORT
t
SU-DAT
Receive
250
SDA Data Setup Time
ns
Transmit (Note 7)
Receive
250
MASTER PORT
t
SU-DAT
1000
1.25
1.25
SCL Low Time
t
Fs
Fs
L
LOW
SCL High Time
L
t
HIGH
Remastered Clock Minimum High
Time
t
1
us
MCL-MIN
LEVEL-SHIFT TIMING
Level Shift Delay (SDA to SDA
Rising or falling edge at 1.5V threshold;
pin-to-pin delay with 100pF loading
L
U
t
t
400
600
1100
800
ns
ns
LS-DAT
or SDA to SDA )
U
L
Rising or falling edge at 1.5V threshold;
pin-to-pin delay with 100pF loading
Level Shift Delay (SCL to SCL )
L
U
LS-CLK
POWER-SUPPLY REQUIREMENTS DCIN
I
DCIN
Acquisition
Mode
3.0
4.1
70
6
High-voltage mux enabled, ADC
converting 12 channels; V
= 30V
mA
DCIN
I
Acquisition
Mode
HV
9.6
I
DCIN
Cell-Balancing
Mode
Cell balancing enabled for four switches,
LDO, REF, and OSC running; V
Current Consumption
=
DCIN
(Note: IDD testing is done in
I
GNDU
Cell-Balancing
Mode
Q
V
= 6V
GNDU
production test with a coverage
of 71%)
63
I
DCIN
55
20
150
130
2
FA
Standy Mode
No conversions or cell balancing; LDO,
REF, and OSC running, SHDN = 1
I
GNDU
Standby Mode
I
DCIN
0.25
0.3
Shutdown Mode
SHDN = 0
I
GNDU
2
Shutdown Mode
Note 3: Guaranteed by design and not production tested.
Note 4: Differential input voltage range for which channel gain and offset error applies.
Note ꢀ: Common-mode level at each pin required for specified operation of the high-voltage mux.
Note 6: Offset and gain error are calibrated at +25NC and 3.0V per cell at the factory, assuming that VC
is met.
XIN
Note 7: This is a derived specification. No characterization required. These specifications involve the clock low time and clock high
time used.
6
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Pin Configuration
TOP VIEW
+
DCIN
CP+
CP-
1
2
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
HV
C12
C11
C10
C9
3
VDD
GND
SCL
4
U
U
U
U
U
5
6
C8
SDA
7
C7
ALRM
8
C6
N.C.
GPIO2
GPIO1
GPIO0
9
C5
MAX11068
10
11
12
13
14
15
16
17
18
19
C4
C3
C2
VDD
GND
SCL
C1
L
L
L
L
L
CO
VAA
AGND
REF
AUXIN1
THRM
SDA
ALRM
SHDN
AUXIN2
TSSOP
9.7mm x 4.4mm
Pin Description
PIN
NAME
FUNCTION
DC Power-Supply Input. DCIN supplies the internal 3.4V regulator, which provides low-voltage power to the
device. Bypass DCIN to GND with a 1FF capacitor.
1
DCIN
Charge-Pump Capacitor Plus Input for the Internal Charge Pump. Connect a 0.1FF high-voltage capacitor
between CP+ and CP-.
2
3
CP+
CP-
Charge-Pump Capacitor Minus Input for the Internal Charge Pump. Connect a 0.1FF high-voltage capacitor
between CP+ and CP-.
Level-Shifted Upper I2C Port Digital Supply for Use in Communicating with an Upper, Neighboring Battery
Module. This is a regulated output voltage from the internal charge pump that is level shifted above the DCIN
pin voltage level.
4
5
VDD
U
Level-Shifted Upper I2C Port Ground. This pin is the reference level and ground return for VDD and also the
U
supply input for the charge pump. It should be tied to the DCIN takeoff point on the battery stack as shown in
the application diagrams.
GND
U
Level-Shifted Upper Port I2C Clock Line. SCL is the I2C clock line communicating with the upper
U
6
7
SCL
U
neighboring battery module. This pin swings between VDD and GND .
U
U
Level-Shifted Upper Port I2C Bidirectional Serial Data Line. SDA is the I2C data line communicating with the
U
SA
U
upper neighboring battery module. This pin swings between VDD and GND .
U
U
Maxim Integrated
7
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Pin Description (continued)
PIN
NAME
FUNCTION
Upper Port Alarm Input. Overvoltage, undervoltage, over/undertemperature, cell mismatch, and
communication fault. The alarm signal is laddered. This signal is referenced to VDD and GND . Connect
8
ALRM
N.C.
U
U
U
this signal to VDD through a pullup resistor.
U
9
Not Internally Connected/Test I/O. Leave open; do not connect any external circuit to this pin.
General-Purpose I/O 2. This pin swings between VDD and GND .
10
11
12
13
14
GPIO2
GPIO1
GPIO0
L
L
General-Purpose I/O 1. This pin swings between VDD and GND .
L
L
General-Purpose I/O 0. This pin swings between VDD and GND .
L
L
VDD
L
Lower Port I2C + 3.4V Digital Supply Input. Connect to VAA and decouple to GND with a 0.47FF capacitor.
L
GND
L
Lower Port I2C Common or Ground. A star ground connection to AGND is recommended.
Lower Port I2C Clock. SCL is the I2C clock line communicating with the lower neighboring battery module.
L
15
16
SCL
L
This pin swings between VDD and GND .
L
L
Lower Port I2C Data I/O. SDA is the I2C serial data line communicating with the lower neighboring battery
L
SDA
L
module. This pin swings between VDD and GND .
L
L
Lower Port Alarm Output. Overvoltage, undervoltage, over/undertemperature, cell mismatch, and
communication faults. The alarm signal is laddered and driven from the highest module down to the lowest.
The alarm output is nominally a clocked heartbeat signal that provides a 16kHz clock when no alarm is
17
18
ALRM
L
present and is held at logic-high during an alarm. This signal swings between VDD and GND .
L
L
Active-Low Shutdown/Input. This pin completely shuts down the MAX11068 internal regulators and oscillators
when the pin is less than +0.6V as referenced to AGND. The I2C bus is nonresponsive when shutdown is
asserted. SHDN for the first pack should be driven by the host controller through the recommended interface
circuit. SHDN for laddered modules should be tied to the lower neighboring battery module through the
recommended interface circuit. The shutdown pin is 60V tolerant for connection directly to the top of the
battery stack.
SHDN
Auxiliary Analog Input 2. A low-voltage analog input pin with a full-scale range of AGND to VAA that can be
used for monitoring an external NTC or general-purpose measurements. This channel uses the VAA voltage
as the reference voltage for the ADC conversion. When used with the THRM pin and a resistor-divider,
ratiometric measurements can be made.
19
20
21
AUXIN2
THRM
External Thermistor Bias Output. This is a switched connection for supplying a bias voltage from the internal
+3.4V regulator (VAA) to an external NTC device for measuring the temperature of the battery module. This
pin can supply up to 2mA from the VAA regulator.
Auxiliary Analog Input 1. A low-voltage analog input pin with a full-scale range of AGND to VAA that can be
used for monitoring an external NTC or general-purpose measurements. This channel uses the VAA voltage
as the reference voltage for the ADC conversion. When used with the THRM pin, ratiometric measurements
can be made.
AUXIN1
22
23
24
25
26
27
28
29
REF
AGND
VAA
C0
+2.5V Voltage Reference. Bypass REF to AGND with a 1FF capacitor placed close to the device.
Analog Ground. Should be tied to the negative terminal of cell 1.
+3.4V Analog Supply Output. Connect to VDD and bypass with a 1.0FF capacitor to AGND.
L
Cell 1 Minus Connection. Bypass to AGND with a 1.0FF capacitor.
Cell 2 Minus Connection and Cell 1 Plus Connection
Cell 3 Minus Connection and Cell 2 Plus Connection
Cell 4 Minus Connection and Cell 3 Plus Connection
Cell 5 Minus connection and Cell 4 Plus Connection
C1
C2
C3
4
8
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Pin Description (continued)
PIN
30
31
32
33
34
35
36
37
NAME
C5
FUNCTION
Cell 6 Minus Connection and Cell 5 Plus Connection
Cell 7 Minus Connection and Cell 6 Plus Connection
Cell 8 Minus Connection and Cell 7 Plus Connection
Cell 9 Minus Connection and Cell 8 Plus Connection
Cell 10 Minus Connection and Cell 9 Plus Connection
Cell 11 Minus Connection and Cell 10 Plus Connection
Cell 12 Minus Connection and Cell 11 Plus Connection
Cell 12 Plus Connection. Top of battery module stack.
C6
C7
C8
C9
C10
C11
C12
High-Voltage Bias Pin. HV is biased through a diode connection to the charge pump. It is used internally to
supply the high-voltage mux. Connect to DCIN through a 3.3FF capacitor.
38
HV
HV
DCIN
REF
GND VDD
U
VAA
U
+6V TO
72V
PRECISION
+2.5V
REFERENCE
THRM
+3.4V
LINEAR
REGULATOR
ALRM
U
2
I C
SCL
U
UPPER
PORT
SDA
AUXIN2
POR
U
6.0MHz
OSC
AUXIN1
C12
C11
C10
C9
VDD
GND
U
CP+
U
GND
U
C8
CONTROL
AND
STATUS
INSTR
AMP
12-BIT
ADC
LEVEL
SHIFT
CP-
C7
C6
CELL
EQUALIZATION
SWITCH
BANK
C5
C4
COM
+3.4V
C3
AGND
C2
ALRM
L
32kHz
OSC
C1
SCL
L
2
I C
C0
LOWER
PORT
SDA
L
12
AGND
MAX11068
+3.4V
SHDN
27
SW_SEL(26:0)
DIS_SEL(11:0)
GPIO0 GPIO1 GPIO2
GND VDD
L L
Figure 1. Functional Diagram
Maxim Integrated
9
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
CELL-
BALANCING
SWITCHES
HIGH-
VOLTAGE
MUX
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
REF
THRM
INSTR
AMP
ADC IN +
ADC IN -
LV
MUX
12-BIT ADC
SELF-
DIAGNOSTIC
REF
AUXIN2
AUXIN1
AGND
Figure 2. Analog Front-End Block Diagram
10
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
HV
VDD
CP+
U
6V
DCIN
ALRM /SDA /SCL
U
U
U
GND
CP-
U
C12
C11
80V
80V
80V
9V
9V
VAA
C3 TO C10 MATCH
OTHER INPUTS
REF/THRM
SHDN
MAX11068
ESD DIODES
C2
C1
VDD
L
9V
9V
4V
AIN0/1
GPIO0/1/2
C0
ALRM /SDA /SCL
L
L
L
4V
4V
4V
80V
AGND
GND
L
NOTE: ALL DIODES ARE RATED FOR ESD CLAMPING CONDITIONS. THEY ARE NOT INTENDED TO
ACCURATELY CLAMP DC VOLTAGE. ALL DIODES SHOWN HAVE A PARASITIC PN DIODE FROM
THEIR CATHODE TO AGND THAT IS OMITTED FOR CLARITY. THIS PARASITIC DIODE HAS ITS
ANODE AT AGND.
Figure 3. MAX11068 ESD Diode Diagram
Maxim Integrated
11
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Typical Operating Circuit Diagrams
MODULE N+1
CELL STACK
MODULE N+1 GND
REFERENCE
MODULE-
(N+1)
A KELVIN CONNECTION IS OPTIONAL FOR
THE DCIN TAKEOFF IN HIGH-CURRENT
APPLICATIONS. SEE THE NOISE TOLERANCE
SECTION FOR DETAILS.
C
HV
3.3µF, 6V
MODULE
+
(N)
22I
FUSE
22I
100kI
GND
U
HV
DCIN
C
1.0µF,
6V
BAT46
5.6V
DD
D
DCIN
VDD
U
BUS BAR
R3
DC
150kI
R1
DC
150kI
C
1.0µF
DCIN
SMCJ70
80V
D
12
SMBus-LADDERED
TO UPPER MODULES
R13
GND
GND
U
U
C3
C12
C11
C10
DC
3.3nF, 630V
CELL #12
CELL #11
C12
C11
R12
R11
ALRM
SCL
ALRM
L
U
U
U
C2
DC
3.3nF, 630V
SCL
L
C1
DC
3.3nF, 630V
CELL #10
CELL #9
CELL #8
CELL #7
CELL #6
CELL #5
CELL #4
CELL #3
CELL #2
CELL #1
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
R10
SDA
SDA
L
C9
C8
C7
C6
C5
C4
C3
C2
C1
R9
MODULE
N+1
GND
U
CP+
CP-
D
HV
GND
U
HV
150I
R8
MAX11068
TO SHDN
C
0.1µF
100V
P
S1B
5.6V
100nF
R7
R6
GND
U
VAA
VDD
L
C
C
L
A
R5
R
R
P3
P2
150kI
0.47
6V
µF
1µF
6V
150kI
GND
L
R4
R3
R2
SCL
L
L
L
SDA
ISOLATOR
AND
CONTROL
INTERFACE
ALRM
1kI
R1
C0
SHDN
MODULE-
(N)
200kI
68nF
5.6V
THRM
RT2
10kI
1%
RT1
10kI
1%
C0
1µF
CT3
100pF
AUXIN2
AUXIN1
GPIO0
GPIO1
GPIO2
BUS BAR
CT2
100pF
CT1
100pF
t
t
AGND
REF
LOCAL
GROUND
C
1µF
REF
THERMISTORS
10kI AT +25NC
MODULE N-1 CELL
STACK
Figure 4. Operating Circuit Diagram for a 12-Cell System
12
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
HV
DCIN
D
HV
MODULE
+
(N)
C12
C11
C10
C9
VDD
U
ALRM
U
SCL
U
SDA
U
R9
R8
C8
C7
C6
C5
C4
C3
C2
C1
GND
CP+
U
CELL 8
CELL 7
CELL 6
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
C8
C7
C6
C5
C4
C3
C2
C1
MAX11068
R7
R6
CP-
VAA
R5
VDD
L
R4
R3
R2
SCL
L
SDA
L
ALRM
L
R1
C0
SHDN
GND
MODULE-
(N)
C0
1µF
THRM
L
AUXIN2
AUXIN1
GPIO0
GPIO1
GPIO2
AGND
REF
Figure 5. Simplified Operating Circuit Diagram for an 8-Cell System
Maxim Integrated
13
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
These bidirectional serial buses can withstand large
Detailed Description
differences in interchip grounds and system noise. The
built-in level-shifting and predefined command protocol
provide a low-cost, flexible, and reliable communication
bus. Command-up forwarding relays communication
along the bus from chip to chip for fast response. A
1Fs delay is incurred in relaying command messages,
bounding the maximum delay in response to a com-
mand to 1Fs multiplied by the number of chips used in
the stack minus 1. For a 31-chip stack, a maximum 30Fs
delay is incurred before the top module responds. This
means that up to 372 cells can be measured with an
elapsed measurement time from start to finish of 137Fs.
For a 16-chip stack, a 15Fs delay is incurred. This allows
measurement of up to 192 cells with an elapsed mea-
surement time from start to finish of 122Fs.
The MAX11068 has two auxiliary analog inputs that can
be used to measure external resistance temperature
detector (RTD) components. A negative temperature
coefficient (NTC) RTD can be configured with the
AUXIN1 or AUXIN2 analog inputs to accurately monitor
module or battery-cell temperature. An internal tem-
perature monitor on the die is used to detect thermal
overload and disables the MAX11068 cell-balancing
switches and linear regulator should the +145NC thermal
limit be exceeded.
The MAX11068 has 12 built-in cell-balancing/discharge
switches that can support up to 200mA cell discharge
currents. The MAX11068 package can support up to
1.2W of power dissipation, which limits the number of
balancing/discharge switches that can be enabled when
using a 200mA set current to three nonconsecutive cells
at no more than +75NC ambient temperature. With a
110mA cell set current, all 12 internal cell switches can
be enabled at the same time. The balancing switches
can also be used to detect an open circuit on any of the
cell sense wire connections.
The MAX11068 incorporates an internal oscillator that
generates a 6.0MHz system clock with Q3.0% accuracy.
Architectural Overview
The MAX11068 is a complete data-acquisition system on
a chip designed for rugged, high-voltage measurement
applications. It can measure up to 12 channels of volt-
ages from batteries or SuperCaps with a high-accuracy,
high-speed SAR ADC. Two auxiliary input channels
may be configured for general-purpose measurements
or as specialized temperature conversion inputs when
used with RTD devices. Simple, yet fast and powerful
digital command and control is implemented through
unique, high-performance, level-shifted I2C communica-
tion ports. This allows SMBus laddering the communica-
tion and control bus on up to 31 battery modules using
the MAX11068.
The MAX11068 contains a 25ppm/NC precision band-
gap reference and an internal regulator that creates the
supply for the analog front end and the interchip, level-
shifted, communication bus. The regulator can operate
from a 6.0V to 72V supply input. The external shutdown
pin can be used to reset the MAX11068.
The MAX11068 incorporates an I2C physical interface
for interchip communication and control. The I2C bus
system is designed to allow SMBus laddering of up to
31 devices without the need for any interchip isolation.
14
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
In hybrid electric vehicles (HEVs), plug-in hybrid electric
vehicles (PHEVs), electric vehicles (EVs), or fuel-cell
vehicles (FCVs), cell counts can range from 36 cells to
200 cells using Li+ batteries and up to as high as 200 to
500 cells using NiMH batteries. SuperCaps are typically
used in fast-charge holding applications such as regen-
erative braking energy storage.
Battery Pack Architectures
Battery packs are designed in a modular fashion to allow
for multiple configurations, and fast and flexible assem-
bly. This reduces cost by streamlining the build or repair
process. The definition of a battery pack is a system
comprising one or more battery modules connected in
either a series or matrix configuration to create a high-
voltage power source. Transportation or high-power
battery-backup-system applications typically use many
series-connected battery modules to generate voltages
of up to several hundred volts. This voltage can then be
inverted and transformed to levels suitable for the given
load. A battery module is a series of cells configured as
a subsystem that can be combined with other modules
to build a high-voltage pack. For the MAX11068, the
minimum cell count per module is limited by the 6.0V
input requirement of the regulator, while the maximum
cell count is 12. The 6.0V minimum requirement usually
limits configurations to at least two lithium-ion (Li+), six
NiMH, or six SuperCap cells per module. Figure 6 is the
module system with redundant fault-detection applica-
tion schematic.
There are two fundamental battery-pack management
architectures that can be realized with the MAX11068:
U
U
Distributed module communication
SMBus-laddered module communication
A distributed module system deploys a point-to-point
connection from each battery module back to a master
microcontroller in the BMS. Because the battery mod-
ules operate from the high-voltage battery stack, galvan-
ic isolation must be used when communicating with the
master microcontroller. Figure 8 shows the distributed
communication battery pack.
An SMBus-laddered module system deploys a serial
communication bus that travels through each battery
module and is then accessed at one entry point in the
system by the master microcontroller in the BMS. The
SMBus ladder method reduces cost and requires at
most a single galvanic isolator between the high-voltage
batteries and the main power net. Galvanic isolation may
not be required in certain low-voltage applications. See
Figure 9.
Battery packs used in transportation applications may
be composed of various battery technologies (NiMH,
Li+, SuperCap, or lead acid) and typically include an
electronic battery-management system (BMS), envi-
ronment control, and several safety features. Figure 7
shows the electric vehicle system (EVS).
Maxim Integrated
15
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
MODULE
N+1 CELL N+1 GND
STACK REFERECNCE
MODULE
SHDN
ALRM
L
3 2 1 0 2 1 0
OVSEL UVSEL TOPSEL
11068
ALRM
VDD
GND
CP+
CP-
ALRM
L
SHDN
U
U
U
MODULE -
ISOLATOR AND
CONTROL
(N+1)
CD
HV
ALRM
L
VAA
AGND
INTERFACE FOR
FIRST MODULE
11068
MAX11080/MAX11081
DCIN
SCL
SDA
L
L
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
GPIO
MODULE +
(N)
HV
DCIN
R13
R12
R11
R10
R9
C12
C11
C10
C9
VDD
U
C12
C11
C10
C9
CELL 12
CELL 11
CELL 10
ALRM
U
SCL
U
SDA
U
CELL 9
CELL 8
C8
GND
CP+
CP-
VAA
U
C8
R8
C7
MAX11068
CELL 7
CELL 6
C7
R7
C6
C6
R6
C5
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
C5
R5
C4
VDD
L
C4
C3
R4
C3
SCL
L
R3
C2
C1
C0
SDA
L
C2
C1
C0
R2
ALRM
L
R1
SHDN
MODULE-
(N)
BATTERY
CONNECTOR
THRM
AUXIN2
AUXIN1
AGND
GND
L
LOCAL
GROUND
GPIO0
GPIO1
GPIO2
REF
MODULE N-1
CELL STACK
NOTE: REFER TO EACH DEVICE’S APPLICATION REFERENCE CIRCUITS FOR COMPONENTS
AND VALUES NOT SHOWN ON THIS SIMPLIFIED SYSTEM-LEVEL SCHEMATIC.
Figure 6. Battery Module System with Redundant Fault-Detection Application Schematic
16
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
BATTERY PACK
MAIN
CONN
SWITCH
MOTOR DRIVE+
VEHICLE
12V PWR
VEHICLE
CONTROL
SYSTEM
(VCS)
BATTERY
MANAGEMENT
SYSTEM
CELL PACK
(Li 40–90 CELLS)
(NiMH 100–300 CELLS)
COMM BUS
COMM BUS
VEHICLE GND
COMM BUS
INVERTER
(BMS)
MOTOR DRIVE-
CONN
Figure 7. Electric Vehicle System
PACK
SWITCHES
INVERTER+
BATTERY
MODULE
SLAVE MONITOR
AND CONTROL
ISOLATOR
TEMP
BATTERY
MODULE
SLAVE MONITOR
AND CONTROL
ISOLATOR
ISOLATOR
ISOLATOR
TEMP
BATTERY
MODULE
SLAVE MONITOR
AND CONTROL
TEMP
VEHICLE 12V PWR
VEHICLE GND
COMM BUS
BATTERY
MODULE
SLAVE MONITOR
AND CONTROL
MASTER
CONTROLLER
FAULT CHECK
TEMP
PACK
SWITCHES
CURRENT
SENSE
INVERTER-
Figure 8. Distributed Communication Battery Pack
Maxim Integrated
17
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
PACK
INVERTER+
SWITCHES
BATTERY
MODULE
SLAVE MONITOR
AND CONTROL
STUB
TEMP
BATTERY
MODULE
SLAVE MONITOR
AND CONTROL
TEMP
VEHICLE 12V PWR
VEHICLE GND
COMM BUS
BATTERY
MODULE
SLAVE MONITOR
AND CONTROL
MASTER
CONTROLLER
ISO
R
R
PACK1
PACK2
FAULT
CHECK
TEMP
PACK V/I
MEASUREMENT
µI
SHUNT
PACK
SWITCHES
INVERTER-
Figure 9. SMBus-Laddered Battery Module Communication
18
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
resistor values to provide lowpass filtering of the ADC
measurement. Capacitor values should be in the 100nF
to 1FF range.
Battery-Management
System (BMS)
The BMS in an electric vehicle monitors cell voltage,
The first cell position between C1 and C0 must be popu-
lated for all applications with a voltage of at least 500mV.
This ensures accurate measurements for all other cell
positions as defined by the ADC specifications. When
implementing a module configuration with fewer than 12
cells, the first cell position should always be used, and
then other cell positions may be used in any configura-
tion. Any unused cell positions should have their inputs
shorted together. Random connection of cells or the
high-voltage supplies during module configuration does
not cause adverse effects.
pack current, and temperature. The BMS is composed
of two components. The first is the master controller of
the system that handles all communication with the VCS.
It also handles state of charge, state of health, and fault-
management features of the battery pack. The second
component is the data-monitoring function, which gath-
ers information on the conditions of the battery cells,
takes voltage/current/temperature measurements, and
signals safety faults.
The slave monitor controller (SLC) is directly connected
to the series stack battery cells. The SLC measures cell
voltages and module temperature, as well as controls
the cell-charge equalization feature that keeps all cells
balanced to equal states of charge. The SLCs are also
designed to report alarm conditions such as cell over-
voltage or undervoltage, sense wire-open circuits, and
in the case of Li+ battery chemistries, overtemperature
situations. The SLCs are managed by the master control-
ler. The master controller orchestrates all data acquisi-
tion and cell-balancing tasks in the slaves. The master
also measures the pack current coincident to voltage
measurements so that state of health of the battery pack
can be determined. Measurement of the current through
the pack is made across a low-value shunt resistor or
hall sensor.
Measurement Scanning
When a cell is enabled for acquisition by setting the
associated scan-enable bits in the CELLEN register
(address 0x09), the appropriate cell differential input is
scheduled for conversion. The auxiliary input channels
along with the self-diagnostic channel may be similarly
enabled using their enable bits in the ADCCFG register
(address 0x08).
Conversion begins with the setting of the SCAN bit in the
SCANCTRL register. The setting of the SCAN bit may
be accomplished using either the WRITEALL command
or the WRITEDEVICE command, depending on whether
all devices are expected to perform the conversion. If
the ADC is still busy from a previous acquisition scan,
the scan command is ignored. Each module in a sys-
tem begins the measurement scan cycle as soon as it
receives the scan signal. The measurement order of the
inputs during a cycle is as follows:
Cell Inputs C0–C12
The MAX11068 contains 13 analog inputs that are used
for the differential measurement of as many as 12 bat-
tery cells. Each differential cell input can withstand up
to 9.0V and can be included in the measurement cycle
through the cell-channel scan-enable bits of the CELLEN
register (address 0x09). Cell inputs are measured differ-
entially and level shifted down to the internal ADC by a
high-voltage mux and ADC preamp. The common-mode
1) All enabled cell inputs phase 1, descending order
(12–1)
2) All enabled cell inputs phase 2, descending order
(12–1)
3) Self-diagnostic measurement phase 1, if enabled
4) Self-diagnostic measurement phase 2, if enabled
range of the cell inputs from C2 to C12 is 0.5V to V
-
HV
2.9V. Common-mode range for C1 is limited to 7.0V and
for C0 it is limited to voltages within 50mV of AGND for
proper measurements. The absolute maximum differen-
tial input between two inputs must always be observed,
which is 9.0V.
5) All enabled auxiliary inputs phase 1, ascending order
(AUXIN1, AUXIN2)
The complete acquisition of the cell voltages takes place
in two phases, which is shown in Figure 10. The first
phase is the raw cell-voltage acquisition. In this stage,
the ADC scans through all the enabled cell input chan-
nels, starting with the highest cell.
The application circuit shows RC filtering for each cell
input. The values of the resistors are chosen in large
part depending on the cell-balancing functionality that is
desired. The capacitor value chosen complements the
Maxim Integrated
19
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
B12+
B12-
B11+
B11-
B10+
B10-
TOP CELL SAMPLING TIME = 5.67µs
OTHER CELLS SAMPLING TIME = 3.83µs
B9+
B9-
B8+
B8-
B7+
B7-
B6+
B6-
B5+
B5-
B4+
B4-
B3+
B3-
B2-
B1-
B2+
B1+
t + 16.97µs
0
t + 59.1µs
0
t + 106.9µs
0
TIME
t - STROBE POINT
0
Figure 10. Cell-Scanning Timing
The second stage in the channel-scanning process
is the correction phase, where the front-end amplifier
chops out any offset and reference-induced errors. This
provides a high-accuracy cell voltage result. In this
stage, the channels are converted in the same highest
to lowest order as the initial measurement. The module-
to-module sampling points differ by the communication
forwarding delay from the I2C command. With the mea-
surements from the two scan phases complete, the ADC
data is then offset corrected, averaged, and updated in
the cell data registers.
ment. So, when both auxiliary channels are measured,
the extra settling time occurs twice. Extra settling time
is not needed by the MAX11068 ADC; it is only for the
benefit of the external application circuit.
Calculating Measurement Time
The first requirement for performing a measurement
conversion is setting the SCAN bit. This can be done
by using the WRITEALL or WRITEDEVICE commands.
The write commands require 5 full bytes of data, plus 5
acknowledge bits and the start and stop bits. This totals
47 bits of data sent by the host, which would require
235Fs at a 200kHz I2C clock rate.
After the cell-measurement cycle is complete, the self-
diagnostic channel is acquired when enabled. It is a
two-phase measurement as described for the cell-volt-
age inputs, with each phase measured one immediately
after the other. Finally, the enabled auxiliary inputs are
measured. They are measured in a single conversion,
with results reported in the AIN1 and AIN2 registers.
The auxiliary channels have a configurable option to
increase settling time that is set in the lower byte of the
ACQCFG register (address 0x0C). The configured extra
settling timimplemented just before the conversion
for each AUXIN channel that is enabled for measure-
The timing of the cell measurements is shown in Figure
10. At the start of the measurement cycle, there is a
measurement setup time prior to the measurement of the
highest cell totaling 11.3Fs. The highest cell measured
requires a sampling time of 5.67Fs, while the rest of the
inputs are sampled at 3.83Fs per channel. When all 12
channels are enabled, the 12-cell voltages for one phase
are acquired in 47.8Fs, not including the measurement
setup time. The total acquisition time for 12 cells is
106.9Fs
20
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
For every module in the battery pack, a 1Fs communi-
Thus, from the time the first device receives the scan
command until the last device completes its measure-
ment conversion, 109.9Fs elapse.
cation delay is incurred while the scan command is for-
warded up the SMBus ladder. Therefore, the difference
in the scan completion time from the first module to the
last module in a chain is no more than 1Fs x (no. of mod-
ules in the chain - 1) as shown in Figure 11.
The final aspect of the measurement conversion is the
retrieval of data from all devices. A READALL command
is the only way to transfer data from each device. Since
up to 12 cells are measured, the READALL command
must be performed for each cell whose data must be
transferred. For each READALL command, there are 5
total bytes of overhead. These include the broadcast
address byte, the command code byte (register address
to be read), the I2C address byte, the data check byte,
and the packet-error check (PEC) byte. Each of these
bytes has an acknowledge bit associated with it. The
register data from each device consists of 2 more bytes
plus 2 acknowledge bits. Finally, the overall data stream
consists of 3 more bits, start, stop, and repeated start.
Thus, for a read of a single register from all modules, the
total bit count is:
Taking the module conversion time and combining it with
the communication delay, the overall sampling window
of the system can be calculated:
Sampling window = 11.3Fs + (5.67Fs + (no. of cells
enabled per module -1) x 3.83Fs) x 2 phases + ((no. of
modules per pack - 1) x 1Fs per module)
So, for a battery pack that uses 12 cells per module and
a system with four modules (total cell count = 48), the
sampling window would be:
Sampling Window = 11.3 + (5.67 + 11 x 3.83Fs) x 2 +
((4 Modules -1) x 1Fs)
Sampling Window = (106.9Fs) + (3Fs) = 109.9Fs
READALL bit count = 3 + 5 x 8 + 5 + no. of modules x
(2 x 8 + 2) = 120
MODULE N
MODULE 5
COMMAND FORWARDING
MODULE 4
DELAY = 1µs
MODULE 3
MODULE 2
MODULE 1
SCAN AT t
t
ALL MODULES
0
t
= (NO. OF MODULES X 1µs) + 107µs
ALL MODULES
Figure 11. Measurement Scan Timing for a Multimodule System
Maxim Integrated
21
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
For the example with four modules and 12 cells per mod-
ule, the total READALL bit count would be 120 bits per
cell or 1440 bits for all 12 cells. At a 200kHz I2C clock
rate, the total time for this command would be 7.2ms.
cell-voltage values, as well as for overvoltage and under-
voltage conditions.
The maximum and minimum cell voltage readings are
stored in the upper 12 bits of the MAXCELL and MINCELL
registers (addresses 0x11 and 0x12). Also stored in the
lowest 4 bits of those registers is the cell number corre-
sponding to the data reading. Where multiple cells had
the same minimum or maximum reading, the highest cell
position having that reading is reported. The sum total
value of cell data whose measurements were enabled
in the last scan is stored in the TOTAL register (address
0x10) as a 16-bit value. Where a conversion is initiated
with no enabled cell inputs, the MINCELL, MAXCELL,
and TOTAL registers retain their current value.
The overall time from the host issuing the scan command
to the last data being received by the host includes the
write time for the scan command, the measurement con-
version time, and the time for the READALL command.
For this 12-cell, four-module, 200kHz I2C example the
total is:
235Fs + 106.9Fs + 7200Fs = 7.542ms
Effectively, the number of complete 12-cell measure-
ments that can be acquired and transferred back to the
host is no more than 132 per second. If the data from
every measurement is not transferred back to the host,
then significantly more measurements may be taken per
second. Enabling the auxiliary or self-diagnostic chan-
nels would decrease the effective sampling rate.
Cell-voltage data is also compared against programma-
ble cell overvoltage and undervoltage thresholds. These
thresholds are configured through the overvoltage and
undervoltage set and clear threshold registers (address-
es 0x18 to 0x1B). Alerts, when enabled, are triggered
as cell voltage data passes through the set threshold
level. Conversely, alerts are cleared when the cell volt-
age data passes through the clear threshold level. If the
voltage data is equal to a relevant cell threshold limit,
no action occurs. Therefore, if the set threshold level is
placed at full scale for the overvoltage alert or at zero
scale for the undervoltage alert, the alert cannot trigger
and is effectively disabled. The two thresholds, set and
clear, for each condition allow for digital hysteresis to be
configured in the alarm trigger. Figure 12 is a diagram
of the programmable overvoltage and undervoltage
thresholds.
Cell Overvoltage
and Undervoltage
The MAX11068 incorporates cell-voltage monitoring with
alert and alarm capability for diagnosing system status.
After each ADC voltage conversion, cell-voltage data is
stored in the cell-data registers. Only data registers for
cell positions that were enabled for the previous mea-
surement scan are updated. Cells that were not in the
measurement scan retain their previous value. The data
is also analyzed for the minimum, maximum, and total
V
OVERVOLTAGE ALERT
SET
OVERVOLTAGE SET AND CLEAR THRESHOLDS
POR DEFAULT VALUE (+5.0V)
OVERVOLTAGE SET THRESHOLD (OVTHRSET)
OVERVOLTAGE CLEAR THRESHOLD (OVTHRCLR)
OVERVOLTAGE ALERT
CLEARED
UNDERVOLTAGE ALERT
CLEARED
CELL VOLTAGE
N
UNDERVOLTAGE CLEAR THRESHOLD (UVTHRCLR)
UNDERVOLTAGE SET THRESHOLD (UVTHRSET)
UNDERVOLTAGE ALERT
SET
UNDERVOLTAGE SET AND CLEAR THRESHOLDS
POR DEFAULT VALUE (+0.0V)
t
Figure 12. Programmable Overvoltage and Undervoltage Thresholds Diagram
22
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Alerts may be enabled on a per-cell basis. Local enable
Managing Power
bits OVEN and UVEN are found in each cell’s data reg-
ister (addresses 0x20 to 0x2B). These bits are mapped
to the equivalent bits of the OVALRTEN and UVALRTEN
registers (address 0x06 and 0x07). If these bits are
enabled for a given cell, the cell reports its overvolt-
age or undervoltage alert status to the appropriate alert
status register (addresses 0x04 and 0x05). The alert
status is updated whenever new cell measurement data
is available. If either of these two alerts are active for
a cell, that cell’s corresponding ALRTCELL register bit
(address 0x03) is also set. All voltage alert status regis-
ter bits are zero when no alert is present and cannot be
manually cleared. To clear an active voltage alert, the
alert condition must be removed and a new measure-
ment must be taken or the alert must be disabled.
The MAX11068 contains 12 independently controlled
switches that have a typical on-resistance (R ) of
SW
6I with Q50% variation due to process and tempera-
ture. The package used for the MAX11068 is a 38-pin
TSSOP package with a maximum power limit (P
) of
MAX
1.2698W and a junction-to-ambient thermal resistance of
+63NC/W for a multilayer board. These parameters are
the fundamental limits for the package-power dissipa-
tion and require careful consideration when using the
internal cell-balancing switches since the switches are
the dominant power consumers in the device. For oper-
ating margin, it is recommended targeting a maximum
power level that is 70% of the absolute maximum rating.
The maximum die junction temperature that is allowed
is +150NC. A built-in overtemperature protection circuit
protects the die at a junction temperature of +145NC,
however. When the overtemperature limit is reached, the
internal cell-balancing switches are disabled. The asso-
ciated cell-balancing switch enable bits in the Balancing
Switch Control register (BALCFG at address 0x0B) are
not directly affected, but the resulting power down of
the linear regulator may cause a power-on reset (POR)
condition, which would reset the BALCFG register and
deassert all switch-enable bits. The maximum number of
cell-balancing switches that can be enabled at any one
time is calculated as shown below:
The global ALRTOV and ALRTUV bits in the STATUS reg-
ister (address 0x02) are set when any cell has an active
alert as indicated in the ALRTOVCELL or ALRTUVCELL
registers. All alerts are automatically cleared following
the next conversion cycle when the alert conditions no
longer exist. Using this tiered approach to alert report-
ing, the system host may quickly establish whether any
voltage alerts are active and, if necessary, determine
exactly which cells and conditions are affected.
The mismatch alert is another status condition flag that
can be enabled to signal when the minimum and max-
imum cell voltages are mismatched by more than a
programmed amount. The alert is enabled by setting
the ALRMMMTCHEN bit of the ADCCFG register. The
MSMTCH register (address 0x1C) sets the 12-bit thresh-
old for the mismatch alert, ALRTMSMTCH. Whenever
MAXCELL - MINCELL > MSMTCH, the ALRTMSMTCH bit in
the STATUS register is set. The alert bit is cleared when new
conversion data does not violate the threshold condition.
Maximum number of enabled switches = (0.7 x P
)/
MAX
((I
)2 x R
)
BALANCE
SW
where:
I
= V
/((2 x R ) + R
)
BALANCE
CELL
EQ
SW
P
= 1.2698W
MAX
R
= 6I, typical
SW
Table 1 lists example results obtained based on the
formula above.
Cell Balancing
The basic cell-balancing circuit for the MAX11068 incor-
porates the use of internal 6I switches and external
resistors to set an equalization discharge current that is
dependent on cell voltage. Figure 13 shows the basic
circuit used with the internal cell-balancing switches.
CELL BALANCING
MAX11068
F1
F2
R
EQ
EQ
C
N+1
R
C
F
SW
The following limitations must be taken into account
when using the basic circuit:
C
N
R
U Maximum power dissipation allowed in the package
U Measurement during cell balancing
U Current variation due to enabled adjacent cell switches
U Protectirom open-circuit faults in the battery stack
Figure 13. Cell-Balancing Switch Network
destroying the MAX11068
Maxim Integrated
23
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 10 Cell-Balancing Circuit Parameter Variation
HIGH-SIDE
ACCURACY (%)
LOW-SIDE
ACCURACY (%)
CELL NAME
MIN
TYP
MAX
UNITS
R
5.1
9
5.2
10
5.3
11
I
FF
I
1
-1
-10
-50
NA
-23
—
EQ
C
10
50
NA
16
—
—
F
R
SW
3
6
9
V
4.1
308
3435
0.6
4.1
250
3061
0.8
4.1
210
2755
1.1
V
CELL
BALANCE
I
mA
Hz
ms
FILTER
3dB
t
—
SETTLE at C
N+1
(Note 1)
Max No. of Switches On
(Note 2)
3
2
2
Switches
—
—
Note 1: tSETTLE is five time constants after the cell-balancing switch is disabled.
Note 2: Nonadjacent cell switches.
Based on the calculations, up to two nonadjacent inter-
nal cell-balancing enabled switches are supported for
a discharge current of 250mA per cell. At least a 0.5W
F1
F2
R
R
EQ
EQ
C
5
rated R
is required to handle the 250mA nominal cur-
EQ
rent and its worst-case range of 210mA to 308mA.
V
V
C
C
R
R
CELL5
CELL4
F
SW
SW
Measurements During Cell Balancing
When using the internal cell-balancing switches, the
C
C
4
3
measured voltage on the C to C
input is reduced
N
N+1
by the external R
resistors. For accurate cell-voltage
F
EQ
I
DIS
measurements, disabling the internal cell-balancing
switch is required. These switches are not disabled
automatically during a conversion. After the internal cell-
balancing switch is disabled, allow the input voltage to
F3
R
EQ
settle for a time period (t
), which is determined by
SETTLE
external components C and R , before performing a
cell-measurement sequence:
F
EQ
Figure 14. Discharge Current Path for Adjacent Enabled
Balancing Switches
t
= 10 x R x C
EQ F
SETTLE
Current Variation Due to Enabled
Adjacent Cell Switches
If adjacent internal cell-balancing switches are enabled,
the discharge current would be much higher than the
desired value. Figure 14 shows the adjacent enabled bal-
ing proportionally, but R
remains fixed no matter how
EQ
many adjacent switches are active. Consequently, the
numerator of the discharge current equation grows faster
than the denominator with increasing active switch count
and discharge current increases. Unless this is accounted
for by the host controller, the package power-dissipation
limit could be reached unexpectedly and damage to the
device could occur. To avoid this possibility, it is recom-
mended to use an odd or even switch-enable control
scheme for the internal cell-balancing switches.
ancing switches and the resulting discharge current (I ):
DIS
I
= (V
+ V )/(2 x R + (2 x R ))
CELL4 EQ SW
DIS
CELL5
From the I
equation, it is apparent that the discharge
current grows with the number of adjacent active internal
cell-balancing switches. This is because the cell voltages
DIS
across the active switches and the R
values are grow-
SW
24
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
mended to protect the circuit. Typical component values
for a 500mA cell discharge current are (see Figure 16):
Protection from Open-Cell Faults
There are two methods of protecting the MAX11068 from
damage due to an open circuit occurring in a series bat-
tery stack:
R
R
= 80I
= 8I
BIAS
EQ
Bipolar transistor = MJD50 (for high-voltage tolerance) or
U
An external fuse placed in series with the internal or
external cell-balancing circuit protects against high-
voltage damage. If an external MOSFET is used, as in
the circuits described below, the high-value resistors
protect the MAX11068 inputs from damage during an
open-cell condition.
MMBTA05 (for low cost and low volt-
age)
External Cell Balancing with a MOSFET
When using an external MOSFET, it is recommended to
select one with low V
(typically around 1.2V) and a
GS
V
voltage that is rated to the overall pack voltage to
U
Detection of any cell dropping below ground or vio-
lating the undervoltage condition indicates an open-
cell condition and that the electric motor is supplying
voltage to the battery pack. To prevent damage, the
switches connecting the battery stack to the load
should be opened immediately after the undervolt-
age flag asserts.
DS
avoid damage should an open circuit occur in the cell
stack. If a MOSFET with lower voltage rating is chosen,
series fuses are recommended to protect the circuit. See
Figure 17. Typical component values for a 500mA cell
discharge current are:
R
R
R
= 10kI
BIAS1
GATE = 470ω
External Cell-Balancing Circuit
= 8I
EQ
The MAX11068 allows external cell balancing to be
implemented by using the internal switch to control
the bias network of an external transistor. When the
MOSFET = NTK3134N (for low cost, low voltage)
External cell balancing with a MOSFET switch results in
little to no cell-to-cell interaction. The R
resistor value
internal switch is closed, the external resistors R
BIAS
BIAS1
combined with the input bias current requirements does
add a small measurement error of less than 1mV worst
and R
form the bias network used to turn on the
BIAS2
external bipolar or MOSFET transistor. The discharge
case for a 10kω R
current of the battery is set with resistor R . The follow-
BIAS value.
EQ
ing sections describe different external cell-balancing
circuits in more detail. Figure 15 is a simplified external
cell-balancing circuit.
The recommended NTK3134N FETs have built-in gate-
protection diodes. During hot-plug conditions, inrush
current flows through BIAS and internal ESD diodes to
R
charge the HV to DCIN capacitor. This current creates a
negative VGS voltage that can turn on the gate-protec-
tion diodes and possibly damage the transistor devices.
A series resistor of no less than 470ω should be placed
in series with the transistor gate to make the circuit
robust under cell hot-plug conditions. For other transis-
External Cell Balancing with
a Bipolar Transistor
When using an external bipolar transistor, it is recom-
mended to select one with current gain (h ) greater
FE
than 100 and a V
voltage that is rated to the overall
CE
pack voltage to avoid damage should an open circuit
occur in the cell stack. If a bipolar transistor with a lower
voltage rating is chosen, then series fuses are recom-
V
tors, the negative GS condition must be controlled so
that it is tolerated by the devices.
F1
R
BIAS1
C
N+1
R
BIAS1
R
EQ
R
EQ
C
F
R
R
R
SW
GATE
D
CLAMP
BIAS2
C
N
F2
R
BIAS2
Figure 16. External Cell-Balancing Circuit with a Bipolar
Transistor
Figure 15. Simplified External Cell-Balancing Circuit
Maxim Integrated
25
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
F1
R
C
N+1
BIAS1
CBPDIV1 CBPDIV0 BIT 3 BIT 2 BIT 1 BIT 0
R
EQ
ZERO
FLAG
CELL-
C
F
32.768kHz
CBPDIV
CBTIMER
BALANCING
SWITCH [n]
ENABLE
R
GATE
BALCFG [bit n]
D
CLAMP
CBTIMER
ENABLE
F2
R
C
N
BIAS2
Figure 17. External Cell-Balancing Circuit with a MOSFET
Transistor
Figure 18. Cell-Balancing Timer Block Diagram
Table 20 Cell-Balancing Predivider
Settings
Cell-Balancing
Watchdog Timeout
The MAX11068 implements a watchdog-style timeout
feature for the cell-balancing switch enables. A count-
down timer is clocked at a rate specified by a predivider.
The full range of possible timeout values is 0 to 240s. In
the event of unexepected communication loss, the cell-
balancing switches are safely disabled after the timer
reaches zero. The timeout disables the cell switches with
a signal separate from those of the BALCFG register.
Thus, the BALCFG register value is not affected by the
cell-balancing timeout condition. Figure 18 shows the
timeout circuit block diagram.
CBPDIV[1:±]
SETTING
TIMER LSB
PERIOD (s)
TIMER RANGE
(MIN TO MAX) (s)
00
Timer disabled
Timer disabled
01
10
11
1
4
1 to 15
4 to 60
16
16 to 240
the timer is enabled by writing the CBPDIV bits while the
CBTIMER value is at 00h, the cell-balancing switches
are not disabled. The first transition of CBTIMER to the
00h value when the timer is enabled disables the bal-
ancing switches.
The cell-balancing timeout feature consists of a 4-bit
countdown timer and a predivider with 2 control bits
for range selection. Both the timer and predivider are
programmed through the MSB of the ACQCFG register
(address 0x0C). The predivider sets the effective LSB
time period of the timer. The user-selectable choices are
shown in Table 2.
Internal Regulator and
Charge Pump
The MAX11068 incorporates a linear regulator for gen-
erating the internal supply from DCIN. The regulator
can accept a supply voltage on the DCIN pin from 6.0V
to +70V, which it regulates to 3.3V to run the voltage-
measurement system, control logic, and low-side com-
munication interface. The regulator is designed to sup-
ply up to 10mA of current. When the SHDN pin and die
temperature protection are not active and a sufficient
voltage is applied to DCIN, the output of the regulator
becomes active. The regulator is paired with a power-
on POR circuit that senses its output voltage and holds
the MAX11068 in a reset state until the internal supply
has reached a sustainable threshold of +3.0V (Q5%).
The internal comparator has built-in hysteresis that can
handle noise on the supply line, as well as slow sup-
ply ramps of 1V/s. Since secondary metal batteries are
never fully discharged to 0V, the MAX11068 is designed
The cell-balancing timer counts down at the rate speci-
fied by the predivider, CBPDIV[1:0]. The timer starts
when the CBPDIV control bits are written to one of the
three enabled settings. The CBTIMER[3:0] bits are read-
able and writeable and return the value of the timer as
sampled during the acknowledge bit time of the register
address bit of the READALL command. The host appli-
cation should periodically rewrite the ACQCFF register
value to ensure that this value does not unintentionally
go to zero. The timeout can be set to any value within the
timer range specified by the CBPDIV setting by choos-
ing the appropriate value to write to the CBTIMER byte.
If the value of the CBTIMER does reach zero, the cell-
balancing ches are disabled until the timer is either
disabled or is refreshed by writing a nonzero value. If
26
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
for a hot-swap insertion of the battery cells. Once the
POR threshold is reached, the internal RESET signal
disables. A status bit, RSTSTAT in the STATUS register
(address 0x02), is set when power is restored to the
digital logic following a reset event to denote that a reset
has occurred. It should be checked and cleared by the
system controller so that any future reset condition can
be resolved. Figure 19 is the internal low-dropout regula-
tor block diagram.
GND , it switches to a standby mode until the voltage
U
drops by 20mV to minimize operation during light load-
ing. The specification accuracies and full operation of
the MAX11068 are not guaranteed until a minimum of
6.0V is applied to the DCIN pin. The regulator has built-in
short-circuit protection in case of a fault condition. Figure
21 shows asynchronous regulator disable events and
Figure 22 shows the POR event sequence.
The regulator incorporates a thermal-shutdown feature.
If the MAX11068 die temperature rises above +145NC,
the device shuts down by disabling the internal regula-
tor. The cell-balancing switches are also independently
disabled in case an external power source maintains
The MAX11068 power-up sequence is shown in Figure
20. Starting with no DC power applied, the device waits
for a power source and then waits until the SHDN signal
is deactivated. If the internal die temperature limit is
not exceeded, the regulator is enabled. The regulator
begins to regulate the DCIN input voltage down to 3.3V.
After VAA has reached the rising POR threshold, the
internal POR signal is deasserted and the various sec-
tions of the device begin to initialize, starting with the
32kHz oscillator. An additional 280Fs after the oscillator
becomes active, the digital logic becomes active and
the charge pump begins operating. The charge pump
reaches full regulation in approximately 3ms depending
on the external circuit components used, at which time
the MAX11068 is ready for operation. When the charge
power to the digital logic through VDD . The settings
L
of the BALCFG register are not directly altered by the
overtemperature condition, but unless VDD is supplied
L
from a source other than VAA, the POR event caused
by the regulator shutting down resets all registers to
their default values. After a thermal shutdown event, the
die temperature must cool 15NC below the shutdown
temperature before the device reenables the regulator.
Figure 23 shows a more detailed view of the charge
pump and the supply and ground references for the
regulator and charge pump. The charge pump is driven
pump achieves regulation of 3.4V between VDD and
U
by a 4mA current source, I
.
PUMP
INTERNAL +3.4V
+6.0V TO +72V
LINEAR
REGULATOR
DCIN
VAA
GND
U
REGULATOR
ENABLE
CHARGE
PUMP
VDD
U
SHDN
CHARGE-PUMP
ENABLE
20mV
HYSTERESIS
-
DIE OVERTEMP
DETECT
BANDGAP
REFERENCE
+3.4V
TO
+
GND
U
+
INTERNAL
POR +3.0V
THRESHOLD ±±5
POR
-
POWER-ON RESET
COMPARATOR
Figure 19. Inal Low-Dropout Regulator Block Diagram
Maxim Integrated
27
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
REGULATOR
DISABLED
POR CLEARED
32kHz OSCILLATOR
ENABLED
VOLTAGE APPLIED TO
DCIN
280Fs
SHDN
DELAY
ACTIVE
CHECK SHDN
CHARGE PUMP AND
DIGITAL LOGIC
ENABLED
DIE TEMP
> +145°C
CHECK DIE
TEMPERATURE
RSTSTAT BIT
SET
REGULATOR ENABLED
3ms DELAY
VAA <
POR_RISING
CHARGE PUMP
SETTLED
V
CHECK VAA
MAX11068 FULLY
FUNCTIONAL
Figure 20. Power-Up Sequence
DIE TEMP > +145NC
SHDN ACTIVE
REGULATOR
DISABLED
Figure 21. Asynchronous Regulator Disable Events
28
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
POR INACTIVE
VAA >
V
POR_RISING
CHECK VAA
VAA <
V
POR_FALLING
POR ACTIVE
OSCILLATOR, CHARGE
PUMP, DIGITAL
LOGIC DISABLED
Figure 22. Power-On-Reset Event Sequence
HV
SCL
U
UPPER
I C
VDD
U
SDA
U
2
INTERFACE
ALRM
U
CHARGE-
PUMP
CP+
CONTROL
C12
C11
C10
C9
GND
U
MAX11068
P
C8
CP-
C7
DCIN
SHDN
VAA
C6
LDO
C5
VDD
L
L
C4
SCL
C3
N
LOWER
I C
INTERFACE
32kHz
SDA
L
ANALOG
ADC
2
CONTROL
C2
ALRM
GND
L
I
C1
PUMP
L
C0
AGND
Figure 23. Detailed View of Supply and Ground Connections
Maxim Integrated
29
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
DCIN Pin Application Circuit
Auxiliary Analog Inputs and
External Thermistor Supply Pin
The DCIN pin is the input to the linear regulator. For
maximum performance, it should be protected from any
overvoltage conditions and also properly decoupled for
peak transient current demands of the linear regulator.
Figure 24 shows a recommended protection and decou-
pling circuit.
The auxiliary analog inputs (1 and 2) can be used to
monitor analog voltages with a full-scale range of 0 to
THRM (3.4V). The full-scale range of the ADC for the
auxiliary channel measurements is the THRM pin voltage
referenced to AGND. The AUXIN1/2 pins are single-end-
ed inputs that are measured against the AGND pin. A
scan of the AUXIN inputs is first configured by enabling
conversion of one or both inputs through the AIN1EN
and AIN2EN bits of the ADCCFG register (address
0x08). After enabling the channels for measurement,
a scan is initiated by setting the SCAN bit of the
SCANCTRL register to 1. Conversions on the enabled
auxiliary channels commence after the conversions for
the cell input channels are complete. Conversion results
are available in the AIN1 and AIN2 registers (addresses
0x40 and 0x41).
Since the linear regulator must supply load peaks to the
ADC and other low-voltage circuitry, the DCIN pin must
be properly decoupled to ensure proper performance. A
1FF high-voltage, high-quality ceramic capacitor should
be used at the pin. The series diode, D1, prevents dis-
charge of the DCIN decoupling capacitor during nega-
tive transients.
During regenerative braking conditions, a surge voltage
is produced by the electric motor. The MAX11068 is
designed to tolerate an absolute maximum of 80V under
this condition. The MAX11068 should be protected
against higher voltages with an external voltage sup-
pressor such as the SMCJ70A. This protection circuit
also helps to reduce power spikes that can occur during
the insertion of the battery cells.
The AUXIN1/AUXIN2 pins can also be used in con-
junction with the thermal supply pin (THRM) to monitor
external RTD devices. The THRM pin has an internal
switch connected to the internal-voltage regulator of the
MAX11068. The purpose of the switch is to save power
when a measurement of an external temperature-sens-
ing device is not needed. During normal operation, the
THRM pin is disabled. When the AIN1EN or AIN2EN bits
of the ADCCFG register (address 0x08) are enabled and
a measurement scan is initiated, a voltage source taken
from the internal regulator is connected to the THRM pin.
This occurs as soon as the scan signal is received and
before any cell or auxiliary channel measurements have
taken place. The THRM pin biases the RTD network so
that the effect of temperature on the RTD component
can be measured as a voltage by the ADC. Figure 25 is
the external temperature-sensor configuration.
Precision Internal-
Voltage Reference
The MAX11068 incorporates a precision, low-temper-
ature coefficient, internal-voltage reference. The refer-
ence is used in the MAX11068 to set the full-scale range
of the ADC. The REF pin is not designed to drive any
external loads, and should be configured with an exter-
nal 1FF capacitor to AGND only. This capacitor should
be mounted as close as possible to the REF pin.
TO GND
U
INPUT
22I
Since the THRM pin is not driving the AIN pin application
circuit at all times, in some cases it may be necessary to
adjust the settling time seen by the AIN pins before the
measurement is started. A customized delay can be pro-
grammed through the ACQCFG register (address 0x0C)
AINCFG bits to allow the application circuit extra time to
settle before taking the ADC measurement for the AIN
pins. The AINCFG bits have a resolution of 5.3Fs, which
is also the minimum delay value. The maximum delay
is 339.2Fs. The programmed delay from the ACQCFG
register is implemented just before the measurement is
taken on an AIN channel. If both channels are enabled
for measurement, the delay is implemented twice, once
just before each channel’s measurement.
R
LIMIT
TOP OF
CELL STACK
100kI
22I
TO DCIN
INPUT
C
DCIN
1FF
80V
SMCJ70
NOTE: SEE THE APPLICATION CIRCUIT DIAGRAM
FOR THE PROPER KELVIN-CONNECTION LOCATION.
Figure 24. DOvervoltage Protection and Decoupling
Circuit
30
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Care must be taken when selecting the AINCFG settling
auxiliary channel-acquisition cycle begins. First, AUXIN1
is measured, if enabled, followed by AUXIN2, if enabled.
time value if the load on VDD is more than that speci-
U
fied by the typical application circuit diagrams. During
the entire measurement cycle, the charge pump is dis-
Each individual voltage reading from the completed acqui-
sition is stored in the appropriate AIN1 (address 0x40) or
AIN2 (address 0x41) register. Since the ADC is 12 bits
with a full-scale voltage of 3.4V, each LSB is approxi-
mately 0.83mV. Overall, a conversion on the AUXIN1 and/
or AUXIN2 input completes in 10Fs when only one of the
auxiliary inputs are enabled and in 17Fs when both are
enabled. When the result is stored, it is compared against
the under- and overtemperature thresholds saved in reg-
isters 0x1E and 0x1F, respectively.
abled and the VDD voltage is supported only by the
U
decoupling capacitor stored charge. If an extra load is
placed on VDD and the AINCFG value is set too high,
U
the VDD voltage may decay below levels that support
U
error-free communication.
The recommended RTD network is a 10kI resistor in
series with a 10kINTC thermistor. For an NTC thermistor,
the resistance increases as the temperature decreases.
They are typically specified by a resistance at +25NC
Separate alert bits ALRTTHOT and ALRTTCOLD in the
STATUS register (address 0x02) may be enabled to indi-
cate when one of these temperature thresholds has been
violated. Individual over- and undertemperature enables
(HOTEN and COLDEN) for each of the two auxiliary ana-
log channels are found in the AIN1 and AIN2 data reg-
isters. The alert bits are automatically cleared if the alert
condition is cleared on subsequent conversions.
(R ) and also by a factor called beta. To first order, the
0
resistance at a temperature T in Kelvin can be found from:
(β(1/T−1/T ))
0
R = R e
0
A typical value of beta for an NTC thermistor might be
approximately 3400. By determining the resistance of
the thermistor at the desired temperature thresholds,
the voltage at the auxiliary inputs can be calculated.
This voltage can then be converted to a digital threshold
value using the ADC step size of 0.83mV/LSB, whose
derivation follows below.
The overtemperature and undertemperature alarm
enable bits ALRMOTEN and ALRMUTEN found in the
ADCCFG register (address 0x08) determine whether
alerts result in an alarm. When 1 of these bits is enabled,
the respective alert causes an alarm signal to occur on
Once the ADC power-up delay and any cell measurements
and the self-diagnostic measurement have completed, the
the ALRM pin.
L
VAA
C
AA
1FF
FROM
REGULATOR
+3.4V
CONVERSIONS
IN PROGRESS
THRM
CT3
100pF
10kI
1%
AUXIN2
10kI
1%
INTERNAL REFERENCE
RT1
RT2
ADC
REF
AUXIN1
ADC
CT1
100pF
CT2
100pF
t
t
THERMISTOR
10kI AT +25°C
Figure 25. External Temperature-Sensor Configuration
Maxim Integrated
31
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Self-Diagnostics
The MAX11068 incorporates the capability to check
the health of its internal voltage reference and regula-
tor output. The results are stored in the DIAG register.
Conversions are enabled by setting the DIAGEN bit of
THRM
INSTR
AMP
ADC IN +
G = 1/2
the ADCCFG register (address 0x08). They are initiated
immediately following the cell conversions. For the self-
diagnostic measurement, the ADC reference is taken
from the internal THRM pin connection. This makes
the full-scale range of the self-diagnostic measurement
3.4V. The reference voltage is measured differentially
against the internal voltage on C0 through an instrumen-
tation amp, the low-voltage mux, and finally the internal
ADC. The instrumentation amp has a gain of 1/2 that
must be taken into account when calculating the expect-
ed diagnostic result. The complete block diagram for the
self-diagnostic measurement is shown in Figure 26.
12-BIT ADC
LV
MUX
ADC IN -
SELF -
DIAGNOSTIC
REF
C0
Figure 26. Block Diagram of Self-Diagnostic Mode
Connections
The expected value of the self-diagnostic measurement
varies depending on the regulator output voltage, the
reference voltage itself, and the accuracy of the ADC.
When discussing the DIAG measurement values, the
least significant nibble of the DIAG register is ignored
since only the three most significant nibbles contain
real data. To first order, the expected value of the self-
diagnostic measurement is:
ranges for the DIAG value for various fault and no-fault
conditions.
In a typical application, the self-diagnostic measurement
should be performed and stored when the system is
operated for the first time. By periodically performing a
new measurement, the results can be compared against
the original value to verify that the system is operating
at the expected performance level. As shown in Table
2, a change on the order of P 4 LSBs can be expected
across the full temperature range.
DIAG = REF − C0 × 0.5 VAA × 4096
(
)
Since the specified regulator voltage can vary by
approximately Q10%, the expected result of the self-
diagnostic varies proportionally. For typical values of
REF = 2.5V and VAA = 3.4V, the nominal DIAG value for
normal operation is 5E1h with a tolerance of Q150 LSBs
(Q0x96). Typical devices may vary from this value due
to trim differences. Table 3 shows typical values and
The REF pin also has a special failure-mode effects
analysis (FMEA) detector to alert when an open-circuit
may exist. The alert is the ALRTREF bit of the FMEA
register. It detects when the REF pin has an oscillating
voltage condition, which is a symptom of an open circuit
on the pin.
Table 30 DIAG Typical Values and Ranges
VARIATION FROM INITIAL
DIAG VALUE RANGE (TYPICAL)
FAULT CONDITION
DIAG VALUE (TYPICAL)
VALUE (LSB)
None
0x5E1
0x54B to 0x677
0x1DA to 0x1DC
+4 to -4
C0 is open
0x1DA to 0x1DC
0x292 to 0x293
0x3C1 to 0x7AE
—
—
—
REF is shorted to AGND
REF pin is open or floating
0x292 to 0x293
Use ALRTREF in the FMEA register
32
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
This connection can reject noise induced across the
Noise Tolerance
High-power batteries are often used in noisy environ-
bus bar to further improve noise immunity for the I2C
interface. Figure 27 demonstrates how to properly
Kelvin-connect modules for maximum noise immunity.
This method requires careful attention to the mechanical
design of the module, since an extra module terminal
connection is required. DCIN and C12 should not share
a common terminal of a module for Kelvin-connected
modules.
ments subject to high dv/dt supply noise and EMI noise.
For example, the supply noise of a power inverter driving
a high-horsepower motor produces a large square wave
at the battery terminals, even though the battery is also a
high-power battery. Typically, the battery dominates the
task of absorbing this noise, since it is impractical to put
hundreds of farads at the inverter. Supply noise between
two modules occurs due to the very large current
transients that are often present in high-power battery
systems. Even very-low-impedance connections of only
a few milliohms between the various battery modules
and the load can produce substantial voltage noise that
would not allow an AC-coupled ground-referenced I2C
communication system to work reliably. Voltage noise is
also induced through the batteries’ impedance, which
cannot be easily reduced. A unique level-shifting SMBus
ladder communication architecture solves these prob-
lems by referencing the communication signals from
one module to the next from a common voltage that is
shared by both modules. The supply noise seen by the
communication interface is thus greatly reduced and is
then able to be rejected completely in most cases.
TO GROUND
REFERENCE OF
NEXT MODULE
MODULE
N+1
PCK+
GND
U
C12
C11
DCIN
C2
C1
C0
In a typical application of up to approximately 200A to
400A, the GND supply may be connected to the top
U
of the battery stack without the communication path
experiencing adverse affects from bus-bar-induced
noise. In some high-current applications where the
load current is greater than 400A, or the module inter-
connect impedance is more than a couple milliohms,
further precautions may be necessary to ensure optimal
performance. In these cases, the extreme current levels
across even tiny interconnect impedances can result in
AGND
MODULE
N
PCK+
GND
U
C12
C11
DCIN
significant noise due to the GND reference connection.
U
Applications with one or more of the following conditions
may benefit from connecting GND with a Kelvin style:
U
U The bus bar impedance is greater than 1mI to 2mI.
U Battery pack current steps are greater than 400A in
less than 100Fs.
C2
C1
C0
U The RC time constant at cell 12 does not match the
time constant at DCIN.
In applications that meet these conditions, a Kelvin con-
AGND
nection should be made from GND to AGND of the
U
next-higher module. For applications that do not have
these conditions, the Kelvin-style connection is optional.
Figure 27. Module-to-Module DCIN Kelvin Connection
Maxim Integrated
33
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Register Map
2
Table 40 I C Register Map
REGISTER
ADDRESS
REGISTER
NAME
POR
STATE
R/W
R
DESCRIPTION
MANAGEMENT FUNCTIONS
Contains coded information corresponding to the device model
number and die version, where n is the least significant byte denot-
ing the die revision code.
0x00
0x01
VERSION
ADDRESS
0x068
A read of this register returns the I2C address of the device and the
device address of the last device in the SMBus ladder. Perform a
ROLLCALL command (special case of READALL) to this address to
determine the number of devices in the stack.
R/W
0x1FA0
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
STATUS
ALRTCELL
ALRTOVCELL
ALRTUVCELL
ALRTOVEN
ALRTUVEN
ADCCFG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read for status flags; write 0s to clear status flags.
Read for cell-alert status flags.
0x8000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Read for overvoltage cell-alert status flags.
Read for undervoltage cell-alert status flags.
Overvoltage cell-alert enables for cells 1–12.
Undervoltage cell-alert enables for cells 1–12.
Aux channel enable, alarm enable, and scan control.
Cell measurement enable.
CELLEN
GPIO
GPIO2 to GPIO0 configuration.
BALCFG
Cell-balancing switch control.
Acquisition time control configuration register for the auxiliary analog
inputs.
0x0C
ACQCFG
R/W
0x0000
0x0D
0x0E
SCANCTRL
FMEA
R/W
R/W
Measurement scan control.
0x0000
0x0000
Failure-mode effects analysis status and control.
BROADCAST
ADDRESS
0x0F
R/W
Broadcast address.
0x0040
34
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
2
Table 40 I C Register Map (continued)
REGISTER
ADDRESS
REGISTER
NAME
POR
STATE
R/W
DESCRIPTION
SUMMARY AND ALERT FUNCTIONS
0x10
0x11
0x12
TOTAL
R
R
R
Result for a sum total of all CELL measurements in the scan.
N
0x0000
0x000F
0x000F
MAXCELL
MINCELL
Result for the highest/maximum cell voltage measured during the scan.
Result for the lowest/minimum cell voltage measured during the scan.
Overvoltage clear
threshold
When any ADC cell conversion is completed,
the value is compared with OVTHRSET,
OVTHRCLR, UVTHRSET, and UVTHRCLR.
The difference between UVTHRSET and
UVTHRCLR or OVTHRSET and OVTHRCLR
is effectively a digital hysteresis for the alert
threshold. If:
0x18
0x19
0x1A
OVTHRCLR
OVTHRSET
UVTHRSET
R/W
R/W
R/W
0xFFF0
0xFFF0
0x0000
Overvoltage set
threshold
Undervoltage set
threshold
CELL > OVTHRSET or CELL < UVTHRSET
N
N
The corresponding alert bits are set. The over-
voltage alert bit is cleared when:
CELL < OVTHRCLR
N
The undervoltage alert bits are cleared when:
CELL > UVTHRCLR
N
Undervoltage
clear
threshold
0x1B
0x1C
UVTHRCLR
R/W
0x0000
When a scan of conversions is completed, a
mismatch alert is generated if the result of:
MAXCELL - MINCELL > MSMTCH
Set MSMTCH = 0xFFFF to disable mismatch
alerts.
Cell mismatch
threshold
MSMTCH
R/W
0xFFF0
0x1E
0x1F
AINOT
AINUT
R/W
R/W
Auxiliary input overtemperature threshold.
Auxiliary input undertemperature threshold.
0x0000
0xFFF0
MEASUREMENTS
0x20
CELL1
CELL2
CELL3
CELL4
CELL5
CELL6
CELL7
CELL8
CELL9
CELL10
CELL11
CELL12
AIN1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Result for ADC conversion of C1.
Result for ADC conversion of C2.
Result for ADC conversion of C3.
Result for ADC conversion of C4.
Result for ADC conversion of C5.
Result for ADC conversion of C6.
Result for ADC conversion of C7.
Result for ADC conversion of C8.
Result for ADC conversion of C9.
Result for ADC conversion of C10.
Result for ADC conversion of C11.
Result for ADC conversion of C12.
Result for ADC conversion of AUXIN1.
Result for ADC conversion of AUXIN2.
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x40
0x41
AIN2
Result for ADC conversion for the diagnostic front-end test (used for
self-test).
0x44
DIAG
R
0x0000
Maxim Integrated
35
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Register Descriptions
The MAX11068 contains 38 registers that control and report the operational status of the device (see Tables 5
through 34).
Table ꢀ0 VERSION—IC Version Register Description (Address ±x±±)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
FUNCTION
0
0
0
0
0
1
MAX11068 model number designator, 0x068
1
0
D8
D7
1
D6
0
D5
0
D4
0
D3
VER3
VER2
VER1
VER0
D2
MAX11068 mask revision version number; Revision 3.0 = 0x7h
D1
D0
Table 60 ADDRESS Register Description (Address ±x±1)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
FUNCTION
0
0
Write ignored; read back 0.
0
LA4
LA3
LA2
LA1
LA0
1
The last address bits are used to support the SMBus ladder alarm feature and the error-
checking bytes of the READALL command. These bits are set by the SETLASTADDRESS
command and correspond to the A[4:0] device address bits of the last device in the chain.
Once properly set in all nodes, the alarm heartbeat function begins.
D8
D7
Write ignored; read back 1.
Write ignored; read back 0.
D6
0
D5
A0
A1
A2
A3
A4
0
I2C device address. A0 is the LSB. The first A[0:4] device address in the SMBus ladder is
set with the HELLOALL command. The HELLOALL command is then propagated up the
SMBus ladder and automatically incremented for each device, up to a maximum of 31
nodes. This gives each device a unique A[0:4] address.
D4
D3
D2
D1
D0
Write ignored; read back 0.
36
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 70 STATUS Register Description (Address ±x±2)
BIT
NAME
FUNCTION
Reset Status:
RSTSTAT = 1 after a power-reset event. Clear RSTSTAT to 0 after power-up and after a suc-
cessful HELLOALL command to detect any future resets. Writing a 1 to this bit has no effect.
PEC errors should be ignored until this bit is cleared.
D15
RSTSTAT
Cell Overvoltage Alert:
ALRTOV = 1 when a corresponding overvoltage has occurred. Check the ALRTOVCELL reg-
ister to determine which cell is responsible. This is a read-only bit. All voltage alerts are auto-
matically cleared when the next conversion occurs and the alert condition disappears.
D14
D13
D12
ALRTOV
ALRTUV
Cell Undervoltage Alert:
ALRTUV = 1 when a corresponding undervoltage has occurred. Check the ALRTUVCELL reg-
ister to determine which cell is responsible. This is a read-only bit. All voltage alerts are auto-
matically cleared when the next conversion occurs and the alert condition disappears.
Mismatch Alert:
ALRTMSMTCH = 1 when MAXCELL - MINCELL > MSMTCH threshold: This is a read-only bit.
All voltage alerts are automatically cleared when the next conversion occurs and the alert con-
dition disappears.
ALRTMSMTCH
Undertemperature Alert:
Set when AIN1 > AINUT or AIN0 > AINUT. This is a read-only bit. All temperature alerts are
automatically cleared when the next conversion occurs and the alert condition disappears. The
comparison with AINUT assumes an NTC thermistor is used as part of the suggested applica-
tion circuit.
D11
D10
D9
ALRTTCOLD
ALRTTHOT
ALRTPEC
Overtemperature Alert:
Set when AIN1 < AINOT or AIN0 < AINOT. This is a read-only bit. All temperature alerts are
automatically cleared when the next conversion occurs and the alert condition disappears. The
comparison with AINOT assumes an NTC thermistor is used as part of the suggested applica-
tion circuit.
Packet Error Check Alert:
Indicates a communication failure occurred due to a slave or master PEC error. The PEC is a
CRC-8 error check byte, calculated on all message bytes except the ACK, NACK, START, and
STOP bits. The ALRTPEC bit must be cleared by writing a 0 to this bit location to detect future
PEC failures. Writing a 1 to this bit has no effect.
Acknowledge Communication Alert:
Indicates a communication fault due to an unexpected slave or master NACK in the ACK/
NACK bit position. ALRTACK must be cleared by writing this bit to 0 to detect future NACK
events. Writing a 1 to this bit has no effect.
D8
D7
ALRTACK
FMEA Status Alert:
ALRTFMEA
Indicates that there is an FMEA alert. This bit is the logical OR of the alert bits in the FMEA reg-
ister. Check the FMEA register to determine which alerts are active.
Maxim Integrated
37
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 70 STATUS Register Description (Address ±x±2) (continued)
BIT
D6
D5
D4
D3
D2
NAME
FUNCTION
0
0
0
0
0
Write ignored; read back 0.
AIN1 Fault:
Indicates a fault condition (over- or undertemperature) was detected on the AIN1 analog input.
A fault occurs when the AIN1 input exceeds the set levels in the AINOT and AINUT registers.
This bit is cleared automatically when the alert condition disappears following a new measure-
ment. Writing a 1 to this bit has no effect.
D1
D0
ALRTAIN2
ALRTAIN1
AIN0 Fault:
Indicates a fault condition (over- or undertemperature) was detected on the AIN0 analog input.
A fault occurs when the AIN0 input exceeds the set levels in the AINOT and AINUT registers.
This bit is cleared automatically when the alert condition disappears following a new measure-
ment. Writing a 1 to this bit has no effect.
Table 80 ALRTCELL—Per-Cell Alert Status Register Description (Address ±x±3)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
FUNCTION
0
0
Write ignored; read back 0.
0
0
ALRTCELL12
ALRTCELL11
ALRTCELL10
ALRTCELL9
ALRTCELL8
ALRTCELL7
ALRTCELL6
ALRTCELL5
ALRTCELL4
ALRTCELL3
ALRTCELL2
ALRTCELL1
D8
Alert Cell Fault:
D7
ALRTCELL is set when the corresponding cell is overvoltage or undervoltage. The
N
D6
register bits are the logical OR of the corresponding ALRTOVCELL and ALRTUVCELL
register bits. All voltage alerts are automatically cleared when the alert condition dis-
appears.
D5
D4
D3
D2
D1
D0
38
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 90 ALRTOVCELL—Per-Cell Overvoltage Alert Register Description (Address
±x±4)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
0
FUNCTION
0
Write ignored; read back 0.
0
0
ALRTOV12
ALRTOV11
ALRTOV10
ALRTOV9
ALRTOV8
ALRTOV7
ALRTOV6
ALRTOV5
ALRTOV4
ALRTOV3
ALRTOV2
ALRTOV1
D8
D7
Alert Cell Overvoltage Fault:
D6
ALRTOV[N] bits are set when the corresponding cell is overvoltage. All voltage alerts are
automatically cleared when the alert condition disappears.
D5
D4
D3
D2
D1
D0
Table 1±0 ALRTUVCELL—Per-Cell Undervoltage Alert Register Description (Address
±x±ꢀ)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
0
FUNCTION
0
Write ignored; read back 0.
0
0
ALRTUV12
ALRTUV11
ALRTUV10
ALRTUV9
ALRTUV8
ALRTUV7
ALRTUV6
ALRTUV5
ALRTUV4
ALRTUV3
ALRTUV2
ALRTUV1
D8
D7
Alert Cell Undervoltage Fault:
D6
ALRTUV[N] bits are set when the corresponding cell is undervoltage. All voltage alerts are
automatically cleared when the alert condition disappears.
D5
D4
D3
D2
D1
D0
Maxim Integrated
39
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 110 ALRTOVEN—Per-Cell Overvoltage Alert Enable Register Description (Address
±x±6)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
FUNCTION
0
0
Write ignored; read back 0.
0
0
OVALRTEN12
OVALRTEN11
OVALRTEN10
OVALRTEN9
OVALRTEN8
OVALRTEN7
OVALRTEN6
OVALRTEN5
OVALRTEN4
OVALRTEN3
OVALRTEN2
OVALRTEN1
D8
Overvoltage Cell-Alert Enable:
D7
Overvoltage alert enable bits for cells 1–12. Set the corresponding bit to enable alert
notification for overvoltage events on that cell input. Set to 0 to disable alarm notification
for a cell or to clear the associated cell alarm. Alert notification is not affected by the
status of the alarm enable bits. This alert enable bit for each cell is also accessible
through bit 1 of the CELLEN register.
D6
D5
D4
D3
D2
D1
D0
Table 120 ALRTUVEN—Per-Cell Undervoltage Alert Enable Register Description
(Address ±x±7)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
FUNCTION
0
0
Write ignored; read back 0.
0
0
UVALRTEN12
UVALRTEN11
UVALRTEN10
UVALRTEN9
UVALRTEN8
UVALRTEN7
UVALRTEN6
UVALRTEN5
UVALRTEN4
UVALRTEN3
UVALRTEN2
UVALRTEN1
D8
Undervoltage Cell Alert Enable:
D7
Undervoltage alert enable bits for cells 1–12. Set the corresponding bit to enable alarm
notification for undervoltage alerts on that cell input. Set to 0 to disable alarm notification
for a cell or to clear the associated cell alarm. Alert notification is not affected by the
status of the alarm enable bits. This alert enable bit for each cell is also accessible
through bit 0 of the CELLEN register.
D6
D5
D4
D3
D2
D1
D0
40
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 130 ADCCFG—ADC Configuration Register Description (Address ±x±8)
BIT
NAME
FUNCTION
Start conversions scan set with 1 to initiate an ADC scan of the enabled cell channels. A
new measurement scan is initiated as long as the ADC is not busy with a previous scan.
Otherwise, the scan start is ignored. This bit always reads back 0.
D15
SCAN
The SCAN bit of the SCANCTRL register has the same function and is the recommended
register control for initiating a scan.
Voltage Mismatch Alarm Enable Mask:
D14
D13
D12
D11
D10
D9
ALRMMMTCHEN
ALRMOVEN
ALRMUVEN
ALRMUTEN
ALRMOTEN
ALRMPEC
Set ALRMMMTCHEN = 1 to force a mismatch alert, ALRTMSMTCH, to generate an alarm.
Set ALRMMMTCHEN = 0 to prevent a mismatch alert from generating an alarm.
Overvoltage Alarm Enable Mask:
Set ALRMOVEN = 1 to force an overvoltage alert, ALRTOV, to generate an alarm. Set
ALRMOVEN = 0 to prevent an overvoltage alert from generating an alarm.
Undervoltage Alarm Enable Mask:
Set ALRMUVEN = 1 to force an undervoltage alert, ALRTUV, to generate an alarm. Set
ALRMUVEN = 0 to prevent an undervoltage alert from generating an alarm.
Undertemperature Alarm Enable Mask:
Set ALRMUTEN = 1 to force an undertemperature alert, ALRTTCOLD, to generate an alarm.
Set ALRMUTEN = 0 to prevent an undertemperature alert from generating an alarm.
Overtemperature Alarm Enable Mask:
Set ALRMOTEN = 1 to force an overtemperature alert, ALRTTHOT, to generate an alarm. Set
ALRMOTEN = 0 to prevent an overtemperature alert from generating an alarm.
Packet-Error Check (PEC) Alarm Enable Mask:
Set ALRMPEC = 1 to force a packet-error check alert, ALRTPEC, to generate an alarm. Set
ALRMPEC = 0 to prevent a packet-error check alert from generating an alarm.
Acknowledge Communication Fault Alarm Enable:
Set ALRMACK = 1 to force an acknowledge communication fault alert, ALRTACK, to
generate an alarm. Set ALRMACK = 0 to prevent an acknowledge communication check
alert from generating an alarm.
D8
ALRMACK
D7
D6
D5
Unused
Unused
Unused
Unused Bit:
Reads back written value.
Self-Test Diagnostic Enable:
D4
DIAGEN
Enable reference channel diagnostic conversion. Used for internal diagnostic self-test. Set
to 1 to enable the measurement to occur during the measurement cycle.
D3
D2
Unused
Unused
Unused Bit:
Reads back written value.
AUXIN2 Channel Conversion Enable:
D1
D0
AIN2EN
AIN1EN
Enables a conversion on the AUXIN2 input. After a conversion is completed, the results are
compared to the over- and undertemperature thresholds.
AUXIN1 Channel Conversion Enable:
Enables a conversion on the AUXIN1 input. After a conversion is completed, the results are
compared to the over- and undertemperature thresholds.
Maxim Integrated
41
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 140 CELLEN—Cell-Scan Enable Register Description (Address ±x±9)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
0
0
Write ignored; read back 0.
0
0
CELL12EN
CELL11EN
CELL10EN
CELL9EN
CELL8EN
CELL7EN
CELL6EN
CELL5EN
CELL4EN
CELL3EN
CELL2EN
CELL1EN
D8
D7
Cell Channel Scan Enable:
D6
Set the cell enable bit to 1 to enable the corresponding channel in the measurement cycle.
Set to 0 to disable a cell measurement for a scan. Disabled channels do not have their
measurement values changed by a scan.
D5
D4
D3
D2
D1
D0
Table 1ꢀ0 GPIO—General-Purpose I/O Register Description (Address ±x±A)
BIT
NAME
FUNCTION
Unused Bit:
Reads back written value.
D15
Unused
D14
D13
DIR2
DIR1
Input/Output Direction:
Write the DIR bits to 1 to set the GPIO pin drivers to output. Write the DIR bits to 0 to set the
drivers as a high-impedance input. The bits default to a 0 and the high-impedance input
state.
D12
D11
DIR0
Unused Bit:
Reads back written value.
Unused
D10
D9
D8
D7
D6
D5
D4
GPIO2
GPIO Pin Logic State:
GPIO1
When reading this byte, the GPIO[N] bits always return the logic state of each GPIO pin.
GPIO0
0
0
0
0
Write ignored; reads 0.
Unused Bit:
Reads back written value.
D3
Unused
D2
D1
D0
GPIO2OUT
GPIO1OUT
GPIO0OUT
The GPIO[N]OUT bits configure the GPIO pin output driver-logic level. These bits only
determine the driver state when the driver is set to be an output by the DIR bits and have
no affect on the GPIO pins if the DIR bits are set to the input state.
42
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 160 BALCFG—Cell-Balancing Configuration Register Description (Address ±x±B)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
0
FUNCTION
0
Write ignored; read back 0.
0
0
BAL12
BAL11
BAL10
BAL9
BAL8
BAL7
BAL6
BAL5
BAL4
BAL3
BAL2
BAL1
D8
Cell-Balancing/Discharge Switch Enable:
Select cell-balancing/discharge switches to activate. Set BAL[N] to 1 to enable the cell-
balancing switch between C and C Clearing to 0 disables the balancing/discharge
switch. The switches are separately disabled by signals from the die overtemperature
detection circuit and the cell-balancing watchdog timer.
D7
D6
N-1
N.
D5
D4
D3
D2
D1
D0
Table 170 ACQCFG—Acquisition Configuration Register Description (Address ±x±C)
BIT
D15
D14
NAME
FUNCTION
0
0
Write ignored; read back 0.
Cell-Balancing Timer Predivider:
D13
D12
CBPDIV1
CBPDIV0
Sets the step size of the cell-balancing timer LSB.
00 = Disabled, no timeout for the cell-balancing switch on-time.
01 = 1s; timer range is then 1s to15s.
10 = 4s; timer range is then 4s to 60s.
11 = 16s; timer range is then 16s to 240s.
Cell-Balancing Timer:
D11
D10
D9
CBTIMER3
CBTIMER2
CBTIMER1
CBTIMER0
Acts as a safety watchdog timeout for the cell-balancing switches. The timer counts down
at a rate set by the CBPDIV bits. When the timer reaches 0, all cell-balancing switches are
disabled. The timer should be periodically rewritten with a timeout value to keep the cell-
balancing switches enabled. When the timer value is read, the value reported is latched
during the 9th bit time following the ACQCFG register address of the READALL command.
D8
D7
D6
0
0
Write ignored; read back 0.
Maxim Integrated
43
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 170 ACQCFG—Acquisition Configuration Register Description (Address ±x±C)
(continued)
BIT
D5
D4
D3
D2
D1
D0
NAME
FUNCTION
AINCFG5
AINCFG4
AINCFG3
AINCFG2
AINCFG1
AINCFG0
Auxiliary Analog Input-Acquisition Time Configuration:
Custom acquisition settling time for AUXIN1/AUXIN2. The auxiliary analog channels
acquisition settling time can be set from 5.3Fs up to 339.2Fs with a count increment of 5.3Fs/
count. This is to allow extra settling time if the application circuit requires it since the THRM
pin becomes active only during the measurement sequence.
AINCFG default is 0x000, which equals an acquisition time of 5.3Fs. The full settling time is
added prior to the measurement for each enabled auxiliary channel.
Table 180 SCANCTRL—Measurement Scan Control Register Description (Address
±x±D)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
FUNCTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write ignored; read back 0.
D8
D7
D6
D5
D4
D3
D2
D1
Start Conversions Scan:
Set to 1 to initiate an ADC scan of the enabled cell channels. A new measurement scan is
initiated as long as the ADC is not busy with a previous scan. Otherwise, the scan signal is
ignored. This bit always reads back 0.
D0
SCAN
44
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 190 FMEA—Failure-Mode Effects Analysis Status and Control Register
Description (Address ±x±E)
BIT
NAME
FUNCTION
Charge-Pump Undervoltage Alarm Enable Mask:
D15
ALRMCPUV
Set ALRMCPUV = 1 to force a charge-pump alert, ALRTCPUV, to generate an alarm. Set ALRMCPUV
= 0 to prevent a charge-pump alert from generating an alarm.
Heartbeat Frequency Alarm Enable Mask:
D14
D13
D12
ALRMHBEAT
Unused
Set ALRMHBEAT = 1 to force a heartbeat frequency alert, ALRTHBEAT, to generate an alarm. Set
ALRMHBEAT = 0 to prevent a heartbeat frequency alert from generating an alarm.
Unused Bit:
Reads back written value.
REF Pin Open-Circuit Alarm Enable Mask:
Set ALRMREF = 1 to force a REF pin open-circuit alert, ALRTREF, to generate an alarm. Set
ALRMREF = 0 to prevent a REF pin open-circuit alert from generating an alarm.
ALRMREF
Unused Bit:
Reads back written value.
D11
D10
Unused
Unused
Unused Bit:
Reads back written value.
VDDL Open-Circuit Alarm Enable Mask:
D9
D8
ALRMVDDL
ALRMGNDL
Set ALRMVDDL = 1 to force a VDD open-circuit alert, ALRTVDDL, to generate an alarm. Set
L
ALRMVDDL = 0 to prevent a VDD open-circuit alert from generating an alarm.
L
GND Open-Circuit Alarm Enable Mask:
L
Set ALRMGNDL = 1 to force a GND open-circuit alert, ALRTGNDL, to generate an alarm. Set
L
ALRMGNDL = 0 to prevent a GND open-circuit alert from generating an alarm.
L
Charge-Pump Undervoltage Alert:
Indicates that the charge-pump output voltage has fallen below the undervoltage threshold V
This bit is not set before the RSTSTAT bit is cleared. Writing a 1 to this bit has no effect. This bit must
be written to 0 to clear the alert condition.
.
CPUV
D7
ALRTCPUV
Heartbeat Frequency Alert:
Indicates that the alarm heartbeat signal has a frequency error of more than ±12.5% relative to the
32.768kHz oscillator divided by 2. This bit is not set before the RSTSTAT bit is cleared. Writing a 1 to
this bit has no effect. This bit must be written to 0 to clear the alert condition.
D6
D5
ALRTHBEAT
Unused
Unused Bit:
Reads back written value.
REF Pin Open-Circuit Alert:
Indicates that the REF pin is oscillating, most likely due to a missing decoupling capacitor or open-
circuit condition. The detection test occurs just after a valid measurement scan is initiated. After each
ADC strobe, there is a time of 4/32kHz where logic transitions are counted. ALRTREF is set for four
positive transitions. If there are no strobes, ALRTREF cannot be set.
D4
ALRTREF
D3,
D2
Unused Bit:
Reads back written value.
Unused
VDD Pin Open-Circuit Alert:
L
D1
D0
ALRTVDDL
Indicates that an open circuit is detected on the VDD pin. This bit is not set before the RSTSTAT bit
L
is cleared. Writing a 1 to this bit has no effect. This bit must be written to 0 to clear the alert condition.
GND Pin Open-Circuit Alert:
L
ALRTGNDL
Indicates that an open circuit is detected on the GND pin. This bit is not set before the RSTSTAT bit
L
is cleared. Writing a 1 to this bit has no effect. This bit must be written to 0 to clear the alert condition.
Maxim Integrated
45
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 2±0 BROADCAST ADDRESS—Broadcast Address Register Description (Address
±x±F)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
FUNCTION
0
0
0
0
Write ignored; read back 0.
0
0
0
D8
0
D7
BRDCST7
BRDCST6
BRDCST5
BRDCST4
BRDCST3
BRDCST2
BRDCST1
BRDCST0
D6
D5
Broadcast Address:
D4
This byte contains the communication bus broadcast address. The LSB, BRDCST0, is not
used and can be considered a don’t care. The default is 0040h.
D3
D2
D1
D0
Table 210 TOTAL—Total Cell Voltages Data Register Description (Address ±x1±)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
SUM15
SUM14
SUM13
SUM12
SUM11
SUM10
SUM9
SUM8
SUM7
SUM6
SUM5
SUM4
SUM3
SUM2
SUM1
SUM0
FUNCTION
D8
16-bit sum total value of all cells enabled in the measurement scan.
D7
D6
D5
D4
D3
D2
D1
D0
46
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 220 MAXCELL—Maximum Cell Reading Register Description (Address ±x11)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
FUNCTION
D8
D7
D6
12-bit ADC conversion result of the highest cell-voltage reading.
D5
D8
D4
D7
D3
D6
D2
D5
D1
D4
D0
D3
CH3
CH2
CH1
CH0
D2
Cell number of the maximum cell voltage acquired. If multiple cells have the same maximum
value, this field contains the highest cell number with that measurement.
D1
D0
Table 230 MINCELL—Minimum Cell Reading Register Description (Address ±x12)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
FUNCTION
D8
D7
D6
12-bit ADC conversion result of the lowest cell-voltage reading.
D5
D8
D4
D7
D3
D6
D2
D5
D1
D4
D0
D3
CH3
CH2
CH1
CH0
D2
Cell number of the minimum cell voltage acquired. If multiple cells have the same minimum
value, this field contains the highest cell number with that measurement.
D1
D0
Maxim Integrated
47
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 240 OVTHCLR—Overvoltage Clear Threshold Register Description (Address ±x18)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FUNCTION
12-bit limit for the reset threshold of overvoltage-alert detection. An alert that is issued when
the overvoltage set threshold is exceeded by a cell voltage is not cleared until the voltage falls
below this lower threshold. The overvoltage alert is updated on each new measurement scan of
the cell voltages by comparing against the threshold values. This alert-clearing threshold builds
in digital hysteresis to the overvoltage detection.
D8
D7
D6
D5
D4
D3
D2
0
Write ignored; read back 0.
D1
0
D0
0
Table 2ꢀ0 OVTHRSET—Overvoltage Set Threshold Register Description (Address ±x19)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FUNCTION
12-bit limit for the triggering threshold of overvoltage-alert detection. An alert for a given cell is
issued when this set threshold is exceeded by the cell voltage and the alert is not cleared until
the cell voltage falls below the clear threshold. The overvoltage alert is updated on each new
measurement scan of the cell voltages by comparing against the overvoltage threshold values.
This alert setting threshold is a critical maximum cell-voltage level.
D8
D7
D6
D5
D4
D3
D2
0
Write ignored; read back 0.
D1
0
D0
0
48
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 260 UVTHRSET—Undervoltage Set Threshold Register Description (Address
±x1A)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FUNCTION
12-bit limit for the triggering threshold of undervoltage-alert detection. An alert for a given cell
is issued when the cell voltage falls below this set threshold and the alert is not cleared until
the cell voltage rises above the clear threshold. The undervoltage alert is updated on each
new measurement scan of the cell voltages by comparing against the undervoltage threshold
values. This alert-setting threshold is a critical minimum cell-voltage level.
D8
D7
D6
D5
D4
D3
D2
0
Write ignored; read back 0.
D1
0
D0
0
Table 270 UVTHRCLR—Undervoltage Clear Threshold Register Description (Address
±x1B)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FUNCTION
12-bit limit for the reset threshold of undervoltage-alert detection. An alert that is issued
when the undervoltage set threshold is tripped by a cell voltage is not cleared until the voltage
rises above this clearing threshold. The undervoltage alert is updated on each new measure-
ment scan of the cell voltages by comparing against the threshold values. This alert-clearing
threshold builds in digital hysteresis to the undervoltage detection.
D8
D7
D6
D5
D4
D3
D2
0
Write ignored; read back 0.
D1
0
D0
0
Maxim Integrated
49
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 280 MSMTCH—Cell Mismatch Threshold Register Description (Address ±x1C)
BIT
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FUNCTION
12-bit threshold limit for mismatch alert. If:
MAXCELL - MINCELL > MSMTCH
then the ALRTMSMTCH alert bit in the STATUS register is set. If the MSMTCH threshold is
set to 0xFFF0, no alert is possible; this immediately clears the alert status. For all other
MSMTCH threshold value changes, the alert status does not change until after the next
measurement scan.
D8
D7
D6
D5
D4
D3
D2
0
Write ignored; read back 0.
D1
0
D0
0
Table 290 AINOT—Auxiliary Analog Input Overtemperature Threshold Register
Description (Address ±x1E)
PIN
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FUNCTION
12-bit threshold limit for an undervoltage alert on the AUXIN1 and AUXIN2 inputs. When the
auxiliary analog inputs are used with an NTC thermistor as part of the recommended circuit,
this register can be used to store the overtemperature threshold. This threshold may also be
used as a general undervoltage trip point for the auxiliary inputs. The ALRTTHOT bit in the
STATUS register is set if:
AIN1 OR AIN± < AINOT
D8
The polarity of this comparison assumes that an NTC thermistor is used in the application
circuit.
D7
D6
D5
D4
D3
D2
0
Write ignored; read back 0.
D1
0
D0
0
50
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 3±0 AINUT—Auxiliary Analog Input Undertemperature Threshold Register
Description (Address ±x1F)
PIN
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FUNCTION
12-bit threshold limit for an overvoltage alert on the AIN0 and AIN1 inputs. When the auxiliary
analog inputs are used with an NTC thermistor as part of the recommended circuit, this register
can be used to store the undertemperature threshold. This threshold may also be used as a
general overvoltage trip point for the auxiliary inputs. The ALRTTCOLD bit in the STATUS register
is set if:
D8
AIN1 OR AIN2 > AINUT
D7
The polarity of this comparison assumes that an NTC thermistor is used in the application circuit.
D6
D5
D4
D3
D2
0
Write ignored; read back 0.
D1
0
D0
0
Table 310 CELLN Data Register Description (Addresses ±x2± to ±x2B)
PIN
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FUNCTION
12-bit ADC conversion result from CELL .
N
D8
D7
D6
D5
D4
D3
Write ignored; read back 0.
Write ignored; read back 0.
D2
0
Enable overvoltage alerts for this cell channel:
Maps to the ALRTOV(N-1) bit.
D1
D0
OVEN
UVEN
Enable undervoltage alerts for this cell channel:
Maps to the ALRTUV(N-1) bit.
Maxim Integrated
51
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 320 AIN1—Auxiliary Analog Input 1 Data Register Description (Address ±x4±)
PIN
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
FUNCTION
D8
D7
D6
12-bit ADC conversion result on the AUXIN1 channel.
D5
D8
D4
D7
D3
D6
D2
D5
D1
D4
D0
D3
0
Write ignored; read back 0.
D2
0
Write ignored; read back 0.
D1
COLDEN
HOTEN
Enable undertemperature or overvoltage alerts for this channel.
Enable overtemperature or undervoltage alerts for this channel.
D0
Table 330 AIN2—Auxiliary Analog Input 2 Data Register Description (Address ±x41)
PIN
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
FUNCTION
D8
D7
D6
12-bit ADC conversion result on the AUXIN2 channel.
D5
D8
D4
D7
D3
D6
D2
D5
D1
D4
D0
D3
0
Write ignored; read back 0.
D2
0
Write ignored; read back 0.
D1
COLDEN
HOTEN
Enable undertemperature or overvoltage alerts for this channel.
Enable overtemperature or undervoltage alerts for this channel.
D0
52
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 340 DIAG—Diagnostic Data Register Description (Address ±x44)
PIN
D15
D14
D13
D12
D11
D10
D9
NAME
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FUNCTION
12-bit ADC conversion result on the diagnostic data value. This diagnostic tests the toler-
ance of the reference, the stability of the internal regulator, and the open/short status of cell
input C0. The converter delivers the data value based on the following formula:
DIAG = ((REF - C±) x ±0ꢀ)/VAA x 4±96
The nominal value for normal operation is 5E1h with a tolerance of Q150 LSBs. The REF
open case also has a special FMEA detector that has a separate alert, ALRTREF, in the
FMEA register.
D8
D7
D6
D5
D4
D3
D2
0
Write ignored; read back 0.
D1
0
D0
0
the need for costly and complex galvanic isolation of
the communication lines while providing very-high-noise
rejection.
2
I C Interface
Overview
The MAX11068 uses an SMBus ladder I2C physical
interface with customized I2C command protocol to
communicate with the host system and from module
to module. Each device contains two I2C ports, one
master and one slave. The slave port is the lower port,
referenced to the chip ground, and communicates with
the host master or the master from a device lower on the
SMBus ladder. The upper port is a master port that is
2
I C Physical Interface Operation
The physical I2C interface for each MAX11068 device
consists of a master block and a slave block. The master
block is level shifted and referenced to the GND sup-
U
ply voltage. A digital controller manages each block and
coordinates the passing of commands and data between
the two as needed. The two standard I2C interface pins
for all ports are SCL for the serial data clock and SDA for
the serial data line. Additional status pins used to com-
plement the I2C communication in the MAX11068 are the
level shifted and referenced to GND . It drives commu-
U
nication with devices higher on the SMBus ladder and
gathers information to be passed back toward the host.
The two ports act together with the help of a digital con-
troller to bridge two separate links of the SMBus ladder.
Each link between master and slave of interconnected
MAX11068 devices can be thought of as its own bus
under the control of the master side device. A standard
I2C hardware master found in many microcontrollers or a
master implemented with firmware and general-purpose
I/O pins is all that is required to successfully implement
the physical communication bus. This level-shifted dual-
port scheme allows modules to be easily stacked without
ground-referenced ALRM output and the level-shifted
L
ALRM input. These pins act as an SMBus-laddered
U
interrupt signal that the host can use to determine the
health of the bus. To support the level-shifted I/O pins, a
level-shifted supply, VDD , is generated by an internal
U
charge pump and referenced to GND This supply
U.
provides a pullup voltage to the level-shifted bus com-
munication signals. Figure 28 shows the simplified view
of the I2C physical interface from the perspective of the
first device in an SMBus ladder.
Maxim Integrated
53
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
2
I C MASTER
BLOCK
ALRM
U
INTERNAL
VDD
U
CLAMP
MAX11068
TO TOP OF
STACK OR
BOTTOM OF
UPPER
NEIGHBOR
STACK
P
1kI
SCL
INTERNAL
L
N
VDD
U
GND
U
GND
U
VDD
U
P
DCIN
ALRM
U
PULLUP
MANAGEMENT
P
ONE SHOT
SCL
U
SDA
U
250ns
INTERNAL
50kI
1kI
SDA
U
GLITCH
FILTER
N
SDA DRIVE
U
CONTROL
GND
VDD
U
CP+
CP-
U
GND
U
GND
U
LEVEL SHIFTER
ALRM
INTERNAL
L
2
I C SLAVE
BLOCK
GND
L
GLITCH
FILTER
SCL
INTERNAL
VDD
L
VAA
VDD
L
P
PULLUP
MANAGEMENT
ALRM
L
P
ONE SHOT
250ns
SCL
L
SDA
L
INTERNAL
50kI
1kI
SDA
L
GLITCH
FILTER
AGND
GND
L
N
SDA DRIVE
L
CONTROL
GND
L
Figure 28. I2C Physical Interface Block Diagram
54
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Each port contains a bidirectional SDA pin with managed
edge transition. This weaker pullup continues to actively
drive the line until the particular SDA pin is no longer in a
transmitting state. During the acknowledge bit time, the
SDA pin that had been receiving data is able to use its
pulldown driver to overcome the 50kI pullup driven by
the transmitting device and successfully acknowledge
the transmission. Internal circuitry prevents the coupling
capacitors from accumulating charge and causing a DC
drift on the signals.
internal pullup drivers. The SCL pin for the lower slave
port is an input only, while the upper port master SCL pin
has a 1kω pullup driver. Glitch filters and Schmitt trig-
ger buffers are present on the input signals to minimize
communication errors. The alarm signal input is Schmitt
trigger with a current and voltage-clamping circuit while
the lower port alarm output is a push-pull driver. Each
port is designed to operate in an AC- or DC-coupled
bus configuration. All signal pins have a weak 150kI
pullup to their respective VDD supply to establish the
customary idle state of the I2C bus. The following operat-
ing description assumes the AC-coupled circuit shown
in Figure 28.
When the host or a device master drives the AC-coupled
SCL line with a signal edge, the high-frequency edge
passes to the slave side of the coupling capacitor where
it is received at the SCL input pin. Since the 150kIpas-
sive pullup resistor value is large, the time constant of
the pullup’s effect during communication when paired
with the typical 3.3nF AC-coupling capacitor is large
compared to the specified range of the I2C clock period.
Using resistor values lower than 150kI or changing
the coupling-capacitor value could affect the margin of
the bus timing specifications at some communication
frequencies. Since the SCL signal is unidirectional, no
internal pullup resistor manipulation for the driver circuit
is necessary. As with the SDA pins, internal circuitry pre-
vents the coupling capacitors from accumulating charge.
Since the SDA signal path must be bidirectional, manag-
ing the handoff of roles between transmitting nodes and
receiving nodes is critical to data integrity. At the same
time, the bus must be able to drive a certain capacitive
load size to maintain specified timing performance. To
meet these requirements, a managed resistance pullup
system with a strong pulldown driver is implemented in
both the master and slave blocks. When the SDA pin for
a given block is the driver of a signal edge on the line,
it first connects both a 1kI resistor and a 50kI resistor
from its VDD supply to SDA to initiate the active edge.
This strong pullup provides extra drive strength initially
to speed the charging of the parasitic capacitances
connected to the SDA pin and is active for the time
2
I C Command Summary
The MAX11068 supports seven different commands.
There are two main cycle formats, one for READALL and
the other for the rest of the commands. Several com-
mands require the host to send a PEC byte or for the
chain to send a PEC byte to the host. This is an imple-
mentation of the SMBus PEC algorithm, which is a CRC-8
process where all bits in the packet are cycled through
the CRC engine. Table 35 is the I2C command list.
period t
, which is typically 250ns. A param-
ONE-SHOT
eter, C
specifies the maximum capacitance that
1_TAU,
may be present on the SDA pin so that the SDA voltage
level transitions to within 70% of its nominal value within
the time period of the one-shot active edge. When the
one-shot period is over, the 1kIresistor is disconnected
and the 50kI pullup remains to complete the active
Maxim Integrated
55
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
2
Table 3ꢀ0 I C Command List
FUNCTION
DESCRIPTION
PEC BYTE
This command sets the device address of the first part in the chain. All
other parts in the chain are then assigned an automatically incremented
address as this command is forwarded from module to module. The
HELLOALL command should be issued after any power cycle or shut-
down event.
HELLOALL
None
None
Reads 2 bytes from each device in the chain, which includes the
address byte. When 0xFF is returned, the host has the addresses
of all devices. The ROLLCALL command should be issued after the
HELLOALL command.
ROLLCALL
The host informs all devices of the device count determined by the
ROLLCALL command so that each device can know when to expect
and generate PEC bytes. The SETLASTADDRESS command should be
issued after the ROLLCALL command.
SETLASTADDRESS
Required from host
WRITEALL
READALL
Broadcasts a common command to all enabled devices in the chain.
Required from host
Sent to host
Reads the available data from the device register specified by the com-
mand code byte for each device in the chain.
WRITEDEVICE
Writes data only to a specified target device.
Required from host
2
I C Communication Cycle Formats
The following cycle formats are used for the MAX11068 command set.
Write Word Format
COMMAND
DEVICE OR
CODE/
DATA
HIGH
[1ꢀ:8]
START
GLOBAL
WR
ACK
ACK
DATA LOW [7:±]
ACK
ACK
STOP
REGISTER
ADDRESS
ADDRESS
7 bits
8 bits
8 bits
8 bits
ReadAll Format, Single Device
DEVICE
OR
GLOBAL
ADDRESS
COMMAND
CODE/
REGISTER
ADDRESS
DATA
DATA
START
WR ACK
ACK SR ADDRESS RD ACK LOW ACK HIGH
NACK STOP
[7:±]
[1ꢀ:8]
7 bits
8 bits
7 bits
8 bits
8 bits
56
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
receives the data bits and sends the acknowledge bit.
So, the data bits have a shaded background and the
acknowledge bit is clear.
2
I C Command
Protocol Descriptions
Conventions
The following conventions are used in the description of
the I2C command protocols.
Address Byte Encoding
All commands begin with an I2C address byte immedi-
ately following a START or repeated START condition.
Each MAX11068 responds to the following bytes after a
START condition:
Binary values are prefixed with the notation 0b, e.g.,
0b11101000.
Hexadecimal values are prefixed by the notation 0x,
e.g., 0xE8.
In the timing diagrams, standard I2C notations have
been used:
U Broadcast address
U WRITEDEVICE command containing the device
address
U HELLOALL command
U
U
U
S represents a START condition (pulls SDA low while
SCL is high).
The format for these bytes is shown in Table 36.
The broadcast address is an address value to which
all enabled devices respond. This address is used for
ROLLCALL, WRITEALL, and READALL commands. The
broadcast address B[7:0] is programmable through the
BRDCST bits of the BROADCAST ADDRESS register
(address 0x0F), but B[0] is not used since it falls in
the position of the I2C R/Wb bit. The default broadcast
address is 0x40. The I2C general-call address 0x00 is
not supported and the MAX11068 does not respond to
messages sent to that address unless the BRDCST bits
are set to this value.
P represents a STOP condition (pulls SDA high while
SCL is high).
Sr represents a repeated START condition. This is
identical to a START condition except that it has not
followed a STOP condition.
U
U
U
U
A represents a positive acknowledge (ACK). The
data receiver drives the SDA line low.
N represents a negative acknowledge (NACK). The
data receiver drives the SDA line high.
W represents the R/Wb bit set low for a write transac-
tion.
The device address is unique to each part within the
chain of devices. This address is used during HELLOALL
and WRITEDEVICE commands, and is essential in deter-
mining which device is the last in the SMBus ladder. The
HELLOALL command sets the address of all de-vices by
initializing the address of the first device in the chain and
autoincrementing the addresses of remaining devices
up the chain. When the MAX11068 is not used on a
dedicated I2C bus, the other devices on the bus should
not be configured to use addresses with a 1 as the MSB.
The broadcast address must also be chosen to avoid
conflicts with the HELLOALL and WRITEDEVICE com-
mands, as well as any other devices on the bus.
R represents the R/Wb bit set high for a read transac-
tion.
U
U
X represents a don’t-care value for a data bit.
N.C. represents an I2C link that is a no connect.
The diagrams also represent the direction of SDA by
shading the data when the slave is the data source. For
example, when the I2C master performs a write, it sends
the data bits and receives the acknowledge bit. So, the
data bits have a clear background and the acknowledge
bit is shaded. When the I2C master performs a read, it
2
Table 360 I C Address Byte Encoding
I2C ADDRESS BIT
7
6
ꢀ
4
3
2
1
R/Wb
Broadcast Address
(default value)
HELLOALL
B7
0
B6
1
B5
0
B4
0
B3
0
B2
0
B1
0
1/0
1/0
1
1
1
0
A0
A0
A1
A1
A2
A2
A3
A3
A4
A4
0
0
WRITEDEVICE
Maxim Integrated
57
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
SMBus ladder device. The command is then forwarded
HELLOALL Command
The purpose of the HELLOALL command is to initialize
the device stack and assign a unique device address
to each MAX11068 in the SMBus ladder. It should be
issued after any power cycle or shutdown event to
reconfigure all addresses. The HELLOALL command is
a standard I2C address byte where the first 2 bits must
be 1s, the next 5 bits specify the desired address of the
first MAX11068 device in the SMBus ladder, and the last
bit is the standard I2C R/Wb bit. This bit should always
be 0 for this command. The starting address A[0:4]
is specified least significant bit first. Since the device
address consists of 5 bits, it has a maximum value of 32,
while the maximum number of SMBus-laddered devices
is 31. The device address A[0:4] wraps to 0 if it exceeds
the maximum value of 0x1F during a HELLOALL com-
mand. The WRITEDEVICE command, which uses the
device address, however, does not properly commu-
nicate with devices whose address is less than that
of device 1. Therefore, the starting address used by
the HELLOALL command should always be set such
that the last device’s address A[0:4] is no greater than
0x1F. When using the maximum number of devices, the
address A[0:4] of the first device must be initialized to
0x00 or 0x01 to meet this requirement.
to the next device in the chain with the A[0:4] bits of the
address byte incremented by 1 LSB. This continues for
each active device in the SMBus ladder. A typical start-
ing address is 0x01, which in this example would make
the HELLOALL address byte value 0b1110000 = 0xE0.
Figure 29 is the I2C address byte for the HELLOALL
command and Figure 30 shows the HELLOALL com-
mand SMBus ladder sequences with four modules.
In the case of a four-module SMBus ladder, the fourth
MAX11068 upper I2C port is not connected to anything.
Therefore, it receives a NACK when it transmits the
HELLOALL command. This sets the ALRTACK status bit,
which should be cleared by the host.
ROLLCALL Command
The ROLLCALL command is used to determine the num-
ber of devices in the stack. It should be issued after the
HELLOALL command following any power cycle or shut-
down event. The format for this command is similar to
the READALL command except that 0xFF is returned in
place of the PEC and data check bytes. The ROLLCALL
command is always a read of the ADDRESS register
(address 0x01). This register cannot be read in any other
way. Figure 31 shows the I2C communication sequence
for the ROLLCALL command as viewed by the host con-
troller and Figure 32 is the ROLLCALL command SMBus
ladder sequences with two modules.
When the HELLOALL command is first issued by the
host, the address specified is stored to the A[0:4] bits
of the ADDRESS register (address 0x01) in the first
2
2
I C BUS FORWARDING DATA STREAM
I C BUS LINK
SCL
HOST TO IC1
IC1 TO IC2
IC2 TO IC3
IC3 TO IC4
IC4 TO N.C.
S
11100000
11010000
11110000
11001000
A
P
1
1
A0
A1
A2
A3
A4
W
A
SDA
S
A
P
S
A
P
S
P
S
A
P
S
11101000
N
P
NOTE: SHOWN IS THE 1Fs FOWARDING DELAY FROM
ONE BUS LINK LEVEL TO THE NEXT. NOT DRAWN
TO SCALE. STARTING ADDRESS OF A[4:0] = 0x01.
Figure 29. I2C Address Byte for the HELLOALL Command
Figure 30. HELLOALL Command SMBus Ladder
Sequences with Four Modules
58
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
SCL
SDA
B7
B6
B5
B4
B3
B2
B1
W
A
A
A
C7
C6
C7
C4
C3
C2
C1
C0
A
A
A
B7
B6
B5
B4
B3
B2
B1
R
A
S
Sr
SCL
SDA
LOW BYTE DEVICE 1
HIGH BYTE DEVICE 1
SCL
SDA
LOW BYTE DEVICE 2
HIGH BYTE DEVICE 2
2
NOTE: THE I C MASTER KNOWS THE
NUMBER OF DEVICES IN THE STACK FROM
A PREVIOUS ROLLCALL COMMAND. IT
THEREFORE KNOWS WHEN TO EXPECT THE
DATA CHECK AND PEC BYTES, AND WHEN
TO NACK AND ISSUE A STOP CONDITION.
SEQUENCE REPEATS. TWO BYTES ARE RETURNED FOR EVERY DEVICE IN THE STACK.
SCL
SDA
LOW BYTE DEVICE N
DATA CHECK BYTE
A
A
HIGH BYTE DEVICE N
A
SCL
SDA
PEC
N
P
2
Figure 31. I C Communication Sequence for the ROLLCALL Command as Seen by the Host
2
2
I C BUS LINK
I
C
BUS FORWARDING DATA STREAM
HOST TO IC1
S
B[7:1]+W
A
00000001
A
SR
B[7:1]+R
A
ADDRESS 1 L
A
ADDRESS 1 H
A
ADDRESS 2 L
A
ADDRESS 2 H
A
0xFF
A
0xFF
N
P
S
B[7:1]+W
A
00000001
A
SR
B[7:1]+R
A
ADDRESS 2 L
A
ADDRESS 2 H
A
IC1 TO IC2
0xFF
A
0xFF
A
0xFF
A
0xFF
A
P
NOTE: THE IC MASTER PORT CONTINUES TO OUTPUT A
CLOCK ON SCL UNTIL IT RECEIVES A STOP
FROM THE LOWER MODULE.
S
B[7:1]+W
N
P
IC2 TO N.C.
NOTE: SHOWN IS THE 1Fs FOWARDING DELAY FROM ONE BUS
LINK LEVEL TO THE NEXT. NOT DRAWN TO SCALE.
Figure 32. ROLLCALL Command SMBus Ladder Sequences with Two Modules
Maxim Integrated
59
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
The ROLLCALL command is formatted like the READALL
cycle format. First, the broadcast address is sent on the
bus as an I2C address byte with the R/Wb bit configured
as a write. Next, the command 0x01 for the ADDRESS
register is sent. This address is always the target of the
ROLLCALL command. Following the broadcast address
and command byte, a repeated start is performed. Next,
the host sends another broadcast address byte with
the last bit set to 1 for an I2C read. All command bytes
are forwarded up the SMBus ladder. After receiving
the broadcast address byte for the read, each device
in the chain starting with the first device responds by
sending both bytes of their ADDRESS registers. When
each device is done sending its own data, it passes
the data of the device above it in the chain. The SCL
signal provides a clock to all devices in the chain until
the host issues a stop event. Therefore, when devices
no longer have valid register data to forward, they will
continue to forward bytes consisting of 0xFF since the
SDA lines are pulled to a logic-high level. When the
host receives 2 bytes of 0xFF, it should recognize that
no more devices are present and send the NACK/stop
sequence. The stop propagates up the SMBus ladder to
halt the transfer of data. The host is then able to examine
all the bytes received and determine the number of valid
devices that are connected, in addition to the address
of the last device. If a device is connected to the chain
but not powered, its data is 0x0000 since the SDA line is
not pulled up by the VDD supplies. This allows the host
processor to determine that a device is present, but not
communicating properly or is faulty. Because of the way
in which data is shifted from the last device in the chain
back to the first device and then to the host, the bus
forwarding delay of the ROLLCALL command is masked
and no delay is perceived by the host once it begins
receiving data from device 1.
As an example, if a HELLOALL command was issued
previously with a starting address of 0x01, the first
device returns in response to the ROLLCALL command
the device address 0x01 encoded as 0b10100000 =
0xA0. The second device returns a device address of
0x02, which is encoded 0b10010000 = 0x90 and so on.
The last address byte is indeterminate during readback
with this command, and should not be relied upon.
SETLASTADDRESS Command
This command is used to tell each MAX11068 in an
SMBus ladder which device address is the last one.
Each device must know this information to properly place
the PEC byte in the data stream during relevant com-
munication operations. The I2C master establishes the
last device identity by using the ROLLCALL command,
which should always precede SETLASTADDRESS. Once
the last device address is known, the host initiates the
SETLASTADDRESS command to write this information to
the LA[4:0] bits of the ADDRESS register (address 0x01).
As with all data bytes in the I2C stream, the last address
byte is encoded MSB first. Figure 33 shows the I2C
communication sequence for the SETLASTADDRESS
command. Figure 34 shows the SETLASTADDRESS
command SMBus ladder sequences with four modules.
SCL
1
0
A0
A1
A2
A3
A4
W
A
A
C7
C6
C5
C4
C3
C2
C1
C0
A
A
SDA
S
SCL
SDA
PEC
A
DATA
DATA
P
Figure 33. I2C Communication Sequence for the SETLASTADDRESS Command
60
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
2
2
I C BUS FORWARDING DATA STREAM
I C BUS LINK
HOST TO IC1
IC1 TO IC2
IC2 TO IC3
IC3 TO IC4
IC4 TO N.C.
S
B[7:1]+W
B[7:1]+W
B[7:1]+W
B[7:1]+W
B[7:1]+W
A
DATA REGISTER
A
DATA LSB
DATA LSB
DATA LSB
A
DATA MSB
DATA MSB
DATA MSB
DATA MSB
A
PEC
PEC
PEC
PEC
A
P
S
A
DATA REGISTER
A
A
A
A
P
S
A
DATA REGISTER
A
A
A
A
P
S
A
DATA REGISTER
P
A
DATA LSB
A
A
A
P
S
N
NOTE: SHOWN IS THE 1Fs FOWARDING DELAY FROM ONE BUS LINK
LEVEL TO THE NEXT. NOT DRAWN TO SCALE.
Figure 34. SETLASTADDRESS Command SMBus Ladder Sequences with Four Modules
The communication sequence for SETLASTADDRESS
follows the write word format. First, the broadcast
address is sent on the bus as an I2C address byte
with the R/Wb bit configured as a write. Next, the com-
mand code byte 0x01 for the ADDRESS register loca-
tion is sent. This address is always the target of the
SETLASTADDRESS command. Next, the 2 data bytes
to be written to each device are sent on the bus. Only
the second byte containing the LA[4:0] bit information
is written into each device’s ADDRESS register for the
SETLASTADDRESS command. Therefore, the first data
byte may have any value. After the second data byte is
sent, the PEC byte, which is calculated from the first 4
bytes, is transmitted and then a stop event from the host
should end the communication sequence.
byte, which consists of bits D[15:8] in the ADDRESS
register, start with 3 zeros, and append the A[4:0] data
(oriented with the MSB first), which results in 0b00001000
= 0x08. This is the byte value for this example that would
be written to D[15:8] of the ADDRESS register using the
SETLASTADDRESS command.
Once the last device has been configured with the last
address bit data, that device acts as the source of the
alarm heartbeat. All other devices relay that heartbeat,
or any alarm conditions that may be present, down the
chain to the host using the ALRM and ALRM pins.
L
U
WRITEALL Command
The WRITEALL command allows a given value to be
written to a certain register in all active MAX11068
devices at the same time (neglecting communication
delays). Since most configuration information is common
to all the devices, this command allows faster setup than
writing to each device individually. First, the broadcast
address is sent on the bus as an I2C address byte with
the R/Wb bit configured as a write. Next, the command
byte is sent with an MSB first value corresponding to the
register address to which the data byte is written. The
For example, if the host determined by use of the
ROLLCALL command that the device address byte
(D[7:0] of the ADDRESS register) for the last device in the
chain was 0x84 = 0b10000100, then the device address
bits (packed LSB first) A[0:4] are 0b00010. This value,
noting proper orientation of the LSB and MSB, is what
must be written to the LA[4:0] bits of the ADDRESS regis-
ter in all connected devices. To construct the last address
Maxim Integrated
61
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
low data byte and then the upper data byte follow the
command byte. Finally, the PEC is sent and a stop event
ends the communication sequence. Figure 35 shows the
I2C communication sequence for the WRITEALL com-
mand. Figure 36 shows the WRITEALL command SMBus
ladder sequences with four modules.
a consistent PEC while others may not. In this case, an
enabled PEC alarm can signal the overall problem while
a READALL command can check the status registers to
reveal which specific devices failed to correctly receive
the command. When using the WRITEALL command to
change the broadcast register, it is important to verify
that the command was executed by all known devices.
This can be accomplished by enabling the PEC alarm
and verifying that the WRITEALL was successful, or by
performing a READALL after the WRITEALL and making
sure a response was received from all expected devices.
If a response was not received from all devices, steps
should be taken to rewrite the new broadcast address or
determine if a device has been removed from the stack.
The PEC byte must be supplied with the WRITEALL
command. It is calculated from the first 4 bytes of the
command. If any MAX11068 device does not receive
a packet with a consistent PEC, it will not perform the
command or the register writes. It will also generate a
PEC alert in the status register, and this may (option-
ally) cause the suspension of the alarm heartbeat. Due
to bus noise, it is possible for some devices to receive
SCL
B7
B6
B5
B4
B3
B2
B1
W
A
A
C7
C6
C7
C4
C3
C2
C1
C0
A
A
SDA
S
SCL
SDA
LOW DATA BYTE
HIGH DATA BYTE
PEC
A
P
Figure 35. I2C Communication Sequence for the WRITEALL Command
2
2
I C BUS FORWARDING DATA STREAM
I C BUS LINK
S
B[7:1]+W
B[7:1]+W
B[7:1]+W
B[7:1]+W
B[7:1]+W
A
00000001
A
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
A
ADDRESS MSB
ADDRESS MSB
ADDRESS MSB
A
PEC
PEC
PEC
PEC
A
P
HOST TO IC1
IC1 TO IC2
IC2 TO IC3
IC3 TO IC4
IC4 TO N.C.
S
A
00000001
A
A
A
A
P
S
A
00000001
A
A
A
A
P
S
A
00000001
N P
A
A
ADDRESS MSB
A
A
P
S
NOTE: SHOWN IS THE 1Fs FOWARDING DELAY FROM ONE BUS LINK
LEVEL TO THE NEXT. NOT DRAWN TO SCALE.
Figure 36. WRITEALL Command SMBus Ladder Sequences with Four Modules
62
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
es or exceeds the receiving device’s address. If the
addresses match, the device executes the command.
If the command address exceeds the device’s address,
the command forwarding stops. This can happen if
the device addresses assigned during the HELLOALL
command exceeded 0x1F, or if the device addressed
by the WRITEDEVICE command is no longer active.
Figure 37 shows the I2C communication sequence for
the WRITEDEVICE command and Figure 38 shows the
WRITEDEVICE command SMBus-laddered sequences
where the device address matches IC3.
WRITEDEVICE Command
This command allows a register in a specific device
within the SMBus ladder to be written. It is similar to the
WRITEALL command except that the I2C address byte
contains the fixed MSbs 0b10, followed by the device
address A[0:4] encoded LSB first instead of the broad-
cast address. Once again, a consistent PEC must be
received for the command to be executed by the device.
The PEC alert is set if the command was aborted. The
command sequence is forwarded up the SMBus ladder
until the device address sent with the command match-
SCL
B7
B6
B5
B4
B3
B2
B1
W
A
A
0
0
0
0
0
0
0
1
A
A
SDA
S
SCL
SDA
DON’T CARE
LAST ADDRESS
PEC
A
P
Figure 37. I2C Communication Sequence for the WRITEDEVICE Command
2
2
I C BUS FORWARDING DATA STREAM
I C BUS LINK
HOST TO IC1
IC1 TO IC2
IC2 TO IC3
S
10+A[0:4]+W
10+A[0:4]+W
A
DATA REGISTER
DATA REGISTER
A
DATA LSB
DATA LSB
DATA LSB
A
DATA MSB
DATA MSB
DATA MSB
A
PEC
PEC
PEC
A
P
S
A
A
A
A
A
P
S
10+A[0:4]+W
A
DATA REGISTER
A
A
A
A
P
NOTE: SHOWN IS THE 1Fs FOWARDING DELAY FROM ONE BUS-
LINK LEVEL TO THE NEXT. NOT DRAWN TO SCALE.
Figure 38. WRITEDEVICE Command SMBus Ladder Sequences Where the Device Address Matches IC3
Maxim Integrated
63
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
bit, at which time it forwards the data from the second
READALL Command
This command is used to retrieve register information
from the stack of devices and it is the only way to read
register values (except for the ADDRESS register, which
is handled by the ROLLCALL command). After sending
the I2C address byte containing the broadcast address
with the R/Wb bit low and then the command byte, the
READALL format requires a repeated start to change
the direction of data flow. Following the repeated start,
another broadcast address byte is sent with the R/Wb
bit, this time set for a read. This starts the flow of device
data back to the host. The data stream as viewed at
the lower port interface of the first device in the stack
appears as shown in Figure 39.
device. This process continues for each MAX11068 in
the SMBus ladder. Because of the way the data is shifted
from each device back toward the host, the module-to-
module communication delays are effectively masked
and the host sees a continuous stream of data once the
first device receives the READALL command.
After the last device sends its data, it creates a data
check byte and PEC byte since it knows it is the last
device in the chain. The PEC byte generated by the
MAX11068 uses a CRC-8 algorithm, which is what the
host should use on the sent data. Each link of the SMBus
ladder contains a unique data sequence. Therefore,
each READALL communication between modules has
a different PEC byte. The data check byte informs the
host whether the entire communication succeeded
by passing a flag containing the PEC error status of
the entire READALL command down the chain. This
makes it easier for the host controller to determine if
the READALL command was successful without hav-
ing to check the ALRTPEC status of each module in the
After the first device receives the READALL command, it
begins to send the requested register data, low byte first,
on the bus toward the host. Approximately 1Fs later, the
next device in the SMBus ladder receives the READALL
command and sends its data to the upper port of the
first device. The first device holds these bits until it is
done sending its own data and receives an acknowledge
SCL
SDA
B7
B6
B5
B4
B3
B2
B1
W
A
A
A
0
0
0
0
0
0
0
1
A
A
A
B7
B6
B5
B4
B3
B2
B1
R
A
S
SR
SCL
SDA
DEVICE ADDRESS 1
LAST ADDRESS
SCL
SDA
DEVICE ADDRESS 2
LAST ADDRESS
2
NOTE: THE I C MASTER KEEPS READING 2
SEQUENCE REPEATS. TWO BYTES ARE RETURNED FOR EVERY DEVICE IN THE STACK.
BYTES AT A TIME UNTIL THE TERMINATING
SEQUENCE 0xFF 0xFF IS SEEN. IT THEN
NACKS AND ISSUES A STOP CONDITION.
SCL
SDA
DEVICE ADDRESS N
A
A
LAST ADDRESS
A
A
SCL
SDA
0xFF
0xFF
P
2
Figure 39. I C Communication Sequence for the ROLLCALL Command as Viewed by the Host Controller
64
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
SMBus ladder. Host processor efficiency is improved as
upper I2C port, it sets PECERR, as well as ALRTPEC to
1 before sending the data check byte down the SMBus
ladder. The next-to-last device recalculates the PEC
byte based on the same READALL command bytes as
the last device, plus all 4 data bytes belonging to the
last two devices and the updated data check byte. The
processing of the data check and PEC bytes continues
as all information is passed from the last device in the
chain to the first device. When the first device has sent
all data bits, it appends the processed data check byte
as each of the devices before it has done. The PEC byte
is then appended having been calculated using all bytes
shown in Figure 40. Any error in the process that causes
an invalid PEC does not terminate the transaction. Since
each intermediate device recalculates the PEC, the host
may receive a valid PEC byte for invalid data, but the
data check byte shows that a PEC error has occurred
along the way. In that case, the host should determine
where the error occurred and take appropriate actions.
As mentioned, the overall data stream appears to the
host as it is shown in Figure 40. In the transactions
between intermediate modules, the data stream is simi-
lar except that it contains only the data bytes from itself
and the modules above it. Since the module-to-module
communication delay is much less than one I2C clock,
and the clock itself is also delayed, there is no apparent
module-to-module delay observed by the host controller
as the real delay is masked in the process of shifting the
data back to the host. A combination of the PEC and
data check byte approaches can ensure a very high
probability of transactional integrity for the READALL
command.
a result. In addition, an ALRTPEC condition can be con-
figured to generate an alarm on the alarm bus by setting
the ALRMPEC bit. This alarm can be monitored by the
host and provides the same information as the ALRM bit
of the data check byte. The benefit of the PECERR bit is
that it provides a specific ALRTPEC flag to the host as
part of each READALL transaction. The data included in
the calculation is the first address byte, the command
byte, the address byte following the repeated start, all
data sent on the bus by the device calculating the PEC,
and the data check byte. For the last device, the PEC is
calculated from the 3 bytes of the READALL command,
the 2 data bytes that it sent, and the data check byte.
The data check byte is defined in Table 37.
The MSB, ALRM, is a flag indicating whether the device
sending the data check byte or a device above it in the
SMBus ladder is in any alarm condition with the ALRM
pin pulled high. For the data check byte sent by the
last device in the chain, the ALRM bit is set according
to the alarm status of the device while the PECERR bit
is a 0, since this is the last device. When the next-to-
last device receives the data check byte from the last
device, it logically ORs this byte with its own alarm
status and whether its upper port received a valid PEC
byte from the last device. It sends out the data check
byte after the last data byte (high byte from the last
device) is sent. The LSB, PECERR, is a flag indicating
whether the device sending the data check byte, or a
device in a module above it, has an active ALRTPEC
flag. When a device receives an invalid PEC byte at its
2
2
I C BUS LINK
I
C
BUS FORWARDING DATASTREAM
HOST TO IC1
S
B[7:1]+W
A
DATA REGISTER
DATA 2 LSB
A
SR
B[7:1]+R
A
A
DATA 1 LSB
A
DATA 1 MSB
A
A
DATA 2 MSB
DATA CHECK
A
PEC
N
P
S
B[7:1]+W
A
DATA REGISTER
DATA CHECK
A
SR
B[7:1]+R
A
DATA 2 LSB
A
DATA 2 MSB
A
IC1 TO IC2
A
PEC
N
P
S
B[7:1]+W
N
P
IC2 TO N.C.
NOTE: SHOWN IS THE 1Fs FOWARDING DELAY FROM ONE BUS
LINK LEVEL TO THE NEXT. NOT DRAWN TO SCALE.
Figure 40. READALL Command SMBus Ladder Sequences with Two Modules
Maxim Integrated
65
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
t
MCL-MIN
SCL
U
t
LS-CLK
DATA
DATA
DATA
SDA
U
t
LS-DAT
t
HD-DAT
t
HIGH
P
S
t
LOW
SCL
L
L
t
HD-DAT
t
SU-DAT
t
HD-STA
SDA
DATA
DATA
DATA
t
BUF
2
Figure 41. I C Lower and Upper Port Timing Diagrams
higher device address than their own. So, some devices
are not addressable if the addresses A[0:4] written by
HELLOALL are allowed to wrap past 0x1Fh.
2
I C Port Timing Diagrams
Figure 41 shows the I2C lower and upper port timing
diagrams.
Pack Insertion and Removal
When a pack is removed or inserted, the SMBus lad-
der must be reconfigured. The HELLOALL, ROLLCALL,
and SETLASTADDRESS sequence should be used to
reinitialize the device addresses and the address of the
last device.
2
I C Functional Description
Autoaddressing
The HELLOALL command automatically assigns each
device a unique address. This address can be used
during a WRITEDEVICE command to write to only one
selected device in the SMBus ladder, and is also read
during the ROLLCALL command to identify all the unique
active devices present on the bus. When all the device
addresses are known, the last device in the chain can
be identified and made known to all ports. It is important
for each node and the host to know the relationship of
devices that make up the SMBus ladder so that the PEC
byte used in some command protocols can be properly
located and calculated.
Communication Timeout
If the SCL input remains high or low for longer than
U
28ms, then any transaction is aborted and the device
behaves as if it observed a STOP condition. The host
can ensure that all devices are in a “ready-to-communi-
cate” state by remaining idle for longer than 28ms.
Interface Speed
For optimal data transfer, the host microcontroller should
make extensive use of the WRITEALL and READALL
commands. One READALL or ROLLCALL command
consumes the following amount of time based on the
number of bits in the command protocol and the number
of devices in the SMBus ladder:
The device address of the first device in the SMBus lad-
der stack is specified with the HELLOALL command.
This address is incremented by 1 before being sent to
each successive downstream device. The maximum
device address is 0x1Fh and the address counter wraps
to 0 if the starting address was set too high for the num-
ber of deviin the chain. The SMBus-laddered devic-
es only forward WRITEDEVICE commands that have a
t
= 5× 8 bits + 5 bits + 3 bits × t
(
)
READALL
SCL
+ N
× 16 bits + 2 bits × t
(
)
MODULES
SCL
66
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 37. Data Check Byte Definition
BIT
7
NAME
DESCRIPTION
ALRM
Set if the device is in an alarm condition, meaning the ALRML pin is high.
6
0
0
0
0
0
0
Unused, read as 0.
Unused, read as 0.
Unused, read as 0.
Unused, read as 0.
Unused, read as 0.
Unused, read as 0.
5
4
3
2
1
During a READALL command, the slave returns PECERR = 0 if the master received a valid
PEC. The slave returns PECERR = 1 if the master received an invalid PEC or the master
received PECERR = 1. In this way, the system can verify communication not only one layer
at a time, but also across all layers.
0
PECERR
For 20 modules with a 200kbps I2C master data rate,
it takes approximately 2.0ms to perform a READALL or
ROLLCALL command for one register. Since there are
16 frequently read registers, it would take 32ms to per-
form a complete read of all devices for those registers.
If an additional nine configuration registers are included,
then 50ms are required. A 100kbps I2C master would be
fast enough to perform this task in a reasonable amount
of time.
device received a valid write command. The success
of the write command further up the chain is unknown
to the host. If verification is critical, the host should fol-
low up any write command with a READALL to verify
the write by checking the register that was updated or
the ALRTPEC bit of the STATUS register. The PEC alert
may also be enabled to trigger an alarm through the
ALRMPEC bit of the ADCCFG register (address 0x08). If
no alarms are present following the write command, the
host can infer that the write command was successful to
all attached devices.
WRITEALL consumes the following amount of time
based on the number of bits in the command protocol,
and the number of modules in the SMBus ladder:
To support PEC, the host must implement a CRC-8 algo-
rithm to perform calculations necessary for the PEC byte.
The CRC-8 polynomial is:
t
= 5× 8 bits + 5 bits + 2 bits × t
(
)
WRITEALL
SCL
−1 × t
LEVEL−SHIFT−DELAY
+ N
(
)
MODULES
8
2
C(x) = x + x + x +1
For 20 modules with a 200kbps I2C master data rate, this
is approximately 250Fs to perform a WRITEALL com-
mand for one register.
All bytes including addresses, command codes, data,
and for READALL, the data check byte should be pro-
cessed by the CRC-8 algorithm as input bytes. START,
repeated START, STOP, and ACK/NACK bits are not
included in the calculation. The bits should be pro-
cessed in the order they are received with MSB first.
The logic implementation can be described as follows.
First, the CRC is initialized to zero for a new calculation.
For each input byte, the byte is first XORed with the CRC
value. This byte is called the remainder. The remainder
is left shifted by 1 bit and is sent to a mux as itself or
XORed with the 8 least significant bits of the polynomial
representation. The bit lost in the left-shift operation is
able to be ignored because either it is a zero, or if it is a
1, it would be XORed with the most significant bit of the
polynomial representation to yield a 0. Therefore, only
Packet-Error Checking (PEC)
The MAX11068 uses the SMBus PEC mechanism for
maintaining data integrity. PEC verifies stage-to-stage
communication both in the write and read directions.
During any write transaction, a device does not execute
the write command internally unless the PEC is received
successfully by the lower port. The host can easily
ignore the PEC byte from a READALL command if the
host does not intend to support PEC for read transac-
tions. The only verification of a successful write trans-
action that the host receives is through the ACK bit
following thPEC byte returned from the first device in
the SMBus ladder. This bit indicates whether the first
Maxim Integrated
67
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
an 8-bit pipeline is shown for all parts of the circuit. The
MSB of the remainder controls a mux to select which
operation is performed on the left-shifted version of the
remainder byte. Once the remainder is operated on, it
Function PEC_Calculation(ByteList(), NumberOfBytes, CRCByte)
{
//CRCByte is typically initialized to 0 for each ByteList. If processing time
//must be conserved, it is possible to precalculate the CRCByte value
is latched and fed back to the input of the shift register
through another mux. This is repeated until eight left
shifts have occurred. After eight left-shift operations
have been processed, the process is repeated on the
next input byte using the working CRC value, which is
the remainder following the left-shift operations. After all
input bytes have been processed, the CRC output byte
is the final result. Figure 42 shows a pseudo-code algo-
rithm for the CRC-8 logic that can be used in a software
or firmware implementation.
//for a known set of bytes at the beginning of a message. Then, this
//CRCByte value for the partial ByteList may be passed into the function
//as the initial value along with the remaining bytes of the message
//resulting in less computation steps.
//Loop once for each byte in the ByteList
For Counter1 = 0 to (NumberOfBytes –1)
(
//Bitwise XOR the current CRC value with the ByteList byte
Remainder = CRCByte XOR ByteList(Counter1)
//Process each of the 8 Remainder bits
For Counter2 = 8 To 1 Step -1
(
//Determine if MSB = 1 prior to left shift
If (Remainder And &H80) = &H80 Then
//When MSB = 1, left shift and XOR with 8 lsbs of the polynomial
Remainder = ((Remainder * 2) XOR &H7)
Else
For write commands that require a PEC byte, the host
should perform this calculation on the byte sequence
that is transmitted. In applications where processing
time is extremely critical, it is possible to precalculate
the CRC value for the first few bytes of common com-
mands, or sometimes even for full commands, and store
these as constants. Then, when those commands are
used, the microcontroller can use the stored CRC value
for the precalculated portion of the message as an initial
value and only calculate the portion of a message that
may have changed in real time. This can save some pro-
cessing time, although the PEC algorithm is designed
to require a relatively small amount of processing
resources in most cases. For a READALL command, the
host should store the bytes of the received data stream,
perform the PEC calculation on the relevant bytes, and
compare the results to the received PEC byte. The PEC
may also be calculated as each byte is received instead
of waiting for the entire message to arrive by storing the
running CRC value and passing it to the PEC calculation
function for each new byte.
//When MSB = 0, left shift 1 bit
Remainder = (Remainder * 2)
End If
//Truncate the CRC value to 8 bits
Remainder = Remainder And &HFF
//Proceed to the next Remainder bit
Next Counter2
)
CRCByte = Remainder
//Operate on the next data byte in the ByteList
Next Counter1
)
Return CRCByte
}
Example PEC Calculation
Figure 43 shows a typical WRITEALL command that is
being sent by the host controller for which the PEC byte
must be calculated.
Figure 42. Example Pseudo-Code Algorithm for a CRC-8 PEC
Calculation
Figure 43 shows 4 bytes preceding the transmission of
the PEC byte. The first is the broadcast address, which
is assumed to be the default of 0x40. The next byte 0x09
is the register address corresponding to the CELLEN
register that is written. The last 2 bytes are the new val-
ues of the register with the LSB first. The value of 0x03FF
that is written corresponds to enabling the first 10 cells
for measurement. These 4 bytes shown above represent
all bits included in the PEC byte calculation, and would
comprise the ByteList() array from the previous pseudo-
code algorithm. Applying the bytes 0x40, 0x09, 0xFF,
and 0x03 in sequence to the CRC algorithm yields a final
CRC result of 0x7F, which would be the value of the PEC
byte that the host should send immediately following the
data MSB.
68
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
2
2
C
I C BUS LINK
I
BUS FORWARDING DATA STREAM
01000000 00001001
HOST TO IC1
S
A
A
11111111
A
00000011
A
BIT STREAM FOR PEC EXAMPLE CALCULATION
Figure 43. Example WRITEALL Bit Stream Prior to PEC Transmission
U
U
Packet error checking (ALRTPEC)
Acknowledge error (ALRTACK)
Power-On-Reset (POR) Event
A VAA voltage below the POR threshold results in an
internal device reset. In this state, the charge pump is
disabled, as well as the digital logic. Therefore, after
The last group of alerts report operational failures of
blocks of the IC. These flags aid in detecting conditions
that signal if the device is operating correctly. They
include:
VAA and VDD have decayed below the power-on
U
reset levels, I2C communication is ignored and is not
forwarded. In some cases, a parasitic power path may
U
U
U
U
U
U
Reset status (RSTSTAT)
exist to VDD , and therefore VAA, through communi-
L
cation pullup resistors or logic signals from the host.
Charge-pump failure (ALRTCPUV)
Heartbeat signal out of specification (ALRTHBEAT)
Voltage reference failure (ALRTREF)
Lower +3.3V supply failure (ALRTVDDL)
Lower GND failure (ALRTGNDL)
These paths typically supply VDD at one diode drop
L
below the pullup level. As long as the pullup level is no
more than one diode drop above the POR threshold, the
entire device, including the digital logic remains in reset.
Supplying VAA or VDD with a power source above
L
the reset threshold can result in active operation, even
though the regulator may be disabled. When the POR is
These alerts are activated when the configured thresh-
olds are violated for a particular monitored condition or
a particular function did not execute as expected. Status
alerts are indicated by individual flag bits in various reg-
isters and must be read through the communication bus
and processed by the host controller.
not active and VDD and VDD are valid, communica-
U
L
tion proceeds as normal.
Alert and Alarm Status Functions
The MAX11068 offers a comprehensive system to inform
the host controller of the device’s status. This is done
with status alerts and status alarms. Status alerts are flag
bits reporting various monitoring functions of the device.
Alerts can be divided into three main groups. Cell moni-
toring alerts are flags that report conditions related to the
cell measurement. They include:
Status alarms are indicated using the alarm ladder bus
comprising the ALRM and ALRM ports. An alarm is
L
U
the result of an active alert that has been enabled to
trigger an alarm. By monitoring the alarm bus with the
system controller, the controller has nearly instant vis-
ibility of critical status conditions. Normally, this alarm
bus carries a 16.384kHz heartbeat signal from the top
device in the SMBus ladder to the bottom device. When
an alarm is activated in a device, the alarming device
pulls the alarm bus to logic high and interrupts the flow
of the heartbeat signal. In this way, the alarm function
acts as a high-priority interrupt signal to the host control-
ler for critical events.
U Cell undervoltage threshold crossed (UVTHRSET)
U Cell overvoltage threshold crossed (OVTHRSET)
U Cell voltage mismatch threshold crossed (MSMTCH)
U Auxiliary channel temperature measurement thresh-
old crossed (AINOT, AINUT)
The second group of alert flags are communication
errors. These flags report conditions related to the func-
tioning of the SMBus ladder. They include:
Maxim Integrated
69
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
The topmost device in an SMBus ladder stackup is
responsible for generating the heartbeat signal when
it is not in an active alarm state and after the RSTSTAT
bit has been cleared. The last device in the stack rec-
ognizes itself as the top module when the last address
bits of the ADDRESS register (address 0x01) match its
own device address. When this condition is true, usu-
ally following the SETLASTADDRESS command, and the
RSTSTAT bit is clear, the top device generates the heart-
beat signal. This signal is propagated down the alarm
bus and is only stopped if a device replaces it with an
active alarm signal. The system controller should monitor
nals and alarm mask bits work together to generate an
alarm on the alarm bus.
Table 38 is a summary of all status alerts present in the
MAX11068, the associated threshold levels or trigger
condition, and the corresponding mask enable bits.
Alert bits are cleared by writing the bit to a logic zero
unless they are automatically cleared when the alert
condition subsides. Clearing an alert bit that caused an
alarm also clears the alarm. If multiple alerts or multiple
devices are triggering an alarm condition, all alerts must
be cleared before the heartbeat signal is again propa-
gated to the host controller.
the ALRM of the lowest device in the SMBus ladder to
U
When the system controller receives an active alarm indi-
cation from the alarm bus, it must poll the SMBus ladder
stack to determine the source of the alarm. A READALL
command should be issued to read each register that
contains alert bits that are enabled to trigger an alarm.
After determining the source of the alarm, appropriate
actions may be taken by the application. The system
controller should periodically poll all registers with alert
status bits to monitor the status of the MAX11068 SMBus
ladder. This ensures any important events are identified
in a timely manner.
determine whether an active alarm exists. The controller
can then read the status of the SMBus ladder to pinpoint
the location of the alerts that triggered the alarm. The
heartbeat signal propagated down the SMBUs ladder is
received and monitored by the upper port ALRM pin
U
according to Figure 44.
Some alerts may be configured to trigger an alarm
condition by using their alarm mask bits. This allows the
application to choose which alerts should generate an
alarm condition. Figure 45 shows how status alert sig-
COUNT > 17
RESET
CLK
LATCH
DIVIDE
BY 8
RISING EDGE
DETECT
ALRM
ALRTHBEAT
U
UP COUNTER
CLOCK
COUNT < 13
32.768kHz
Figure 44. ALRM Pin and ALRTHBEAT Block Diagram
U
ALRM
U
ALRM
L
ALERT
STATUS BIT
ALARM MASK
ENABLE BIT
Figure 45. LDiagram of Alert Conditions and Associated Alarm Enable Bits
70
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 38. Alert Bits with Descriptions and Corresponding Alarm Mask Bits
ALERT THRESHOLD
ALERT STATUS BIT
(REGISTER.BIT)
ALERT
DESCRIPTION
ALERT CLEAR
CONDITION
ALARM MASK ENABLE
BIT (REGISTER.BIT)
OR TRIGGER
CONDITION
Device reset
occurred
STATUS.RSTSTAT
STATUS.ALRTOV
VAA < V
Write alert bit to 0
Always enabled
POR-FALL
Overvoltage was
detected for at least in the ALRTOVCELL
one cell
Logical OR of bits
Disable active
alert or remove the
overvoltage condition
ADCCFG.ALRMOVEN
register
Disable active
alert or remove
the undervoltage
condition
Undervoltage was
detected for at least in the ALRTUVCELL
one cell
Logical OR of bits
STATUS.ALRTUV
ADCCFG.ALRMUVEN
register
Remove the cause
of the mismatch or
set the threshold to
0xFFF0 to disable the
comparison
Cell-voltage
mismatch between
min and max
MAXCELL - MINCELL
> MSMTCH
STATUS.ALRTMSMTCH
ADCCFG.ALRMMMTCHEN
measurements
Auxiliary input
overvoltage/
undertemperature
Disable the active
alert or remove the
overvoltage condition
AIN0 or AIN1 >
AINUT
STATUS.ALRTTCOLD
STATUS.ALRTTHOT
ADCCFG.ALRMUTEN
ADCCFG.ALRMOTEN
Disable the active
alert or remove
the undervoltage
condition
Auxiliary input
undervoltage/
overtemperature
AIN0 or AIN1 <
AINOT
PEC byte checked
for a received packet
was incorrect
Communication
PEC error
STATUS.ALRTPEC
STATUS.ALRTACK
STATUS.ALRTFMEA
Write alert bit to 0
Write alert bit to 0
ADCCFG.ALRMPEC
ADCCFG.ALRMACK
None
A NACK was
received when an
ACK was expected
Communication
NACK error
At least one alert
from FMEA register
is active
Logical OR of the
alert bits in the FMEA
register
Clear all alerts in the
FMEA register
Disable the active
alert or remove the
undervoltage or
overvoltage condition
and take a new
Auxiliary analog
input 1 is outside
one of the set
thresholds
AIN1 > AINUT or
AIN1 < AINOT
STATUS.ALRTAIN2
None
measurement
Maxim Integrated
71
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 38. Alert Bits with Descriptions and Corresponding Alarm Mask Bits (continued)
ALERT THRESHOLD
ALERT STATUS BIT
(REGISTER.BIT)
ALERT
DESCRIPTION
ALERT CLEAR
CONDITION
ALARM MASK ENABLE
BIT (REGISTER.BIT)
OR TRIGGER
CONDITION
Disable the active
alert or remove the
undervoltage or
overvoltage condition
and take a new
Auxiliary analog
input 0 is outside
one of the set
thresholds
AIN0 > AINUT or
AIN0 < AINOT
STATUS.ALRTAIN1
None
measurement
Each bit [n] is a
logical OR of the
corresponding bit in
the ALRTOVCELL
and ALRTUVCELL
registers
Set CELL[n].OVEN
and CELL[n].UVEN
to 0 or remove
the overvoltage
or undervoltage
Specifies whether
each cell has
ALRTCELL.ALRTCELL[n] an overvoltage
or undervoltage
None; use the ALRTOV
and ALRTUV status bits as
alarm triggers
condition
condition from the cell
CELL[n] >
Set CELL[n].OVEN
to 0 or remove the
overvoltage condition
from the cell
Specifies whether
ALRTOVCELL.
None; use the ALRTOV
status bit as an alarm
trigger
OVTHRSET and
CELL[n].OVEN set
to 1
each cell is in an
ALRTOVCELL[n]
overvoltage state
CELL[n] <
Set CELL[n].UVEN
to 0 or remove
the undervoltage
condition from the cell
Specifies whether
ALRTUVCELL.
None; use the ALRTUV
status bit as an alarm
trigger
UVTHRSET and
CELL[n].UVEN set
to 1
each cell is in an
ALRTUVCELL[n]
undervoltage state
The charge-pump
output VDD has
U
fallen below the
undervoltage
threshold
Remove alert
VDD - GND
<
condition and write
alert bit to 0 alert
condition
U
U
FMEA.ALRTCPUV
FMEA.ALRTHBEAT
FMEA.ALRTREF
FMEA.ALRMCPUV
FMEA.ALRMHBEAT
FMEA.ALRMREF
V
CPUV
Remove alert
Alarm bus
heartbeat signal is
out of specification
ALRM frequency is
L
more than 12.5% from
nominal
condition and write
alert bit to 0 alert
condition
REF pin is
Remove alert
oscillating, most
likely due to an
open-circuit
condition
condition and write
alert bit to 0 alert
condition
Remove alert
VDD pin is open
L
circuit
VAA - VDD > 0.3V
L
typical
condition and write
alert bit to 0 alert
condition
FMEA.ALRTVDDL
FMEA.ALRTGNDL
FMEA.ALRMVDDL
FMEA.ALRMGNDL
Remove alert
GND pin is open
L
circuit
GND - AGND > 0.3V condition and write
L
typical
alert bit to 0 alert
condition
72
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
If SHDN was shorted to the ALRM pin, the ALRM pin
L
L
Shutdown Control
must be protected from seeing the full DCIN voltage. A
resistor value of 100kI is recommended to work across
the entire DCIN voltage range.
The SHDN pin of the MAX11068 is connected in a man-
ner that allows the shutdown/wakeup command to trickle
up through the series of SMBus-laddered packs. The
propagation time is on the order of 3ms per module with
the recommended shutdown circuit. The shutdown func-
tion is intended to be a reset and power-saving mode
for the entire IC. When coming out of shutdown mode,
the device goes through the power-up sequence shown
for the linear regulator once the SHDN pin is above the
inactive state threshold. The shutdown function must still
operate when the VAA is shut down, so it cannot depend
on a Schmitt trigger. A special low-current, high-voltage
circuit is used to detect the state of the SHDN pin. The
shutdown pin has a +1.8V threshold. When SHDN >
1.8V, the MAX11068 turns on and begins regulating
The SHDN pin has a weak internal pulldown resistor in
the order of 12MI. So, a 200kI or similar resistor from
SHDN to GND should be installed to ensure that the
L
SHDN pin is pulled low when the active SHDN signal
is propagated up the SMBus ladder. This resistor is not
needed for applications that tie SHDN high at all times.
2
I C SMBus Ladder
Initialization Sequence
When the MAX11068 becomes functional after any reset
event, its I2C address, broadcast address, and place
in the SMBus ladder are set to a default value. Prior to
performing battery-monitoring tasks, each device must
be configured to operate as part of the SMBus ladder.
The following configuration sequence (Figure 47) is rec-
ommended to initialize the system of SMBus-laddered
modules after a power cycle or change in the number of
battery stack modules.
VDD and VDD . If SHDN < 0.6V, the MAX11068 shuts
down. Figure 46 shows the shutdown circuit interface of
two SMBus ladder devices.
U
L
When SHDN is high for the device, the charge pump
is enabled and begins to charge the capacitors in the
interface circuit. When the voltage of the SHDN pin for
device (n+1) rises above the V threshold, that device
begins its power-up sequence. This action propagates
up the SMBus ladder until the last battery module is
IH
First, the HELLOALL command is sent to sequentially ini-
tialize the individual device addresses. The first device
address is specified in the command byte and should
be chosen carefully based on the application require-
ments. After a successful HELLOALL command, the
ROLLCALL command should be sent. This reads the
ADDRESS register of all properly communicating mod-
ules. When the host sees two consecutive 0xFF bytes,
meaning that all valid data has been received, it should
send a NACK and a STOP bit to halt data flow. Once
the ADDRESS register data is received, the host can
determine how many devices are active on the bus. After
ensuring that the number of active devices matches
what is expected by the application, the host should
send the SETLASTADDRESS command to configure the
last device in the chain to be the heartbeat initiator.
enabled. Conversely, pulling SHDN to GND powers
L
down a module and thus propagates the power down
to all higher SMBus-laddered modules as the charge on
their SHDN capacitors is dissipated. The zener diodes
provide additional ESD protection. The filter capacitors
and resistors are sized to provide robust noise immunity.
The diode from the CP+ pin should be S1B or a similar
low-leakage type for high-temperature stability.
The SHDN pin is a high-voltage input rated to 60V. SHDN
may be tied to DCIN through a resistor instead of using the
interface circuit above for applications that do not require
use of the shutdown mode. The resistor in that case is
necessary for failure-mode effects analysis considerations.
S1B
150I
1kI
CP+
SHDN
DEVICE
(n)
DEVICE
(n+1)
5.6V
100nF
5.6V
68nF
200kI
GND
GND
L
U
Figure 46. Shutdown Circuit Interface
Maxim Integrated
73
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
MAX11068
FULLY FUNCTIONAL
NO
MODULE COUNT
CORRECT?
SYSTEM ERROR
YES
SEND HELLOALL
COMMAND
SEND
SETLASTADDRESS
COMMAND
NACK
COMMUNICATION
ERROR
ACK?
ACK
NACK
COMMUNICATION
ERROR
ACK?
ACK
SEND ROLLCALL
COMMAND
SEND
SETLASTADDRESS
COMMAND AGAIN
YES
ALRTPEC?
NO
NACK
COMMUNICATION
ERROR
ACK?
ACK
CLEAR STATUS REGISTER
BITS TO 0
RECEIVE SLAVE DATA UNTIL
CONSECUTIVE 0xFF BYTES,
THEN NACK THE SLAVE
HEARTBEAT
NO
SYSTEM ERROR
ON ALRM
L
AT HOST?
YES
HOST CALCULATES
NUMBER OF MODULES
MAX11068
COMMUNICATION
INITIALIZED
Figure 47. Communication Initialization Sequence Following Any Reset Event or Module Connection Change
74
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
After the SMBus ladder modules are configured for com-
munication, they should be configured for operation:
6) When the first conversion is complete, process the
cell and auxiliary input channel data and take any
necessary actions.
1) Perform a READALL to check device status:
7) Continue monitoring the system status while initiating
new measurements.
a) The RSTSTAT bit should be set in all devices to
signify a POR event has occurred.
b) The last device in the chain shows an ALRTACK
fault because there is no device above it to
acknowledge its communication.
Changing the
Broadcast Address
If the default broadcast address must be changed for
an application, the host should manage the process
carefully since the READALL and WRITEALL commands
rely on this address for proper operation. Although
a WRITEALL command can be used to change the
address at any time, it is recommended that a broadcast
address change not be performed until after the SMBus
ladder is fully initialized so that subsequent ROLLCALL
or READALL commands may be used to verify the
address change for all devices.
2) Clear the ALRTACK status for the last device using a
WRITEDEVICE or WRITEALL command.
3) Clear the RSTSTAT bit on all devices so that future
power-cycle events can be detected. This also
allows the last device in the daisy-chain to begin
generating the heartbeat signal.
4) Change configuration registers as necessary with
WRITEALL commands:
a)Change the broadcast address in register 0x0F if
a different one is required.
With the device in a fully initialized state, the new broad-
cast address is written to the BROADCAST ADDRESS
register (address 0x0F) using a WRITEALL command,
although a series of WRITEDEVICE commands may be
used as well. Prior to changing the broadcast address,
the host should save the original address in case it is
needed later in the process. Once the WRITEALL com-
mand is issued, it must be verified. The most straightfor-
ward way of accomplishing this is to issue a ROLLCALL
command and count the number of active devices using
the new address. If the count matches what is expected,
the broadcast address change was successful for all
modules. If the count is incorrect, at least one device
rejected the WRITEALL command and the count signi-
fies which module is not responding to the new address.
A WRITEDEVICE command may be used to rewrite to
individual modules, or another WRITEALL command
may be sent to the old broadcast address. After updating
the missing modules, the ROLLCALL procedure should
again be used to make sure all devices are responding
to the new broadcast address. See Figure 48.
b)Configure the undervoltage and overvoltage cell
thresholds in registers 0x18 to 0x1B.
c)Configure the mismatch threshold if required in
register 0x1C.
d)Configure the undertemperature and overtem-
perature thresholds used for thermistor measure-
ments, if required.
e)Configure the auxiliary input-acquisition settling
time in the ACQCFG register if necessary.
f) Enable the cell input channels that are used for
measurement and enable auxiliary channels that
are used.
g)Configure cell-voltage alert enables.
h)Set desired alarm enable flags in the ADCCFG
and FMEA registers.
5) When the device is fully configured, initiate a measure-
ment conversion by setting bit 0 of the SCANCTRL
register (address 0x0D).
Maxim Integrated
75
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
MAX11068
COMMUNICATION
INITIALIZED
USE MODULE COUNT TO
HOST STORES
DETERMINE MODULE NEEDING
ORIGINAL BROADCAST
UPDATE
ADDRESS
SEND NEW BROADCAST
ADDRESS WITH WRITEALL
COMMAND TO ADDRESS 0x0F
REWRITE NEW BROADCAST
ADDRESS TO REGISTER 0x0F
OF AFFECTED MODULES
NACK
NACK
NO
COMMUNICATION
PROPER ACKs?
ACK
ERROR
SEND ROLLCALL
COMMAND USING
NEW ADDRESS
COMMUNICATION
ERROR
PROPER ACKs?
HOST CALCULATES
NUMBER OF MODULES
MODULE COUNT
CORRECT
YES
DISCARD ORIGINAL
BROADCAST ADDRESS
BROADCAST ADDRESS
CHANGE SUCCESSFUL
Figure 48. Broadcast Address Change Procedure
76
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
be readily detected for fault diagnosis and should be
tolerated whenever possible. A number of circuits are
employed within the MAX11068 specifically to detect
Failure Mode and
Effects Analysis
High-voltage battery-pack systems can be subjected
such conditions and progress to a known device state.
to severe stresses during in-service fault conditions
and could experience similar conditions during the
manufacturing and assembly process. The MAX11068
is designed with high regard to these potential states.
Open and short circuits at the package level must
Table 39 summarizes other conditions typical in a nor-
mal manufacturing process along with their effect on the
MAX11068 device. See Table 40 for the failure-mode
effects analysis of the MAX11068.
Table 39. System Fault Modes
CONDITION
EFFECT
DESIGN RECOMMENDATION
See pin-level failure-mode
effects analysis spreadsheet
available from the factory
PCB or IC package open or
short circuit—no stack load
The built-in features of the MAX11068 should ensure low
failure-mode effects risk in most cases.
Random connection of cells to
IC—no stack load
Circuit design of Figures 4 and 5 ensure protection
against random power-supply or ground connections.
No effect
No effect
Random connection of
modules—no stack load
Each module is referenced to its neighbor, so no special
connection order is necessary.
Random connect/disconnect of
communication bus—no stack
load; AC- or DC-coupled
The level-shifted interface design of the MAX11068
Communication from host to the
first break in the daisy-chain bus
ensures that the SHDN, GND , ALRM communication
U
U
bus can be connected at any time with no load.
The level-shifted interface design of the MAX11068
ensures that the SHDN, GND , ALRM communication
U U
Random connect/disconnect of
communication bus—with stack
load; AC- or DC-coupled
Communication from host to the
first break in the daisy-chain bus bus can be connected at any time as long as the power
bus is properly connected.
Connect/disconnect module
interconnect (bus bar)—no stack
load
No effect for DC- or AC-coupled
communication bus
A break in the power bus does not cause a problem as
long as there is no load on the stack.
Removal/fault of module
interconnect (bus bar)—with
stack load
No effect for AC-coupled
communication bus; device
damage for DC-coupled bus
An AC-coupled bus with isolation on the SHDN pin or a
redundant bus bar connection should be used to protect
against this case.
Removal/fault of module
interconnect (bus bar)—with
stack under charge
No effect for AC-coupled
communication bus; device
damage for DC-coupled bus
An AC-coupled bus with isolation on the SHDN pin or a
redundant bus bar connection should be used to protect
against this case.
Maxim Integrated
77
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 40 . Failure-Mode Effects Analysis
PIN
NAME
ACTION
EFFECT
Open or
disconnected
I2C lost communication. No heartbeat.
1
DCIN
Short to
pin 2
ALRTCPUV of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
ALRTCPUV of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
ALRTCPUV of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
ALRTCPUV of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
ALRTCPUV of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
ALRTCPUV of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
ALRTCPUV of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
Open or
disconnected
2
3
4
5
6
7
8
9
CP+
CP-
Short to
pin 3
Open or
disconnected
Short to
pin 4
Open or
disconnected
VDD
U
Short to
pin 5
Open or
disconnected
I2C lost communication. No heartbeat. ALRTCPUV of the FMEA register is set to 1.
ALRTFMEA of the STATUS register is set to 1.
GND
U
Short to
pin 6
The up-device cell registers are read back all 1. ALRTACK of the STATUS register is set to
1. No effect for the single device or the top device.
Open or
disconnected
The up-device cell registers are read back all 1. ALRTACK and ALRTPEC of the STATUS
register are set to 1. No effect for the single device or the top device.
SCL
U
Short to
pin 7
The up-device cell registers are read back all 1. No effect for the single device or the top
device.
Open or
disconnected
The up-device cell registers are read back all 1. ALRTACK of the STATUS register is set to
1. No effect for the single device or the top device.
SDA
U
Short to
pin 8
ALRTPEC and ALRTACK of the STATUS register are set to 1. The up-device cell registers
are read back as the random number. No effect for the single device or the top device.
Open or
disconnected
ALRTHBEAT of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to
1. No heartbeat. No effect for the single device or the top device.
ALRM
U
Short to
pin 9
No effect.
Open or
disconnected
No effect.
N.C.
Short to
pin 10
No effect.
Open or
disconnected
Lost the input status or no drive capability.
10
GPIO2
If both GPIO2 and GPIO1 are configured as the input or the same status for the output,
there is no effect. If they are configured as a different value as the output, it shows the
output of 0V and the part is reset.
Short to
pin 11
78
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 40 . Failure-Mode Effects Analysis (continued)
PIN
NAME
ACTION
EFFECT
Open or
disconnected
Lost the input status or no drive capability.
11
GPIO1
If both GPIO1 and GPIO0 are configured as the input or the same status for the output,
there is no effect. If they are configured as a different value as the output, it shows the
output of 0V and the part is reset.
Short to
pin 12
Open or
disconnected
Lost the input status or no drive capability.
12
13
14
15
16
GPIO0
Short to
pin 13
If the GPIO0 is configured as input or the high status for the output, there is no effect. If it
is configured as low status for the output, the part is reset.
Open or
disconnected
ALRTVDDL of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
I2C lost communication. No heartbeat.
I2C lost communication.
VDD
L
Short to
pin 14
Open or
disconnected
GND
L
Short to
pin 15
I2C lost communication.
Open or
disconnected
I2C lost communication.
SCL
L
Short to
pin 16
I2C lost communication.
Open or
disconnected
I2C lost communication.
SDA
L
Short to
pin 17
I2C lost communication. No heartbeat.
Open or
disconnected
No heartbeat.
The result is dependent on the circuit that drives the SHDN pin. If the circuit has strong
17
ALRM
L
Short to
pin 18
drive capability (ALRM follows SHDN), the heartbeat goes away. Otherwise the heartbeat
L
is OK as the VAA charged faster than the discharge so the part keeps in the normal
working mode.
Open or
disconnected
I2C lost communication as the device is shut down by the internal pulldown resistor.
18
19
20
SHDN
AUXIN2
THRM
Short to
pin 19
The result is dependent on the circuit that drives the SHDN pin and AUXIN2.
Open or
disconnected
The AIN2 register is around 0.
Open or
disconnected
External temperature circuit lost the bias supply. So the AIN0 and AIN1 should be read as
close to 0V. Otherwise there is no effect.
Short to
pin 21
The AIN1 register is close to full scale (0xFFF).
Maxim Integrated
79
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 40 . Failure-Mode Effects Analysis (continued)
PIN
NAME
ACTION
EFFECT
Open or
disconnected
The AIN1 register is around 0.
21
AUXIN1
The result is dependent on the circuit setup of AUXIN1. If REF is driven to VAA, all the
cell input measurements are lower by 1V. If REF is pulled low to AGND, cells 1 to 10
measurement results are all full scale (5V). The DIAG register changes to 0x296 from 0x5D4.
Short to
pin 22
Cells 1 to 12 measurement results vary from 3V to 5V. The DIAG register varies from 0x300
to 0x800. ALRTREF of the FMEA register is set to 1, ALRTFMEA of the STATUS register is
set to 1.
Open or
disconnected
22
REF
Short to
pin 23
Cell 1 to 12 measurement results are all full scale (5V).
The DIAG register changes to 0x296 from 0x5D4.
Open or
disconnected
No effect.
23
24
25
26
27
28
29
30
AGND
VAA
C0
Short to
pin 24
I2C lost communication and no heartbeat.
Open or
disconnected
ALRTVDDL of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
I2C lost communication and no heartbeat.
Short to
pin 25
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
Short to
pin 26
V
= 1V (3V lower).
CELL1
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
C1
Short to
pin 27
V
CELL2
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
C2
Short to
pin 28
V
CELL3
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
C3
Short to
pin 29
V
CELL4
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
C4
Short to
pin 30
V
CELL5
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
C5
Short to
pin 31
V
CELL6
80
Maxim Integrated
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Table 40 . Failure-Mode Effects Analysis (continued)
PIN
NAME
ACTION
EFFECT
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
31
C6
Short to
pin 32
V
= 0V.
CELL7
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
32
33
34
35
36
C7
C8
Short to
pin 33
V
CELL8
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
Short to
pin 34
V
CELL9
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
C9
Short to
pin 35
V
CELL10
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
C10
C11
Short to
pin 36
V
CELL11
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
= 0V.
Short to
pin 37
V
CELL12
Open or
disconnected
This situation can be detected by the cell sense line open-circuit detection feature.
ALRTCPUV of the FMEA register is set to 1. ALRTFMEA of the STATUS register is set to 1.
37
38
C12
HV
Short to
pin 38
Open or
disconnected
V
= 0.6V (3.4V lower).
CELL12
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0 0 81
38 TSSOP
U38-1
Maxim Integrated
81
MAX11068
12-Channel, High-Voltage Sensor, Smart
Data-Acquisition Interface
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
6/10
Initial release
—
Maxim cannot me responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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