MAX1108_03 [MAXIM]
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs; 单电源，低功耗， 2通道，串行8位ADC
| 型号： | MAX1108_03 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs |
| 文件： | 总20页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1399; Rev 1; 6/03
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
General Description
Features
The MAX1108/MAX1109 low-power, 8-bit, dual-channel,
analog-to-digital converters (ADCs) feature an internal
track/hold (T/H) voltage reference, clock, and serial inter-
face. The MAX1108 is specified from +2.7V to +3.6V and
consumes only 105µA. The MAX1109 is specified from
+4.5V to +5.5V and consumes only 130µA. The analog
inputs are software configurable, allowing unipolar/bipolar
and single-ended/differential operation; battery monitor-
ing capability is also included.
ꢀ Single Supply: +2.7V to +3.6V (MAX1108)
+4.5V to +5.5V (MAX1109)
ꢀ Low Power: 105µA at +3V and 50ksps
0.5µA in Power-Down Mode
ꢀ Software-Configurable Unipolar or Bipolar Inputs
ꢀ Input Voltage Range: 0 to V
ꢀ Internal Track/Hold
DD
The full-scale analog input range is determined by the
internal reference of +2.048V (MAX1108) or +4.096V
(MAX1109), or by an externally applied reference rang-
ꢀ Internal Reference: +2.048V (MAX1108)
+4.096V (MAX1109)
ing from 1V to V . The MAX1108/MAX1109 also feature
DD
ꢀ Reference Input Range: 1V to V
DD
a software power-down mode that reduces power con-
sumption to 0.5µA when the device is not in use. The
4-wire serial interface directly connects to SPI™, QSPI™,
and MICROWIRE™ devices without external logic.
Conversions up to 50ksps are performed using either the
internal clock or an external serial-interface clock.
ꢀ SPI/QSPI/MICROWIRE-Compatible Serial Interface
ꢀ V Monitoring Mode
DD
ꢀ Small 10-Pin µMAX Package
The MAX1108 and MAX1109 are available in a 10-pin
µMAX package with a footprint that is just 20% of an
8-pin plastic DIP.
Ordering Information
PART
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
10 µMAX
MAX1108CUB
MAX1108EUB
MAX1109CUB
MAX1109EUB
Applications
Portable Data Logging
10 µMAX
10 µMAX
Hand-Held Measurement Devices
Medical Instruments
10 µMAX
System Diagnostics
Functional Diagram
Solar-Powered Remote Systems
4–20mA-Powered Remote Systems
Receive-Signal Strength Indicators
V
DD
CS
SCLK
OUTPUT
SHIFT
REGISTER
INPUT
SHIFT
REGISTER
DOUT
DIN
Pin Configuration
MAX1108
MAX1109
INTERNAL
OSCILLATOR
TOP VIEW
CONTROL
LOGIC
V
1
2
3
4
5
10 SCLK
DD
SAR
CH0
CH1
T/H
ANALOG
INPUT
MUX
CH0
CH1
GND
REF
9
8
7
6
DOUT
DIN
MAX1108
MAX1109
COM
CHARGE
REDISTRIBUTION
DAC
CS
INTERNAL
REFERENCE
COM
REF
µMAX
GND
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND..............................................................-0.3V to +6V
Operating Temperature Ranges
CH0, CH1, COM, REF, DOUT to GND .......-0.3V to (V
DIN, SCLK, CS to GND ............................................-0.3V to +6V
+ 0.3V)
MAX110_CUB......................................................0°C to +70°C
MAX110_EUB ...................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
Continuous Power Dissipation (T = +70°C)
A
10-pin µMAX (derate 5.6mW/°C above +70°C)............444mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1108
(V
= +2.7V to +3.6V; unipolar input mode; COM = GND, f
= 500kHz, external clock mode (50% duty cycle); 10 clocks/conver-
DD
SCLK
sion cycle (50ksps); 1µF capacitor at REF, external +2.048V reference at REF; T = T
to T
; unless otherwise noted. Typical
MAX
A
MIN
values are at T = +25°C.)
A
PARAMETER
DC ACCURACY
Resolution
SYMBOL
CONDITIONS
MIN
8
TYP
MAX
UNITS
bits
LSB
LSB
LSB
V
V
= 2.7V to 3.6V
0.15
0.2
0.5
DD
Relative Accuracy (Note 1)
Differential Nonlinearity
Offset Error
INL
= 5.5V (Note 2)
DD
DNL
No missing codes over temperature
1
1
V
DD
V
DD
= 2.7V to 3.6V
= 5.5V (Note 2)
0.2
0.5
Gain Error (Note 3)
1
1
LSB
Gain Temperature Coefficient
0.8
ppm/°C
T
T
= +25°C
A
Total Unadjusted Error
TUE
LSB
= T
to T
0.5
0.1
50
A
MIN
MAX
Channel-to-Channel
Offset Matching
LSB
mV
V
DD
/ 2 Sampling Accuracy
DYNAMIC PERFORMANCE (10kHz sine-wave input, 2.048Vp-p, 50ksps, 500kHz external clock)
Signal-to-Noise Plus Distortion
SINAD
49
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Full-Power Bandwidth
ANALOG INPUTS
SFDR
68
1.5
0.8
dB
BW
-3dB rolloff
MHz
MHz
-3dB
Unipolar input, V
= 0
0
V
REF
COM
Input Voltage Range (Note 4)
V
CH_
V
Bipolar input, V
referenced to COM or CH1
or V
= V
/ 2,
COM
CH1
REF
V
REF
/ 2
On/off-leakage current,
Multiplexer Leakage Current
Input Capacitance
0.01
18
1
µA
pF
V
COM
or V = 0 or V
CH DD
C
IN
2
_______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS—MAX1108 (continued)
(V
= +2.7V to +3.6V; unipolar input mode; COM = GND, f
= 500kHz, external clock mode (50% duty cycle); 10 clocks/conver-
DD
SCLK
sion cycle (50ksps); 1µF capacitor at REF, external +2.048V reference at REF; T = T
to T
; unless otherwise noted. Typical
MAX
A
MIN
values are at T = +25°C.)
A
PARAMETER
TRACK/HOLD
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal clock
35
Conversion Time (Note 5)
t
µs
CONV
External clock, 500kHz, 10 sclks/conv
External clock, 2MHz
20
1
Track/Hold Acquisition Time
Aperture Delay
t
µs
ns
ACQ
10
Aperture Jitter
<50
400
ps
Internal Clock Frequency
kHz
kHz
MHz
50
500
2
External Clock Frequency Range
For data transfer only
INTERNAL REFERENCE
Output Voltage
V
1.968
2.048
150
50
2.128
V
µA
REF
REF Short-Circuit Current
REF Tempco
I
(Note 6)
REFSC
ppm/°C
mV
Load Regulation
0 to 0.5mA (Note 7)
2.5
Capacitive Bypass at REF
EXTERNAL REFERENCE
Input Voltage Range
1
µF
1.0
V
+ 0.05
20
V
DD
+2.048V at REF, full scale,
500kHz external clock
Input Current
1
µA
POWER REQUIREMENTS
Supply Voltage
V
I
2.7
3
5.5
V
DD
Internal reference
External reference
105
70
250
V
= 2.7V to 3.6V,
DD
C = 10pF
L
µA
Internal reference
130
95
Supply Current (Notes 2, 8)
V
DD
= 5.5V,
DD
C = 10pF
L
External reference
Power down, V
= 2.7V to 3.6V (Note 9)
0.5
0.4
2.5
4
DD
Power-Supply Rejection (Note 10)
PSR
Full-scale input, V
= 2.7V to 3.6V
mV
DD
DIGITAL INPUTS (DIN, SCLK, and CS)
V
V
≤ 3.6V
2
3
V
V
DD
Threshold Voltage High
V
IH
> 3.6V
DD
Threshold Voltage Low
Input Hysteresis
V
0.8
V
IL
V
0.2
15
V
HYST
Input Current High
Input Current Low
Input Capacitance
I
IH
1
1
µA
µA
pF
I
IL
C
IN
_______________________________________________________________________________________
3
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS—MAX1108 (continued)
(V
= +2.7V to +3.6V; unipolar input mode; COM = GND, f
= 500kHz, external clock mode (50% duty cycle); 10 clocks/conver-
DD
SCLK
sion cycle (50ksps); 1µF capacitor at REF, external +2.048V reference at REF; T = T
to T
; unless otherwise noted. Typical
MAX
A
MIN
values are at T = +25°C.)
A
PARAMETER
DIGITAL OUTPUT (DOUT)
Output High Voltage
SYMBOL
CONDITIONS
MIN
- 0.5
TYP
MAX
UNITS
V
OH
I
I
I
= 0.5mA
V
V
V
SOURCE
DD
= 5mA
0.4
10
SINK
SINK
Output Low Voltage
V
OL
= 16mA
0.8
0.01
15
V
Three-State Leakage Current
I
L
µA
pF
CS = V
CS = V
DD
Three-State Output Capacitance
C
OUT
DD
TIMING CHARACTERISTICS (Figures 8, 9, and 10)
Acquisition Time
t
1.0
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ACQ
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
t
100
0
DS
DH
DO
t
t
Figure 1, C
Figure 1, C
Figure 2, C
= 100pF
= 100pF
= 100pF
20
200
240
240
LOAD
LOAD
LOAD
t
DV
t
TR
t
100
0
CSS
CSH
t
t
200
200
CH
t
CL
Wake-Up Time
External reference
20
12
t
WAKE
Internal reference (Note 11)
ELECTRICAL CHARACTERISTICS—MAX1109
(V
= +4.5V to +5.5V; unipolar input mode; COM = GND, f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
DD
SCLK
cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; T = T
to T
; unless otherwise noted. Typical values
MAX
A
MIN
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
8
bits
LSB
Relative Accuracy (Note 1)
Differential Nonlinearity
Offset Error
INL
V
= 4.5V to 5.5V
0.15
0.2
0.5
1
DD
DNL
No missing codes over temperature
= 4.5V to 5.5V
LSB
V
DD
1
LSB
Gain Error (Note 3)
Gain Temperature Coefficient
1
LSB
0.8
ppm/°C
T
T
= +25°C
1
A
Total Unadjusted Error
TUE
LSB
= T
to T
0.5
0.1
50
A
MIN
MAX
Channel-to-Channel
Offset Matching
LSB
mV
V
DD
/ 2 Sampling Accuracy
4
_______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS—MAX1109 (continued)
(V
= +4.5V to +5.5V; unipolar input mode; COM = GND, f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
DD
SCLK
cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; T = T
to T
; unless otherwise noted. Typical values
MAX
A
MIN
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (10kHz sine-wave input, 4.096Vp-p, 50ksps, 500kHz external clock)
Signal-to-Noise Plus Distortion
SINAD
THD
49
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
-70
Spurious Free Dynamic Range
Small-Signal Bandwidth
Full-Power Bandwidth
ANALOG INPUTS
SFDR
68
1.5
0.8
dB
BW
-3dB rolloff
MHz
MHz
-3dB
Unipolar input, V
= 0
0
V
REF
COM
Input Voltage Range (Note 4)
Multiplexer Leakage Current
V
V
CH_
Bipolar input, V
referenced to COM or CH1
or V
= V
/ 2,
COM
CH1
REF
V
REF
/ 2
On/off-leakage current,
0.01
18
1
µA
pF
V
CH
= 0 or V
DD
Input Capacitance
C
IN
TRACK/HOLD
Internal clock
35
Conversion Time (Note 5)
t
µs
CONV
External clock, 500kHz, 10 sclks/conv
External clock, 2MHz
20
1
Track/Hold Acquisition Time
Aperture Delay
t
µs
ns
ACQ
10
Aperture Jitter
<50
400
ps
Internal Clock Frequency
kHz
kHz
MHz
50
500
2
External Clock Frequency Range
For data transfer only
0 to 0.5mA (Note 7)
INTERNAL REFERENCE
Output Voltage
V
3.936
4.096
5
4.256
V
mA
REF
REF Short-Circuit Current
REF Tempco
I
REFSC
50
ppm/°C
mV
Load Regulation
2.5
Capacitive Bypass at REF
EXTERNAL REFERENCE
Input Voltage Range
1
µF
1.0
V
+ 0.05
20
V
DD
+4.096V at REF, full scale,
500kHz external clock
Input Current
1
µA
_______________________________________________________________________________________
5
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS—MAX1109 (continued)
(V
= +4.5V to +5.5V; unipolar input mode; COM = GND, f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
DD
SCLK
cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; T = T
to T
; unless otherwise noted. Typical values
MAX
A
MIN
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Voltage
V
DD
4.5
5
5.5
V
V
DD
= 4.5V to 5.5V,
Internal reference
130
250
C = 10pF,
L
full-scale input
µA
Supply Current (Notes 2, 8)
I
DD
External reference
95
Power down, V
= 4.5V to 5.5V (Note 9)
0.5
2.5
4
DD
External reference = +4.096V,
full-scale input, V = 4.5V to 5.5V
Power-Supply Rejection (Note 10)
PSR
0.4
mV
DD
DIGITAL INPUTS (DIN, SCLK, and CS)
Threshold Voltage High
Threshold Voltage Low
Input Hysteresis
V
3
V
V
IH
V
0.8
IL
V
0.2
15
V
HYST
Input Current High
I
IH
1
1
µA
µA
pF
Input Current Low
I
IL
Input Capacitance
C
IN
DIGITAL OUTPUT (DOUT)
Output High Voltage
V
I
I
I
= 0.5mA
V - 0.5
DD
V
V
OH
SOURCE
= 5mA
0.4
10
SINK
SINK
Output Low Voltage
V
OL
= 16mA
0.8
0.01
15
Three-State Leakage Current
I
µA
pF
CS = V
CS = V
L
DD
Three-State Output Capacitance
C
OUT
DD
TIMING CHARACTERISTICS (Figures 8, 9, and 10)
Acquisition Time
t
1.0
µs
ns
ns
ns
ns
ns
ACQ
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
t
100
0
DS
DH
DO
t
t
Figure 1, C
Figure 1, C
Figure 2, C
= 100pF
= 100pF
= 100pF
20
200
240
240
LOAD
LOAD
LOAD
t
DV
t
TR
6
_______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS—MAX1109 (continued)
(V
= +4.5V to +5.5V; unipolar input mode; COM = GND, f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
DD
SCLK
cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; T = T
to T
; unless otherwise noted. Typical values
MAX
A
MIN
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
100
0
TYP
MAX
UNITS
ns
t
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
CSS
t
ns
CSH
t
200
200
ns
CH
t
CL
ns
External reference
Internal reference (Note 11)
20
12
µs
Wake-Up Time
t
WAKE
ms
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 2: See Typical Operating Characteristics.
Note 3:
V
REF
= +2.048V (MAX1108), V
= +4.096V (MAX1109), offset nulled.
REF
Note 4: Common-mode range (CH0, CH1, COM) GND to V
.
DD
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle (Figures 6 and 8).
Note 6: REF supplies typically 2.5mA under normal operating conditions.
Note 7: External load should not change during the conversion for specified accuracy.
Note 8: Power consumption with CMOS levels.
Note 9: Power-down test performed using the following sequence 1) SHDN 5bit = 0 in the configuration register; 2) Wait for 10
SCLK cycles to complete current conversion; 3) Measure shutdown current with CS, SCLK, D = V
or GND.
IN
DD
Note 10: Measured as V (2.7V) - V (3.6V) for MAX1108, and measured as V (4.5V) - V (5.5V) for MAX1109.
FS
FS
FS
FS
Note 11: 1µF at REF, internal reference settling to 0.5LSB.
Typical Operating Characteristics
(V
= +3.0V (MAX1108), V
= +5.0V (MAX1109); external conversion mode; f
= 500kHz; 50ksps; external reference; 1µF at
DD
DD
SCLK
REF; T = +25°C; unless otherwise noted.)
A
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
0.50
200
200
180
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
180
C
= 47pF
LOAD
V
= 5V
= 3V
DD
160
140
120
100
80
160
140
120
100
80
C
LOAD
= 10pF
V
DD
60
60
D
OUT
= 10101010
D
C
= 10101010
LOAD
INTERNAL REFERENCE
40
40
MAX1108 (2.7V TO 5.5V)
MAX1109 (4.5V TO 5.5V)
INTERNAL REFERENCE
OUT
= 10pF
20
20
0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
1
2
3
4
5
6
-40 -20 20
0
40
60
80
100
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
Typical Operating Characteristics (continued)
(V
= +3.0V (MAX1108), V
= +5.0V (MAX1109); external conversion mode; f = 500kHz; 50ksps; external reference; 1µF at
SCLK
DD
DD
REF; T = +25°C; unless otherwise noted.)
A
OFFSET ERROR vs. TEMPERATURE
OFFSET ERROR vs. REFERENCE VOLTAGE
OFFSET ERROR vs. SUPPLY VOLTAGE
0.5
0.5
0.4
0.20
0.4
0.3
0.15
0.10
0.05
0
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.10
-0.15
-0.20
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80
100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. REFERENCE VOLTAGE
GAIN ERROR vs. TEMPERATURE
0.5
0.4
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.3
0.2
0.6
0.4
0.1
0.2
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
-40 -20
0
20
40
60
80
100
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
vs. CODE
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.5
0.4
0.5
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.4
-0.5
0
50
100
150
200
250
300
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
DIGITAL CODE
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
Typical Operating Characteristics (continued)
(V
= +3.0V (MAX1108), V
= +5.0V (MAX1109); external conversion mode; f = 500kHz; 50ksps; external reference; 1µF at
SCLK
DD
DD
REF; T = +25°C; unless otherwise noted.)
A
INTEGRAL NONLINEARITY
FFT PLOT
vs. CODE
CONVERSION TIME vs. SUPPLY VOLTAGE
20
0
0.5
21.0
f
f
= 9997Hz, 2Vp-p
CH_
0.4
0.3
0.2
0.1
0
INTERNAL CONVERSION MODE
20.5
= 53.25kHz
SAMPLE
-20
-40
-60
-80
-100
20.0
19.5
19.0
18.5
18.0
-0.1
-0.2
-0.3
-0.4
-0.5
0
5
10
15
20
25
30
0
50
100
150
200
250
300
0
1
2
3
4
5
6
FREQUENCY (kHz)
DIGITAL CODE
SUPPLY VOLTAGE (V)
NORMALIZED REFERENCE VOLTAGE
vs. TEMPERATURE
CHANNEL-TO-CHANNEL
CROSSTALK vs. FREQUENCY
CONVERSION TIME vs. TEMPERATURE
25
24
23
22
21
20
19
18
17
16
15
1.0010
1.0005
1.0000
0.9995
0.9990
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
= V
REFp-p
INTERNAL CONVERSION MODE
CH_OFF
V
DD
= 3V
V
DD
= 5V
0.9985
0.9980
-40 -20
0
20
40
60
80
100
-40 -20
0
20
40
60
80
100
0
5
10
15
20
25
TEMPERATURE (°C)
TEMPERATURE (°C)
FREQUENCY (kHz)
Pin Description
PIN
1
NAME
FUNCTION
V
DD
Positive Supply Voltage
Sampling Analog Inputs
Ground
2, 3
4
CH0, CH1
GND
Reference voltage for analog-to-digital conversion (internal or external reference). Reference input for
external reference. Bypass internal reference with 1µF capacitor to GND.
5
6
7
REF
COM
CS
Common reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
0.5LSB during conversion.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high
impedance.
8
9
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK.
DOUT
Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is high.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the
conversion speed.
10
SCLK
_______________________________________________________________________________________
9
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
V
DD
VDD
3kΩ
3kΩ
DOUT
DOUT
DOUT
DOUT
C
LOAD
3kΩ
C
LOAD
3kΩ
C
LOAD
C
LOAD
DGND
DGND
DGND
a) High-Z to V and V to V
OH
DGND
b) High-Z to V and V to V
OL
OH
OL
OL
OH
a) V to High-Z
b) V to High-Z
OH
OL
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________Detailed Description
V
The MAX1108/MAX1109 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible
serial interface provides easy interface to microproces-
sors (µPs). No external hold capacitors are required. All
of the MAX1108/MAX1109 operating modes are soft-
ware-configurable: internal or external reference, inter-
nal or external conversion clock, single-ended unipolar
or pseudo-differential unipolar/bipolar conversion, and
power down (Table 1).
DD
V
DD
V
CH0
CH1
DD
0.1µF
1µF
ANALOG
INPUTS
GND
COM
CPU
MAX1108
MAX1109
I/O
CS
SCLK
DIN
REF
SCK (SK)
MOSI (SO)
1µF
Analog Inputs
DOUT
MISO (SI)
Track/Hold
The input architecture of the ADCs is illustrated in the
equivalent-input circuit of Figure 4 and is composed of
the T/H, the input multiplexer, the input comparator, the
switched capacitor DAC, the reference, and the auto-
zero rail.
V
SS
Figure 3. Typical Operating Circuit
GND
The analog-inputs configuration is determined by the
control-byte through the serial interface as shown in
Table 2 (see Modes of Operation section and Table 1).
The eight modes of operation include single-ended,
CAPACITIVE DAC
REF
pseudo-differential, unipolar/bipolar, and a V
moni-
DD
CH1
C
HOLD
18pF
toring mode. During acquisition and conversion, only
one of the switches in Figure 4 is closed at any time.
COMPARATOR
CH0
The T/H enters its tracking mode on the falling clock
edge after bit 4 (SEL0) of the control byte has been
shifted in. It enters its hold mode on the falling edge
after the bit 2 (I/EREF) of the control byte has been
shifted in.
COM
R
IN
6.5kΩ
HOLD
V
/ 2
DD
TRACK
GND
For example, If CH0 and COM are chosen (SEL2 =
SEL1 = SEL0 = 1) for conversion, CH0 is defined as the
sampled input (SI), and COM is defined as the refer-
ence input (RI). During acquisition mode, the CH0
switch and the T/H switch are closed, charging the
AUTOZERO
RAIL
Figure 4. Equivalent Input Circuit
10 ______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
holding capacitor C
through R . At the end of
The input configuration selection also determines
unipolar or bipolar conversion mode. The common-
HOLD
IN
acquisition the T/H switch opens and C
is con-
HOLD
nected to COM, retaining charge on C
as a sam-
mode input range of CH0, CH1, and COM is 0 to +V
.
HOLD
DD
ple of the signal at CH0, and the difference between
CH0 and COM is the converted signal. Once conver-
sion is complete, the T/H returns immediately to its
tracking mode. This procedure holds for the different
combinations summarized in Table 2.
In unipolar mode, full scale is achieved when (SI - RI) =
; in bipolar mode, full scale is achieved when (SI
V
REF
- RI) = V
/ 2. In unipolar mode, SI must be higher
REF
than RI; in bipolar mode, SI can span above and below
RI provided that it is within the common-mode range.
The time available for the T/H to acquire an input signal
ACQ
at the maximum clock frequency of 2MHz. The acquisi-
tion time is also the minimum time needed for the signal
to be acquired. It is calculated by:
Conversion Process
The comparator negative input is connected to the auto-
zero rail. Since the device requires only a single supply,
the ZERO node at the input of the comparator equals
(t
) is determined by the clock frequency, and is 1µs
V
/2. The capacitive DAC restores node ZERO to have
DD
t
= 6(R + R )18pF
S IN
0V difference at the comparator inputs within the limits
of 8-bit resolution. This action is equivalent to transfer-
ACQ
where R = 6.5kΩ, R = the source impedance of
IN
S
ACQ
ring a charge of 18pF(V
- V ) from C
to the
HOLD
IN+
IN-
the input signal, and t
is never less than 1µs.
binary-weighted capacitive DAC which, in turn, forms a
digital representation of the analog-input signal.
Note that source impedances below 2.7kΩ do not
significantly affect the AC performance of the ADC at
the maximum clock speed. If the input-source imped-
ance is higher than 3kΩ, the clock speed must be
reduced accordingly.
Input Voltage Range
Internal protection diodes that clamp the analog input
to V
and AGND allow the channel input pins (CH0,
DD
CH1, and COM) to swing from (AGND - 0.3V) to (V
+
DD
Pseudo-Differential Input
The MAX1108/MAX1109 input configuration is pseudo-
differential to the extent that only the signal at the sam-
pled input (SI) is stored in the holding capacitor
0.3V) without damage. However, for accurate conver-
sions, the inputs must not exceed (V
less than (GND - 50mV).
+ 50mV) or be
DD
(C
). The reference input (RI) must remain stable
If the analog input voltage on an “off” channel
exceeds 50mV beyond the supplies, the current
should be limited to 2mA to maintain conversion
accuracy on the “on” channel.
HOLD
within 0.5LSB ( 0.1LSB for best results) in relation to
GND during a conversion. Sampled input and refer-
ence input configuration is determined by bit6–bit4
(SEL2–SEL0) of the control byte (Table 2).
The MAX1108/MAX1109 input range is from 0 to V
;
DD
If a varying signal is applied at the selected reference
input, its amplitude and frequency need to be limited.
The following equations determine the relationship
between the maximum signal amplitude and its fre-
quency to maintain 0.5LSB accuracy:
unipolar or bipolar conversion is available. In unipolar
mode, the output code is invalid (code zero) when a
negative input voltage (or a negative differential input
voltage) is applied. The reference input-voltage range
at REF is from 1V to (V
+ 50mV.)
DD
Assuming a sinusoidal signal at the reference input
Input Bandwidth
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
v
= V sin(2πft)
RI
RI
the maximum voltage variation is determined by:
dv 1 LSB
V
RI
REF
max
= 2πf⋅v
≤
=
RI
8
dt
t
CONV
2 t
CONV
a 60Hz signal at RI with an amplitude of 1.2V will gener-
ate a 0.5LSB of error. This is with a 35µs conversion
Serial Interface
The MAX1108/MAX1109 have a 4-wire serial interface.
The CS, DIN, and SCLK inputs are used to control the
device, while the three-state DOUT pin is used to
access the result of conversion.
time (maximum t
in internal conversion mode) and
CONV
a reference voltage of +4.096V. When a DC reference
voltage is used at RI, connect a 0.1µF capacitor to
GND to minimize noise at the input.
______________________________________________________________________________________ 11
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
The serial interface provides easy connection to micro-
controllers with SPI, QSPI and MICROWIRE serial inter-
faces at clock rates up to 2MHz. For SPI and QSPI, set
CPOL = CPHA = 0 in the SPI control registers of the
microcontroller. Figure 5 shows the MAX1108/MAX1109
common serial-interface connections.
DOUT is active when CS is low and high impedance
when CS is high. DOUT does not accept external volt-
ages greater than V . In external-clock mode, data is
DD
clocked out at the maximum clock rate of 500kHz while
conversion is in progress. In internal-clock mode, data
can be clocked out at up to 2MHz clock rate.
Digital Inputs
The logic levels of the MAX1108/MAX1109 digital input
are set to accept voltage levels from both +3V and +5V
systems, regardless of the supply voltages. Input data
(control byte) is clocked in at the DIN pin on the rising
edge of serial clock (SCLK). CS is the standard chip-
select signal which enables communication with the
device. SCLK is used to clock data in and out of serial
interface. In external clock mode, SCLK also sets the
conversion speed.
Modes of Operation
The MAX1108/MAX1109 feature single-ended or pseu-
do-differential operation in unipolar or bipolar configu-
ration. The device is programmed through the input
control-byte at the DIN pin of the serial interface
(Table 1). Table 2 shows the analog-input configuration
and Table 3 shows the input-voltage ranges in unipolar
and bipolar configuration.
How to Start a Conversion
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a
bit from DIN into the MAX1108/MAX1109’s internal shift
register. After CS falls, the first arriving logic “1” bit at
DIN defines the MSB of the control byte. Until this first
start bit arrives, any number of logic “0” bits can be
clocked into DIN with no effect. Table 1 shows the con-
trol-byte format.
Digital Output
Output data is read on the rising edge of SCLK at
DOUT, MSB first (D7). In unipolar input mode, the out-
put is straight binary. For bipolar input mode, the output
is twos-complement (see Transfer Function section).
I/O
CS
Using the Typical Operating Circuit (Figure 3), the sim-
plest software interface requires two 8-bit transfers to
perform a conversion (one 8-bit transfer to configure
the ADC, and one 8-bit transfer to clock out the 8-bit
conversion result). Figure 6 shows a single-conversion
timing diagram using external clock mode.
SCK
SCLK
MISO
MOSI
DOUT
DIN
+3V
MAX1108
MAX1109
SS
Clock Modes
The MAX1108/MAX1109 can use either an external ser-
ial clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the devices. Bit
3 of control-byte (I/ECLK) programs the clock mode.
Figure 8 shows the timing characteristics common to
both modes.
a) SPI
CS
CS
SCK
SCLK
MISO
MOSI
DOUT
DIN
+3V
MAX1108
MAX1109
SS
External Clock
In external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
conversion steps. In this mode the clock frequency
must be between 50kHz and 500kHz. Single-conver-
sion timing using an external clock begins with a falling
edge on CS. When this occurs, DOUT leaves the high
impedance state and goes low. The first “1” clocked
into DIN by SCLK after CS is set low is considered as
the start bit. The next seven clocks latch in the rest of
the control byte. On the falling edge of the fourth clock,
track mode is enabled, and on the falling edge of the
sixth clock, acquisition is complete and conversion is
b) QSPI
I/O
SK
CS
SCLK
SI
DOUT
DIN
SO
MAX1108
MAX1109
c) MICROWIRE
Figure 5. Common Serial-Interface Connections
12 ______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
Table 1. Control Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
I/ECLK
I/EREF
REFSHDN
SHDN
BIT
NAME
DESCRIPTION
7 (MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
Selects the mode of operation (Table 2).
1 = external clock, 0 = internal clock. The SAR can be driven by the internal oscillator, or with the
SCLK signal.
3
2
I/ECLK
I/EREF
1 = internal reference, 0 = external reference. Internal reference selects +2.048V (MAX1108) or
+4.096V (MAX1109), or an external reference can be applied to the REF pin.
1 = operational (if I / EREF = 1), 0 = reference shutdown. When using an external reference, power
consumption can be minimized by powering down the internal reference separately (I / EREF = 0).
REFSHDN must be set to 0 when SHDN = 0.
1
REFSHDN
SHDN
1 = operational, 0 = power down. For a full power down set REFSHDN = SHDN = 0. (See Power-
Down Mode section.)
0 (LSB)
Table 2. Conversion Configuration
SAMPLED INPUT
(SI)
REFERENCE INPUT
(RI)
SEL2
SEL1
SEL0
CONVERSION MODE
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CH0
CH1
CH0
CH1
CH0
CH1
CH0
COM
COM
GND
GND
COM
COM
CH1
Unipolar
Unipolar
Unipolar
Unipolar
Bipolar
Bipolar
Bipolar
V
/ 2
GND
Unipolar
DD
Table 3. Full- and Zero-Scale Voltages
UNIPOLAR MODE
BIPOLAR MODE
Negative
Full Scale
Zero
Scale
Positive
Full Scale
Zero Scale
Full Scale
RI + V
RI*
RI - V
/ 2
RI
RI + V
/ 2
REF
REF
REF
*RI = Reference Input (Table 2)
______________________________________________________________________________________ 13
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
initiated. The MSB successive-approximation bit deci-
Internal Clock
sion is made on the rising edge of the seventh SCLK.
On the falling edge of the eighth SCLK, the MSB is
clocked out on the DOUT pin; on each of the next
seven SCLK falling edges, the remaining bits of conver-
sion are clocked out. Zeros are clocked out on DOUT
after the LSB has been clocked out, until CS is dis-
abled. Then DOUT becomes high impedance and the
part is ready for another conversion (Figure 6).
Internal clock mode frees the µP from the burden of
running the SAR conversion clock. This allows the con-
version results to be read back at the processor’s con-
venience, at any clock rate up to 2MHz.
An internal register stores data when the conversion is
in progress. On the falling edge of the fourth SCLK,
track mode is enabled, and on the falling edge of the
eighth SCLK, acquisition is complete and internal con-
version is initiated. The internal 400kHz clock com-
pletes the conversion in 20µs typically (35µs max), at
which time the MSB of the conversion is present at the
DOUT pin. The falling edge of SCLK clocks the remain-
ing data out of this register at any time after the conver-
sion is complete (Figure 8).
The conversion must complete in 1ms, or droop on the
sample-and-hold capacitors may degrade conversion
results. Use internal clock mode if the serial-clock fre-
quency is less than 50kHz, or if serial-clock interruptions
could cause the conversion interval to exceed 1ms.
CS
1
4
8
12
16
20
SCLK
MSB
LSB
REF
SHDN
SEL2
SEL1 SEL0 I/ECLK I/EREF
SHDN
DIN
START
MSB
D7
LSB
D0
D6
D5
D4
D3
D2
D1
DOUT
t
ACQ
t
A/D STATE
CONV
IDLE
IDLE
Figure 6. Single Conversion Timing, External Clock Mode
CS
• • •
• • •
t
t
t
CSH
CSS
CH
t
t
CL
CSH
SCLK
t
DS
t
DH
DIN
• • •
• • •
t
DV
t
t
TR
DO
DOUT
Figure 7. Detailed Serial-Interface Timing
14 ______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
Quick Look
To quickly evaluate the MAX1108/MAX1109’s analog
performance, use the circuit of Figure 9. The device
requires a control byte to be written to DIN before each
CS does not need to be held low once a conversion is
started. Pulling CS high prevents data from being
clocked into the MAX1108/MAX1109 and three-states
DOUT, but it does not adversely affect an internal
clock-mode conversion already in progress. In this
mode, data can be shifted in and out of the
MAX1108/MAX1109 at clock rates up to 2MHz, provid-
conversion. Tying CS to GND and DIN to V
feeds in
DD
control bytes of FFH. In turn, this triggers single-ended,
unipolar conversions on CH0 in relation to COM in
external clock mode without powering down between
conversions. Apply an external 50kHz to 500kHz clock
ed that the minimum acquisition time (t
above 1µs.
) is kept
ACQ
CS
1
4
8
10
14
18
SCLK
REF
SHDN
SEL2 SEL0 SEL1 I/EREF I/ECLK
SHDN
DIN
START
DOUT
D4
D7
D6
D5
D3
D2
D1
D0
t
CONV
t
ACQ
A/D STATE
IDLE
IDLE
35µs MAX
Figure 8. Single Conversion Timing, Internal Clock Mode
V
DD
V
SUPPLY
OSCILLOSCOPE
0.1µF
1µF
DOUT*
SCLK
LSB
MSB
GND
CS
MAX1108
MAX1109
ANALOG
INPUT
CH0
0.01µF
SCLK
DIN
5µs/div
500kHz
OSCILLATOR
COM
CH2
CH1
V
DD
DOUT
REF
C1
1µF
*CONVERSION RESULT = 10101010
Figure 9. Quick-Look Schematic
______________________________________________________________________________________ 15
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
to the SCLK pin; varying the analog input alters the
result of conversion that is clocked out at the DOUT pin.
A total of 10 clock cycles is required per conversion.
In external clock mode, the first high bit
clocked into DIN after the bit 5 (D5) of a con-
version in progress is clocked onto the
DOUT pin.
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte.
Acquisition starts on the falling edge of the fourth SCLK
and lasts for two SCLKs in external clock mode or four
SCLKs in internal clock mode. Conversion starts imme-
diately after acquisition is completed. The start bit is
defined as:
OR
In internal clock mode, the first high bit
clocked into DIN after the bit 4 (D4) is
clocked onto the DOUT pin.
The MAX1108/MAX1109 can run at a maximum speed
of 10 clocks per conversion. Figure 10 shows the serial-
interface timing necessary to perform a conversion
every 10 SCLK cycles in external clock mode.
The first high bit clocked into DIN with CS
Many microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion is
typically the fastest that a microcontroller can drive the
MAX1108/MAX1109. Figure 11 shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
low any time the converter is idle; e.g., after
V
DD
is applied.
OR
CS
1
8
10
1
10
1
10
1
SCLK
DIN
S
CONTROL BYTE 2
S
S
CONTROL BYTE 0
S
CONTROL BYTE 1
CONVERSION RESULT 0
D5
CONVERSION RESULT 1
D5 D0
DOUT
D7
D7
D0
D7
t
t
t
t
t
CONV
t
CONV
ACQ
CONV
ACQ
ACQ
A/D STATE
IDLE
Figure 10. Continuous Conversion, External Clock Mode, 10 Clocks/Conversion Timing
CS
1
8
17
25
SCLK
DIN
S
CONTROL BYTE 0
S
S
CONTROL BYTE 1
CONVERSION RESULT 0
CONVERSION RESULT 1
D7
D0
D7
D0
DOUT
Figure 11. Continuous Conversion, External Clock Mode, 16 Clocks/Conversion Timing
16 ______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
In external clock mode, if CS is toggled before the cur-
Table 4. Power-Down Modes of the
MAX1108/MAX1109
rent conversion is complete, the current conversion is
terminated, and the next high bit clocked into DIN is
recognized as a new start bit. This can be useful in
extending acquisition time by selecting conversion on
the same channel with the second control byte (double-
clocking mode), effectively extending acquisition to 6
SCLKs. This technique is ideal if the analog input
source has high impedance, or if it requires more than
1µs to settle; it can also be used to allow the device
and the reference to settle when using power down-
modes (see Power-Down Modes section).
BIT 2–BIT 0 OF
CONTROL BYTE
OPERATING MODE
I/EREF
REFSHDN SHDN
Device Active/Internal
Reference Active
1
1
1
Device Active; Internal refer-
ence powered down after con-
version, powered up at next
start bit.
1
0
1
__________Applications Information
Device Active/External
Reference Mode
0
1
X
0
1
0
Battery Monitoring Mode
Device and internal reference
powered down after conversion,
powered up at next start bit.
This mode of operation samples and converts the mid-
supply voltage, V
/ 2, which is internally generated.
DD
Set SEL2 = SEL1 = SEL0 = 0 in the control byte to
select this configuration. This allows the user to monitor
Device powered down after
each conversion, powered up
at next start bit. External
Reference Mode.
the condition of a battery providing V . The reference
DD
0
X
1
0
0
voltage must be larger than V
/ 2 for this mode of
DD
operation to work properly. From the result of conver-
sion (CODE), V is determined as follows:
1
Reserved. Do not use.
DD
V
= CODE · V
/ 128.
DD
REF
X = Don’t care
Power-On Configuration
The first logical 1 clocked into DIN after CS falls powers
up the MAX1108/MAX1109 (20µs required for the
device to power up). The reference is powered up only
if internal reference was selected during the previous
conversion. When the reference is powered up after
being disabled, consider the settling time before using
the result of conversion. Typically, 12ms are required
for the reference to settle from a discharge state; less
time may be considered if the external capacitor is not
discharged completely when exiting shutdown. In all
power-down modes, the interface remains active and
conversion results may be read. Use the double clock-
ing technique described in the Data Framing section to
allow more time for the reference to settle before start-
ing a conversion after short power-down.
When power is first applied, the MAX1108/MAX1109’s
reference is powered down and SHDN is not enabled.
The device needs to be configured by setting CS low
and writing the control byte. Conversion can be started
within 20µs if an external reference is used. When using
the internal reference, allow 12ms for the reference to
settle. This is done by first performing a configuration
conversion to power up the reference and then perform-
ing a second conversion once the reference is settled. No
conversions should be considered correct until the refer-
ence voltage (internal or external) has stabilized.
Power-Down Modes
To save power, place the converter into low-current
power-down mode between conversions. Minimum
power consumption is achieved by programming
REFSHDN = 0 and SHDN = 0 in the input control byte
(Table 4). When software power-down is asserted, it
becomes effective only after the conversion. If the con-
trol byte contains REFSHDN = 0, then the reference will
turn off at the end of conversion. If SHDN = 0, then the
chip will power-down at the end of conversion (in this
mode I/EREF or REFSHDN should also be set to zero).
Table 4 lists the power-down modes of the MAX1108/
MAX1109.
Voltage Reference
The MAX1108/MAX1109 operate from a single supply
and feature a software-controlled internal reference of
+2.048V (MAX1108) and +4.096V (MAX1109). The
device can operate with either the internal reference or
an external reference applied at the REF pin. See the
Power-Down Modes and Modes of Operation sections
for detailed instructions on reference configuration.
The reference voltage determines the full-scale range:
in unipolar mode, the input range is from 0 to V
; in
REF
/ 2 with
bipolar mode, the input range spans RI
RI = V / 2.
V
REF
REF
______________________________________________________________________________________ 17
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
External Reference
OUTPUT CODE
To use an external reference, set bit 2 (I/EREF) and bit
FULL-SCALE
TRANSITION
1 (REFSHDN) of control byte to 0 and connect the
11111111
11111110
external reference (V
between 1V and V ) directly
DD
REF
at the REF pin. The DC input impedance at REF is
extremely high, consisting of leakage current only (typi-
cally 10nA). During a conversion, the reference must
be able to deliver up to 20µA average load current and
have an output impedance of 1kΩ or less at the conver-
sion clock frequency. If the reference has higher output
impedance or is noisy, bypass it close to the REF pin
with a 0.1µF capacitor. MAX1109 has an internal refer-
ence of +4.096V. To use the device with supply volt-
ages below 4.5V, external reference mode is required.
11111101
FS = V + COM
REF
1LSB = V
REF
256
00000011
00000010
With an external reference voltage of less than +2.048V
(MAX1108) or +4.096V (MAX1109) at REF, the increase
in the ratio of the RMS noise to the LSB value (FS / 256)
results in performance degradation and decreased
dynamic range.
00000001
00000000
0
1
2
3
FS
FS - 1LSB
(COM)
INPUT VOLTAGE (LSB)
Figure 12a. Unipolar Transfer Function
Internal Reference
To use the internal reference, set bit 2 (I/EREF) and bit 1
(REFSHDN) of the control byte to 1 and bypass REF with
a 1µF capacitor to ground. The internal reference can be
powered down after a conversion by setting bit 1 (REF-
SHDN) of the control byte to 0. When using the internal
reference, use MAX1108 and MAX1109 with supply volt-
age below 4.5V and above 4.5V, respectively.
OUTPUT CODE
V
REF
2
+FS =
+ COM
01111111
01111110
V
REF
COM =
2
-V
REF
2
-FS =
+ COM
00000010
00000001
00000000
V
REF
1LSB =
Transfer Function
Table 4 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 12a depicts the nominal,
unipolar I/O transfer function, and Figure 12b shows the
bipolar I/O transfer function. The zero scale is deter-
mined by the input selection setting and is either COM,
GND, or CH1.
256
11111111
11111110
11111101
10000001
10000000
Code transitions occur at integer LSB values. Output
coding is straight binary for unipolar operation and
two’s complement for bipolar operation. With a +2.048V
COM
INPUT VOLTAGE (LSB)
-FS
reference, 1LSB = 8mV (V
/ 256).
1
REF
+FS - LSB
2
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another or run
digital lines underneath the ADC package.
Figure 12b. Bipolar Transfer Function
The ground return to the power supply for the star
ground should be low impedance and as short as pos-
sible for noise-free operation.
High-frequency noise in the V
power supply may
DD
affect the comparator in the ADC. Bypass the supply to
the star ground with 0.1µF and 1µF capacitors close to
Figure 13 shows the recommended system-ground
connections. A single-point analog ground (star-ground
point) should be established at the A/D ground.
Connect all analog grounds to the star ground. No digi-
tal-system ground should be connected to this point.
the V
pin of the MAX1108/MAX1109. Minimize
DD
capacitor lead lengths for best supply-noise rejection. If
the power supply is very noisy, a 10Ω resistor can be
connected to form a lowpass filter.
18 ______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
Chip Information
TRANSISTOR COUNT: 2373
SYSTEM POWER SUPPLIES
GND
+3V/+5V
1µF
10Ω
0.1µF
GND
COM
V
DD
DGND
V
DD
DIGITAL
CIRCUITRY
MAX1108
MAX1109
Figure 13. Power-Supply Connections
______________________________________________________________________________________ 19
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.
e
4X S
10
10
INCHES
MAX
MILLIMETERS
MAX
1.10
0.15
0.95
3.05
3.00
3.05
3.00
5.05
0.70
DIM MIN
MIN
-
A
-
0.043
0.006
0.037
0.120
0.118
0.120
0.118
0.199
A1
A2
D1
D2
E1
E2
H
0.002
0.030
0.116
0.114
0.116
0.114
0.187
0.05
0.75
2.95
2.89
2.95
2.89
4.75
0.40
H
ÿ 0.50 0.1
0.6 0.1
L
0.0157 0.0275
0.037 REF
L1
b
0.940 REF
0.007
0.0106
0.177
0.270
0.200
1
1
e
0.0197 BSC
0.500 BSC
0.6 0.1
c
0.0035 0.0078
0.0196 REF
0.090
BOTTOM VIEW
0.498 REF
S
α
TOP VIEW
0∞
6∞
0∞
6∞
D2
E2
GAGE PLANE
A2
c
A
E1
b
L
α
A1
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0061
I
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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