MAX11160 [MAXIM]
16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN; 16位， 500KSPS / 250ksps的，为± 5V的SAR ADC ，TDFN封装内部参考
| 型号： | MAX11160 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN |
| 文件： | 总33页 (文件大小：1358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs with
Internal Reference in TDFN
General Description
The MAX11166/MAX11167 16-bit, 500ksps/250ksps,
SAR ADCs offer excellent AC and DC performance with
true bipolar input range, small size, and internal reference.
Features
● High DC and AC Accuracy
● 16-Bit Resolution with No Missing Codes
● SNR: 92.6dB
The MAX11166/MAX11167 measure a Q5V (10V ) input
P-P
● THD: -105dB at 10kHz
● ±0.5 LSB INL (typ)
range while operating from a single 5V supply. A patented
charge-pump architecture allows direct sampling of high-
impedance sources. The MAX11166/MAX11167 integrate
an optional 6ppm/NC reference with internal buffer, saving
the cost and space of an external reference.
● ±0.2 LSB DNL (typ)
● Internal Reference and Reference Buffer Saves Cost
and Board Space
● 6ppm/°C typ
These ADCs achieve 92.6dB SNR and -105dB THD. The
MAX11166/MAX11167 guarantee 16-bit no-missing codes
and Q0.5 LSB INL (typ).
● Tiny 12-Pin 3mm x 3mm TDFN Package
● Bipolar ±5V Analog Input Range Saves External
Signal Conditioning
The MAX11166/MAX11167 communicate using an SPI-
compatible serial interface at 2.5V, 3V, 3.3V, or 5V logic.
The serial interface can be used to daisy-chain multiple
ADCs in parallel for multichannel applications and pro-
vides a busy indicator option for simplified system syn-
chronization and timing.
● Single-Supply ADC with Low Power
● 5V Analog Supply
● 2.3V to 5V Digital Supply
● 26.4mW at 500ksps
● 1µA Shutdown Mode
The MAX11166/MAX11167 are offered in 12-pin, 3mm x
3mm, TDFN packages and are specified over the -40NC
to +85NC temperature range.
● 500ksps Throughput Rate (MAX11166)
● 250ksps Throughput Rate (MAX11167)
● No Pipeline Delay/Latency
Applications
● Flexible Industry-Standard Serial Interface Saves I/O
●ꢀ Data Acquisition Systems
●ꢀ Industrial Control Systems/Process Control
●ꢀ Medical Instrumentation
●ꢀ Automatic Test Equipment
Pins
®
● SPI/QSPI™/MICROWIRE /DSP-Compatible
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
Selector Guide and Ordering Information appear at end of
data sheet.
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX11166.related.
Typical Operating Circuit
V
OVDD
1µF
DD
1µF
(5V)
(2.3V TO 5V)
SCLK
DIN
DOUT
50Ω
500pF
AIN+
AIN-
INTERFACE
HOST
CONTROLLER
5V
16-BIT ADC
AND CONTROL
MAX9632
CNVST
MAX11166
MAX11167
CONFIGURATION REGISTER
INTERNAL REFERENCE
REF
REF
BUF
10µF
REFIO
0.1µF
AGNDS
GND
19-6445; Rev 1; 12/12
MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Absolute Maximum Ratings
DD
V
to GND ............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70NC)
A
OVDD to GND....... -0.3V to the lower of (V
AIN+ to GND ........................................................................ Q7V
AIN-, REF, REFIO, AGNDS
+ 0.3V) and +6V
TDFN (derate 18.2mW/NC above +70NC)..................1349mW
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) .................................+300NC
Soldering Temperature (reflow).......................................+260NC
DD
to GND............... -0.3V to the lower of (V
SCLK, DIN, DOUT, CNVST
+ 0.3V) and +6V
+ 0.3V) and +6V
DD
to GND............... -0.3V to the lower of (V
DD
Maximum Current into Any Pin...........................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (q ).......59.3NC/W
JA
Junction-to-Case Thermal Resistance (q )...........22.5NC/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= 4.75V to 5.25V, V
= 2.3V to 5.25V, f
= 500kHz or 250kHz, V
CONDITIONS
5.000
= 4.096V; T = T
A
to T
, unless otherwise
DD
OVDD
SAMPLE
REF
MIN
MAX
noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
ANALOG INPUT (Note 3)
Input Voltage Range
AIN+ to AIN-, K =
-K x V
+K x V
V
V
REF
REF
4.096
-(V
+
+(V
+
DD
DD
AIN+ to GND
0.1)
0.1)
Absolute Input Voltage Range
AIN- to GND
-0.1
+0.1
Input Leakage Current
Input Capacitance
Input-Clamp Protection Current
DC ACCURACY (Note 4)
Resolution
Acquisition phase
-10
-20
+0.001
15
+10
+20
µA
pF
Both inputs
mA
N
16
16
Bits
Bits
No Missing Codes
Offset Error
-1.5
±0.1
±2.4
±2
+1.5
±10
mV
Offset Temperature Coefficient
Gain Error
µV/°C
LSB
Gain Error Temperature
Coefficient
±1
ppm/°C
MAX11167, T = T
to T
MAX
-2.0
-1.0
-2.4
-1.5
-0.5
±0.5
±0.5
±0.5
±0.5
±0.2
+2.0
+1.0
+2.4
+1.5
+0.5
±14
A
MIN
MAX11167, T = +25°C to +85°C
A
Integral Nonlinearity
INL
LSB
MAX11166, T = T
to T
MAX
A
MIN
MAX11166, T = +25°C to +85°C
A
Differential Nonlinearity
Positive Full-Scale Error
DNL
LSB
LSB
Maxim Integrated
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Electrical Characteristics (continued)
(V
= 4.75V to 5.25V, V
= 2.3V to 5.25V, f
= 500kHz or 250kHz, V
= 4.096V; T = T
A
to T
, unless otherwise
DD
OVDD
SAMPLE
REF
MIN
MAX
noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
Negative Full-Scale Error
Analog Input CMRR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LSB
dB
±13
CMRR
PSR
-77
±3.0
0.5
Power-Supply Rejection (Note 5)
Transition Noise
LSB
LSB
RMS
REFERENCE (Note 7)
REF Output Initial Accuracy
V
Reference mode 0
4.092
4.092
4.096
±9
4.100
±17
V
REF
REF Output Temperature
Coefficient
TC
Reference mode 0
ppm/°C
V
REF
REFIO Output Initial Accuracy
V
Reference modes 0 and 2
Reference modes 0 and 2
4.096
±6
4.100
±15
REFIO
REFIO Output Temperature
Coefficient
TC
ppm/°C
REFIO
REFIO Output Impedance
REFIO Input Voltage Range
Reference Buffer Initial Offset
Reference modes 0 and 2
Reference mode 1
10
kΩ
V
3
4.096
4.25
Reference mode 1
-500
+500
µV
Reference Buffer Temperature
Coefficient
Reference mode 1
±6
±10
µV/°C
µF
Required for reference modes 0 and 1,
recommended for reference modes 2 and 3
External Compensation Capacitor
C
EXT
10
REF Voltage Input Range
REF Input Capacitance
V
Reference modes 2 and 3
Reference modes 2 and 3
2.5
4.25
V
REF
20
65
pF
V
= 4.096V,
MAX11167, 250ksps
MAX11166, 500ksps
REF
REF Load Current
I
reference modes 2
µA
REF
130
and 3
AC ACCURACY (Note 6)
V
= 4.096V, reference
REF
mode 3
91.5
92.6
92.4
89.8
92.4
92.3
92.3
89.5
91.8
V
= 4.096V, reference
REF
mode 1
Signal-to-Noise Ratio (Note 7)
SNR
f
= 10kHz
IN
dB
V
= 2.5V, reference
REF
mode 3
Internal reference,
reference mode 0
V
= 4.096V, reference
REF
mode 3
90
V
= 4.096V, reference
REF
mode 1
Signal-to-Noise Plus Distortion
(Note 7)
SINAD
f
= 10kHz
dB
IN
V
= 2.5V, reference
REF
mode 3
Internal reference,
reference mode 0
Spurious-Free Dynamic Range
Total Harmonic Distortion
SFDR
THD
IMD
96
105
-105
-115
dB
dB
dB
-96
Intermodulation Distortion (Note 8)
Maxim Integrated
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Electrical Characteristics (continued)
(V
= 4.75V to 5.25V, V
= 2.3V to 5.25V, f
= 500kHz or 250kHz, V
= 4.096V; T = T
A
to T
, unless otherwise
DD
OVDD
SAMPLE
REF
MIN
MAX
noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SAMPLING DYNAMICS
MAX11166
0.01
0.01
500
250
400
Throughput Sample Rate
Transient Response
ksps
ns
MAX11167
Full-scale step
-3dB point
6
Full-Power Bandwidth
MHz
-0.1dB point
> 0.2
2.5
Aperture Delay
ns
Aperture Jitter
< 50
ps
RMS
POWER SUPPLIES
Analog Supply Voltage
Interface Supply Voltage
V
4.75
5.25
V
V
DD
V
2.3
5.0
3.0
5.25
6.5
OVDD
Internal reference mode
External reference mode
5.8
3.5
Analog Supply Current
I
mA
µA
VDD
4.0
V
DD
Shutdown Current
6.3
10
V
V
V
V
= 2.3V, MAX11167
= 5.25V, MAX11167
= 2.3V, MAX11166
= 5.25V, MAX11166
0.75
0.85
OVDD
OVDD
OVDD
OVDD
2.0
1.5
4.3
0.9
2.4
2.0
5.0
10
Interface Supply Current (Note 9)
OVDD Shutdown Current
I
mA
µA
OVDD
V
= 5V, V
= 3.3V, MAX11167
OVDD
DD
21.2
33.3
26.4
40.5
reference mode = 2, 3
V
= 5V, V = 3.3V, MAX11167
DD
OVDD
reference mode = 0, 1
Power Dissipation
mW
V
= 5V, V = 3.3V, MAX11166
DD
OVDD
reference mode = 2, 3
V
= 5V, V = 3.3V, MAX11166
DD
OVDD
reference mode = 0, 1
DIGITAL INPUTS (DIN, SCLK, CNVST)
0.7 x
Input Voltage High
V
V
IH
V
OVDD
Input Voltage Low
Input Hysteresis
V
0.3 x V
V
V
IL
OVDD
V
±0.05 x V
HYS
OVDD
Input Capacitance
Input Current
C
10
pF
µA
IN
I
V
= 0V or V
OVDD
-10
+10
IN
IN
DIGITAL OUTPUT (DOUT)
V
- 0.4
OVDD
Output Voltage High
V
I
I
= 2mA
SOURCE
V
OH
Output Voltage Low
V
= 2mA
SINK
0.4
V
OL
Three-State Leakage Current
Three-State Output Capacitance
-10
+10
µA
pF
15
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Electrical Characteristics (continued)
(V
= 4.75V to 5.25V, V
= 2.3V to 5.25V, f
= 500kHz or 250kHz, V
= 4.096V; T = T
A
to T
, unless otherwise
DD
OVDD
SAMPLE
REF
MIN
MAX
noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
TIMING (Note 9)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX11166
2
4
100000
100000
1.5
µs
µs
Time Between Conversions
Conversion Time
t
CYC
MAX11167
MAX11166
1.35
2.7
0.5
1
CNVST rising to
data available
t
µs
CONV
MAX11167
MAX11166
MAX11167
3.0
Acquisition Time
t
t
= t - t
CYC CONV
µs
ns
ACQ
ACQ
CNVST Pulse Width
t
CS mode
5
CNVPW
V
V
V
V
V
V
> 4.5V
> 2.7V
> 2.3V
> 4.5V
> 2.7V
> 2.3V
14
20
26
16
24
30
5
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
SCLK Period (CS Mode)
t
ns
ns
SCLK
SCLK Period (Daisy-Chain Mode)
t
SCLK
SCLK Low Time
SCLK High Time
t
ns
ns
SCLKL
t
5
SCLKH
V
V
V
V
> 4.5V
> 2.7V
> 2.3V
> 2.7V
< 2.7V
12
18
23
14
17
OVDD
OVDD
OVDD
OVDD
OVDD
SCLK Falling Edge to Data Valid
Delay
t
ns
DDO
CNVST Low to DOUT D15 MSB
Valid (CS Mode)
t
ns
ns
EN
V
CNVST High or Last SCLK
Falling Edge to DOUT High
Impedance
t
CS Mode
20
DIS
V
V
V
> 4.5V
> 2.7V
> 2.3V
3
5
6
OVDD
OVDD
OVDD
DIN Valid Setup Time from SCLK
Falling Edge
t
ns
SDINSCK
DIN Valid Hold Time from SCLK
Falling Edge
t
0
3
6
ns
ns
ns
HDINSCK
SCLK Valid Setup Time to
CNVST Falling Edge
t
SSCKCNF
HSCKCNF
SCLK Valid Hold Time to CNVST
Falling Edge
t
Note 2: Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25°C
and +85°C. Limits below +25°C are guaranteed by design and device characterization. Typical values are not guaranteed.
Note 3: See the Analog Inputs and Overvoltage Input Clamps sections.
Note 4: See the Definitions section.
Note 5: Defined as the change in positive full-scale code transition caused by a Q5% variation in the V
Note 6: 10kHz sine wave input, -0.1dB below full scale.
supply voltage.
DD
Note 7: See Table 4 for definition of the reference modes.
Note 8: f
~ 9.4kHz, f
~ 10.7kHz, Each tone at -6.1dB below full scale.
IN1
IN2
Note 9: C
= 65pF on DOUT.
LOAD
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11166
OFFSET AND GAIN ERROR
OFFSET AND GAIN ERROR
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
MAX11166 toc01
MAX11166 toc02
1.0
0.5
0
2.0
1.0
0
1.0
0.6
1.0
OFFSET ERROR (mV)
GAIN ERROR (LSB)
OFFSET ERROR (mV)
GAIN ERROR (LSB)
0.6
0.2
0.2
-0.2
-0.6
-1.0
-0.2
-0.6
-1.0
f
= 500ksps
-0.5
-1.0
f
= 500ksps
-1.0
-2.0
SAMPLE
SAMPLE
V
V
T
= 4.096V
= 3.3V
V
V
V
= 4.096V
REF
OVDD
REF
DD
OVDD
= 5.0V
= 3.3V
= +25°C
A
-40
-15
10
35
60
85
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
DD
INTEGRAL NONLINEARITY vs. CODE
DIFFERENTIAL NONLINEARITY vs. CODE
1.0
0.8
0.6
0.4
0.2
0
0.5
0.4
0.3
0.2
0.1
0
f
= 500ksps
= 4.096V
SAMPLE
V
f
= 500ksps
SAMPLE
REF
V
= 4.096V
REF
V
= 5.0V
= 3.3V
DD
V
= 5.0V
= 3.3V
DD
OVDD
V
OVDD
V
T
= +25°C
A
T
= +25°C
A
-0.2
-0.4
-0.6
-0.8
-1.0
-0.1
-0.2
-0.3
-0.4
-0.5
0
16384
24576
OUTPUT CODE (DECIMAL)
32768
49152
65536
0
16384
24576
OUTPUT CODE (DECIMAL)
32768
49152
65536
8192
40960
57344
8192
40960
57344
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11166 (continued)
INL AND DNL
OUTPUT NOISE HISTOGRAM WITH
INPUT CONNECTED TO GND
vs. V
SUPPLY VOLTAGE
DD
INL AND DNL vs. TEMPERATURE
200k
150k
100k
50k
0
1.4
1.0
1.4
1.0
MAX INL
MIN INL
MAX DNL
MIN DNL
MAX INL
MIN INL
MAX DNL
MIN DNL
f
= 500ksps
AINP
SAMPLE
V
= 0V
= 5V
V
DD
V
= 4.096V
= +25°C
0.6
REF
0.6
T
A
0.2
0.2
-0.2
-0.6
-1.0
-1.4
-0.2
-0.6
-1.0
-1.4
f
= 500ksps
REF
SAMPLE
f
= 500ksps
SAMPLE
V
V
= 4.096V
V
V
V
= 4.096V
REF
DD
OVDD
= 3.3V
OVDD
= 5.0V
= 3.3V
T
= +25°C
A
32765
32767 32769
32768
32771
32770 32772
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
32766
TEMPERATURE (°C)
DD
OUTPUT CODE (DECIMAL)
INTERNAL REFERENCE VOLTAGES
vs. V VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE (REF PIN)
DD
4.09604
4.100
4.099
4.098
4.097
4.096
4.095
4.094
4.093
4.092
4.091
4.090
V
= 3.3V
OVDD
A
REFIO
REF
T
= +25°C
REF MODE = 0
4.09602
4.09600
4.09598
4.09596
4.09594
V
= 5.0V
DD
MAX MEASURED
MIN MEASURED
REF MODE = 0
30 DEVICES
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
TEMPERATURE (°C)
DD
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11166 (continued)
SNR AND SINAD
SUPPLY VOLTAGE
vs. V
DD
FFT PLOT
= 500ksps
TWO TONES IMD
= 500ksps
93.0
92.8
92.5
92.3
92.0
91.8
91.5
0
-20
0
-20
SNR
SINAD
f
f
SAMPLE
FFT N
IN1
IN1
IN2
IN2
SAMPLE
FFT N
= 4096
= 16384
SAMPLE
= S9A3M6P8L.9EHz
f
= 10101Hz
f
IN
V
= -0.1dBFS
IN
V
= -6.1dBFS
REF MODE = 3
f
= 10651Hz
-40
-40
V
V
V
= 4.096V
REF
= 5.0V
V
= -6.1dBFS
DD
OVDD
= +25°C
REF MODE = 3
-60
= 3.3V
-60
V
V
V
= 4.096V
REF
DD
OVDD
T
A
= 5.0V
SNR = 92.7dB
SINAD = 92.4dB
SFDR = 107.4dB
THD = -104.4dB
-80
-80
= 3.3V
= +25°C
f
f
= 500ksps
SAMPLE
T
A
= 10kHz
IN
IN
A
IMD = -119.7dBFS
-100
-120
-140
-100
-120
-140
V
= -0.1dBFS
T
= +25°C
REF MODE = 3
= 4.096V
V
REF
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
0
50
100
150
200
250
5
7
9
11
13
15
FREQUENCY (kHz)
FREQUENCY (kHz)
DD
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-NOISE AND
THD vs. V
DD
SUPPLY VOLTAGE
DISTORTION RATIO vs. TEMPERATURE
THD vs. TEMPERATURE
= 500ksps
-100
-102
-104
-106
-108
-110
-112
93.5
93.0
92.5
92.0
91.5
-98
-100
-102
-104
-106
-108
SNR
SINAD
f
f
SAMPLE
= 10kHz
IN
V
IN
= -0.1dBFS
REF MODE = 3
V
V
V
= 4.096V
REF
= 5.0V
DD
OVDD
= 3.3V
f
f
= 500ksps
SAMPLE
IN
f
f
V
= 500ksps
SAMPLE
IN
IN
= 10kHz
= 10kHz
V
A
= -0.1dBFS
IN
= -0.1dBFS
T
= +25°C
REF MODE = 3
REF MODE = 3
V
V
V
= 4.096V
= 5.0V
REF
VDD
OVDD
V
V
= 4.096V
REF
OVDD
= 3.3V
= 3.3V
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
DD
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
Maxim Integrated
│ 8
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11166 (continued)
SINAD vs. FREQUENCY
ENOB vs. INPUT SIGNAL FREQUENCY
94
92
90
88
86
84
82
15.4
15.0
14.6
14.2
13.8
13.4
f
= 500ksps
f
= 500ksps
SAMPLE
SAMPLE
V
A
= -0.1dBFS
V = -0.1dBFS
IN
IN
T
= +25°C
T = +25°C
A
REF MODE = 3
REF MODE = 3
V
V
V
= 4.096V
V
V
V
= 4.096V
REF
REF
= 5.0V
= 5.0V
DD
OVDD
DD
OVDD
= 3.3V
= 3.3V
0.1
1.0
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
THD vs. INPUT FREQUENCY
= 500ksps
CMRR vs. INPUT FREQUENCY
= 500ksps
-80
-85
-40
-50
-60
-70
-80
-90
f
SAMPLE
A
f
SAMPLE
IN
A
T
= +25°C
V
= -0.1dBFS
V
V
V
V
= 5.0V
DD
OVDD
T
= +25°C
-90
= 3.3V
= 4.096V
AIN-
REF MODE = 3
REF
AIN+
V
V
V
= 4.096V
REF
-95
= V
= 100ꢀV
P-P
= 5.0V
DD
OVDD
= 3.3V
-100
-105
-110
-115
-120
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Maxim Integrated
│ 9
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11166 (continued)
V
SUPPLY CURRENT
V
SUPPLY CURRENT
DD
vs. TEMPERATURE
DD
OVDD SUPPLY CURRENT
vs. TEMPERATURE
vs. V SUPPLY VOLTAGE
DD
8
7
6
5
4
3
2
8.0
7.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
REF MODE 0 AND 1
REF MODE 2 AND 3
REF MODE 0 AND 1
REF MODE 2 AND 3
500ksps
10ksps
6.0
5.0
4.0
3.0
2.0
V
= 5.0V
= 3.3V
= 65pF
DD
OVDD
f
= 500ksps
SAMPLE
f
V
V
= 500ksps
SAMPLE
V
C
T
= +25°C
A
= 5.0V
DD
DOUT
V
= 3.3V
OVDD
= 3.3V
OVDD
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
DD
TEMPERATURE (°C)
V
AND OVDD SHUTDOWN
ANALOG AND DIGITAL SHUTDOWN
CURRENT vs. TEMPERATURE
OVDD SUPPLY CURRENT
vs. OVDD SUPPLY VOLTAGE
DD
CURRENT vs. SUPPY VOLTAGE
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= +25°C
V
= 5.0V
= 3.3V
A
IVDD
DD
OVDD
IVDD
IOVDD
500ksps
10ksps
V
IOVDD
T
= +25°C
A
V
= 5.0V
= 65pF
DD
DOUT
C
2.25 2.75 3.25 3.75 4.25 4.75 5.25
OR V (V)
-40
-15
10
35
60
85
2.25 2.75 3.25 3.75 4.25 4.75 5.25
(V)
V
DD
TEMPERATURE (°C)
V
OVDD
OVDD
Maxim Integrated
│ 10
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11166 (continued)
OFFSET AND GAIN ERROR
vs. TEMPERATURE
OFFSET AND GAIN ERROR
vs. SUPPLY VOLTAGE
MAX11166 toc27
MAX11166 toc26
1.0
0.5
0
2.0
1.0
0
1.0
0.6
1.0
OFFSET ERROR (mV)
GAIN ERROR (LSB)
OFFSET ERROR (mV)
GAIN ERROR (LSB)
0.6
0.2
0.2
-0.2
-0.6
-1.0
-0.2
-0.6
-1.0
f
= 250ksps
f
= 250ksps
SAMPLE
SAMPLE
-0.5
-1.0
-1.0
-2.0
V
V
T
= 4.096V
= 3.3V
V
V
V
= 4.096V
REF
OVDD
A
REF
= 5.0V
DD
OVDD
= +25°C
= 3.3V
-40
-15
10
35
60
85
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
DD
DIFFERENTIAL NONLINEARITY
vs. CODE
INTEGRAL NONLINEARITY vs. CODE
1.0
0.8
0.6
0.4
0.2
0
0.5
0.4
0.3
0.2
0.1
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.1
-0.2
-0.3
-0.4
-0.5
f
= 250ksps
SAMPLE
f
= 250ksps
SAMPLE
V
V
V
= 4.096V
REF
= 5.0V
V
V
V
= 4.096V
REF
= 5.0V
DD
OVDD
DD
= 3.3V
= 3.3V
OVDD
T
= +25°C
A
T
= +25°C
A
0
16384
32768
49152
65536
0
16384
32768
49152
65536
8192
24576 40960
57344
8192
24576 40960
57344
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
Maxim Integrated
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11167 (continued)
INL AND DNL
OUTPUT NOISE HISTOGRAM WITH
INPUT CONNECTED TO GND
vs. V SUPPLY VOLTAGE
DD
INL AND DNL vs. TEMPERATURE
200k
150k
100k
50k
0
1.4
1.0
1.4
1.0
MAX INL
MIN INL
MAX INL
MIN INL
f
= 250ksps
SAMPLE
V
= 0V
AINP
DD
= 4.096V
= +25°C
MAX DNL
MIN DNL
MAX DNL
MIN DNL
V
= 5.0V
V
REF
0.6
0.6
T
A
0.2
0.2
-0.2
-0.6
-1.0
-1.4
-0.2
-0.6
-1.0
-1.4
f
= 250ksps
SAMPLE
f
= 250ksps
SAMPLE
V = 4.096V
REF
V
V
V
= 4.096V
REF
= 5.0V
V
= 3.3V
OVDD
= +25°C
DD
OVDD
T
= 3.3V
A
32765
32767
32769
32771
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
32766 32768
32770
32772
TEMPERATURE (°C)
DD
OUTPUT CODE (DECIMAL)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE (REF PIN)
INTERNAL REFERENCE VOLTAGES
vs. V VOLTAGE
DD
4.09604
4.100
V
A
= 5.0V
DD
= +25°C
REFIO
REF
4.099
4.098
4.097
4.096
4.095
4.094
4.093
4.092
4.091
4.090
T
REF MODE = 0
4.09602
4.09600
4.09598
4.09596
4.09594
V
= 5.0V
DD
REF MODE = 0
30 DEVICES
MAX MEASURED
MIN MEASURED
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
TEMPERATURE (°C)
DD
Maxim Integrated
│ 12
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11167 (continued)
TWO TONES IMD
FFT PLOT
SNR AND SINAD vs. TEMPERATURE
0
-20
93.5
93.0
92.5
92.0
91.5
f
= 250ksps
f
= 250ksps
SAMPLE
SAMPLE
SNR
SINAD
FFT N
FFT N
= 8192
SAMPLE
SAMPLE
= 10101Hz
0
-20
= 32768
f
IN
IN
V
= -0.1dBFS
f
= 9376.5HZ
IN1
REF MODE = 3
V
f
= -6.1dBFS
-40
IN1
IN2
IN2
V
V
V
= 4.096V
= 10674Hz
= -6.1dBFS
REF
-40
= 5.0V
V
DD
OVDD
-60
= 3.3V
REF MODE = 3
-60
T
= +25°C
A
V
V
V
= 4.096V
REF
= 5.0V
SNR = 92.7dB
SINAD = 92.5dB
SFDR = 108.9dB
THD = -107.7dB
-80
DD
OVDD
= +25°C
f
f
= 250ksps
SAMPLE
= 10kHz
-80
= 3.3V
IN
T
A
V
= -0.1dBFS
-100
-120
-140
IN
IMD = -126.5dBFS
-100
-120
-140
REF MODE = 3
V
V
V
= 4.096V
REF
= 5.0V
DD
OVDD
= 3.3V
5.0
7.0
9.0
11.0
13.0
15.0
0
25
50
75
100
125
-40
-15
10
35
60
85
FREQUENCY (kHz)
FREQUENCY (kHz)
TEMPERATURE (°C)
SNR AND SINAD
vs. V SUPPLY VOLTAGE
THD vs. V SUPPLY VOLTAGE
DD
THD vs. TEMPERATURE
DD
93.0
92.8
92.5
92.3
92.0
91.8
91.5
-100
-102
-104
-106
-108
-110
-112
-100
-102
-104
-106
-108
-110
f
= 250ksps
= 10kHz
f
= 250ksps
SAMPLE
SAMPLE
SNR
f
IN
f = 10kHz
IN
SINAD
V
IN
= -0.1dBFS
T
V
= -0.1dBFS
IN
= +25°C
REF MODE = 3
A
REF MODE = 3
V
V
V
= 4.096V
REF
= 5.0V
V
V
= 4.096V
= 3.3V
REF
DD
OVDD
= 3.3V
OVDD
f
= 250ksps
SAMPLE
f
= 10kHz
IN
V
= -0.1dBFS
IN
T
= +25°C
A
REF MODE = 3
= 4.096V
V
REF
OVDD
V
= 3.3V
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
DD
TEMPERATURE (°C)
DD
Maxim Integrated
│ 13
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11167 (continued)
SINAD vs. FREQUENCY
ENOB vs. INPUT SIGNAL FREQUENCY
94
92
90
88
86
84
82
15.4
15.0
14.6
14.2
13.8
13.4
f
= 250ksps
SAMPLE
IN
A
V
T
= -0.1dBFS
f
= 250ksps
SAMPLE
IN
A
= +25°C
V
= -0.1dBFS
REF MODE = 3
T
= +25°C
V
V
V
= 4.096V
REF MODE = 3
REF
DD
OVDD
= 5.0V
V
V
= 4.096V
= 3.3V
REF
OVDD
= 3.3V
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
THD vs. INPUT FREQUENCY
CMRR vs. INPUT FREQUENCY
-80
-85
-40
-50
-60
-70
-80
-90
f
= 250ksps
f
= 250ksps
SAMPLE
SAMPLE
T
= +25°C
V
T
= -0.1dBFS
A
DD
IN
A
V
V
V
V
= 5.0V
= 3.3V
= +25°C
-90
REF MODE = 3
OVDD
REF
AIN+
= 4.096V
V
V
V
= 4.096V
REF
-95
= V
AIN-
= 100ꢀV
P-P
= 5.0V
DD
OVDD
= 3.3V
-100
-105
-110
-115
-120
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Maxim Integrated
│ 14
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Typical Operating Characteristics—MAX11167 (continued)
V
DD
SUPPLY CURRENT
V
SUPPLY CURRENT
OVDD SUPPLY CURRENT
vs. TEMPERATURE
DD
vs. TEMPERATURE
vs. V SUPPLY VOLTAGE
DD
8
7
6
5
4
3
2
8
7
6
5
4
3
2
2.0
1.5
1.0
0.5
0
V
V
= 5.0V
REF MODE 0 AND 1
REF MODE 2 AND 3
REF MODE 0 AND 1
REF MODE 2 AND 3
250ksps
10ksps
DD
OVDD
= 3.3V
= 65pF
C
DOUT
f
= 250ksps
f
= 250ksps
SAMPLE
A
OVDD
SAMPLE
DD
OVDD
T
= +25°C
V
V
= 5.0V
V
= 3.3V
= 3.3V
-40
-15
10
35
60
85
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
DD
OVDD SUPPLY CURRENT
ANALOG AND DIGITAL SHUTDOWN
CURRENT vs. TEMPERATURE
V
AND OVDD SHUTDOWN
DD
vs. OVDD SUPPLY VOLTAGE
CURRENT vs. SUPPY VOLTAGE
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
= 5.0V
T = +25°C
A
DD
OVDD
IVDD
IOVDD
IVDD
IOVDD
250ksps
10ksps
T
= +25°C
= 5.0V
DOUT
A
DD
= 3.3V
V
C
= 65pF
-40
-15
10
35
60
85
2.25 2.75 3.25 3.75 4.25 4.75 5.25
OR V (V)
2.25 2.75 3.25 3.75 4.25 4.75 5.25
(V)
TEMPERATURE (°C)
V
DD
OVDD
V
OVDD
Maxim Integrated
│ 15
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Pin Configuration
TOP VIEW
AGNDS
1
2
3
4
5
6
12
REFIO
REF
11
10
9
OVDD
DIN
V
DD
MAX11166
MAX11167
AIN+
AIN-
GND
SCLK
8
DOUT
CNVST
EP
7
TDFN
Pin Description
PIN
NAME
I/O
FUNCTION
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to
AGNDS.
1
REFIO
I/O
External Reference Input/Reference Buffer Decoupling. Bypass to AGNDS in close proximity with a
X5R or X7R 10µF 16V chip. See the Layout, Grounding, and Bypassing section.
2
3
REF
I/O
I
Analog Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF
per PCB.
V
DD
4
5
6
AIN+
AIN-
GND
I
I
I
Positive Analog Input
Negative Analog Input. Connect AIN- to the analog ground plane or to a remote-sense ground.
Power-Supply Ground
Convert Start Input. The rising edge of CNVST initiates conversions. The falling edge of CNVST
with SCLK high enables the serial interface.
7
CNVST
I
8
9
DOUT
SCLK
DIN
O
I
Serial Data Output. DOUT will change stated on the falling edge of SCLK.
Serial Clock Input. Clocks data out of the serial interface when the device is selected.
Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK.
10
I
Digital Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF
per PCB.
11
OVDD
I
Analog Ground Sense. Zero current reference for the on-board DAC and reference source.
Reference for REFIO and REF.
12
—
AGNDS
EP
I
—
Exposed Pad. EP is connected internally to GND. Connect to PCB GND.
Maxim Integrated
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Functional Diagram
DIN
AIN+
SCLK
DOUT
CNVST
INTERFACE
AND CONTROL
16-BIT ADC
AIN-
CONFIGURATION
REGISTER
REFERENCE SWITCH
STATE
CONFIGURATION REGISTER
REFERENCE
MODE
MAX11166
AGNDS
REFIO
MAX11167
B5
0
B4
0
SW1
CLOSED
OPEN
SW2
CLOSED
CLOSED
OPEN
V
DD
0
1
2
3
OVDD
GND
0
1
1
0
CLOSED
OPEN
SW1
SW2
1
1
OPEN
10kΩ
REF
REF
BUF
INTERNAL
REFERENCE
This allows for accurate sampling of a number of scanned
channels through an external multiplexer.
Detailed Description
The MAX11166/MAX11167 are 16-bit single-channel,
pseudo-differential ADCs with maximum throughput rates
of 500ksps/250ksps. These ADCs include a precision
internal reference that allows for measuring a bipolar
input voltage range of Q5V. An external reference can also
be applied for input ranges between Q3.05V and Q5.19V.
Both inputs (AIN+ and AIN-) are sampled with a pseudo-
differential on-chip track-and-hold.
The MAX11166/MAX11167 can thus convert input sig-
nals on AIN+ in the range of -(K O V
+ AIN-) to +(K
REF
O V
+ AIN-) where K = 5.000/4.096. AIN+ should also
REF
be limited to ±(V
+ 0.1V) for accurate conversions.
DD
AIN- has an input range of -0.1V to +0.1V and should
be connected to the ground reference of the input signal
source. The MAX11166/MAX11167 performs a true dif-
ferential sampling on inputs between AIN+ and AIN- with
good common-mode rejection (see the Typical Operating
Circuit). This allows for improved sampling of remote
transducer inputs.
The MAX11166/MAX11167 measure a true bipolar volt-
age of Q5V (10V ) and the inputs are protected for up
P-P
to Q20mA of overrange current. These ADCs are powered
from a 4.75 to 5.25V analog supply (V ) and a separate
DD
Many traditional ADCs with single supplies that mea-
sure bipolar input signals use resistive divider networks
directly on the analog inputs. These networks increase
the complexity of the input signal conditioning. However,
the MAX11166/MAX11167 include a patented input switch
architecture that allows direct sampling of high-imped-
ance sources. This architecture requires a minimum
sample rate of 10Hz to maintain accurate conversions
over the designed temperature and supply ranges.
2.3V to 5.25V digital supply (OVDD). The MAX11166/
MAX11167 require 500ns/1Fs to acquire the input sam-
ple on an internal track-and-hold and then convert the
sampled signal to 16 bits of accuracy using an internally
clocked converter.
Analog Inputs
The MAX11166/MAX11167 ADCs consist of a true sam-
pling pseudo-differential input stage with high-impedance,
capacitive inputs. The internal T/H circuitry feature a small-
signal bandwidth of about 6MHz to provide 16-bit accu-
rate sampling in 500ns (MAX11166)/1Fs (MAX11167).
Maxim Integrated
│ 17
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Overvoltage Input Clamps
Internal/External Reference
(REFIO) Configuration
The MAX11166/MAX11167 include an input clamping
circuit that activates when the input voltage at AIN+ is
The MAX11166/MAX11167 include a standard SPI inter-
face that selects internal or external reference modes of
operation through an input configuration register (see the
Input Configuration Interface section). The MAX11166/
MAX11167 feature an internal bandgap reference circuit
above (V
+ 300mV) or below -(V
+ 300mV). The
DD
DD
clamp circuit remains high impedance while the input sig-
nal is within the range of Q(V + 100mV) and draws little
DD
to no current. However, when the input signal exceeds
this range the clamps begin to turn on. Consequently, to
obtain the highest accuracy, ensure that the input voltage
(V
= 4.096V) that is buffered with an internal ref-
REFIO
erence buffer that drives the REF pin. The MAX11166/
MAX11167 configure register allows four combinations of
reference configuration. These reference mode are:
does not exceed the range of Q(V
+ 100mV).
DD
To make use of the input clamps, connect a resistor (R )
S
between the AIN+ input and the voltage source to limit the
voltage at the analog input and to ensure the fault current
into the devices does not exceed Q20mA. Note that the
voltage at the AIN+ input pin limits to approximately 7V
during a fault condition so the following equation can be
Reference Mode 00: ADC reference is provided by the
internal bandgap feed out the REFIO pin, noise filtered
with an external capacitor on the REFIO pin, then buff-
ered by the internal reference buffer and decoupled with
an external capacitor on the REF pin. In this mode the
ADC requires no external reference source.
used to calculate the value of R :
S
Reference Mode 01: ADC reference is provided external-
ly and feeds into the REFIO pin, buffered with the internal
reference buffer and decoupled with an external capaci-
tor on the REF pin. This mode is typically used when a
common reference source is needed for more than one
MAX11166/MAX11167.
V
− 7V
FAULT MAX
R
=
S
20mA
is the maximum voltage that the
source produces during a fault condition.
where V
FAULT
MAX
Figure 1 and Figure 2 illustrate the clamp circuit volt-
age current characteristics for a source impedance
Reference Mode 10: The internal bandgap is used as
a reference source output and feed out the REFIO pin.
However, the internal reference buffer is in a shutdown
state and the REF pin is high impedance. This state
would typically be used to provide a common reference
source to a set of external reference buffers for several
MAX11166/MAX11167.
R
= 1280I. While the input voltage is within the Q(V
S
DD
+ 300mV) range, no current flows in the input clamps.
Once the input voltage goes beyond this voltage range,
the clamps turn on and limit the voltage at the input pin.
MAX11166/MAX11167 INPUT CLAMP
CHARACTERISTICS
MAX11166/MAX11167 INPUT CLAMP
CHARACTERISTICS
25
25
AIN+ PIN
INPUT SOURCE
AIN+ PIN
INPUT SOURCE
15
20
15
10
5
5
-5
0
-5
-10
-15
-15
R
DD
= 1280I
S
R
DD
= 1280I
S
-20
-25
V
= 5.0V
V
= 5.0V
-25
-40 -30 -20 -10
0
10 20 30 40
-10
-5
0
5
10
SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V)
SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V)
Figure 1. Input Clamp Characteristics
Figure 2. Input Clamp Characteristics (Zoom In)
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
sampling capacitor charges during the acquisition period.
During this acquisition period, the settling of the sampled
voltage is affected by the source resistance and the input
sampling capacitance. Sampling error can be estimated
by modeling the time constant of the total input capaci-
tance and the driving source impedance.
Reference Mode 11: The internal bandgap reference
source as well as the internal reference buffer are both
in a shutdown state. The REF pin is in a high-impedance
state. This mode would typically be used when an exter-
nal reference source and external reference buffer is used
to drive all MAX11166/MAX11167 parts in a system.
Although the MAX11166/MAX11167 are easy to drive, an
amplifier buffer is recommended if the source impedance
is such that when driving a switch capacitor of ~20pF a
significant settling error in the desired sampling period will
occur. If this is the case, it is recommended that a con-
figuration shown in the Typical Operating Circuit is used
where at least a 500pF capacitor is attached to the AIN+
pin. This capacitance reduces the size of the transient at
the start of the acquisition period, which in some buffers
will cause an input signal dependent offsets.
Regardless of the reference mode used, the MAX11166/
MAX11167 require a low-impedance reference source on
the REF pin to support 16-bit accuracy. When using the
internal reference buffer, externally bypass the reference
buffer output using at least a 10FF, low-inductance, low-
ESR capacitor placed as close as possible to the REF pin,
thus minimizing additional PCB inductance. When using
the internal bandgap reference source, bypass the REFIO
pin with a 0.1FF capacitor to ground. If providing an exter-
nal reference and using the internal reference buffer, drive
the REFIO pin directly with an external reference source
in the range of 3.0V to 4.25V. Finally, if disabling the
MAX11166/MAX11167 internal bandgap reference source
and internal reference buffer, drive the REF pin with a ref-
erence voltage in the range of 2.5V to 4.25V and place at
least a 10FF, low-inductance, low-ESR capacitor placed
as close as possible to the REF pin .
Regardless of whether an external buffer amp is used or
not, the time constant, R
× C
, of the input
LOAD
SOURCE
should not exceed t
/12, where R
is the total
ACQ
SOURCE
signal source impedance, C
is the total capacitance
LOAD
at the ADC input (external and internal) and t
is the
ACQ
acquisition period. Thus to obtain accurate sampling in a
500ns acquisition time a source impedance of less than
1042ΩꢀshouldꢀbeꢀusedꢀifꢀdrivingꢀtheꢀADCꢀdirectly.ꢀWhenꢀ
driving the ADC from a buffer, it is recommended a series
resistanceꢀ(5Ωꢀtoꢀ50Ωꢀtypical)ꢀbetweenꢀtheꢀamplifierꢀandꢀ
the external input capacitance as shown in the Typical
Operating Circuit.
When using the MAX11166/MAX11167 in external refer-
ence mode, it is recommended that an external reference
buffer be used. For bypass capacitors on the REF pin,
X7R or X5R ceramic capacitors in a 1210 case size or
smaller have been found to provide adequate bypass
performance. Y5U or Z5U ceramics capacitors are not
recommended due to their high voltage and temperature
coefficients.
1) Fast settling time: For multichannel multiplexed appli-
cations the driving operational amplifier must be able
to settle to 16-bit resolution when a full-scale step is
applied during the minimum acquisition time.
Maxim offers a wide range of precision references ideal
for 16-bit accuracy. Table 1 lists some of the options rec-
ommended.
2) Low noise: It is important to ensure that the driver
amplifier has a low average noise density appropriate
for the desired bandwidth of the application. When
the MAX11166/MAX11167 are used with its full band-
width of 6MHz, it is preferable to use an amplifier that
will produce an output noise spectral density of less
thanꢀ6nV/√Hz, to ensure that the overall SNR is not
Input Amplifier
The conversion results are accurate when the ADC
acquires the input signal for an interval longer than the
input signal's worst-case settling time. The ADC input
Table 1. MAX11166/MAX11167 External Reference Recommendations
TEMPERATURE
COEFFICIENT (MAX)
INITIAL
ACCURACY (%)
NOISE (0.1Hz TO
PART
V
(V)
PACKAGE
OUT
10Hz) (µV
)
P-P
µMAX-8
SO-8
MAX6126
2.5, 3, 4.096, 5.0
2.5, 4.096, 5.0
3 (A), 5 (B)
1
0.06
1.35
MAX6325
MAX6341
MAX6350
0.04, 0.02
1.5, 2.4, 3.0
SO-8
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
degraded significantly. It is recommended to insert
an external RC filter at the MAX11166/MAX11167
AIN+ input to attenuate out-of-band input noise and
preserve the ADCs SNR. The effective RMS noise at
the MAX11166/MAX11167 AIN+ input is 64FV, thus
additional noise from a buffer circuit should be sig-
nificantly lower in order to achieve the maximum SNR
performance.
1) This is also the code for an overranged analog
input (V
- V
greater than +K x V
, K =
AIN+
AIN-
REF
5.000/4.096).
2) This is also the code for an underranged analog input
(V
- V
less than -K x V , K = 5.000/4.096)
REF
AIN+
AIN-
5 x V
4.096
-5 x V
REF
+FS =
-FS =
FULL-SCALE
TRANSITION
FFFF
FFFE
3) THD performance: The input buffer amplifier used
should have a comparable THD performance with that
of the MAX11166/MAX11167 to ensure the THD of the
digitized signal is not degraded.
REF
4.096
+FS - (-FS)
65536
LSB =
8001
8000
7FFF
7FFE
Table 2 summarizes the operational amplifiers that are
compatible with the MAX11166/MAX11167. The MAX9632
has sufficient bandwidth, low enough noise and distor-
tion to support the full performance of the MAX11166/
MAX11167. The MAX9633 is a dual amp and can support
buffering for true pseudo-differential sampling.
0001
0000
Transfer Function
The ideal transfer characteristic for the MAX11166/
MAX11167 is shown in Figure 3. The precise location of
various points on the transfer function are given in Table 3.
0
-FS
-FS
-FS + 0.5 × LSB
+FS - 1.5 × LSB
INPUT VOLTAGE (LSB)
Figure 3. Bipolar Transfer Function
Table 2. List of Recommended ADC Driver Op Amps for MAX11166/MAX11167
INPUT-NOISE
DENSITY
(nV/√Hz)
SMALL-SIGNAL
BANDWIDTH
(MHz)
SLEW RATE
(V/µs)
THD
(dB)
I
CC
(mA)
AMPLIFIER
COMMENTS
MAX9632
MAX9633
1
3
55
27
30
18
-128
-128
3.9
3.5
Low noise, THD at 10kHz
Low noise, dual amp, THD at 10kHz
Table 3. Transfer Function Example
CODE TRANSITION
+FS - 1.5 LSB
BIPOLAR INPUT (V)
+4.999771
+0.000076
0
DIGITAL OUTPUT CODE (HEX)
FFFE - FFFF
Midscale + 0.5 LSB
Midscale
8000 - 8001
8000
Midscale - 0.5 LSB
-FS + 0.5 LSB
-0.000076
-4.999924
7FFF - 8000
2
0000 - 0001
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Input Configuration Interface
Configuring in CS Mode
An SPI interface clocked at up to 50MHz controls the
MAX11166/MAX11167. Input configuration data is clocked
into the configuration register on the falling edge of SCLK
through the DIN pin. The data on DIN is used to program
the ADC configuration register. The construct of this reg-
ister is illustrated in Table 4. The configuration register
defines the output interface mode, the reference mode,
and the power-down state of the MAX11166/MAX11167.
Figure 4 details the timing for loading the input configuration
register when the MAX11166/MAX11167 are connected in
CS mode (see Figure 6 and Figure 8 for hardware connec-
tions). The load process is enabled on the falling edge of
CNVST when SCLK is held high. The configuration data is
clocked into the configuration register through DIN on the
next 8 SCLK falling edges. Pull CNVST high to complete
the input configuration register load process. DIN should
idle high outside an input configuration register read.
Table 4. ADC Configuration Register
DEFAULT
STATE
LOGIC
STATE
BIT NAME
BIT
FUNCTION
00
01
10
11
CS Mode, No-Busy Indicator
CS Mode, with Busy Indicator
MODE
7:6
00
Daisy-Chain Mode, No-Busy Indicator
Daisy-Chain Mode, with Busy Indicator
Reference Mode 0. Internal reference and reference buffer are both
powered on.
00
01
Reference Mode 1. Internal reference is turned off, but internal reference
buffer powered on. Apply the external reference voltage at REFIO.
REF
5:4
00
Reference Mode 2. Internal reference is powered on, but the internal
reference buffer is powered off. This mode allows for internal reference to
be used with an external reference buffer.
10
Reference Mode 3. Internal reference and reference buffer are both
powered off. Apply an external reference voltage at REF.
11
0
1
0
Normal Mode. All circuitry is fully powered up at all times.
Static Shutdown. All circuitry is powered down.
Reserved, Set to 0
SHDN
3
0
0
Reserved
2:0
CNVST
SCLK
DIN
t
HSCKCNF
1
t
SSCKCNF
0
2
3
4
SDINSCK
B3
5
6
7
t
t
HDINSCK
B7
B6
B5
B4
B2
B1
B0
Figure 4. Input Configuration Timing in CS Mode
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
CNVST
t
HSCKCNF
2
t
SSCKCNF
SCLK
DIN
0
1
3
4
5
6
7
0
1
2
3
4
5
6
7
t
t
HDINSCK
SDINSCK
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
DATA LOADED TO PART B
SHIFTED THROUGH PART A
DATA LOADED TO PART A
Figure 5. Input Configuration Timing in Daisy-Chain Mode
Configuring in Daisy-Chain Mode
Output Interface
Figure 5 details the configuration register load process
when the MAX11166/MAX11167 are connected in a
daisy-chain configuration (see Figure 12 and Figure 14
for hardware connections). The load process is enabled
on the falling edge of CNVST when SCLK is held high.
In daisy-chain mode, the input configuration registers are
chained together through DOUT to DIN. Device A’s DOUT
will drive device B’s DIN. The input configuration register
is an 8-bit, first-in first-out shift register. The configuration
data is clocked in N times through 8 O N falling SCLK
edges. After the MAX11166/MAX11167 ADCs in the chain
are loaded with the configuration byte, pull CNVST high
to complete the configuration register loading process.
Figure 5 illustrates a configuration sequence for loading
two devices in a chain.
The MAX11166/MAX11167 can be programmed into one
of four output modes; CS modes with and without busy
indicator and daisy-chain modes with and without busy
indicator. When operating without busy indication, the
user must externally timeout the maximum ADC conver-
sion time before commencing readback. When operating
in one of the two busy indication modes, the user can
connect the DOUT output of the MAX11166/MAX11167 to
an interrupt input on the digital host and use this interrupt
to trigger the output data read.
Regardless of the output interface mode used, digital
activity should be limited to the first half of the conversion
phase. Having SCLK or DIN transitions near the sampling
instance can also corrupt the input sample accuracy.
Therefore, keep the digital inputs quiet for approximately
25ns before and 10ns after the rising edge of CNVST.
Data loaded into the configuration register alters the state
of the MAX11166/MAX11167 on the next conversion cycle
after the register is loaded. However, powering up the inter-
nal reference buffer or stabilizing the REFIO pin voltage
will take several milliseconds to settle to 16-bit accuracy.
These times are denoted as t
quent timing diagrams.
and t
in all subse-
SQ
HQ
In all interface modes, the data on DOUT is valid on
both SCLK edges. However, the input setup time into
the receiving digital host will be maximized when data is
clocked into that digital host on the falling SCLK edge.
Doing so will allow for higher data transfer rates between
the MAX11166/MAX11167 and the digital host and conse-
quently higher converter throughput.
Shutdown Mode
The SHDN bit in the configuration register forces the
MAX11166/MAX11167 into and out of shutdown. Set
SHDN to 0 for normal operation. Set SHDN to 1 to shut
down all internal circuitry and reset all registers to their
default state.
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
In all interface modes, it is recommended that the SCLK be
idled low to avoid triggering an input configuration write on
the falling edge of CNVST. If at anytime the device detects
a high SCLK state on a falling edge of CNVST, it will enter
the input configuration write mode and will write the state
of DIN on the next 8 falling SCLK edges to the input con-
figuration register.
Table 5. ADC Output Interface Mode
Selector Guide
MODE
TYPICAL APPLICATION AND BENEFITS
Single or multiple ADCs connected to SPI-
compatible digital host. Ideally suited for
maximum throughput.
CS Mode,
No-Busy
Indicator
In all interface modes, all data bits from a previous conver-
sion must be read before reading bits from a new conver-
sion. When reading out conversion data, if too few SCLK
falling edges are provided and all data bits are not read out,
only the remaining unread data bits will be outputted during
the next readout cycle. In such an event, the output data
in every other readout cycle will appear to have been trun-
cated as only the leftover bits from the previous readout
cycle are outputted. This is an indication to the user that
there are insufficient SCLK falling edges in a given readout
cycle. Table 5 provides a guide to aid in the selection of the
appropriate output interface mode for a given application.
Single ADC connected to SPI-compatible
digital host with interrupt input. Ideally suited
for maximum throughput.
CS Mode,
With Busy
Indicator
Daisy-Chain
Mode,
No-Busy
Indicator
Multiple ADCs connected to a SPI-
compatible digital host. Ideally suited for
multichannel simultaneous sampled isolated
applications.
Daisy-Chain
Mode,
With Busy
Indicator
Multiple ADCs connected to a SPI-
compatible digital host with interrupt input.
Ideally suited for multichannel simultaneous
sampled isolated applications.
CS No-Busy Indicator Mode
The CS no-busy indicator mode is ideally suited for maxi-
mum throughput when a single MAX11166/MAX11167 is
connected to a SPI-compatible digital host. The connec-
tion diagram is shown in Figure 6, and the corresponding
timing is provided in Figure 7.
CONVERT
DIGITAL HOST
A rising edge on CNVST completes the acquisition, initi-
ates the conversion, and forces DOUT to high impedance.
The conversion continues to completion irrespective of the
state of CNVST allowing CNVST to be used as a select line
for other devices on the board. If CNVST is brought low
during a conversion and held low throughout the maximum
conversion time, the MSB will be output at the end of the
conversion.
CNVST
DOUT
DIN
DATA IN
CONFIG
MAX11166
MAX11167
SCLK
CLK
When the conversion is complete, the MAX11166/
MAX11167 enter the acquisition phase. Drive CNVST
low to output the MSB onto DOUT. The remaining data
bits are then clocked by subsequent SCLK falling edges.
DOUT returns to high impedance after the 16th SCLK fall-
ing edge, or when CNVST goes high.
Figure 6. CS No-Busy Indicator Mode Connection Diagram
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
A rising edge on CNVST completes the acquisition, initi-
ates the conversion and forces DOUT to high impedance.
The conversion continues to completion irrespective of
the state of CNVST allowing CNVST to be used as a
select line for other devices on the board.
CS with Busy Indicator Mode
The CS with busy indicator mode is shown in Figure 8
where a single ADC is connected to a SPI-compatible
digital host with interrupt input. The corresponding timing
is given in Figure 9.
t
CNVPW
CNVST
DIN
t
CYC
t
t
ACQ
CONV
ACQUISITION
CONVERSION
ACQUISITION
t
SSCKCNF
t
SCLK
t
SCLKL
t
HSCKCNF
SCLK
DOUT
1
2
3
14
15
16
t
SCLKH
t
t
t
DIS
EN
DDO
D15
D14
D13
D1
D0
Figure 7. CS No Busy Indicator Mode Timing
CONVERT
DIGITAL HOST
OVDD
10kΩ
CNVST
DOUT
DATA IN
MAX11166
MAX11167
IRQ
DIN
CONFIG
SCLK
CLK
Figure 8. CS With Busy Indicator Mode Connection Diagram
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
t
CNVPW
CNVST
DIN
t
CYC
t
t
ACQ
CONV
ACQUISITION
CONVERSION
ACQUISITION
t
SCLK
t
SSCKCNF
t
SCLKL
t
HSCKCNF
SCLK
DOUT
1
2
3
4
15
16
17
t
SCLKH
t
t
DIS
DDO
BUSY BIT
D15
D14
D13
D1
D0
Figure 9. CS With Busy Indicator Mode Timing
When the conversion is complete, DOUT transitions from
high impedance to a low logic level, signaling to the digital
host through the interrupt input that data readback can
commence. The MAX11166/MAX11167 then enter the
acquisition phase. The data bits are then clocked out,
MSB first, by subsequent SCLK falling edges. DOUT
returns to high impedance after the 17th SCLK falling
edge or when CNVST goes high, and is then pulled to
OVDD through the external pullup resistor.
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
irrespective of the state of CNVST allowing CNVST
to be used as a select line for other devices on the
board. However, CNVST must be returned high before
the minimum conversion time for proper operation so
that another conversion is not initiated with insufficient
acquisition time and data correctly read out of the
device.
Multichannel CS Configuration,
Asynchronous or Simultaneous Sampling
The multichannel CS configuration is generally used when
multiple MAX11166/MAX11167 ADCs are connected to an
SPI-compatible digital host. Figure 10 shows the connec-
tion diagram example using two MAX11166/MAX11167
devices. Figure 11 shows the corresponding timing.
When the conversion is complete, the MAX11166/
MAX11167 enter the acquisition phase. Each ADC result
can be read by bringing its CNVST input low, which conse-
quently outputs the MSB onto DOUT. The remaining data
bits are then clocked by subsequent SCLK falling edges.
For each device, its DOUT will return to a high-impedance
state after the 16th SCLK falling edge or when CNVST
goes high. This control allows multiple devices to share
the same DOUT bus.
Asynchronous or simultaneous sampling is possible by
controlling the CS1 and CS2 edges. In Figure 10, the
DOUT bus is shared with the digital host limiting the
throughput rate. However, maximum throughput is pos-
sible if the host accommodates each ADC’s DOUT pin
independently.
A rising edge on CNVST completes the acquisition,
initiates the conversion and forces DOUT to high
impedance. The conversion continues to completion
CS2
CS1
CNVST
DOUT
CNVST
DOUT
DIN
DIGITAL HOST
MAX11166
MAX11166
MAX11167
MAX11167
DIN
CONFIG
DEVICE A
DEVICE B
SCLK
SCLK
DATA IN
CLK
Figure 10. Multichannel CS Configuration Diagram
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
t
t
CNVPW
CNVPW
CNVSTA(CS1)
CNVSTB(CS2)
DIN
t
CYC
t
t
CONV
ACQ
ACQUISITION
t
CONVERSION
ACQUISITION
t
SCLK
SSCKCNF
t
SCLKL
t
HSCKCNF
17
18
19
31
t
32
SCLK
DOUT
1
2
3
15
16
t
SCLKH
t
EN
t
EN
t
DDO
DIS
t
DIS
D15
D14
D13
D1
D0
D15
D14
D13
D1
D0
Figure 11. Multichannel CS Configuration Timing
Each ADC in the chain outputs its MSB data first requir-
ing 16 × N clocks to read back N ADCs.
Daisy-Chain, No-Busy Indicator Mode
The daisy-chain mode with no-busy indicator is ideally
suited for multichannel isolated applications that require
minimal wiring complexity. Simultaneous sampling of
multiple ADC channels is realized on the serial interface
where data readback is analogous to clocking a shift
register. Figure 12 shows a connection diagram of two
MAX11166/MAX11167s configured in a daisy chain. The
corresponding timing is given in Figure 13.
In daisy-chain mode, the maximum conversion rate
is reduced due to the increased readback time. For
instance, with a 6ns or less digital host setup time and
3V interface, up to four MAX11166/MAX11167 devices
running at a conversion rate of 218ksps (MAX11167) or
324ksps (MAX11166) can be daisy-chained.
Daisy-Chain with Busy Indicator Mode
A rising edge on CNVST completes the acquisition and
initiates the conversion. Once a conversion is initiated,
it continues to completion irrespective of the state of
CNVST. When a conversion is complete, the MSB is
presented onto DOUT and the MAX11166/MAX11167
return to the acquisition phase. The remaining data bits
are stored within an internal shift register. To read these
bits out, CNVST is brought low and each bit is shifted
out on subsequent SCLK falling edge. The DIN input
of each ADC in the chain is used to transfer conversion
data from the previous ADC into the internal shift register
of the next ADC, thus allowing for data to be clocked
through the multichip chain on each SCLK falling edge.
The daisy-chain mode with busy indicator is ideally suited
for multichannel isolated applications that require minimal
wiring complexity while providing a conversion complete
indication that can be used to interrupt a host processor
to read data.
Simultaneous sampling of multiple ADC channels is real-
ized on the serial interface where data readback is analo-
gous to clocking a shift register. The daisy-chain mode
with busy indicator is shown in Figure 14 where three
MAX11166/MAX11167s are connected to a SPI-compatible
digital host with corresponding timing given in Figure 15.
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
A rising edge on CNVST completes the acquisition and
initiates the conversion. Once a conversion is initiated, it
continues to completion irrespective of the state of CNVST.
When a conversion is complete, the busy indicator is pre-
sented onto each DOUT and the MAX11166/MAX11167
return to the acquisition phase. The busy indicator for the
last ADC in the chain can be connected to an interrupt input
on the digital host. The digital host should insert a 50ns
delay from the receipt of this interrupt before reading out
data from all ADCs to ensure that all devices in the chain
have completed conversion.
The conversion data is stored within an internal shift reg-
ister. To read these bits out, CNVST is brought low and
each bit is shifted out on subsequent SCLK falling edge.
The DIN input of each ADC in the chain is used to transfer
conversion data from the previous ADC into the internal
shift register of the next ADC, thus allowing for data to be
clocked through the multichip chain on each SCLK falling
edge. The total of number of falling SCLKs needed to read
back all data from N ADCs is 16 × N + 1 edges, the one
additional SCLK falling edge required to clock out the busy
mode bit from the host side ADC.
CONFIG
CONVERT
CNVST
CNVST
DIGITAL HOST
D
D
B
MAX11166
MAX11167
MAX11166
MAX11167
A
DIN
DOUT
DIN
DOUT
DATA IN
DEVICE A
SCLK
DEVICE B
SCLK
CLK
Figure 12. Daisy-Chain, No-Busy Indicator Mode Connection Diagram
t
CNVPW
CNVST
t
CYC
DIN
t
CONV
t
ACQ
ACQUISITION
SCLK
CONVERSION
ACQUISITION
t
t
SSCKCNF
SCLK
t
SCLKL
t
HSCKCNF
1
2
3
14
15
16
17
18
30
31
32
t
SCLKH
t
DDO
D 14
D 15
B
D 13
B
D 1
B
D 0
B
D 15
A
D 14
A
D 1
A
D 0
A
DOUT
B
B
Figure 13. Daisy-Chain, No-Busy Indicator Mode Timing
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
CONFIG
CONVERT
CNVST
CNVST
CNVST
DIGITAL HOST
D
D
B
MAX11166
MAX11167
DEVICE A
SCLK
MAX11166
MAX11167
DEVICE B
SCLK
MAX11166
MAX11167
DEVICE C
SCLK
D
C
A
DIN
DOUT
DIN
DOUT
DIN
DOUT
DATA IN
IRQ
CLK
Figure 14. Daisy-Chain Mode with Busy Indicator Connection Diagram
t
CNVPW
CNVST
t
CYC
DIN
t
t
ACQ
CONV
ACQUISITION
SCLK
CONVERSION
ACQUISITION
t
t
SSCKCNF
48
SCLK
t
t
HSCKCNF
SCLKH
4
1
2
3
15
16
17
18
19
31
32
33
34
35
47
49
t
SCLKL
t
DDO
DOUT = DIN
D 15 D 14 D 13
D 1 D 0
A A
BUSY
BIT
A
B
A
A
A
DOUT = DIN
B
D 15 D 14 D 13
D 1 D 0 D 15 D 14
D 1 D 0
A A
C
B
B
B
B
B
A
A
BUSY
BIT
DOUT
C
D 15 D 14 D 13
D 15 D 14
D 1 D 10
D 1 D 0 D 15 D 14
D 1 D 0
B B
BUSY
BIT
C
C
C
A
A
A
A
C
C
B
B
Figure 15. Daisy-Chain Mode with Busy Indicator Timing
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
In daisy-chain mode, the maximum conversion rate is
reduced due to the increased readback time. For instance,
with a 6ns or less digital host setup time and 3V interface, up
to four MAX11166/MAX11167 devices running at a conver-
sion rate of 217ksps (MAX11167) or 322ksps (MAX11166)
can be daisy-chained on a 3-wire port.
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specification
of less than Q1 LSB guarantees no missing codes and a
monotonic transfer function.
Offset Error
Layout, Grounding, and Bypassing
For the MAX11166/MAX11167, the offset error is defined
at code center 0x8000. This code center should occur at
0V input between AIN+ and AIN-. The offset error is the
actual voltage required to produce code center 0X8000,
expressed in mV.
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines parallel
to one another (especially clock lines), and avoid running
digital lines underneath the ADC package. A single solid
GND plane configuration with digital signals routed from
one direction and analog signals from the other provides
the best performance. Connect the GND and AGNDS pins
on the MAX11166/MAX11167 to this ground plane. Keep
the ground return to the power-supply low impedance and
as short as possible for noise-free operation.
Gain Error
Gain error is defined as the difference between the change
in analog input voltage required to produce a top code
transition minus a bottom code transition, subtracted from
the ideal change in analog input voltage on (5.0V/4.096V)
x V
x (65534/65536). For the MAX11166/MAX11167,
REF
top code transition is 0xFFFE to 0xFFFF. The bottom
code transition is 0x0000 and 0x0001. For the MAX11166/
MAX11167, the analog input voltage to produce these
code transitions is measured and then the gain error is
A 500pF C0G (or NPO) ceramic chip capacitor should
be placed between AIN+ and the ground plane as close
as possible to the MAX11166/MAX11167. This capaci-
tor reduces the inductance seen by the sampling cir-
cuitry and reduces the voltage transient seen by the input
source circuit.
computed by subtracting 2.0 x (5.0V/4.096V) x V
(65534/65536) from this measurement.
x
REF
Signal-to-Noise Ratio
For best performance, connect the REF output to the
ground plane with a 16V, 10FF ceramic chip capacitor
with a X5R or X7R dielectric in a 1210 or smaller case
size. Ensure that all bypass capacitors are connected
directly into the ground plane with an independent via.
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantiza-
tion error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization noise
error only and results directly from the ADC’s resolution
(N bits):
Bypass V
and OVDD to the ground plane with 0.1FF
DD
ceramic chip capacitors on each pin as close as pos-
sible to the device to minimize parasitic inductance.
Add at least one bulk 10FF decoupling capacitor to V
SNR = (6.02 x N + 1.76)dB
DD
and OVDD per PCB. For best performance, bring a
where N = 16 bits. In reality, there are other noise sources
besides quantization noise: thermal noise, reference
noise, clock jitter, etc. SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components not including the fundamental, the
first five harmonics, and the DC offset.
V
DD
power plane in on the analog interface side of the
MAX11166/MAX11167 and a OVDD power plane from the
digital interface side of the device.
Definitions
Integral Nonlinearity
Signal-to-Noise Plus Distortion
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. For these
devices, this straight line is a line drawn between the end
points of the transfer function, once offset and gain errors
have been nullified.
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
Signal
RMS
Differential Nonlinearity
SINAD(dB) = 20 ×log
(Noise + Distortion)
RMS
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. For
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Effective Number of Bits
Aperture Delay
The effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
Aperture delay (t ) is the time delay from the sampling
AD
clock edge to the instant when an actual sample is taken.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
aperture delay.
SINAD −1.76
ENOB =
Small-Signal Bandwidth
6.02
A small -20dBFS analog input signal is applied to an ADC
in a manner that ensures that the signal’s slew rate does
not limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased 3dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Full-Power Bandwidth
2
2
2
2
V
+ V
+ V
+ V
2
3
4
5
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as full-power
input bandwidth frequency.
THD = 10×log
2
1
V
where V is the fundamental amplitude and V through V
are the 2nd- through 5th-order harmonics.
1
2
5
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest fre-
quency component.
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Selector Guide
PART
BITS
16
16
16
16
16
16
16
16
16
16
INPUT RANGE (V)
REFERENCE
Internal
PACKAGE
SPEED (ksps)
MAX11160
MAX11161
MAX11162
MAX11163
MAX11164
MAX11165
MAX11166
MAX11167
MAX11168
MAX11169
0 to 5
0 to 5
0 to 5
0 to 5
0 to 5
0 to 5
±5
µMAX-10
µMAX-10
µMAX-10
µMAX-10
500
250
500
250
500
250
500
250
500
250
Internal
External
External
Internal/External
Internal/External
Internal/External
Internal/External
Internal
3mm x 3mm TDFN-12
3mm x 3mm TDFN-12
3mm x 3mm TDFN-12
3mm x 3mm TDFN-12
µMAX-10
±5
±5
±5
Internal
µMAX-10
Ordering Information
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
PIN-PACKAGE
12 TDFN-EP*
12 TDFN-EP*
MAX11166ETC+T
MAX11167ETC+T
-40°C to +85°C
-40°C to +85°C
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
*EP = Exposed Pad.
12 TDFN-EP
TD1233+1
21-0664
90-0397
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MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
8/12
Initial release
—
Released the MAX11166. Updated the Electrical Characteristics, Typical Operating
Characteristics, Table 2, and the Input Amplifier section.
1
12/12
1–9, 11–14, 26
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2012 Maxim Integrated Products, Inc.
│ 33
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