MAX11254ATJ/V+_技术文档

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

General Description

Beneﬁts and Features

● High Resolution for Industrial Applications that

The MAX11254 is a 6-channel, 24-bit delta-sigma ADC

that achieves exceptional performance while consuming

very low power. Sample rates up to 64ksps allow preci-

sion DC measurements. The MAX11254 communicates

via a SPI serial interface and is available in a small (5mm

x 5mm) TQFN package.

Require a Wide Dynamic Range

• 133dB SNR at 50sps

• 124dB SNR at 1000sps

● Longer Battery Life for Portable Applications

• 2.2mA Operating Mode Current

• 1μA Sleep Current

The MAX11254 offers a 6.2nV/√Hz noise programmable

gain amplifier (PGA) with gain settings from 1x to 128x.

The integrated PGA provides isolation of the signal inputs

from the switched capacitor sampling network. The PGA

also enables the MAX11254 to interface directly with

high-impedance sources without compromising available

dynamic range.

● Single or Split Analog Supplies Provide Input Voltage

Range Flexibility

• 2.7V to 3.6V (Single Supply) or ±1.8V (Split Supply)

● Enables System Integration

• Low Noise, 6.2nV/√Hz PGA with Gains of 1, 2, 4,

The MAX11254 operates from a single 2.7V to 3.6V

analog supply, or split ±1.8V analog supplies, allowing

the analog input to be sampled below ground. The digital

supply range is 1.7V to 2.0V or 2.0V to 3.6V, allowing

communication with 1.8V, 2.5V, 3V, or 3.3V logic.

8, 16, 32, 64, 128

• 6-Channel, Fully Diﬀerential Input

● Enables On-Demand Device and System Gain and

Offset Calibration

• User-Programmable Offset and Gain Registers

Applications

● Analog I/O for Programmable Logic Controllers

● Weigh Scales

● Pressure Sensors

● Robust Performance in a Small Package

• -40°C to +125°C Operating Temperature Range

• TQFN Package, 5mm x 5mm

● Battery-Powered Instrumentation

● Automotive

● AEC-Q100 Qualified, Refer to Ordering Information

for List of /V Parts

Typical Application Circuit

2.7V TO 3.6V

REF

2.0V TO 3.6V

1µF

10nF

1µF

REFN REFP

AIN0P

AVDD

DVDD

1nF

C0G

RSTB

CSB

AIN0N

SCLK

µC

MAX11254

DIN

DOUT

AIN5P

RDYB

1nF

C0G

AIN5N

GPO0 GPO1 GPOGND CAPP CAPN CAPREG AVSS

DGND

220nF

0603

X7R

1nF

C0G

RESISTIVE BRIDGE MEASUREMENT CIRCUIT, SPI CONFIGURATION

19-7542; Rev 5; 9/18

MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Absolute Maximum Ratings

AVDD to AVSS .....................................................-0.3V to +3.9V

AVDD to DGND....................................................-0.3V to +3.9V

DVDD to DGND....................................................-0.3V to +3.9V

AVSS to DGND ..................................................-1.95V to +0.3V

DVDD to AVSS.....................................................-0.3V to +3.9V

AVSS to GPOGND.............................................-1.95V to +0.3V

GPOGND to DGND............................................-1.95V to +0.3V

AIN_P, AIN_N,REFP, REFN,

CAPREG to DGND...............................................-0.3V to +2.1V

All Other Pins to DGND.............................. -0.3V to the lower of

+3.9V or (V

+ 0.3V)

DVDD

Maximum Continuous Current into Any Pins

Except GPOGND Pin...................................................±50mA

Maximum Continuous Current into

GPOGND Pin .............................................................±100mA

Continuous Power Dissipation (T = +70°C)

A

CAPP, CAPN to AVSS ............................ -0.3V to the lower of

TQFN (derate 34.5mW/°C above +70°C)...............2758.6mW

Operating Temperature Range......................... -40°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range............................ -55°C to +150°C

Soldering Temperature (reflow).......................................+260°C

+3.9V or (V

+ 0.3V)

AVDD

GPO_ to GPOGND .................................... -0.3V to the lower of

+3.9V or (V + 0.3V)

AVDD

CAPREG to AVSS................................................-0.3V to +3.9V

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

(Note 1)

Package Thermal Characteristics

TQFN

Junction-to-Ambient Thermal Resistance (θ )…….29°C/W

JA

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics

(V

= 3.6V, V

= 0V, V

= 2.0V to 3.6V, V

- V

= V

, DATA RATE = 1ksps, PGA low-noise mode, single-cycle

AVDD

AVSS

DVDD

REFP

REFN

conversion mode (SCYCLE = 1). T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)(Note 2)

MAX A

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE (Single-Cycle Conversion Mode)

PGA low-

noise mode

PGA gain of

128, single-cycle

mode at 1ksps

data rate

0.19

0.26

0.83

1.16

0.83

PGA low-

power mode

PGA low-

noise mode

PGA gain of 128,

single-cycle

mode at 12.8ksps

data rate

Noise Voltage

(Referred to Input)

V

µV

RMS

n

PGA low-

power mode

PGA low-

noise mode

PGA gain of 128,

continuous

mode at 64ksps

data rate

PGA low-

power mode

1.16

3

Integral Nonlinearity

Zero Error

INL

15

ppm

After system zero-scale

calibration

Z

1

µV

ERR

Zero Drift

Z

50

2

nV/°C

Drift

After system full-scale

calibration (Notes 3 and 4)

Full-Scale Error

FSE

ppmFSR

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Electrical Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V to 3.6V, V

- V

= V

, DATA RATE = 1ksps, PGA low-noise mode, single-cycle

AVDD

AVSS

DVDD

REFP

REFN

conversion mode (SCYCLE = 1). T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)(Note 2)

MAX A

A

MIN

PARAMETER

SYMBOL

FSE

CONDITIONS

MIN

TYP

0.05

130

105

95

MAX

UNITS

Full-Scale Error Drift

ppmFSR/°C

Drift

DC rejection

110

80

50Hz/60Hz rejection (Note 5)

DC rejection with PGA gain 64

DC rejection with PGA gain 128

DC rejection

Common-Mode Rejection

CMR

dB

73

75

95

AVDD, AVSS Supply Rejection

Ratio

PSRRA

PSRRD

50Hz/60Hz rejection (Note 5)

DC rejection with PGA gain 128

DC rejection

95

dB

65

75

105

90

115

110

DVDD Supply Rejection Ratio

50Hz/60Hz rejection (Note 5)

DC rejection with PGA gain 128

PGA

Gain Setting

1

128

V/V

Low-noise mode

Low-power mode

Gain = 1

6.2

10

0.75

1.2

2

Noise-Spectral Density

NSD

nV/√Hz

Gain = 2

Gain = 4

Gain = 8

3

Gain Error, Not Calibrated

Output Voltage Range

G

%

ERR

Gain = 16

4.5

6

Gain = 32

Gain = 64

5.5

2

Gain = 128

V

AVSS

+ 0.3

V

AVDD

- 0.3

VOUT

V

RNG

MUX

Channel-to-Channel Isolation

GENERAL-PURPOSE OUTPUTS

ISO

DC

140

dB

CH-CH

GPO_ output current = 30mA,

GPOGND connected to AVSS

Resistance (On)

R

3.5

30

10

90

Ω

ON

Per output

mA

Maximum Current (On)

I

MAX

Total from all outputs into

GPOGND pin (Note 5)

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Electrical Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V to 3.6V, V

- V

= V

, DATA RATE = 1ksps, PGA low-noise mode, single-cycle

AVDD

AVSS

DVDD

REFP

REFN

conversion mode (SCYCLE = 1). T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)(Note 2)

MAX A

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Current into the GPOGND pin

with one individual GPO_ pin

connected to 3V

I

0.4

leak1

leak3

Leakage Current (Oﬀ)

nA

Current into the GPOGND pin

with all GPO_ pins connected

to 3V

I

13

100

POWER-UP DELAYS (Note 5)

SLEEP state (full power-down)

to LDO wake-up

T

23

4

45

8

PUPSLP

V

= 2.7V, V

= 2.0V,

AVDD

DVDD

CAPREG = 220nF

Power-Up Time

µs

STANDBY state (analog blocks

powered down, LDO on) to

Active

T

PUPSBY

ANALOG INPUTS/REFERENCE INPUTS

Direct (PGA bypassed)

V

AVDD

Common-Mode Input Voltage

AVSS

Range,

= (V

CMI

V

RNG

V

+ 0.4

V

AVSS

AVDD

- 1.3

PGA

V

+ V

)/2

CM

AIN_P

AIN_N

Direct (PGA bypassed)

PGA

V

AVSS

AVDD

Input Voltage Range (AIN_P,

AIN_N)

V

+ 0.4

IN(RNG)

AVSS

AVDD

- 1.3

Unipolar

0

V

REF

Diﬀerential Input Voltage

Range (AIN_P – AIN_N)

V

IN(DIFF)

Bipolar

-V

+V

REF

DC Input Leakage

I

SLEEP state enabled

Direct (PGA bypassed)

PGA enabled

±0.1

±11.6

±1

nA

µA/V

nA

IN_LEAK

Diﬀerential Input Conductance

Diﬀerential Input Current

G

DIFF

I

DIFF

Common-Mode Input

Conductance

G

Direct (PGA bypassed)

PGA enabled

±1

±10

26

µA/V

nA

CM

Common-Mode Input Current

I

CM

Reference Diﬀerential

Input Resistance

R

Active state

kΩ

REF

Reference Diﬀerential

Input Current

I

STANDBY and SLEEP state

±1

nA

pF

REF_PD

C

Direct (PGA bypassed)

PGA

2.5

0.25

4.096

IN

Input Capacitance

CP

GAIN

AIN_P, AIN_N Sampling Rate

f

MHz

V

S

Reference Voltage Range

(REFP, REFN)

V

(Note 6)

V

AVDD

REF(RNG)

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Electrical Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V to 3.6V, V

- V

= V

, DATA RATE = 1ksps, PGA low-noise mode, single-cycle

AVDD

AVSS

DVDD

REFP

REFN

conversion mode (SCYCLE = 1). T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)(Note 2)

MAX A

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

Diﬀerential Reference Voltage

Range (REFP – REFN)

V

1.5

V

AVDD

REF

REFP, REFN Sampling Rate

4.096

MHz

SENSOR FAULT DETECT CURRENTS

Current

1.1

±10

0.3

µA

%

Initial Tolerance

Drift

%/°C

DIGITAL SINC FILTER RESPONSE

0.203

x DATA

RATE

Bandwidth (-3dB)

Hz

s

5/DATA

RATE

Settling Time (Latency)

LOGIC INPUTS

Input Current

IDIGI

Leakage current

±1

µA

V

LEAK

0.3 x

Input Low Voltage

V

IL

V

DVDD

0.7 x

Input High Voltage

V

IH

V

DVDD

Input Hysteresis

V

200

20

mV

V

HYS

GPIO Input Low Voltage

GPIO Input High Voltage

GPIO Input Hysteresis

LOGIC OUTPUTS

V

0.3

IL_GPIO

IH_GPIO

V

1.2

V

mV

HYS_GPIO

Output Low Level

V

I

= 1mA

0.4

V

OL

Output High Level (RDYB,

DOUT, GPIO_ )

0.9 x

V

= 1mA

OH

V

DVDD

Floating State Leakage Current

IDIGO

±10

µA

pF

LEAK

DIGO

Floating State Output

Capacitance

C

9

POWER REQUIREMENTS

Negative Analog Supply

Voltage

V

-1.8

0

V

AVSS

V

AVSS

+ 3.6

AVSS

+ 2.7

Positive Analog Supply Voltage

Negative I/O Supply Voltage

V

AVDD

V

0

DGND

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Electrical Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V to 3.6V, V

- V

= V

, DATA RATE = 1ksps, PGA low-noise mode, single-cycle

AVDD

AVSS

DVDD

REFP

REFN

conversion mode (SCYCLE = 1). T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)(Note 2)

MAX A

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CAPREG not driven by external

supply

2.0

3.6

Positive I/O Supply Voltage

V

DVDD

DVDD and CAPREG pins

connected together on the circuit

board

1.7

1.8

1.7

2.0

Internal LDO enabled

When CAPREG pin is driven

externally, ensure it is connected

directly to DVDD pin

CAPREG Supply Voltage

V

CAPREG

Direct

2.2

3.5

3

Analog Supply Current

I

PGA low-power mode

PGA low-noise mode

4.7

5.75

1.1

mA

AVDD(CNV)

4.2

V

= 2.0V, LDO enabled

0.65

DVDD

DVDD Operating Current

I

DVDD(CNV)

V

= V

= 2.0V,

CAPREG

0.58

LDO disabled

V

= 3.6V, V

= 2.0V

= 0V,

AVDD

DVDD

AVSS

AVDD Sleep Current

DVDD Sleep Current

AVDD Standby Current

1

µA

I_AVDD(SLP)

I

V

= 2.0V

0.3

1.5

50

2.3

DVDD(SLP)

AVDD(SBY)

DVDD

V

= 3.6V, V

= 2.0V

AVDD

DVDD

I

V

= 2.0V, LDO enabled

175

DVDD

DVDD Standby Current

I

µA

V

= V

= 2.0V,

DVDD(SBY)

CAPREG

2.5

LDO disabled

AVDD, DVDD supply

undervoltage lockout

0.8

0.65

0.6

1.2

1.0

1.1

1.65

1.35

1.55

UVLO Threshold Low to High

V

LH

HL

CAPREG supply undervoltage

lockout

AVDD, DVDD supply

undervoltage lockout

UVLO Threshold High to Low

V

CAPREG supply undervoltage

lockout

0.45

0.95

1.3

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Electrical Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V to 3.6V, V

- V

= V

, DATA RATE = 1ksps, PGA low-noise mode, single-cycle

AVDD

AVSS

DVDD

REFP

REFN

conversion mode (SCYCLE = 1). T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)(Note 2)

MAX A

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

AVDD, DVDD supply

undervoltage lockout

4

UVLO Hysteresis

V

%

HYS

CAPREG supply undervoltage

lockout

5

AVDD, DVDD supply

undervoltage lockout

10

3.5

10

UVLO Delay Low to High or

High to Low

T

µs

ns

DEL

CAPREG supply undervoltage

lockout

AVDD, DVDD supply

undervoltage lockout

UVLO Glitch Suppression

T

P

CAPREG supply undervoltage

lockout

SPI 24B DATA READ

RDYB

CSB

t_CSW

t_R1

t_CSS0

t_CSH1

t_CH

t_CL

t_CP

9

t_CSS1

SCLK

DIN

1

8

31

24b data

t_DS

t_DH

‘X’

‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’ ‘1’

t_DOE

t_DOT

t_DOH

t_DOD

HIGH-Z

DOUT

‘X’

MSB

LSB

Figure 1. SPI Timing Diagram

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

SPI Timing Requirements

(V

= 3.6V, V

= 0V, V

= 1.7V to 3.6V, T = T

to T

, unless otherwise noted. For output pins, C = 20pF.)

LOAD

AVDD

AVSS

DVDD

A

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

0.05

125

50

TYP

MAX

UNITS

MHz

ns

SCLK Frequency

f

Note 5 applies to minimum value

8

SCLK

SCLK Clock Period

t

CP

SCLK Pulse-Width High

SCLK Pulse-Width Low

CSB Low Setup

t

Allow 40% duty cycle

ns

CH

t

Allow 40% duty cycle

50

ns

CL

t

CSB low to 1st SCLK rise setup

40

ns

CSS0

CSB rising edge to SCLK rising edge

setup time (Note 5)

CSB High Setup

SCLK Fall Hold

40

3

ns

CSS1

SCLK falling edge to CSB rising edge,

SCLK hold time

t

CSH1

CSB Pulse Width

DIN Setup

t

Minimum CSB pulse-width high

DIN setup to SCLK rising edge

DIN hold after SCLK rising edge

40

0

ns

CSW

t

DS

DIN Hold

t

DH

DOUT transition valid after SCLK fall

(Note 5)

DOUT Transition

DOUT Hold

t

40

ns

DOT

Output hold time remains valid after

SCLK fall (Note 5)

t

3

DOH

DOD

DOUT Disable

CSB rise to DOUT disable (Note 5)

(Note 5)

25

40

ns

CSB Fall to DOUT Valid

t

0

DOE

RDYB transitions from ‘0’ to ‘1’ on

rising edge of SCLK when LSB-1 of

DATA is shifted onto DOUT (Note 5)

SCLK Rise to RDYB ‘1’

RSTB Fall to RDYB ‘1’

t

40

ns

R1

RDYB transition from ‘0’ to ‘1’ on

falling edge of RSTB, internal clock

mode (Note 5)

300

t

R2

RDYB transition from ‘0’ to ‘1’ on

falling edge of RSTB, external clock

2/f

s

CLK

mode, clock frequency = f

(Note 5)

CLK

Note 2: Limits are 100% tested at T = +25°C, unless otherwise noted. Limits over the operating temperature range and relevant

A

supply voltage range are guaranteed by design and characterization.

Note 3: Full-scale error includes errors from gain and offset or zero-scale error.

Note 4: ppmFSR is parts per million of full-scale range.

Note 5: These specifications are guaranteed by design, characterization, or SPI protocol.

Note 6: Reference common mode (V

+ V

)/2 ≤ (V

+ V

)/2 + 0.1V.

REFP

REFN

AVDD

AVSS

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Typical Operating Characteristics

(V

= +3.6V, V

= 0V, V

= +2.0V, V

- V

= V

; T = T

to T

, LDO enabled, PGA enabled, unless oth-

MAX

AVDD

AVSS

DVDD

REFP

REFN

AVDD

A

MIN

erwise noted. Data rate = 1ksps, single-cycle conversion mode (SCYCLE = 1) Typical values are at T = +25°C.)

A

INPUT-REFERRED NOISE

vs. COMMON-MODE VOLTAGE

INL vs. INPUT VOLTAGE

toc02

toc03

toc01

5

4

0.50

0.40

0.30

0.20

0.10

0.00

5

4

PGA GAIN = 4V/V

PGA GAIN = 128V/V

BYPASS MODE

T_A= -40°C

T_A= +25°C

T_A= +125°C

3

2

T_A= +25°C

1

T_A= +125°C

T_A= -40°C

0

-1

-2

-3

-4

-5

-1

-2

-3

-4

-5

T_A= -40°C

T_A= +125°C

0

0.5

1

1.5

2

2.5

-3.5 -2.5 -1.5 -0.5

0.5

1.5

2.5

3.5

-3.5 -2.5 -1.5 -0.5

0.5

1.5

2.5

3.5

COMMON-MODE VOLTAGE (V)

DIFFERENTIAL INPUT (V)

INPUT-REFERRED NOISE

vs. TEMPERATURE

OFFSET ERROR

vs. TEMPERATURE

OFFSET ERROR

vs. AVDD VOLTAGE

toc04

toc05

toc06

0.5

0.4

0.3

0.2

0.1

0.0

0

-5

5

0

PGA GAIN = 128V/V

BYPASS MODE

T_A= +125°C

T_A= -40°C

-10

-15

-20

-25

-5

BYPASS MODE

-10

-15

-20

T_A= +25°C

PGA = 4

-50

0

50

100

150

-40 -25 -10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

2.7

3

3.3

3.6

V_AVDD(V)

TEMPERATURE (°C)

OFFSET ERROR

vs. V_REFP- V_REFN

OFFSET ERROR

vs. V_REFP- V_REFN

OFFSET ERROR

vs. AVDD VOLTAGE

toc09

toc08

toc07

5

-5

10

0

PGA = 4

BYPASS MODE

T_A= -40°C

PGA = 4

T_A= -40°C

-8

-13

-18

-23

-28

T_A= -40°C

-15

-25

-35

-45

-55

-10

-20

-30

-40

-50

T_A= +25°C

T_A= +125°C

1.5

2.2

2.9

3.6

1.5

2.2

2.9

3.6

2.7

3

3.3

3.6

V_AVDD(V)

V_REFP- V_REFN(V)

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Typical Operating Characteristics (continued)

(V

= +3.6V, V

= 0V, V

= +2.0V, V

- V

= V

; T = T

to T

, LDO enabled, PGA enabled, unless oth-

MAX

AVDD

AVSS

DVDD

REFP

REFN

AVDD

A

MIN

erwise noted. Data rate = 1ksps, single-cycle conversion mode (SCYCLE = 1) Typical values are at T = +25°C.)

A

INTERNAL OSCILLATOR FREQUENCY

vs. TEMPERATURE

INTERNAL OSCILLATOR FREQUENCY

vs. DVDD VOLTAGE

INTERNAL OSCILLATOR FREQUENCY

vs. DVDD VOLTAGE

toc12

toc10

toc11

8.5

8.4

8.3

8.2

8.1

8.0

8.20

8.19

8.18

8.17

8.16

8.20

8.19

8.18

8.17

8.16

LDO DISABLED

LDO ENABLED

-40 -25 -10

5

20 35 50 65 80 95 110 125

1.7

1.8

1.9

2

2.5

3

3.5

V_DVDD(V)

TEMPERATURE (°C)

V_DVDD(V)

PSRR

ACTIVE CURRENT

vs. TEMPERATURE

vs. FREQUENCY ON AVDD

vs. FREQUENCY ON DVDD

toc13

toc15

toc14

-85

-90

-100

-105

-110

-115

-120

-125

-130

f_sample= 64ksps

BYPASS MODE

V_AVDD= 3.3V 50mV_P-P

f_sample= 64ksps

Bypass Mode

_DVDD= 2.1V 50mV_P-P

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

PGA LOW NOISE

T_A= -40°C

V

T_A= +125°C

-95

T_A= +25°C

-100

-105

-110

-115

-120

I_AVDD

T_A= -40°C

I_DVDD

T_A= +125°C

T_A= +25°C

10

100

1000

10000 100000 1000000

-40 -25 -10

5

20 35 50 65 80 95 110 125

10

100

1000

10000 100000 1000000

FREQUENCY ON AVDD (Hz)

TEMPERATURE (°C)

FREQUENCY ON DVDD (Hz)

STANDBY CURRENT

vs. TEMPERATURE

ACTIVE CURRENT

vs. AVDD VOLTAGE

SLEEP CURRENT

vs. TEMPERATURE

toc17

toc18

toc16

100

10

1

6

5.5

5

3

2.5

2

PGA LOW NOISE

I_{DVDD_STBY}

T_A= +125°C

4.5

4

1.5

1

I_{AVDD_SLEEP}

T_A= +25°C

T_A= -40°C

I_{AVDD_STBY}

3.5

3

0.5

0

I_{DVDD_SLEEP}

-40 -25 -10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

2.7

3

3.3

3.6

-40 -25 -10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

V_AVDD(V)

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Typical Operating Characteristics (continued)

(V

= +3.6V, V

= 0V, V

= +2.0V, V

- V

= V

; T = T

to T

, LDO enabled, PGA enabled, unless oth-

MAX

AVDD

AVSS

DVDD

REFP

REFN

AVDD

A

MIN

erwise noted. Data rate = 1ksps, single-cycle conversion mode (SCYCLE = 1) Typical values are at T = +25°C.)

A

STANDBY CURRENT

vs. AVDD VOLTAGE

ACTIVE CURRENT

vs. DVDD VOLTAGE

SLEEP CURRENT

vs. AVDD VOLTAGE

toc20

toc21

toc19

750

730

710

690

670

650

630

610

590

LDO ENABLED

2.5

2

2.8

2.3

1.8

1.3

0.8

0.3

T_A= +125°C

1.5

1

T_A= -40°C

T_A= +25°C

T_A= -40°C

0.5

0

T_A= +25°C

3.3

2.7

3

3.3

3.6

2

2.4

2.8

3.2

3.6

2.7

3

3.6

V_AVDD(V)

V_DVDD(V)

SLEEP CURRENT

vs. DVDD VOLTAGE

STANDBY CURRENT

vs. DVDD VOLTAGE

toc23

toc22

90

80

70

60

50

40

LDO DISABLED

LDO ENABLED

1.4

T_A= +125°C

1.2

1

T_A= -40°C

0.8

0.6

0.4

0.2

T_A= +125°C

T_A= +25°C

T_A= -40°C

2

2.4

2.8

3.2

3.6

2

2.4

2.8

V_DVDD(V)

3.2

3.6

V_DVDD(V)

THD

vs. FREQUENCY

OUTPUT SPECTRUM

SHORTED INPUTS

SNR

vs. TEMPERATURE

toc25

toc26

toc24

0

-20

0

120

119

118

117

116

115

BYPASS MODE

CONTINUOUS

_sample= 8ksps

BYPASS MODE

SINGLE CYCLE CONTINOUS

BYPASS MODE

SINGLE CYCLE CONTINUOUS

_sample= 1ksps

-20

-40

f

f_sample= 1ksps

f

-40

-60

-80

-100

-120

-140

-160

-180

-80

-100

-120

-140

-40

10

60

110

0

200

400

600

800

1000

0

100

200

300

400

500

TEMPERATURE (ºC)

FREQUENCY (Hz)

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Pin Conﬁguration

+

RDYB

SCLK

AVDD

AVSS

REFP

REFN

AIN0N

AIN0P

1

24 GPO0

2

3

4

5

6

7

8

23 GPIO0/CLK

22 GPO1

21 GPOGND

MAX11254

20 CAPP

19 CAPN

18 AIN5P

17 AIN5N

EP

Pin Description

NAME

FUNCTION

Active-Low Data Ready Output. RDYB goes low when a new conversion result is available in the

data register. When a read operation of a full output word completes, RDYB returns high. RDYB is

1

RDYB

always driven.

2

3

SCLK

AVDD

AVSS

REFP

REFN

AIN0N

AIN0P

AIN1N

AIN1P

SPI Serial Clock Input

Positive Analog Supply

Negative Analog Supply

Positive Reference Input

Negative Reference Input

Negative Analog Input 0

Positive Analog Input 0

Negative Analog Input 1

Positive Analog Input 1

4

5

6

7

8

9

10

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Pin Description (continued)

11

NAME

AIN2N

AIN2P

AIN3N

AIN3P

AIN4N

AIN4P

AIN5N

AIN5P

CAPN

FUNCTION

Negative Analog Input 2

Positive Analog Input 2

Negative Analog Input 3

Positive Analog Input 3

Negative Analog Input 4

Positive Analog Input 4

Negative Analog Input 5

Positive Analog Input 5

12

13

14

15

16

17

18

19

20

21

PGA Filter Input. Connect 1nF C0G capacitor between CAPP and CAPN.

Analog Switch/General-Purpose Output, GND Terminal

CAPP

GPOGND

Analog Switch Normally Open Terminal/General-Purpose Output 1. Register controlled, close

position connects GPO1 to GPOGND. Current sink only.

22

23

24

GPO1

General-Purpose I/O Pin (Default) or External Clock Signal for the Device. When external clock

mode is selected, provide a digital clock signal at this pin. The MAX11254 is speciﬁed with a clock

frequency of 8.192MHz. Clock frequencies below 8.192MHz are supported. The data rate and

digital ﬁlter notch frequencies scale with the clock frequency.

GPIO0/

CLK

Analog Switch Normally Open Terminal/General-Purpose Output 0. Register controlled, close

position connects GPO0 to GPOGND. Current sink only.

GPO0

Synchronization Input (default) or General-Purpose I/O Pin. SYNC resets both the digital ﬁlter and

the modulator. Connect SYNC from multiple MAX11254s in parallel to synchronize more than one

ADC to an external trigger.

GPIO1/

SYNC

25

26

1.8V Subregulator Output. Connects to DVDD when driven externally by a 1.8V supply. Connect a

220nF or larger capacitor between CAPREG and DGND.

CAPREG

27

28

29

30

31

32

—

RSTB

DVDD

DGND

DOUT

CSB

Active-Low Power-On-Reset Input

Digital Power Supply, 1.7V to 3.6V

Digital Ground

Serial Data Output

Active-Low Chip-Select Input

Serial Data Input

DIN

EP

Exposed Pad. Connect EP directly to AVSS plane.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Functional Diagram

AVDD

AVSS

DVDD

AVDD

DGND

CLOCK

GENERATOR

1µA

TIMING

AIN0P

AIN0N

AIN1P

AIN1N

AIN2P

AIN2N

AIN3P

AIN3N

AIN4P

AIN4N

AIN5P

AIN5N

RSTB

CSB

SCLK

DIN

DELTA-SIGMA

ADC

DIGITAL

FILTER

SERIAL

INTERFACE

MUX

PGA

DOUT

RDYB

GPIO0/CLK

GPIO1/SYNC

GPOGND

1µA

1.8V

REGULATOR

AVSS

CAPP CAPN REFP REFN

CAPREG

GPO0 GPO1

Voltage Reference Inputs

Detailed Description

The MAX11254 provides diﬀerential inputs REFP and

REFN for an external reference voltage. Connect the

external reference directly across the REFP and REFN

pins to obtain the diﬀerential reference voltage. The

The MAX11254 is a 24-bit delta-sigma ADC that achieves

exceptional performance consuming minimal power.

Sample rates up to 64ksps support precision DC mea-

surements. The built-in sequencer supports scanning

of selected analog channels, programmable conversion

delay, and math operations to automate sensor monitor-

ing.

V

voltage should always be greater than the V

REFP

REFN

voltage, and the common-mode voltage range is between

0.75V and V - 0.75V.

AVDD

The fourth order delta-sigma modulator is unconditionally

stable and measures six differential input voltages. The

modulator is monitored for overrange conditions, which

are reported in the status register. The digital filter is a

variable decimation-rate SINC filter with overflow monitor-

ing reported in the status register.

Analog Inputs

The MAX11254 measures six pairs of diﬀerential analog

inputs (AIN_P, AIN_N) in direct connection or buﬀered

through the PGA.

See the CTRL2: Control Register 2 (Read/Write) table

for programming and enabling the PGA or direct connect

mode. The default conﬁguration is direct connect, with the

PGA powered down.

The programmable gain differential amplifier (PGA) is low

noise and is programmable from 1 to 128. The PGA buf-

fers the modulator and provides a high-impedance input

to the analog channels.

Bypass/Direct Connect

System Clock

The MAX11254 oﬀers the option to bypass the PGA and

route the analog inputs directly to the modulator. This

option lowers the power of the device since the PGA is

powered down.

The MAX11254 incorporates a highly stable internal oscil-

lator that provides the system clock. The system clock is

trimmed to 8.192MHz, providing digital and analog timing.

The MAX11254 also supports an external clock mode.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Programmable Gain Ampliﬁer (PGA)

Input Voltage Range

The integrated PGA provides gain settings from 1x to

128x. (Figure 2). Direct connection is available to bypass

the PGA and directly connect to the modulator. The PGA’s

The ADC input range is programmable for bipolar (-V

REF

to +V

) or unipolar (0 to VREF) ranges. The U/B bit in

REF

the CTRL1 register conﬁgures the MAX11254 for unipolar

or bipolar transfer functions.

absolute input voltage range is CMI

and the PGA

RNG

output voltage range is VOUT

Electrical Characteristics.

, as specified in the

RNG

Data Rates

Table 1 lists the available data rates for the MAX11254,

RATE[3:0] setting of the conversion command (see the

Modes and Registers section). The single-cycle mode has

an overhead of 48 digital master clocks that is approxi-

mately 5.86µs for a typical digital master clock frequency

of 8.192MHz. The single-cycle effective column contains

the data rate values including the 48 clock startup delays.

The 48 clocks are required to stabilize the modulator at

startup. In continuous conversion mode, the output data

rate is five times the single-cycle rate up to a maximum

of 64ksps. During continuous conversions, the output

sample data requires five 24-bit cycles to settle to a valid

conversion from an input step, PGA gain changes, or a

change of input channel through the multiplexer.

Note that linearity and performance degrade when the

specified input common-mode voltage of the PGA is

exceeded. The input common-mode range and output

common-mode range are shown in Figure 3. The fol-

lowing equations describe the relationship between the

analog inputs and PGA output.

AINP = Positive input to the PGA

AINN = Negative input to the PGA

CAPP = Positive output of PGA

CAPN = Negative output of PGA

V

CM

= Input common mode

GAIN = PGA gain

If self-calibration is used, 48 additional master clocks are

required to process the data per conversion. Likewise,

system calibration takes an additional 48 master clocks to

complete.

V

= ADC reference input voltage

REF

= V

- V

AINN

IN

AINP

Note: Input voltage range is limited by the reference volt-

If both self and system calibration are used, it takes an

additional 80 master clocks to complete. If self and/or

system calibration are used, the effective data rate will be

age as described by V

≤ ±V

/GAIN

IN

REF

reduced by these additional clock cycles per conversion

.

V

+ V

(

)

AINP

AINN

V

=

CM

Noise Performance

2

The MAX11254 provides exceptional noise performance.

SNR is dependent on data rate, PGA gain, and power

mode. Bandwidth is reduced at low data rates; both noise

and SNR are improved proportionally. Tables 2 and 3

summarize the noise performance for both single-cycle

V

= V

+ GAIN× V

− V

CM

(

)

CAPP

CM

AINP

− V

AINN

V

− GAIN× V

(

)

CAPN

CM

AINP

R3

CAPP

A1

R1

C_CAPP/N

(C0G capacitor)

R2

R1

R3

CAPN

A2

AINN

Figure 2. Simplified Equivalent Diagram of the PGA

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Table 1. Available Programmable Data Rates

DATA RATE (sps)

CONVERSION PLUS

CONVERSION

PLUS SELF-

SINGLE

CYCLE

CONVERSION

SELF-CALIBRATION

PLUS SYSTEM

RATE[3:0]

CONTINUOUS

ONLY

CALIBRATION*

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1.9

3.9

50

62.5

100

50.01

62.51

49.99

62.48

49.98

62.47

7.8

99.98

99.92

99.88

15.6

31.2

62.5

125

124.95

199.80

249.66

398.98

498.34

796.11

991.86

1578.72

1974.16

3114.26

3895.78

6135.27

11776.90

124.86

199.57

249.29

398.05

496.89

792.41

986.13

1564.26

1951.60

3058.48

3808.89

5922.49

11017.10

124.80

199.41

249.05

397.44

495.93

789.97

982.35

1554.77

1936.84

3022.39

3753.08

5788.64

10562.79

200

250

400

250

500

800

1000

2000

4000

8000

16000

32000

64000

1000

1600

2000

3200

4000

6400

12800

*The eﬀective data rate is lower when the calibration is enabled due to additional MAC (multiply/accumulate) operations required after

the conversion is complete to perform the calibration adjustment.

ANALOG INPUTS

PGA OUTPUT

V

AVDD

V

AVDD

- 0.3V

OUTPUT VOLTAGE RANGE = GAIN

x INPUT VOLTAGE RANGE

V

AVDD

- 1.3V

COMMON-MODE

INPUT VOLTAGE

≤ V

REF

INPUT VOLTAGE RANGE

V

+ 0.4V

AVSS

V

+ 0.3V

AVSS

V

AVSS

Figure 3. Analog Input Voltage Range Compared to PGA Output Range

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Table 2. Noise vs. PGA Mode and Gain (Single-Cycle Conversion)

SINGLE-CYCLE CONVERSION MODE

INPUT-REFERRED NOISE VOLTAGE (µV

) vs. PGA GAIN SETTING

RMS

DATA

RATE

(sps)

1

2

4

8

16

32

64

128

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

50

0.81

0.88

1.18

1.24

1.38

1.63

1.79

2.12

2.38

3.21

3.76

4.41

5.18

7.34

0.58 0.38 0.27 0.18 0.13 0.10 0.07 0.09 0.07 0.08 0.06 0.08 0.06 0.08 0.06

0.63 0.48 0.34 0.21 0.15 0.12 0.09 0.09 0.07 0.08 0.06 0.08 0.05 0.08 0.05

0.84 0.61 0.44 0.30 0.21 0.17 0.12 0.12 0.08 0.09 0.07 0.09 0.07 0.10 0.07

0.89 0.59 0.42 0.31 0.22 0.18 0.13 0.12 0.08 0.10 0.07 0.10 0.07 0.10 0.07

0.99 0.68 0.49 0.35 0.25 0.21 0.15 0.15 0.10 0.12 0.08 0.11 0.08 0.11 0.08

0.99 0.72 0.52 0.39 0.28 0.23 0.16 0.16 0.11 0.13 0.09 0.12 0.09 0.12 0.09

1.16 0.85 0.61 0.45 0.32 0.27 0.19 0.19 0.14 0.16 0.12 0.15 0.11 0.16 0.11

1.28 0.93 0.66 0.48 0.34 0.29 0.21 0.21 0.15 0.18 0.13 0.17 0.12 0.18 0.13

1.51 1.10 0.79 0.61 0.43 0.36 0.26 0.27 0.20 0.24 0.17 0.23 0.16 0.23 0.16

1.70 1.25 0.89 0.69 0.49 0.41 0.29 0.31 0.22 0.27 0.19 0.26 0.18 0.26 0.19

2.29 1.67 1.19 0.89 0.64 0.56 0.40 0.41 0.29 0.36 0.26 0.35 0.25 0.35 0.25

2.69 1.95 1.39 1.04 0.74 0.65 0.47 0.48 0.34 0.43 0.30 0.41 0.29 0.42 0.30

3.15 2.28 1.63 1.25 0.89 0.78 0.55 0.58 0.41 0.51 0.36 0.49 0.35 0.49 0.35

3.70 2.68 1.91 1.48 1.06 0.91 0.65 0.69 0.49 0.60 0.43 0.58 0.41 0.59 0.42

5.24 3.83 2.73 2.08 1.48 1.29 0.92 0.98 0.70 0.86 0.61 0.81 0.58 0.83 0.59

62.5

100

125

200

250

400

500

800

1,000

1,600

2,000

3,200

4,000

6,400

12,800 10.84 7.74 5.59 3.99 3.01 2.15 1.85 1.32 1.37 0.98 1.23 0.88 1.17 0.83 1.16 0.83

LP = Low Power, LN = Low Noise

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Table 3. Noise vs. PGA Mode and Gain (Continuous Conversion)

CONTINUOUS CONVERSION MODE

INPUT-REFERRED NOISE VOLTAGE (µV

) vs. PGA GAIN SETTING

RMS

DATA

RATE

(sps)

1

2

4

8

16

32

64

128

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

15.6

31.2

0.45 0.32 0.20 0.14 0.11 0.08 0.06 0.04 0.04 0.03 0.03 0.02 0.03 0.02 0.03 0.02

0.58 0.41 0.26 0.18 0.13 0.10 0.08 0.06 0.05 0.04 0.04 0.03 0.04 0.03 0.04 0.03

0.68 0.48 0.34 0.25 0.18 0.13 0.10 0.07 0.07 0.05 0.06 0.04 0.06 0.04 0.06 0.04

0.86 0.61 0.44 0.32 0.23 0.16 0.14 0.10 0.10 0.07 0.08 0.06 0.08 0.06 0.08 0.06

1.14 0.82 0.56 0.40 0.30 0.22 0.18 0.13 0.14 0.10 0.11 0.08 0.11 0.08 0.11 0.08

1.47 1.05 0.76 0.54 0.41 0.29 0.25 0.18 0.19 0.13 0.16 0.11 0.16 0.11 0.16 0.11

1.99 1.42 1.03 0.73 0.56 0.40 0.35 0.25 0.26 0.19 0.23 0.16 0.21 0.15 0.22 0.16

2.73 1.95 1.40 1.00 0.76 0.54 0.47 0.34 0.36 0.26 0.31 0.22 0.30 0.21 0.30 0.21

3.68 2.63 1.86 1.33 1.03 0.73 0.64 0.45 0.49 0.35 0.42 0.30 0.40 0.28 0.41 0.29

4.57 3.26 2.36 1.69 1.30 0.93 0.81 0.58 0.61 0.43 0.53 0.38 0.52 0.37 0.52 0.37

5.22 3.73 2.66 1.90 1.48 1.06 0.93 0.67 0.68 0.49 0.61 0.44 0.58 0.41 0.60 0.43

7.60 5.50 4.00 2.86 2.20 1.57 1.34 0.96 1.00 0.71 0.86 0.61 0.86 0.61 0.86 0.61

62.5

125

250

500

1000

2000

4000

8000

16000

32000

64000

13.6 9.79

6.1

4.36 3.25 2.32 1.93 1.38 1.38 0.98 1.20 0.86 1.22 0.87 1.16 0.83

LP = Low Power, LN = Low Noise

and continuous operation versus data rate, PGA gain, and

power mode.

out on the falling edge of SCLK. SCLK remains low when

not active.

DIN (Serial Data Input)

Serial Interface

Data present on DIN is clocked into internal registers on

the rising edge of SCLK.

The MAX11254 interface is fully compatible with SPI,

QSPI™, and MICROWIRE®-standard serial interfaces.

The SPI interface provides access to on-chip registers

that are 8 bits to 24 bits wide. The interface consists of

the standard SPI signals CSB, SCLK, DIN and DOUT. An

additional RDYB output signals data availability.

DOUT (Serial Data Output)

The DOUT pin is actively driven when CSB is low and

high impedance when CSB is high. Data is shifted out on

DOUT on the falling edge of SCLK.

CSB (Chip Select)

RDYB (Data Ready)

CSB is an active-low chip-select input to communicate

with the MAX11254. CSB transitioning from low to high

is used to reset the SPI interface. When CSB is low, data

is clocked into the device from DIN on the rising edge of

SCLK. Data is clocked out of DOUT on the falling edge of

SCLK. When CSB is high, SCLK and DIN are ignored and

DOUT is high impedance, allowing DOUT to be shared

with other devices.

RDYB indicates the ADC conversion status and the avail-

ability of the conversion result. When RDYB is low, a

conversion result is available. When RDYB is high, a con-

version is in progress and the data for the current conver-

sion is not available. RDYB is driven high after a complete

read of the data register. RDYB resets to high four master

clock cycles prior to the next DATA register update.

If data was read, then RDYB transitions from high to

low at the output data rate. If the previous data was not

read, then the RDYB transitions from low to high for four

master clock cycles and then transitions from high to low.

SCLK (Serial Clock)

The SCLK is used to synchronize data communication

between the host device and the MAX11254.Data is

shifted in on the rising edge of SCLK and data is shifted

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National

Semiconductor Corporation.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

In continuous mode, RDYB remains high for the first four

conversion results and on the 5th result, RDYB goes low.

8 SCLKs for register access byte and 24 SCLKs (data

bits to be written). If only 15 SCLKs were issued out of

the 32 expected, the register value will not be updated.

At least 16 SCLKs are required to update the MSB byte.

For example, when the user issues a write command for

a 24-bit register write and terminates after 16 SCLKs, only

the MSB byte, bits 23 to 16 of the register are updated.

Bits 15 to 0 retain the old value of the register.

For sequencer mode 2 and sequencer mode 3, the

RDYB behavior for a multichannel conversion can be

controlled by the SEQ:RDYBEN bit. The default value

of SEQ:RDYBEN is ‘0’. When set to ‘0’, RDYB behaves

the same for multichannel conversion and single chan-

nel operation. The RDYB toggles high to low after each

channel is ready to update its corresponding data register.

After the channel data is read, the RDYB will reset back

to ‘1’. If the channel data is not read and the next chan-

nel is ready to update its data, the RDYB will toggle low

to high four cycles before the data update (similar to a

single channel operation), and then toggle high to low

indicating the new channel’s conversion data is available.

If ‘N’ channels are enabled, RDYB will toggle high to low

‘N’ times. If SEQ:RDYBEN is set to ‘1’, the RDYB event

for each channel is suppressed. The RDYB toggles high

to low when the last channel is ready to update its corre-

sponding data register and a single high to low transition

happens.

SPI Incomplete Read Command Termination

The SPI interface stays in read mode for as long as CSB

stays low independent of the number of SCLKs issued.

The CSB pin must be toggled high to remove the device

from the bus and reset the internal SPI controller. Any

activity on the DIN pin is ignored while in the register read

mode. The read operation is terminated if the CSB pin is

toggled high before the maximum number of SCLKs is

issued.

When reading from DATA registers, the behavior of RDYB

will depend on how many bits are read. If at least 23 bits

are read, the read operation is complete and RDYB resets

to high. If the user reads less than 23 bits, internally the

logic considers the read incomplete, and RDYB stays low.

The user can initiate a new read within the same conver-

sion cycle; however, the new 24-bit read must complete

before the next DATA register update.

The STAT:SRDY[5:0] bits get set to ‘1’ when their corre-

sponding channel finishes converting, irrespective of the

RDYBEN setting for sequencer modes 2 and 3. The con-

version status is available by reading the STAT:MSTAT bit.

This stays high as long as the modulator is converting.

SPI Timing Characteristics

See Figure 4 for timing of RDYB.

The SPI timing diagrams illustrating command byte and

register access operations are shown in Figure 5 to

Figure 8. The MAX11254 timing allows for the input data

to be changed by the user at both rising and falling edges

of SCLK. The data read out by the device on SCLK falling

edges can be sampled by the user on subsequent rising

or falling edges.

SPI Incomplete Write Command Termination

In case of register writes, the register values get updated

every 8th clock cycle with a byte of data starting from

the MSB. A minimum of 16 SCLKs are needed to write

the first byte of data in a multibyte register or for an 8-bit

register. For example, a 24-bit register write requires

CONVERT COMMANDS

CSB/SCLK/DIN

N × t_CNV

SCYCLE=’1',

CONTSC=’0'

RDYB

DATA not retrieved

DATA

RETRIEVED

t_CNV

SCYCLE=’1',

CONTSC=’1'

RDYB

5 t_CNV

t_CNV

SCYCLE=’0',

CONTSC=’x'

RDYB

Figure 4. Timing of RDYB in All Conversion Configurations: Single-Cycle, Single-Cycle Continuous and Continuous. In sequencer

mode 1 and in sequencer modes 2 and 3, with SEQ:RDYBEN=’0’ N = 1. In sequencer modes 2 and 3 with SEQ:RDYBEN=’1’ N =

number of active channels.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

SPI COMMAND WRITE BYTE

RDYB

CSB

‘X’

t_CSW

t_CSS0

t_CSH1

t_CH

t_CL

t_CP

t_CSS1

SCLK

DIN

1

8

t_DH

t_DS

MODE MODE RATE RATE RATE RATE

‘X’

‘1’

‘0’

1

0

3

2

1

0

t_DOD

t_DOE

HIGH-Z

DOUT

‘X’

Figure 5. SPI Command Byte Timing Diagram

SPI 8b REGISTER WRITE

RDYB

‘X’

t_CSW

t_CSS0

t_CSH1

CSB

t_CH

t_CL

t_CP

t_CSS1

SCLK

DIN

1

8

16

t_DH

t_DS

‘X’

‘1’ ‘1’ RS4 RS3 RS2 RS1 RS0 ‘0’ D7 D6 D5 D4 D3 D2 D1 D0

‘X’

t_DOD

t_DOE

HIGH-Z

DOUT

‘X’

Figure 6. SPI Register Write Timing Diagram

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

SPI 8b REGISTER READ

RDYB

‘X’

t_CSW

t_CSS0

t_CSH1

CSB

SCLK

DIN

t_CH

t_CL

t_CP

t_CSS1

1

8

16

18b data

‘X’

t_DS

t_DH

‘X’

‘1’ ‘1’ RS4 RS3 RS2 RS1 RS0 ‘1’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’

t_DOTt_DOH

D7 D6 D5 D4 D3 D2 D1 D0

t_DOD

HIGH-Z

t_DOE

HIGH-Z

DOUT

‘X’

Figure 7. SPI Register Read Timing Diagram. For read patterns, the user may latch the MAX11254 output data on either rising edges

(9–16) running at minimum latency or falling edges 9–16 running at increased latency.

SPI 24B DATA READ

RDYB

t_CSW

t_R1

t_CSS0

t_CSH1

CSB

SCLK

DIN

t_CH

t_CL

t_CP

9

t_CSS1

1

8

31

24b data

t_DS

t_DH

‘X’

‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’ ‘1’

t_DOE

t_DOT

t_DOH

t_DOD

HIGH-Z

DOUT

‘X’

MSB

LSB

Figure 8. SPI DATA Readout Timing Diagram

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Modes and Registers

Channel Sequencing

The MAX11254 interface operates in two fundamental

modes, either to issue a conversion command or to

access registers. The mode of operation is selected by a

command byte. Every SPI transaction to the MAX11254

starts with a command byte. The command byte begins

with the MSB (B7) set to ‘1’. The next bit (B6) determines

whether a conversion command is sent or register read/

write access is requested.

Changing SEQUENCER Modes

Mode Exit (See Table 8. Register Map for Register

Definitions)

To exit any of the three sequencer modes at any time

program the following sequence:

1) Issue a power-down command to exit the conver-

sion process to STANDBY or SLEEP, as defined in

CTRL1:PD[1:0]:

a. Write a conversion command byte (see Table 4.

Command Byte Definition) and set MODE[1:0] of the

During a register read/write access, hold CSB low for the

entire read or write operation and pull CSB high at the

end of the command. For example, if the command is to

read a 24-bit data register, hold CSB low for 32 SCLK

cycles (8 cycles for the command byte plus 24 cycles

for the data). CSB transitions must not occur near the

rising edge of SCLK and must conform to the setup and

hold timing detailed in the timing section. See SPI Timing

Requirements table.

command byte to ‘01’

2) Wait for STAT:PDSTAT[1:0] = ‘01’ (SLEEP) or

STAT:PDSTAT[1:0] = ‘10’ (STANDBY).

Note: For all sequencer modes, the default exit state

upon completion of all conversions is SLEEP. In

sequencer mode 1, however, continuous conversion

operation (CTRL1:SCYCLE=’0’) and continuous sin-

gle-cycle conversion operation (CTRL1:SCYCLE=’1’

and CTRL1:CONTSC=’1’) are running continuously

and must be terminated with the Mode Exit sequence.

Command Byte

The conversion command sets the mode of operation

(conversion, calibration, or power-down) as well as the

conversion speed of the MAX11254. The register read/

write command specifies the register address as well as

the direction of the access (read or write).

Table 4. Command Byte Definition

B7 (MSB)

B6

0

B5

MODE1

RS4

B4

MODE0

RS3

B3

B2

B1

B0

Conversion Command

Register Read/Write

1

RATE3

RS2

RATE2

RS1

RATE1

RS0

RATE0

R/W

1

Table 5. Command Byte Decoding

BIT NAME

DESCRIPTION

The MODE bits are used to set the functional operation of the MAX11254 according to the following decoding.

MODE1

MODE0

DESCRIPTION

0

1

0

1

0

1

Unused

MODE[1:0]

Power-down performed based on the CTRL1:PD[1:0] setting

Calibration performed based on the CTRL1:CAL[1:0] setting

Sequencer mode. The operation is based on the conﬁguration of the SEQ register

RATE[3:0]

RS[4:0]

These bits determine the conversion speed of the MAX11254. The decoding is shown in Table 1.

Register address as shown in Table 8.

The R/W bit enables either a read or a write access to the address speciﬁed in RS[4:0]. If R/W is set to ‘0’, then data

is written to the register. If the R/W bit is set to ‘1’, then data is read from the register.

R/W

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

g. Set register GPO_DIR and, if desired, GPIO_CTRL

to enable or disable the desired GPO and GPIO

pins

Mode Change

To change sequencer modes or to update the SEQ regis-

ter, program the following sequence:

2) Write a conversion command (see Table 4, Command

Byte Definition).

1) Perform Sequencer Mode Exit (see the Mode Exit

section).

a. Set data rate using bits RATE[3:0] of the command

byte

2) Set up the following registers: SEQ, CTRL1.

a. Set SEQ:MODE[1:0] to select the new sequencer

mode

b. Set MODE[1:0] of the command byte to ‘11’ for

sequencer mode

b. Set CTRL1:PD[1:0] to STANDBY or SLEEP state

to set the desired exit state if a conversion com-

mand with MODE[1:0] set to ‘01’ is issued during

the conversion.

3) Monitor RDYB for availability of conversion results in

the DATA register (See Figure 4 for RDYB timing).

Mode Exit

3) Write the command byte (see Table 4).

1) In single-cycle conversion mode (CTRL1:SCYCLE

=’1’) the sequencer exits into SLEEP state.

a. Set MODE[1:0] of the command byte to ‘11’

(sequencer mode)

2) In continuous conversion mode (CTRL1: SCYCLE=’0’

or (CTRL:SCYCLE=’1’ and CTRL1:CONTSC =’1’)),

conversions continue nonstop until the mode is exited.

To interrupt and exit continuous conversion or con-

tinuous single-cycle conversion follow the Changing

SEQUENCER Modes—Mode Exit section to put

the part into STANDBY or SLEEP state based on

CTRL1:PD[1:0] set in step 1(f) of Mode Entry section.

4) Wait for STAT:PDSTAT[1:0] = ‘00’ to confirm conversion

mode.

SEQUENCER MODE 1—Single-Channel Conver-

sion with GPO Control and MUX Delays

This mode is used for single-channel conversions where

the sequencer is disabled. Figure 9 illustrates the timing.

To support high-impedance source networks, the conver-

sion delay (SEQ:MDREN) feature must be enabled. The

states of the GPO and GPIO pins are configured using the

GPO_DIR and GPIO_CTRL registers and can be modi-

fied anytime during mode 1 operation. The values of the

CHMAP0/CHMAP1 registers and DELAY:GPO[7:0] bits

are ignored in this mode.

Changing Input Channel During Continuous

Single-Cycle Conversion in Mode 1

1) Issue a conversion command with MODE[1:0] set

to ‘01’ to exit the conversion process to STANDBY

or SLEEP state (see the Changing SEQUENCER

Modes—Mode Exit section).

2) Monitor STAT:PDSTAT = ‘10’ or ‘01’ to confirm exit to

STANDBY or SLEEP state.

Programming Sequence

Mode Entry

1) Set up the following registers: SEQ, DELAY, CTRL1,

GPO_DIR, GPIO_CTRL.

3) Set SEQ:MUX[2:0] to select the new channel for con-

version

4) Write a conversion command (see Table 4) and set

MODE[1:0] of command byte to ‘11’

a. SEQ:MODE[1:0] = ‘00’ for sequencer mode 1

SEQUENCER MODE 2 – Multichannel Scan with

GPO Control and MUX Delays

b. SEQ:MUX[2:0] to select the channel for conversion

c. Enable SEQ:MDREN to delay conversion start to

allow for input settling. Set DELAY:MUX[7:0] to the

desired conversion delay

This mode is used to sequentially convert a programmed

set of channels in a preset order. Figure 10 illustrates the

timing.

d. Set CTRL1:SCYCLE for either single cycle (no

latency) or continuous conversion

The states of the GPO and GPIO pins are configured

using the GPO_DIR and GPIO_CTRL registers and can

be modified anytime during mode 2 operation. In mode

2, register bits CHMAP0:CHn_ORD[2:0], CHMAP1:CHn_

ORD[2:0], CHMAP0:CHn_EN, and CHMAP1:CHn_EN

are used to select channels and conversion order.

e. If single-cycle conversion is selected, set

CTRL1:CONTSC to ‘1’ if continuous single-cycle

conversion is desired

f. Set CTRL1:PD[1:0] to STANDBY or SLEEP state to

set the desired exit state if a conversion command

with MODE[1:0] set to ‘01’ is issued during the

conversion

Bits

DELAY:GPO[7:0],

CHMAP0:CHn_GPO[2:0],

CHMAP0:CHn_GPOEN, CHMAP1:CHn_GPO[2:0], and

CHMAP1:CHn_GPOEN are ignored in this mode. The bit

CTRL1:CONTSC is ignored and bit CTRL1:SCYCLE = ‘0’

is invalid in this mode.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

SEQUENCER MODE 1

CHANNEL CONVERSION

DEL

SEQ:MDREN • DELAY:MUX

SEQ:MUX[2:0]

Figure 9. Sequencer Mode 1 Timing Diagram

SEQUENCER MODE 2

CHANNEL

CONVERSION

CHANNEL

CONVERSION

CHANNEL

CONVERSION

CHANNEL

CONVERSION

CHANNEL

CONVERSION

CHANNEL

CONVERSION

DEL

SEQ:MDREN •

DELAY:MUX

SEQ:MDREN •

DELAY:MUX

SEQ:MDREN •

DELAY:MUX

SEQ:MDREN •

DELAY:MUX

SEQ:MDREN •

DELAY:MUX

SEQ:MDREN •

DELAY:MUX

CHANMAP:ORD[2:0] = 001

CHANMAP:ORD[2:0] = 010

CHANMAP:ORD[2:0] = 011

CHANMAP:ORD[2:0] = 100

CHANMAP:ORD[2:0] = 101

CHANMAP:ORD[2:0] = 110

Figure 10. Sequencer Mode 2 Timing Diagram

b. Set MODE[1:0] of the command byte to ‘11’

Programming Sequence

Mode Entry

1) Set up the following registers: SEQ, CHMAP0,

CHMAP1, DELAY, GPO_DIR, GPIO_CTRL, CTRL1

3) Monitor RDYB (if SEQ:RDYBEN=’0’) and bits

STAT:SRDY[5:0] for availability of per channel conver-

sion results in DATA[x] registers.

Mode Exit

a. SEQ:MODE[1:0] = ‘01’ for sequencer mode 2

1) This mode exits to SLEEP state upon completion of

sequencing all channels

b. If desired set SEQ:RDYBEN to ‘1’ to signal data

ready only when all channel conversions are com-

pleted

2) To interrupt current sequencing perform mode exit,

see the Changing SEQUENCER Modes—Mode Exit

section. This device is put in STANDBY or SLEEP

state based on CTRL1:PD[1:0] set in step 1(e) of

Mode Entry section.

c. Enable SEQ:MDREN to delay conversion start to

allow for input settling. Set DELAY:MUX[7:0] to the

desired conversion delay

d. Set CHMAP0 and CHMAP1 to select the channels

and channel order for conversion

SEQUENCER MODE 3 – Scan, With Sequenced

GPO Controls

e. Set CTRL1:PD[1:0] to STANDBY or SLEEP state

to set the desired exit state if a conversion com-

mand with MODE[1:0] set to ‘01’ is issued during

the conversion

This mode is used to sequentially convert a programmed

set of channels in a preset order and sequence the

GPO/GPIO pins concurrently. The GPO/GPIO pins are

used to bias external circuitry such as bridge sensors;

the common reference (GPOGND) is typically ground.

After all channel conversions have completed, the

MAX11254 automatically powers down into SLEEP mode.

Figure 11 illustrates the Sequencer Mode 3 timing dia-

gram for a three-channel scan. As long as CTRL3:GPO_

MODE is set to ‘1’, registers GPO_DIR and GPIO_CTRL

are ignored in this mode, as the GPO/GPIO pins are

controlled by the sequencer.

f. Set register GPO_DIR and GPIO_CTRL to enable or

disable the desired GPO and GPIO pins

g. Set CTRL1:SCYCLE = ‘1’ for single-cycle conver-

sion mode

2) Write a conversion command (see Table 4).

a. Set data rate using bits RATE[3:0] of the command

byte

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

If CTRL3:GPO_MODE is set to ‘0’, the GPO/GPIO pins

are directly controlled by the GPO_DIR and GPIO_CTRL

registers and are not controlled by the sequencer.

g. Set CTRL1:PD[1:0] to STANDBY or SLEEP state to

set the desired exit state if a conversion command with

MODE[1:0] set to ‘01’ is issued during the conversion

h. Set CTRL1:SCYCLE = ‘1’ for single conversion

mode

Programming Sequence

Mode Entry

1) Set up the following registers: SEQ, CHMAP0,

2) Write the conversion command (see Table 4)

CHMAP1, DELAY, CTRL1, CTRL3

a. Set the data rate using bits RATE[3:0] of the com-

mand byte

a. SEQ:MODE[1:0]=’10’ for sequencer mode 3

b. Set MODE[1:0] of command byte to ‘11’

b. If desired, set SEQ:RDYBEN to ‘1’ to signal data

ready only when all channel conversions are com-

pleted

3) Monitor RDYB (if SEQ:RDYBEN = ‘0’) and bits

STAT:SRDY[5:0] for availability of per channel con-

version results in DATA[x] registers.

c. Enable SEQ:MDREN if conversion start

is to be delayed to allow for input settling. Set

DELAY:MUX[7:0] to the desired conversion delay

Mode Exit

1) This mode exits to SLEEP state upon completion of

sequencing all channels and GPO/GPIO pins.

d. Set CTRL3:GPO_MODE to ‘1’ to enable GPO/

GPIO sequencing

2) To interrupt the current sequencing, perform mode

exit. See the Changing SEQUENCER Modes—Mode

Exit section. This puts the part in STANDBY or

SLEEP state based on CTRL1:PD[1:0] set in step

1(g) of Mode Entry.

e. Set CHMAP0 and CHMAP1 to enable the chan-

nels for conversion and to set the channel con-

version order. Map the corresponding GPO/GPIO

pins to a channel.

f. Enable SEQ:GPODREN to add

a

delay

The bit CTRL1:CONTSC is ignored and bit

CTRL1:SCYCLE = ‘0’ is invalid in this mode.

before the multiplexer selects this channel

for conversion. Set DELAY:GPO to a delay

value sufficient for the bias to settle.

SEQUENCER MODE 3 TIMING

MUX SELECTS CHANNEL

DEL1 – PROGRAMMED DELAY USING BITS

CONVERSION

STARTS

CONVERSION

ENDS

DELAY:GPO[7:0] TO PROVIDE SUFFICIENT

SETTLING TIME FOR THE SENSOR BEFORE THE

FIRST CHANNEL IS CONVERTED.

GPO/GPIO ACTIVATED

DEL1

SCAN

CHANNEL #1

DEL2

TCONVERT

DEL2 – PROGRAMMED DELAY USING BITS

DELAY:MUX[7:0] FOR SENSOR AND ANALOG

INPUT SETTLING AFTER THE MULTIPLIER

SELECTS THE CHANNEL FOR CONVERSION.

SEQ:MDREN • DELAY:MUX

CHANMAP:ORD[2:0] = 001

(TCONVERT AND DEL1)

END TRIGGER

DELAY:GPO

MUX SELECTS CHANNEL

CONVERSION

STARTS

CONVERSION

ENDS

GPO/GPIO

ACTIVATED

DEL2

TCONVERT

SCAN

CHANNEL #2

CHANMAP:ORD[2:0]

= 010

(TCONVERT AND DEL1)

END TRIGGER

MUX SELECTS CHANNEL

CONVERSION

STARTS

CONVERSION

ENDS

GPO/GPIO

ACTIVATED

DEL2

TCONVERT

SCAN

CHANNEL #3

CHANMAP:ORD[2:0] = 011

Figure 11. Sequencer Mode 3 Timing Diagram for a Three-Channel Scan

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

STAT:GPOERR is set when more than one input chan-

nel is mapped to the same GPO/GPIO pin.

Operating Examples—From Full Power-Down to

Mode 3

In this example, channels 0, 1, and 2 are configured for

conversion in mode 3. Channel 0 is configured last in the

scan order and the GPIO0 is mapped to this channel.

Channel 1 is configured first in the scan order and GPO1

is mapped to this channel. Channel 2 is configured sec-

ond in the scan order and GPO0 is mapped to this chan-

nel. Channels 0, 1, and 2 are enabled for scan and GPO/

GPIO switching is also enabled. The RDYBEN is not set

which generates a RDYB transition after each channel is

converted. The PGA is configured for a gain of 128 and

the data rate is 6,400sps in single-cycle mode. The MUX

delays are enabled for all used channels and the GPO/

GPIO delays are disabled. Reference SPI Command

Sequence section.

STAT:ORDERR is set when CHn_ORD is set

as ‘000’ or ‘111’ and channel n is enabled using

CHMAPx:CHn_EN.

Supplies and Power-On Sequence

The MAX11254 requires two power supplies, AVDD and

DVDD. These power supplies can be sequenced in any

order. The analog supply (AVDD) powers the analog

inputs and the modulator. The DVDD supply powers the

SPI interface. The low-voltage core logic can either be

powered by the integrated LDO (default) or via DVDD.

Figure 12 shows the two possible schemes. CAPREG

denotes the internally generated supply voltage. If the

LDO is used, the DVDD operating voltage range is from

2.0V to 3.6V. If the core logic is directly powered by DVDD

(DVDD and CAPREG connected togeter), the DVDD

operating voltage range is from 1.7V to 2.0V.

Error Checking Sequencer Mode 3

The MAX11254 perform checks on registers CHMAP0

and CHMAP1. Error flags are set when invalid values are

set:

DVDD OPERATING BETWEEN 2.0V TO 3.6V

LDO ENABLED (SET CTRL2:LDOEN = ‘1’) AND BYPASS

CAPREG TO DGND WITH 220nF

DVDD OPERATING BETWEEN 1.7V TO 2.0V

LDO DISABLED (SET CTRL2:LDOEN = ‘0’) AND

CONNECT CAPREG TO DVDD AT BOARD LEVEL

AVDD

DVDD

AVDD

DVDD

LDO

MAX11254

DIGITAL

INTERFACE

INPUTS

AND

OUTPUTS

DIGITAL

INTERFACE

INPUTS

AND

OUTPUTS

ANALOG

2V DIGITAL

LOGIC

2V DIGITAL

LOGIC

CAPREG

220nF

0603

X7R

DGND

Figure 12. MAX11254 Digital Power Architecture

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

SPI Command Sequence

SPI Transactions

Description

CSB=0; SPI=0xD012; CSB=1;

Write to SEQ register

Set MUX to 0b000, MODE to 0b10, GPODREN to

0b0, MDREN to 0b1, RDYBEN to 0b0

CSB=0; SPI=0xCAF000; CSB=1;

CSB=0; SPI=0xC65C; CSB=1;

Write to DELAY register

Set MUX[7:0] to 0xF0, GPO[7:0] to 0x00

Write to CTRL3 register

Set GPO_MODE to 0b1, all others to the

default value;

CSB=0; SPI=0xCE0B274F; CSB=1

Write to CHMAP0 register

CH2=0x0B: CH2_GPO=0b00, CH2_ORD=0b010,

CH2_EN=0b1, CH2_GPOEN=0b1

CH1=0x27: CH1_GPO=0b01, CH1_ORD=0b001,

CH1_EN=0b1, CH1_GPOEN=0b1

CH0=0x4F: CH0_GPO=0b10,

CH0_ORD=0b011, CH0_EN=0b1, CH0_GPOEN=0b1

CSB=0; SPI=0xC43F; CSB=1;

Write to CTRL2 register

set PGA gain to 0b111, LDOEN=0b1,

LPMODE=0b1, PGAEN=0b1;

CSB=0; SPI=0xBE; CSB=1;

Wait

Convert using sequencer mode, data rate

selected is 6,400 sps;

RDYB negative edge transition from ‘1’ to

‘0’ indicates conversion completed and

DATA register ready for read

CSB=0; SPI=0xD3000000; CSB=1;

Wait

Read register DATA1;

RDYB negative edge transition from ‘1’ to

‘0’ indicates conversion completed and

DATA register ready for read

CSB=0; SPI=0xD5000000; CSB=1;

Wait

Read register DATA2

RDYB negative edge transition from ‘1’ to

‘0’ indicates conversion completed and

DATA register ready for read

CSB=0; SPI=0xD1000000; CSB=1;

STOP

Read register DATA0;

Mode activity is completed. The MAX11254

powers down into SLEEP state waiting for

the next command

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Power-On Reset and Undervoltage Lockout

Reset

A global power-on reset (POR) is triggered until AVDD,

DVDD, and CAPREG cross a minimum threshold voltage

(V ), as shown in Figure 13.

LH

Hardware Reset Using RSTB

The MAX11254 features an active-low RSTB pin to per-

form a hardware reset. Pulling the RSTB pin low stops

any conversion in progress, reconfigures the internal

registers to the power-on reset state and resets all digital

filter states to zero. After the reset cycle is completed, the

MAX11254 remains in STANDBY state and awaits further

commands.

To prevent ambiguous power-supply conditions from

causing erratic behavior, voltage detectors monitor AVDD,

DVDD, and CAPREG and hold the MAX11254 in reset

when supplies fall below V

(see Figure 13). The ana-

HL

log undervoltage lockout (AVDD UVLO) prevents the

ADC from converting when AVDD falls below V . The

HL

Software Reset

CAPREG UVLO resets and prevents the low-voltage

The host can issue a software reset to restore the default

state of the MAX11254. A software reset sets the interface

registers back into their default states and resets the inter-

nal state machines. However, a software reset does not

emulate the complete POR or hardware reset sequence.

digital logic from operating at voltages below V . DVDD

HL

UVLO thresholds supersede CAPREG thresholds when

CAPREG is externally driven. Figure 14 shows a flow dia-

gram of the POR sequence. Glitches on supplies AVDD,

DVDD, and CAPREG for durations shorter than T are

P

suppressed without triggering POR or UVLO. For glitch

durations longer than T , POR is triggered within T

seconds. See the Electrical Characteristics table for val-

Two SPI transactions are required to issue a software

reset: First set CTRL1:PD[1:0] to ‘11’ (RESET). Then

issue a conversion command with MODE[1:0] set to ‘01’.

P

DEL

ues of V , V , T , and T

.

DEL

LH HL

P

To confirm the completion of the reset operation,

STAT:PDSTAT and STAT:INRESET must be monitored.

Power-On Reset Timing

Power-on reset is triggered during power-up and under-

voltage conditions as described above. Completion of the

POR process is monitored by polling STAT:PDSTAT[1:0]

= ‘10’ for STANDBY state (see Figure 15).

Figure 16 shows the state transition for the RESET com-

mand and the relative timing of STAT register update.

During reset, INRESET = ’1’ and PDSTAT= ‘11’. The

SPI interface cannot be written until MAX11254 enters

STANDBY state where PDSTAT = ‘10’. To confirm com-

pletion of the RESET command, monitor for INRESET =

‘0’ and PDSTAT = ‘10’.0 Table 6 summarizes the maxi-

mum delay for reset operation.

AVDD

V_LH

DVDD

V_HYS

V_HL

CAPREG

T_P

T_DEL

T_P

T_DEL

PORB

Figure 13. Undervoltage Lockout Characteristic Voltage Levels and Timing

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Table 6. Maximum Delay Time for Mode Transitions

MAX11254

STATE BEFORE

MAXIMUM

DELAY TIME TO STATE AFTER

NEXT STATE

MAX11254

COMMAND

ISSUED*

COMMAND INTERPRETATION

†

COMMAND

RESET

Command ignored

0

RESET

SLEEP

Command ignored

STANDBY

MAX11254 powers down into SLEEP mode

20ms

Issue a conversion command and then monitor

STAT:PDSTAT[1:0] for change of mode; then send

conversion command with MODE[1:0] set to ‘01’

STANDBY (fast)

15µs

SLEEP

Calibration stops, MAX11254 powers down into

SLEEP mode

Calibration

Conversion

3µs

SLEEP

Conversion stops, MAX11254 powers down into

SLEEP mode

Mode change from SLEEP to conversion

SAT: PDSTAT changes to ‘00’

SLEEP

T

+ 3µs

Conversion

PUPSLP

CONVERT

STANDBY

RESET

STANDBY to conversion

Command ignored

T

Conversion

RESET

PUPSBY

0

SLEEP

MAX11254 changes to STANDBY

20ms

STANDBY

Issue a conversion command and then monitor

STAT:PDSTAT[1:0] for change of mode; then send

conversion command with MODE[1:0] set to ‘01’

SLEEP (fast)

85µs

STANDBY

Calibration

Conversion

RESET

Command ignored

0

3µs

0

STANDBY

RESET

Calibration stops

Conversion stops

Command ignored

SLEEP

Command ignored

0

SLEEP

RESET

STANDBY

Calibration

Conversion

OFF

Register values reset to default

Calibration stops, register values reset to default

Conversion stops, register values reset to default

From complete power-down to STANDBY mode

From any state to STANDBY mode

28ms

6µs

10ms

STANDBY

POR

RSTB

Any

*The commands are deﬁned as follows:

SLEEP: Set CTRL1:PD[1:0] to ‘01’; issue a conversion command with MODE[1:0] set to ‘01’

STANDBY: Set CTRL1:PD[1:0] to ‘10’; issue a conversion command with MODE[1:0] set to ‘01’

RESET: Set CTRL1:PD[1:0] to ‘11’; issue a conversion command with MODE[1:0] set to ‘01’

CONVERT: Any conversion command with MODE[1:0] set to ‘11’

POR: Power-on reset during initial power-up or UVLO

RSTB: Hardware reset with RSTB pin

†

See the Electrical Characteristics for T

PUPSLP

and T

PUPSBY

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

POWER-ON

NO

AVDD UVLO

TRIGGERED?

CAPREG UVLO

TRIGGERED?

DVDD UVLO

TRIGGERED?

YES

POWER-ON

RESET FOR 2V

DIGITAL LOGIC

POWER-ON RESET

FOR DIGITAL LOGIC

AND INTERFACE

ANALOG

RESET

OSCILLATOR

RESET

Figure 14. MAX11254 UVLO and POR Flow Diagram

OUT OF POWER-ON RESET

SERIAL

IN POWER-ON RESET

INTERFACE

READ ONLY

SERIAL INTERFACE AVAILABLE FOR BOTH READ AND WRITE

V_DVDD

‘10’ (STANDBY)

‘11’

STAT:PDSTAT=’XX’

Figure 15. Power-On Reset and PDSTAT Timing

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

STANDBY STATE TO SLEEP STATE (FAST)

1) Set CTRL1:PD[1:0] = ‘01’ for STANDBY state.

2) Set SEQ:MODE[1:0] = ‘00’ for sequencer mode 1

Power-Down States

To reduce overall power consumption, the MAX11254

features two power-down states: STANDBY and SLEEP.

In SLEEP mode all circuitry is powered down, and the

supply currents are reduced to leakage currents. In

STANDBY mode the internal LDO and a low-frequency

oscillator are powered up to enable fast start-up. After

POR or a hardware reset the MAX11254 is in STANDBY

mode until a command is issued.

3) Issue a conversion command with MODE[1:0] set to

‘11’.

4) Monitor STAT:PDSTAT[1:0] = ‘00’ for active state.

5) Write the conversion command with MODE[1:0] set to

‘01’.

6) Monitor STAT:PDSTAT = ‘01’ for completion.

Changing Power-Down States

Mode transition times are dependent on the current mode

of operation. STAT:PDSTAT is updated at the end of all

mode changes and is a confirmation of a completed trans-

action. The MAX11254 does not use a command FIFO or

queue. The user must confirm the completed transaction

by polling STAT:PDSTAT after the expected delay, as

described in Table 6. Once the transition is complete, it is

safe to send the next command.

Calibration

Two types of calibration are available: self calibration

and system calibration. Self calibration is used to reduce

the MAX11254’s gain and offset errors during changing

operating conditions such as supply voltages, ambi-

ent temperature, and time. System calibration is used

to reduce the gain and offset error of the entire signal

path. This enables calibration of board level components

and the integrated PGA. System calibration requires the

MAX11254’s inputs to be reconfigured for zero scale and

full scale during calibration. The GPO/GPIO pins can be

used for this purpose. See Figure 17 for details of the

calibration signal flow.

Verify that STAT:PDSTAT indicates the desired state

before issuing a conversion command.

Writes to any CTRL register during a conversion aborts

the conversion and returns the MAX11254 to STANDBY

state.

The calibration coefficients are stored in the registers

SCOC, SCGC, SOC and SGC. Data written to these

registers is stored within the SPI domain and copied to

internal registers before a conversion starts to process

the raw data (see Figure 17). An internal or system cali-

bration only updates the internal register values and does

not alter the contents stored in the SPI domain. The bit

CTRL3:CALREGSEL decides whether the internal con-

tents or the contents stored in the SPI domain are read

back during a read access of these registers.

SLEEP STATE TO STANDBY STATE (FAST)

1) Set CTRL1:PD[1:0] = ‘10’ for STANDBY state.

2) Set SEQ:MODE[1:0] = ‘00’ for sequencer mode 1

3) Issue a conversion command with MODE[1:0] set to

‘11’.

4) Monitor STAT:PDSTAT[1:0] = ‘00’ for active state.

5) Write the conversion command with MODE[1:0] set to

‘01’.

6) Monitor STAT:PDSTAT = ‘10’ for completion.

SERIAL INTERFACE IS

AVAIABLE FOR BOTH

READ AND WRITE

SERIAL INTERFACE IS READ

ONLY DURING THIS PERIOD

COMMAND LATCHED

RESET COMMAND

STAT:INRESET

IDLE

‘10’

‘11’

STAT:PDSTAT = ‘00’/’10'

Figure 16. STAT:INRESET and STAT:PDSTAT Timing

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

RAW RESULT

SPI BLOCK

CAL BLOCK

F

NOSCO=0

T

SCOC

SUBTRACT

SCOC_INTERNAL

24

F

NOSCG=0

T

SCGC

MULTIPLY

SCGC_INTERNAL

NOSYSO=0

T

SOC

SUBTRACT

SOC_INTERNAL

NOSYSG=0

T

SGC

MULTIPLY

SGC_INTERNAL

F

FINAL

RESULT

UNIPOLAR

DATA

T

STATUS REG

x2

LIMITER

Figure 17. Calibration Flow Diagram

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Bits NOSCO, NOSCG, NOSYSO, NOSYSG enable or

disable the use of the individual calibration coefficients

during data processing. See Figure 17, Calibration Flow

Diagram.

to ‘10’ (calibration). The system offset calibration requires

100ms to complete.

To perform a system full-scale calibration, the inputs must

be configured for full scale. The input full-scale value does

not necessarily need to be equal to V

since the input

REF

Self-Calibration

voltage range of the calibration registers can scale up

or down appropriately within the range of the calibration

registers.

The self-calibration is an internal operation and does not

disturb the analog inputs. The self-calibration command

can only be issued in sequencer mode 1 (SEQ:MODE[1:0]

= ‘00’). Self-calibration is accomplished in two indepen-

dent phases, offset and gain. The first phase disconnects

the inputs to the modulator and shorts them together

internally to develop a zero-scale signal. A conversion

is then completed and the results are post-processed to

generate an offset coefficient which cancels all internally

generated offsets. The second phase connects the inputs

to the reference to develop a full-scale signal. A conver-

sion is then completed and the results are post-processed

to generate a full-scale coefficient, which scales the

converters full-scale analog range to the full-scale digital

range.

A system full-scale calibration is started as follows: Set

CTRL1:CAL[1:0] to ‘10’ (system full-scale calibration).

Then issue a conversion command with the MODE[1:0]

bits set to ‘10’ (calibration). The system full-scale calibra-

tion requires 100ms to complete.

The GPO/GPIO pins can be used during a system cali-

bration.

All four calibration registers (SOC, SGC, SCOC, and

SCGC) can be written by the host to store special calibra-

tion values. The new values will be copied to the internal

registers at the beginning of a new conversion.

GPIOs

The entire self-calibration sequence requires two inde-

pendent conversions, one for offset and one for full scale.

The conversion rate is 50sps in the single-cycle mode.

This rate provides the lowest noise and most accurate

calibrations.

The MAX11254 provides two general-purpose input/out-

put ports that are programmable through the GPIO_CTRL

register. Enable the GPIO pins by setting bits GPIO1_EN

and GPIO0_EN, respectively. Set the DIR bits to select

the pins to be configured as inputs or outputs. All pins are

inputs by default. When programmed as output, set the

DIO bits to set the pin state to ‘0’ or ‘1’.

The self-calibration operation excludes the PGA. A sys-

tem level calibration is available in order to calibrate the

PGA signal path.

Conversion Synchronization Using SYNC Pin

and External Clock

Aself-calibration is started as follows: Set CTRL1:CAL[1:0]

to ‘00’ (self-calibration). Then issue a conversion com-

mand with the MODE[1:0] bits set to ‘10’ (calibration). A

self-calibration requires 200ms to complete.

The SYNC pin—in conjunction with an external clock—

can be used to synchronize the data conversions to

external events. Set GPIO_CTRL:GPIO1_EN to ‘0’ and

GPI_CTRL:GPIO0_EN to ‘0’ to configure the GPIO1/

SYNC and GPIO0/CLK pins. Configure sync mode by set-

ting CTRL3:SYNC_MODE to ‘1’ and external clock mode

by setting CTRL2:EXTCLK to ‘1’.

System Calibration

This mode is used when calibration of board level compo-

nents and the integrated PGA is required. The system cal-

ibration command is only available in sequencer mode 1.

A system calibration requires the input to be configured

to the proper level for calibration. The offset and full-scale

system calibrations are, therefore, performed using sepa-

rate commands. The channel selected in the SEQ:MUX

bits is used for system calibrations.

The synchronization mode is used to detect if the cur-

rent conversions are synchronized to a continuous pulse

signal with a period greater than the data rate. Ideally,

the frequency of the synchronization signal is an integer

multiple of the conversion rate. The synchronization mode

records the number of device master clock cycles between

a RDYB assertion and the rising edge of the next SYNC

pulse. At the following SYNC pulse, the number of master

clock cycles between a RDYB assertion and the rising

edge of the SYNC pulse is evaluated again and com-

pared to the recorded value. If the new number of master

clock cycles differs by more than one from the recorded

To perform a system offset calibration, the inputs must be

configured for zero scale. The inputs do not necessarily

need to be shorted to 0V as any voltage within the range

of the calibration registers can be nulled in this calibration.

A system offset calibration is started as follows: Set

CTRL1:CAL[1:0] to ‘01’ (system offset calibration). Then

issue a conversion command with the MODE[1:0] bits set

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

value, the conversion in progress is stopped, the digital

filter contents are reset, and a new conversion starts.

As the digital filter is reset, the full digital filter latency is

required before valid results are available. If the new mas-

ter clock count is within the ±1 count limit, the conversions

continue uninterrupted.

Components of the ADC

Modulator

MODULATOR DIGITAL OVERRANGE

The output of the SINC filter is monitored for overflow.

When SINC filter overflow is detected, the STAT:DOR bit

is set to ‘1’ and a default value is loaded into the DATA

register depending on the polarity of the overload. A

positive overrange causes 0x7FFFFF to be written to the

DATA register. A negative overrange causes 0x800000 to

be written to the DATA register. See Table 7.

Figure 18 shows the timing relationship between the

MAX11254 master clock and the SYNC signal. Due to

startup delays, any SYNC pulses before the first RDYB

assertion (low-going edge) are ignored. The first rising

edge on the SYNC pin after a RDYB assertion establishes

the relationship between the SYNC signal and the conver-

sion timing.

MODULATOR ANALOG OVERRANGE

The modulator analog overrange is used to signal the user

that the input analog voltage has exceeded preset limits

defined by the modulator operating range. These limits

Table 7. Analog Overrange Behavior for Different Operating Conditions and Modes

STAT REGISTER

INPUT VOLTAGE

AOR

DOR

DATA

RESULT

-V

< V < V

0

1

0

1

REF

IN

REF

V

< V < V

RESULT

REF

IN

OVRRNG

-V

< V < -V

RESULT

OVRRNG

IN

REF

V

> V

0x7FFFFF

IN

OVRRNG

V

< -V

0x800000

OVRRNG

The DATA values shown are for bipolar ranges with two’s complement number format. V

is the overrange volt-

OVRRNG

age value typically > 120% of V

.

REF

FIRST VALID

SYNC

> 2 x t

CLK

IGNORED

CLK

SYNC SIGNAL

RDYB

CLK

FIRST

CONVERSION

READY

N

N’

...

t

CLK

DEVICE INITIATES A RESET AND RESTARTS CONVERSIONS WHEN N AND N’ DIFFER BY

MORE THAN ±1CLK COUNT. OTHERWISE CONVERSIONS CONTINUE UNINTERRUPTED.

Figure 18. Timing Relationship between SYNC Signal, External Clock and RDYB

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

SINC5 FILTER, NORMAL MODE

REJECTION DATA RATE 64000.0sps

SINC5 FILTER, NORMAL MODE REJECTION

SINGLE CYCLE DATA RATE 4000.0sps

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

-200

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

-200

0

2

4

6

8

10

12

0

1

2

3

4

5

6

x 10⁴

FREQUENCY (Hz)

x 10⁴

FREQUENCY (Hz)

Figure 19. Digital Filter Frequency Response for 64ksps

Continuous Data Rate and 12.8ksps Single-Cycle Data Rate

Figure 20. Digital Filter Frequency Response for 4ksps Single-

Cycle Data Rate

are approximately 120% of the applied reference voltage.

When analog overrange is detected the STAT:AOR bit is

set to ‘1’ after DATA is updated. The AOR bit will always

correspond to the current value in the DATA register. See

Table 7.

Split Supplies

The MAX11254 supports unipolar and split analog power

supplies for input range flexibility. Using a split analog

supply enables sampling below ground reference. The

true bipolar input range is up to ±1.8V. See Figure 3 for

analog input voltage range for both unipolar and split

supplies.

SINC Filter

The digital filter is a mode-configurable digital filter and

decimator that processes the data stream from the fourth

order delta-sigma modulator and implements a fifth order

SINC function with an averaging function to produce a

24-bit wide data stream.

Sensor Fault Detection

The MAX11254 includes a 1µA current source and a

1µA current sink. The source pulls current from AVDD to

AIN_P and sink from AIN_N to AVSS. The currents are

enabled by register bit CTRL3:CSSEN. These currents

are used to detect damaged sensors in either open or

shorted state. The current sources and sinks are func-

tional over the normal input operating voltage range, as

specified.

The SINC filter allows the MAX11254 to achieve very

high SNR. The bandwidth of the fifth order SINC filter

is approximately twenty percent of the data rate. See

Figures 19 and 20 for the filter response of 64ksps and

4ksps, respectively. See Figure 21 for the bandwidth of

the individual signal stages.

These currents are used to test sensors for functional

operation before taking measurements on that input

channel. With the source and sink enabled, the currents

flow into the external sensor circuit and measurement

of the input voltage is used to diagnose sensor faults. A

full-scale reading could indicate a sensor is open circuit

or overloaded or that the ADC’s reference is absent. If a

zero-scale is read back, this may indicate the sensor is

short-circuited.

Applications Information

Connecting an External 1.8V Supply to DVDD

for Digital I/O and Digital Core

The voltage range of the DVDD I/O supply is specified

from 2.0V to 3.6V if the internal LDO is used to power the

digital core. If a lower I/O supply voltage is desired, the

internal LDO can be disabled, and DVDD and CAPREG

can be connected together as shown in Figure 22. In this

mode of operation, DVDD can vary from 1.7V to 2.0V. The

internal LDO must be disabled by setting CTRL2:LDOEN to ‘0’.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

G=128

PGA

24

N

ANALOG

FILTER

DELTA-SIGMA

ADC

DIGITAL

FILTER

Sn = 5nV/√Hz

N

BW3

NEB3

FDATA

NEB1 = /2 x BW3

BW3 NEB

NEB2 = /2 x BW3

BW3 NEB

10nF 23k 36k

1nF 230k 361k

100pF 2.3M 3.6M

NEB3 = 0.215 x FDATA

64ksps = 13.2kHz

10nF 21k 33k

1nF 69k 108k

100pF 73k 115k

Figure 21. Signal Path Block Diagram Including Bandwidth of Each Stage

2.7V TO 3.6V

REF

1.7V TO 2.0V

10nF

1µF

X7R

REFN REFP

AIN0P

AVDD

DVDD

1nF

C0G

RSTB

CSB

AIN0N

SCLK

DIN

MAX11254

µC

DOUT

AIN5P

RDYB

1nF

C0G

AIN5N

GPO0 GPO1 GPOGND CAPP CAPN CAPREG AVSS

DGND

1nF

C0G

Figure 22. Application Diagram for 1.8V DVDD

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Register Map

Legend:

CNV IN PROGRESS column – behavior during conversion:

CNV – Normal read/write activities are available.

CS – Writes to these registers immediately abort conversion in progress and the MAX11254 enters STANDBY state.

IG – No changes, write is ignored.

RETENTION column – behavior during SLEEP mode:

R – The value of the register is retained.

M – Only bits in < > are retained. Others are cleared.

The address column shows the register address as used in the command byte definition (see Table 4).

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Table 8. Register Map

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

—

INRESET

REFDET

RATE2

<SRDY5>

ORDERR

RATE1

<SRDY4>

GPOERR

RATE0

<SRDY3>

ERROR

U/B

<SRDY2>

SYSGOR

FORMAT

PGAG2

<SRDY1>

DOR

<SRDY0>

AOR

STAT

R

—

M

0

SCANERR

RATE3

CAL1

MSTAT

SCYCLE

PGAG1

NOSCG

DIO1

<RDY>

CONTSC

PGAG0

NOSCO

DIO0

CTRL1

CTRL2

CTRL3

R/W

CS

R

1

2

3

4

CAL0

PD1

PD0

EXTCLK

—

CSSEN

LDOEN

LPMODE

PGAEN

NOSYSG

DIR0

CS

GPO_MODE SYNC_MODE CALREGSEL

GPIO0_EN DIR1

NOSYSO

—

GPIO_CTRL R/W

CNV

GPIO1_EN

—

MUX[7:0]

GPO[7:0]

DELAY

R/W

IG

R

5

—

CH5_GPO1 CH5_ GPO0

CH4_GPO1 CH4_ GPO0

CH3_GPO1 CH3_GPO0

CH2_GPO1 CH2_GPO0

CH1_GPO1 CH1_GPO0

CH0_GPO1 CH0_GPO0

CH5_ORD2

CH4_ORD2

CH3_ORD2

CH2_ORD2

CH1_ORD2

CH0_ORD2

MODE1

CH5_ORD1

CH4_ORD1

CH3_ORD1

CH2_ORD1

CH1_ORD1

CH0_ORD1

MODE0

CH5_ORD0

CH4_ORD0

CH3_ORD0

CH2_ORD0

CH1_ORD0

CH0_ORD0

GPODREN

—

CH5_EN

CH4_EN

CH3_EN

CH2_EN

CH1_EN

CH0_EN

MDREN

GPO1

CH5_GPOEN

CH4_GPOEN

CH3_GPOEN

CH2_GPOEN

CH1_GPOEN

CH0_GPOEN

RDYBEN

CHMAP1

R

6

—

CHMAP0

R/W

IG

R

7

—

SEQ

GPO_DIR

SOC

R/W

R

CNV

IG

R

8

MUX2

—

MUX1

—

MUX0

—

9

—

GPO0

10

11

12

13

14

15

16

17

18

19

D[23:0]

SGC

IG

D[23:0]

SCOC

SCGC

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

IG

—

R

—

R

—

R

—

R

—

R

—

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Register Deﬁnitions

STAT: Status Register (Read)

BIT NAME

INRESET

0

SRDY5

0

SRDY4

0

SRDY3

0

SRDY2

0

SRDY1

0

SRDY0

0

DEFAULT

0

BIT NAME

SCANERR

0

REFDET

1

ORDERR

0

GPOERR

0

ERROR

0

SYSGOR

0

DOR

0

AOR

0

DEFAULT

BIT NAME

RATE3

0

RATE2

0

RATE1

0

RATE0

0

PDSTAT1

0

PDSTAT0

0

MSTAT

0

RDY

0

DEFAULT

This register provides the functional status of the MAX11254.

BIT NAME

DESCRIPTION

This bit is set to ‘1’ to indicate that the MAX11254 is in reset.

INRESET

This bit is set to ‘1’ in sequencer modes 2 and 3 to indicate that a new conversion result is available from the

channel indicated by the SRDY bit position. A complete read of the DATA register associated with the SRDY bit

will reset the bit to ‘0’. At the start of a scan mode these bits are reset to ‘0’.

SRDY[5:0]

This bit is set to ‘1’ if sequencer mode 2 or 3 is selected and no channels or invalid channel numbers (‘000’ or

‘111’) are enabled in the CHMAP1 or CHMAP0 register. Until SCANERR is cleared, conversion commands are

aborted.

SCANERR

REFDET

This bit is set to ‘1’ if a proper reference voltage is detected and ‘0’ if a proper reference voltage is missing. In

SLEEP or STANDBY mode the value of this bit is ‘0’. The trigger level for this bit is V

< 0.35V. This error

REF

does not inhibit normal operation and is intended for status only. The value of this status bit is valid within 30µs

after a conversion start command and is invalid when not in conversion.

This bit is set to ‘1’ if two or more CHX_ORD bits decode to the same scan sequence order and are also

enabled. This bit is also set to ‘1’ in the case when a channel is enabled for scan with CHX_EN=’1’ and CHX_

ORD[2:0] = ‘000’ or ‘111’. The CHX_ORD[2:0] values of ‘000’ and ‘111’ are not allowed as order of an enabled

channel. The allowable orders are ‘001’, ‘010’, ‘011’, ‘100’, ‘101’, ‘110’. The MAX11254 remains in STANDBY

state until this error is removed. The channel order must be strictly sequential and no missing numbers are

allowed. For instance, if 4 channels are enabled then the order must be ‘001’, ‘010’, ‘011’, ‘100’. Any other

order is ﬂagged as ORDERR and the MAX11254 remains in STANDBY mode.

ORDERR

This bit is set to ‘1’ if more than one input channel is mapped to the same GPO/GPIO pin, and CHX_GPOEN

is enabled for more than one channel. The MAX11254 remains in STANDBY state until this error is removed.

GPOERR

ERROR

This bit is set to ‘1’ to indicate invalid conﬁguration states. This bit is set if CAL[1:0] is programmed to ‘11’

which is an invalid state. This bit is set if CTRL1:SCYCLE = ‘0’ for scan modes 2 and 3. This error puts the

MAX11254 into STANDBY mode.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

STAT: Status Register (Read) (continued)

BIT NAME

DESCRIPTION

This bit is set to ‘1’ to indicate that a system gain calibration results in an overrange condition of the calibration

coeﬃcient. The SCGC calibration coeﬃcient is set to the maximum value of 1.9999999.

SYSGOR

DOR

This bit is set to ‘1’ to indicate that the conversion result has exceeded the maximum or minimum value of the

converter and that the result has been clipped or limited to the maximum or minimum value. When set to ‘0’

the conversion result is within the full-scale range of the inputs.

This bit is set to ‘1’ to indicate that the modulator detected an analog overrange condition by having the input

signal level greater than the reference voltage. This check for overrange includes the PGA gain.

AOR

These bits indicate the conversion rate that corresponds to the result in the DATA registers or the rate that was

used for calibration coeﬃcient calculation. The corresponding RATE[3:0] is only valid until the DATA registers

are read. The decoding of RATE[3:0] is shown in Table 1.

RATE[3:0]

These bits indicate the state of the MAX11254. See Table 6 for transition times.

PDSTAT1

PDSTAT0

DESCRIPTION

0

1

0

1

0

1

CONVERSION

SLEEP

PDSTAT[1:0]

STANDBY (default)

RESET

This bit is set to ‘1’ to indicate when a signal measurement is in progress. This indicates that a conversion,

self-calibration, or system calibration is in progress and that the modulator is busy. When the modulator is not

converting, this bit will be set to ‘0’.

MSTAT

RDY

This bit is set to ‘1’ to indicate that a new conversion result is available in sequencer mode 1. A complete read

of the corresponding DATA register will reset this bit to ‘0’. This bit is invalid in sequencer mode 2 or 3. The

function of this bit is redundant and is duplicated by the RDYB pin.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

CTRL1: Control Register 1 (Read/Write)

Default = 0x02l

BIT NAME

CAL1

0

CAL0

0

PD1

0

PD0

0

U/B

FORMAT

0

SCYCLE

1

CONTSC

0

DEFAULT

0

This register controls the selection of operational modes and conﬁgurations.

BIT NAME

DESCRIPTION

The calibration bits control the type of calibration performed when a calibration command byte is issued:

CAL1

CAL0

DESCRIPTION

0

1

0

1

0

1

Performs a self-calibration

CAL[1:0]

Performs a system-level oﬀset calibration

Performs a system-level full-scale calibration

Reserved. Do not use.

Selects the power-down state to be executed. The MAX11254 enters the selected power-down state

after a conversion command with MODE[1:0] set to ‘01’ is written. The state is decoded as below:

PD1

PD0

DESCRIPTION

0

1

0

1

0

1

NOP (default)

SLEEP

PD[1:0]

STANDBY

RESET

The ‘unipolar/bipolar’ bit controls the input range. A ‘1’ selects unipolar input range and a ‘0’ selects

bipolar input range.

U/B

The ‘format’ bit controls the digital format of the bipolar range data. A ‘0’ selects two’s complement and

a ‘1’ selects oﬀset binary format of the bipolar range. The data for unipolar range is always formatted

in oﬀset binary format.

FORMAT

The ‘single-cycle’ bit selects either no-latency single conversion mode or continuous conversion in

sequencer mode 1. A ‘1’ selects single-cycle mode where a no-latency conversion is followed by a

power-down to SLEEP mode. A ‘0’ selects continuous conversion mode with a latency of 5 conversion

cycles for ﬁltering. The RDYB pin goes low when valid/settled data is available. Only SCYCLE = ‘1’ is

valid in sequencer mode 2 and 3.

SCYCLE

CONTSC

The ‘continuous single-cycle’ bit selects between single or continuous conversions while operating

in single-cycle mode in sequencer mode 1. A ‘1’ selects continuous conversions and a ‘0’ selects a

single conversion.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

CTRL2: Control Register 2 (Read/Write)

Default = 0x20

BIT NAME

EXTCLK

0

CSSEN

0

LDOEN

1

LPMODE

0

PGAEN

0

PGAG2

0

PGAG1

0

PGAG0

0

DEFAULT

This register controls the selection and conﬁguration of optional functions.

BIT NAME

DESCRIPTION

External clock mode is enabled by setting this bit to ‘1’. In this mode, the internal oscillator is bypassed

and the GPIO0/CLK pin is conﬁgured as external clock input.

EXTCLK

Setting this bit to ‘1’ enables the current source and current sink on the analog inputs to detect sensor

opens or shorts.

CSSEN

LDOEN

Set this bit to ‘1’ to enable the internal LDO. Set this bit to ‘0’ when driving the CAPREG pin externally

with a 1.8V supply. When driving the CAPREG pin with external supply, the user must ensure that the

CAPREG pin is connected to the DVDD pin.

PGA low-power mode is enabled by setting this bit to ‘1’. The PGA operates with reduced power

consumption and reduced performance. The LPMODE does not aﬀect power or performance when

the PGA is not enabled.

LPMODE

PGAEN

The PGA enable bit controls the operation of the PGA. A ‘1’ enables and a ‘0’ disables the PGA.

The ‘PGA’ bits control the PGA gain. The PGA gain is set by:

PGA2

PGA1

PGA0

DESCRIPTION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Gain = 32

Gain = 64

Gain = 128

PGA[2:0]

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

CTRL3: Control Register 3 (Read/Write)

Default = 0x1C

BIT NAME

GPO_MODE

0

SYNC_MODE

0

CALREGSEL

1

NOSYSG

1

NOSYSO

1

NOSCG

0

NOSCO

0

DEFAULT

This register is used to control the operation and calibration of the MAX11254.

BIT NAME

DESCRIPTION

The value of this bit controls the GPO mode for sequencer mode 3. When set to ‘1’, the GPO and the

GPIO pins are sequenced based on the channel mapping in the CHMAP1 and CHMAP0 registers.

When set to ‘0’, the GPO and GPIO pins are directly controlled by the GPO_DIR and GPIO_CTRL

registers, respectively, during conversion or STANDBY state. This bit has no eﬀect in sequencer

modes 1 and 2.

GPO_MODE

This bit controls sync mode (see the Conversion Synchronization Using Sync Pin and External Clock

section). When set to ‘1’, the synchronization mode is enabled, when set to ‘0’ it is disabled.

SYNC_MODE

CALREGSEL

This bit controls which calibration value is read during a calibration register inquiry. Set this bit to ‘1’ to

read back the interface value. Set this bit to ‘0’ to read back the internal register value.

The ‘no system gain’ bit controls the use of the system gain calibration coeﬃcient. Set this bit to ‘1’

to disable the use of the system gain value when computing the ﬁnal oﬀset and gain corrected data

value. Set this bit to ‘0’ to enable the use of the system gain value when computing the ﬁnal oﬀset and

gain corrected data value.

NOSYSG

NOSYSO

NOSCG

NOSCO

The ‘no system oﬀset’ bit controls the use of the system oﬀset calibration coeﬃcient. Set this bit to ’1’

to disable the use of the system oﬀset value when computing the ﬁnal oﬀset and gain corrected data

value. Set this bit to ‘0’ to enable the use of the system oﬀset value when computing the ﬁnal oﬀset

and gain corrected data value.

The ‘no self-calibration gain’ bit controls the use of the self-calibration gain calibration coeﬃcient. Set

this bit to ‘1’ to disable the use of the self-calibration gain value when computing the ﬁnal oﬀset and

gain corrected data value. Set this bit to ‘0’ to enable the use of the self-calibration gain value when

computing the ﬁnal oﬀset and gain corrected data value.

The ‘no self-calibration oﬀset’ bit controls the use of the self-calibration oﬀset calibration coeﬃcient.

Set this bit to ‘1’ to disable the use of the self-calibration oﬀset value when computing the ﬁnal oﬀset

and gain corrected data value. Set this bit to ‘0’ to enable the use of the self-calibration oﬀset value

when computing the ﬁnal oﬀset and gain corrected data value.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

GPIO_CTRL: GPIO Control Register (Read/Write)

Default = 0x4x

BIT NAME

GPIO1_EN

0

GPIO0_EN

1

DIR1

0

DIR0

0

DIO1

X

DIO0

X

DEFAULT

This register controls the direction and values of the general-purpose I/O (GPIO) pins.

BIT NAME

DESCRIPTION

This bit selects the functionality of the GPIO1/SYNC pin. Set this bit to ‘1’ to use the pin as GPIO, or

set the bit to ‘0’ to use the pin as SYNC input.

GPIO1_EN

This bit selects the functionality of the GPIO0/CLK pin. Set this bit to ‘1’ to use the pin as GPIO, or set

the bit to ‘0’ to use the pin as external clock input.

GPIO0_EN

The ‘direction’ bits conﬁgure the GPIO pins either as input or output. DIR1 corresponds to GPIO1,

while DIR0 controls GPIO0. Set the DIR bit to ‘1’ to conﬁgure the GPIO pin as output. The output

value of the GPIO pin is determined by the value of the DIO bit. Set the DIR bit to ‘0’ to conﬁgure the

associated GPIO pin as input. The logic input value of the GPIO pin can be read back from the DIO bit.

DIR[1:0]

The ‘data input/output’ bits reﬂect the status of the GPIO pins. DIO1 corresponds to GPIO1, while

DIO0 corresponds to GPIO0. If the GPIO pin is conﬁgured as output, the pin is driven to the logic value

of DIO. If the GPIO pin is conﬁgured as input, DIO reﬂects the logic value seen at the pin.

DIO[1:0]

DELAY: Delay Register (Read/Write)

Default = 0x0000

BIT NAME

MUX[7:0]

0x00

GPO[7:0]

0x00

DEFAULT

BIT NAME

DESCRIPTION

Used to program the mux delay. The mux delay ranges from 4µs to 1.02ms. The default value of 0x00

corresponds to no delay. 1 LSB = 4µs of delay.

MUX[7:0]

Used to program the GPO/GPIO delay. The GPO/GPIO delay ranges from 20µs to 5.1ms. The default

value of 0x00 corresponds to no delay. 1 LSB = 20µs of delay.

GPO[7:0]

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

CHMAP1: Channel Map Register (Read/Write)

Default = 0x00_0000

BIT NAME

DEFAULT

BIT NAME

DEFAULT

BIT NAME

DEFAULT

CH5_GPO1 CH5_GPO0 CH5_ORD2 CH5_ORD1 CH5_ORD0

CH5_EN

CH5_GPOEN

0

CH4_GPO1 CH4_GPO0 CH4_ORD2 CH4_ORD1 CH4_ORD0

CH4_EN

CH4_GPOEN

0

CH3_EN

0

CH3_GPO1 CH3_GPO0 CH3_ORD2 CH3_ORD1 CH3_ORD0

CH3_GPOEN

0

CHMAP0: Channel Map Register (Read/Write)

Default = 0x00_0000

BIT NAME

DEFAULT

BIT NAME

DEFAULT

BIT NAME

DEFAULT

CH2_GPO1 CH2_GPO0 CH2_ORD2 CH2_ORD1

CH2_ORD0

CH2_EN

CH2_GPOEN

0

CH1_GPO1 CH1_GPO0 CH1_ORD2 CH1_ORD1

CH1_ORD0

CH1_EN

CH1_GPOEN

0

CH0_EN

0

CH0_GPO1 CH0_GPO0 CH0_ORD2 CH0_ORD1

CH0_ORD0

0

CH0_GPOEN

0

These registers are used to enable channels for scan, enable GPO/GPIO pins for scan, program the channel scan order, and pair

the GPO/GPIO pins with its associated channel. These registers cannot be written during an active conversion.

BIT NAME

DESCRIPTION

Used to map which GPO or GPIO pin is activated when this channel is selected. The STAT:GPOERR

ﬂag is set if more than one input channel is mapped to the same GPO/GPIO pin. The decoding is as

follows:

CHX_GPO1 CHX_GPO0

DESCRIPTION

CHX_GPO[1:0]

0

1

0

1

0

1

GPO0

GPO1

GPIO0

GPIO1

Deﬁnes the order during scan when the channel is enabled. The CHX_ORD[2:0] values of ‘000’ and ‘111’

are not allowed for the order of an enabled channel. The allowable orders are ‘001’, ‘010’, ‘011’, ‘100’,

‘101’, ‘110’ representing ﬁrst, second, third channel to be scanned, and so on. The value of ‘000’ is a

default value and the value of ‘111’ is greater than the number of scannable channels. A value greater

than the number of enabled channels is invalid and will set an error condition at STAT:ORDERR. Setting

a channel’s order to ‘000’ or ‘111’ and enabling it will set the STAT:ORDERR ﬂag in the STAT register.

If sequencer mode 3 is selected, and more channels are enabled for sequencing than available GPO/

GPIO pins, then the sequence order of the channels for which a GPO/GPIO pin is enabled must be

lower than for the channels which do not have a GPO/GPIO pin mapped to them.

CHX_ORD[2:0]

CHX_EN

Set this bit to ‘1’ to enable scanning of this channel. Set this bit to ‘0’ to disable scanning of this channel.

Used to enable activation of the GPO/GPIO pins when this channel is selected during scan. Set this bit

to ‘1’ to enable. Set this bit to ‘0’ to disable.

CHX_GPOEN

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

SEQ: Sequencer Register (Read/Write)

Default = 0x00

BIT NAME

MUX2

0

MUX1

0

MUX0

0

MODE1

0

MODE0

0

GPODREN

0

MDREN

0

RDYBEN

0

DEFAULT

This register is used to control the operation of the sequencer when enabled.

BIT NAME

DESCRIPTION

Binary channel selection for sequencer mode 1. Valid channels are from 000 (channel 0) to 101

(channel 5).

MUX[2:0]

Sequencer mode is decoded as shown in the following table:

MODE1

MODE0

DESCRIPTION

0

1

0

1

0

1

Sequencer Mode 1

Sequencer Mode 2

Sequencer Mode 3

Reserved. Do not use.

MODE[1:0]

GPO/GPIO delay enable. Enables operation of the GPO/GPIO switch delay. When enabled, the

channel selection is delayed. The value of the delay is set by the DELAY:GPO bits.

GPODREN

MDREN

MUX delay enable. Enables the timer setting in the DELAY:MUX register to delay the conversion start

of the selected channel.

Ready Bar enable. When this bit is ‘1’ the RDYB is inhibited from asserting in sequencer mode 2 and

3 until all channels are converted

RDYBEN

GPO_DIR: GPO Direct Access Register (Read/Write)

Default = 0x00

BIT NAME

GPO1

0

GPO0

0

DEFAULT

This register is used to turn on and oﬀ the general-purpose outputs directly after an associated bit is written except when

CTRL3:GPO_MODE=’1’ during sequencer mode 3. When operating in sequencer mode 1 or 2, the activation of the GPOs is

immediate upon setting a bit to ’1’, and the deactivation of the GPOs is immediate upon setting the bit to ‘0’. In SLEEP state, the

values in this register do not control the state of the GPOs, as they all are deactivated. The register is writeable, but the values will

not control the GPOs in SLEEP mode. In STANDBY state when CTRL3:GPO_MODE=’0’, this register accepts writes and updates

the state of the GPOs immediately after the value of a bit changes. Writes to this register are ignored when operating in mode 3 when

CTRL3:GPO_MODE=’1’. This register is enabled during system oﬀset calibration, system gain calibration and self-calibration modes.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

SOC: System Offset Calibration Register (Read/Write)

Default = 0x00_0000

BIT NAME

B23

0

B22

0

B21

0

….

B3

0

B2

0

B1

0

B0

0

DEFAULT

The system oﬀset calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB

ﬁrst. This register holds the system oﬀset calibration value. The format is in two’s complement binary format. A system calibration

does not overwrite the SOC register.

The readback value of this register depends on CTRL3:CALREGSEL. A ‘1’ reads back the user programmed value. A ‘0’ reads back

the results of an internal register as described in CTRL3:CALREGSEL. The internal register can only be read during conversion.

The system oﬀset calibration value is subtracted from each conversion result—provided the NOSYSO bit in the CTRL3 register is

set to ‘0’. The system oﬀset calibration value is subtracted from the conversion result after self-calibration but before system gain

correction. It is also applied prior to the 1x or 2x scale factor associated with bipolar and unipolar modes. When a system oﬀset

calibration is in progress, this register is not writable by the user.

SGC: System Gain Calibration Register (Read/Write)

Default = 0x7F_FFFF

BIT NAME

B23

0

B22

1

B21

1

….

B3

1

B2

1

B1

1

B0

1

DEFAULT

The system gain calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB

ﬁrst. This register holds the system gain calibration value. The format is unsigned 24-bit binary. A system calibration does not

overwrite the SGC register.

The readback value of this register depends on CTRL3:CALREGSEL. A ‘1’ reads back the user programmed value. A ‘0’ reads back

the results of an internal register as described in CTRL3:CALREGSEL. The internal register can only be read during conversion.

The system gain calibration value is used to scale the oﬀset corrected conversion result—provided the NOSYSG bit in the CTRL3

register is set to ‘0’. The system gain calibration value scales the oﬀset corrected result by up to 2x or can correct a gain error of

approximately -50%. The amount of positive gain error that can be corrected is determined by modulator overload characteristics,

which may be as much as +25%. When a system gain calibration is in progress, this register is not writable by the user.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

SCOC: Self-Calibration Offset Calibration Register (Read/Write)

Default = 0x00_0000

BIT NAME

B23

0

B22

0

B21

0

….

B3

0

B2

0

B1

0

B0

0

DEFAULT

The self-calibration oﬀset register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB

ﬁrst. This register holds the self-calibration oﬀset value. The format is always in two’s complement binary format. An internal self-

calibration does not overwrite the SCOC register.

The readback value of this register depends on CTRL3:CALREGSEL. A ‘1’ reads back the user programmed value. A ‘0’ reads back

the results of an internal register as described in CTRL3:CALREGSEL. The internal register can only be read during conversion.

The self-calibration oﬀset value is subtracted from each conversion result—provided the NOSCO bit in the CTRL3 register is set to

‘0’. The self-calibration oﬀset value is subtracted from the conversion result before the self-calibration gain correction and before the

system oﬀset and gain correction. It is also applied prior to the 2x scale factor associated with unipolar mode. When a self-calibration

is in progress, this register is not writable by the user.

SCGC: Self-Calibration Gain Calibration Register (Read/Write)

Default = 0xBF_851B

BIT NAME

B23

1

B22

0

B21

1

….

B3

1

B2

0

B1

1

B0

1

DEFAULT

The self-calibration gain register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB ﬁrst.

This register holds the self-calibration gain value. The format is unsigned 24-bit binary. An internal self- calibration does not overwrite

the SCGC register.

The readback value of this register depends on CTRL3:CALREGSEL. A ‘1’ reads back the user programmed value. A ‘0’ reads back

the results of an internal register as described in CTRL3:CALREGSEL. The internal register can only be read during conversion.

The self-calibration gain calibration value is used to scale the self-calibration oﬀset corrected conversion result before the system oﬀset

and gain calibration values have been applied – provided the NOSCG bit in the CTRL3 register is set to ‘0’. The self-calibration gain

calibration value scales the self-calibration oﬀset corrected conversion result by up to 2x or can correct a gain error of approximately

–50%. The gain will be corrected to within 2 LSB. When a self- calibration is in progress, this register is not writable by the user.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

DATA[5:0]: Data Registers (Read Only)

Default = 0x00_0000

BIT NAME

D23

0

D22

0

D21

0

…

D3

0

D2

0

D1

0

D0

0

DEFAULT

Each data register holds the conversion result for the corresponding channel. DATA0 is the data register for channel 0, DATA1 is

for channel 1, etc.

Each data register is a 24-bit read-only register. Any attempt to write data to this location will have no eﬀect. The data read from

these registers is clocked out MSB ﬁrst. The result is stored in a format according to the FORMAT bit in the CTRL1 register. The data

format while in unipolar mode is always oﬀset binary. In oﬀset binary format the most negative value is 0x000000, the midscale value

is 0x800000 and the most positive value is 0xFFFFFF. In bipolar mode if the FORMAT bit = ‘1’ then the data format is oﬀset binary. If

the FORMAT bit = ‘0’, then the data format is two’s complement. In two’s complement the negative full-scale value is 0x800000, the

midscale is 0x000000 and the positive full scale is 0x7FFFFF. Any input exceeding the available input range is limited to the minimum

or maximum data value.

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MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Ordering Information

Chip Information

PROCESS: CMOS

PART

TEMP RANGE

PIN-PACKAGE

32 TQFN-EP*

MAX11254ATJ+

MAX11254ATJ+T

MAX11254ATJ/V+

MAX11254ATJ/V+T

-40°C to +125°C

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

*EP = Exposed pad.

Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

PART

PACKAGE TYPE

32 TQFN

PACKAGE CODE

T3255+4

OUTLINE NO.

21-0140

LAND PATTERN NO.

90-0012

MAX11254ATJ+

MAX11254ATJ/V+

32 TQFN

T3255+4

21-0140

90-0012

Maxim Integrated

│ 50

www.maximintegrated.com

MAX11254

24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,

Delta-Sigma ADC with SPI Interface

Revision History

REVISION REVISION

PAGES

DESCRIPTION

CHANGED

NUMBER

DATE

0

1

3/15

Initial release

—

4/15

Revised Typical Operating Characteristics section

10, 11

Adding MAX11254ATJ/V+ as future product to Ordering Information table.

Updated Package Information table

2

8/17

50

3

4

5

3/18

9/18

Updated Ordering Information table

Updated Beneﬁts and Features section

Updated Applications section

50

1

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2018 Maxim Integrated Products, Inc.

│ 51


型号：	MAX11254ATJ/V+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	24-Bit, 6-Channel, 64ksps, 6.2nV/âHz PGA, Delta-Sigma ADC with SPI Interface
文件：	总51页 (文件大小：1162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX11254ATJ/V+ [MAXIM]

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