MAX11270EUG+_技术文档

EVALUATION KIT AVAILABLE

MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

General Description

Features and Beneﬁts

The MAX11270 is a 24-bit delta-sigma ADC that achieves

excellent 130dB SNR while dissipating an ultra-low 10mW.

Sample rates up to 64ksps allow both precision DC and

AC measurements. Integral nonlinearity is guaranteed

to 4ppm maximum. The THD is -122dB. The MAX11270

communicates via an SPI-compatible serial interface and

is available in a small 24-pin TSSOP package.

●

High Resolution for Instrumentation Applications that

Require a Wide Dynamic Range

∙ 130dB SNR at 1.9sps

∙ 112dB SNR at 1000sps

∙ 20.4-Bit Noise-Free Resolution at 1.9sps

∙ 17.4-Bit Noise-Free Resolution at 1000sps

● Longer Battery Life for Portable Applications

∙ 2.4mA Operating Mode Current

∙ 4.4mA PGA Low-Noise Mode Current

∙ 1μA Sleep Current

● High Accuracy for DC Measurements

∙ 1ppm INL (typ), 4ppm (max)

The MAX11270 offers a 6.5nV/√Hz noise programmable

gain amplifier with gain settings between 1x to 128x.

Optional buffers are also included to provide isolation of

the signal inputs from the switched capacitor sampling

network. This allows the MAX11270 to be used with

high-impedance sources without compromising available

dynamic range.

● Single or Split Analog Supplies Provide Input Voltage

Range Flexibility

The MAX11270 operates from a single 2.7V to 3.6V

analog supply, or split ±1.8V analog supplies, allowing

the analog input to be sampled below ground. The digital

supply range is 2.0V to 3.6V, allowing communication with

2.5V, 3V, or 3.3V logic.

∙ 2.7V to 3.6V (Single Supply) or

±1.8V (Split Supplies)

● Flexible High-Performance Filter Architecture

Simplifies Design

∙ Programmable SINC Filter

Applications

● Enables System Integration

∙ Low-Noise PGA with Gains of 1, 2, 4, 8, 16, 32,

64, 128

● Scientiﬁc Instrumentation

● High-Precision Portable Sensors

● Medical Equipment

● ATE

∙ Signal Buffer Optional

∙ 3 General-Purpose I/Os

● Enables Integrated Part and System Calibration for

Gain and Offset

Ordering Information and Functional Diagram appear at

end of data sheet.

● Robust 24-Pin TSSOP Packaging

Typical Application Circuit

2.7V TO 3.6V

REF

2.0V TO 3.6V

1µF

10nF

1µF

REFN REFP

AVDD

DVDD

RSTB

SYNC

AINP

AINN

CSB

µC

SCLK

10nF

C0G

MAX11270

DIN

DOUT

RDYB

GPI02

GPIO3

GPI01

CAPP CAPN CAPREG AVSS AVSS DGND

1µF

0603

X7R

10nF

C0G

19-7048; Rev 1; 5/15

MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

TABLE OF CONTENTS

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Voltage Reference Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Input Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Bypass/Direct Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Programmable Gain Amplifier (PGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Noise Performance vs. Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

SINC Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Chip Select (CSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

SCLK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

DIN (Serial Data Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

DOUT (Serial Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Data Ready (RDYB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

SPI Incomplete Write Command Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

SPI Incomplete Read Command Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Modes and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Conversion Mode (MODE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Register Access Mode (MODE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

TABLE OF CONTENTS (continued)

Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Status Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Control 1 Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Control 2 Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Control 3 Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Control 4 Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Control 5 Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Data Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

System Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

SPI System Offset Calibration Register (SOC_SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

ADC System Offset Calibration Register (SOC_ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

SPI System Gain Calibration Register (SGC_SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

ADC System Gain Calibration Register (SGC_ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

SPI Self-Cal Offset Calibration Register (SCOC_SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

ADC Self-Cal Offset Calibration Register (SCOC_ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

SPI Self-Cal Gain Calibration Register (SCGC_SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

ADC Self-Cal Gain Calibration Register (SCGC_ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Conversion Synchronization Using SYNC Pin or SYNC_SPI Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Continuous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Pulse Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Modulator MODBITS Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Initializing MODBITS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Exiting MODBITS Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

MODBITS Mode Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

DOUT/MB0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

GPIO3/MSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

GPIO1/MB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

RDYB/ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

LIST OF FIGURES

Figure 1. PGA Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Usable Input and Output Common-Mode Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3a. SINC Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 3b. SINC Mag Response Zoomed-In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4. DATA Ready Timing for All Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5. SPI Register Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 6. SPI Register Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 7. SPI Data Readout Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8. SPI Command Byte Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9. Calibration Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 10. Synchronization Using Continuous Sync Mode Showing Relationship Between SYNC Pin and CLK Pin 41

Figure 11. Synchronization Using Pulse Sync Mode Showing Relationship Between SYNC, RDYB, and CLK Pins. 42

Figure 12. Pin Configuration with MODBITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 13. Timing Diagram for MODBITS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

LIST OF TABLES

Table 1. Continuous Mode SNR (dB) vs Data Rate and PGA Gain with Sinc Filter^*. . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 2. Continuous Mode Input-Referred Noise (µV

) vs. Data Rate and PGA Gain with Sinc Filter^*. . . . . . . . 19

RMS

Table 3. Single-Cycle Mode SNR (dB) vs. Data Rate and PGA Gain with Sinc Filter*. . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4. Single-Cycle Mode Input-Referred Noise (µVRMS) vs. Data Rate and PGA Gain with Sinc Filter* . . . . . . 21

Table 5. MAX11270 Command Behavior from Pin (RSTB, SYNC) and SPI (RESET, SYNC_SPI) . . . . . . . . . . . . . . . . . . . 22

Table 6. Command Byte for Conversion Modes (MODE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 7. Command Byte for Register Access Mode (MODE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8. Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 9. Programmable Conversion Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10. ADC Output Code Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 11. MODBITS Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Absolute Maximum Ratings

AVDD to AVSS .....................................................-0.3V to +3.9V

DVDD to DGND....................................................-0.3V to +3.9V

DVDD to AVSS.....................................................-0.3V to +3.9V

AVSS to DGND ..................................................-1.95V to +0.3V

Analog Inputs

(AINP, AINM, REFP, REFN, CAPP, CAPN)

to AVSS ........... -0.3V to the lower of 3.9V or (V

Digital Inputs to DGND

(RSTB, SYNC, DIN, SCLK, CLK,

GPIO1-3) .........-0.3V to the lower of 3.9V or (V

Digital Outputs to DGND

(RDYB, DOUT,

GPIO1-3) .........-0.3V to the lower of 3.9V or (V

Digital Inputs to AVSS

(RSTB, SYNC, DIN, SCLK, CLK,

GPIO1–GPIO3).................................................-0.3V to +3.9V

Digital Outputs to AVSS

(RDYB, DOUT, GPIO1–3)....................................-0.3V to +3.9V

CAPREG to DGND...............................................-0.3V to +2.2V

CAPREG to AVSS................................................-0.3V to +3.9V

Continuous Power Dissipation (Single-Layer Board)

TSSOP (derate 13.9mW/°C above +70°C) .......... 1111.10mW

Operating Temperature Range........................... -40°C to +85°C

Storage Temperature Range............................ -55°C to +150°C

Junction Temperature (continuous).................................+150°C

Lead temperature (soldering, 10s)..................................+300°C

Soldering Temperature (reflow).......................................+260°C

+ 0.3V)

AVDD

DVDD

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

(Note 1)

Package Thermal Characteristics

TSSOP

Junction-to-Case Thermal Resistance (θ )................13°C/W

Junction-to-Ambient Thermal Resistance (θ )...........72°C/W

JA

JC

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics

(V

= 3.6V, V

= 0V, V

= 2.0V, V

= 2.5V, V

= 0V; f

= 1000sps, External Clock = 8.192MHz; Continuous

AVDD

AVSS

DVDD

REFP

REFN

DATA

conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,

= T to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)

T

A

MIN

MAX

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

1.9sps data rate (Bypass Mode only)

1ksps data rate (Bypass Mode only)

19.2

16.9

20.4

17.4

Noise-Free Resolution

(Note 3)

NFR

Bits

NOISE REFERRED TO INPUT V (See Tables 1–4)

N

Bypass, Buffer, PGA = 1, 2

PGA > 2

1

2

4

Integral Nonlinearity

INL

ppm

Offset Error

Offset Drift

Gain Error

Gain Drift

V_OS

After system offset calibration

10

nV

V_{OS_DRIFT}

G_ERR

50

nV/°C

ppm

After system gain calibration

2

G_{ERR_DRIFT}

2.5

135

120

105

100

120

ppm/°C

Bypass and Buffer mode

PGA Gain = 4

120

100

80

DC Common-Mode

Rejection (Note 4)

CMR

dB

DC

Bypass and Buffer mode

PGA Gain = 4

AVDD, AVSS DC Supply

Rejection Ratio

PSRRA

PSRRD

80

Bypass and Buffer mode

PGA Gain = 4

95

DVDD DC Supply Rejection

Ratio

95

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Electrical Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V, V

= 2.5V, V

= 0V; f

= 1000sps, External Clock = 8.192MHz; Continuous

AVDD

AVSS

DVDD

REFP

REFN

DATA

conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,

= T to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)

T

A

MIN

MAX

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG INPUTS/REFERENCE INPUTS

Unipolar

0

V

REF

AIN Voltage Range

V_RNG

V

Bipolar

-V

REF

Bypass mode

V

AVSS

AVDD

AVSS

AVDD

PGA mode

+ 0.3

- 1.3

Absolute Input Voltage

VABS_RNG

V

AVSS

+ 0.1

V

AVDD

- 0.1

Buffer mode

AIN DC Input Leakage

(Note 4)

IIN_LEAK

Sleep mode enabled

-10

+10

nA

AIN Common-Mode Input

Conductance

G_AINCMBypass

±8

nA/V

Buffer

I_AINCM

±500

±21

nA

AIN Common-Mode Input

Current

PGA

AIN Differential Mode Input

Conductance

G_AINDIFFBypass

±23

µA/V

Buffer

I_AINDIFF

±20

nA

AIN Differential Mode Input

Current

PGA

±0.15

REF Differential Input

Conductance

G_REFDIFFActive conversion state

±46.5

±100

µA/V

nA

REF Input Current at Power

Down

I

Sleep and Standby states

REF_PD

AIN Input Capacitance

REF Input Capacitance

C

Buffer disabled

3

pF

IN

C

4.5

REF

Input and REF Sampling

Rate

f

4.096

MHz

S

V

- V

Voltage

REFP

REFN

VRABS

(Note 5)

V

RNG

AVDD

Range

REF Voltage Range

V

2.0

V

REF

AVDD

DIGITAL FILTER RESPONSE

SINC FILTER

Bandwidth (-3dB)

Settling Time (Latency)

BW

0.203

5

f

DATA

SINC

1/f

DATA

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Electrical Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V, V

= 2.5V, V

= 0V; f

= 1000sps, External Clock = 8.192MHz; Continuous

AVDD

AVSS

DVDD

REFP

REFN

DATA

conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,

= T to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)

T

A

MIN

MAX

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

LOGIC INPUTS

Input Current

I

Leakage current only

-1

+1

µA

V

LEAK_DIG

0.3x

Input Low Voltage

Input High Voltage

V

IL

V

DVDD

0.7x

V

IH

V

DVDD

Input Hysteresis

V

200

20

mV

V

HYS

GPIO Input Low Voltage

GPIO Input High Voltage

GPIO Input Hysterisis

LOGIC OUTPUTS

V

0.4

IL_GPIO

V

1.0

V

IH_GPIO

V

mV

HYS_GPIO

Output Low Level

V

I

= 1mA

0.4

V

OL

0.9x

Output High Level

V

OH

V

DVDD

Floating State Leakage

Current

I_{DIGO_LEAK}

-10

+10

µA

pF

Floating State Output

Capacitance

C

9

DIGO

POWER REQUIREMENTS

Analog Negative Supply

V

For split supplies, V

= - V

-1.8

0

V

AVSS

AVDD

V

+

V

+

AVSS

2.7

AVSS

3.6

Analog Positive Supply

Digital Supply

V

AVDD

AVSS

V

2.0

3.6

DVDD

AVDD Sleep Current

I_{AVDD_SLEEP}

I_{AVDD_STBY}

I_{DVDD_SLEEP}

I_{DVDD_STBY}

0.9

1.5

3

µA

AVDD Standby Current

DVDD Sleep Current

DVDD Standby Current

3

1

µA

0.25

21

200

Bypass mode

Buffers mode

2.4

2.8

3.0

3.5

5.0

6.0

1.5

Analog Supply Current

I

mA

AVDD

PGA low-power mode

PGA low-noise mode

SINC ﬁlter

3.6

4.4

DVDD Operating Current

I

0.77

DVDD

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Electrical Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V, V

= 2.5V, V

= 0V; f

= 1000sps, External Clock = 8.192MHz; Continuous

AVDD

AVSS

DVDD

REFP

REFN

DATA

conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,

= T to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)

T

A

MIN

MAX

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SPI TIMING REQUIREMENTS (See Figures 4–7)

SCLK Frequency

f

5

MHz

ns

SCLK

SCLK Clock Period

SCLK Pulse Width High

SCLK Pulse Width Low

CSB Low Setup

t

200

80

CP

CH

t

Allow 40% duty cycle

ns

t

Allow 40% duty cycle

80

ns

CL

t

CSB low to 1st SCLK rise setup

40

ns

CSS0

Required to prevent a 17th SCLK RE from

being recognized by the device in a free-

running application

CSB High Setup (Note 4)

40

ns

CSS1

SCLK falling edge to CSB rising edge,

CSB hold time

CSB Hold

t

3

ns

CSH1

CSB Pulse Width

DIN Setup

t

Minimum CSB pulse width high

DIN setup to SCLK rising edge

DIN hold after SCLK rising edge

DOUT transition valid after SCLK fall

40

0

ns

CSW

t

DS

DIN Hold

t

DH

DOUT Transition

t

40

DOT

Output hold time remains valid after SCLK

fall

DOUT Hold

t

3

ns

DOH

CSB rise to DOUT disable,

DOUT Disable

25

40

DOD

C

LOAD

= 20pF

Default value of DOUT is ‘1’ for minimum

speciﬁcation, max speciﬁcation for valid ‘0’

on RDYB

CSB Fall to DOUT Valid

SCLK Fall to RDYB ‘1’

t

0

ns

DOE

RDYB transitions from ‘0’ to ‘1’ on falling

edge of SCLK after LSB of DATA is shifted

onto DOUT

t

40

2

R1

R2

RDYB transitions from ‘0’ to ‘1’ on falling

edge of RSTB or rising edge of SYNC

RSTB Fall or SYNC Rise to

RDYB ‘1’

1/f

CLK

after 2 f

cycles

CLK

Minimum SYNC High Pulse

Width

t

2

1/f

SYNC1

CLK

Minimum RSTB Low Pulse

Width

t

RSTB0

Note 2: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design

A

and device characterization.

Note 3: Noise-free resolution is defined using the peak-to-peak input range and the peak-to-peak noise voltage. The peak-to-peak

input range, V

is defined as 2 x V

. The peak-to-peak noise voltage is defined as the RMS noise voltage

IN_RANGE_P-P

REF

times 6.6. The NFR is calculated for bypass mode only and with SINC filter using the formula, NFR = log(V

/

IN_RANGE_P-P

(6.6 x V

))/log(2).

NOISE_RMS

Note 4: These specifications are not fully tested and are guaranteed by design and/or characterization.

Note 5: Reference common mode (V

+ V

)/2 ≤ (V

+ V

)/2 +0.1V.

REFP

REFN

AVDD

AVSS

Maxim Integrated

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Typical Operating Characteristics

(V

= 3.6V, V

= 0V, V

= 2.0V, V

= 2.5V, V

= 0V; f

= 1000sps, External Clock = 8.192MHz; Continuous

AVDD

AVSS

DVDD

REFP

REFN

DATA

conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,

T

= T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

A

MIN

STANDBY CURRENT

vs. TEMPERATURE

ACTIVE CURRENT

vs. TEMPERATURE

SLEEP CURRENT

vs. TEMPERATURE

toc02

toc01

toc03

1000.00

100.00

10.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

BYPASS MODE

I_{AVDD_ACT}

I_{DVDD_STBY}

I_{AVDD_SLEEP}

I_{DVDD_SLEEP}

I_{AVDD_STBY}

SINC I_{DVDD_ACT}

1.00

-50

0

50

TEMPERATURE (ºC)

100

150

-50

0

50

100

150

-50

0

50

100

150

TEMPERATURE (ºC)

INTERNAL OSCILLATOR

FREQUENCY VARIATION

vs. TEMPERATURE

INTERNAL OSCILLATOR

FREQUENCY VARIATION

vs. DVDD

NOISE vs. COMMON-MODE VOLTAGE

toc05

toc04

toc06

2.0

1.5

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

6

5

4

3

BYPASS MODE

SINC FILTER

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-50

0

50

100

150

1.00

2.00

3.00

4.00

5.00

0

1

2

3

4

TEMPERATURE (ºC)

V_DVDD(V)

COMMON-MODE VOLTAGE (V)

NOISE vs. V_REF

1ksps NOISE HISTOGRAM

NOISE vs. TEMPERATURE

toc06b

toc07

toc08

10

9

100

90

80

70

60

50

40

30

20

10

0

8.0

BYPASS MODE

SINC FILTER

SHORTED INPUTS

7.0

6.0

5.0

4.0

3.0

2.0

8

7

6

5

4

3

BYPASS MODE

100 150

2

1

2

3

4

-50

0

50

-10 -8 -6 -4 -2

0

2

4

6

8

10 12

V_REFP- V_REFN(V)

TEMPERATURE (ºC)

OUTPUT VOLTAGE (µV)

Maxim Integrated

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Typical Operating Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V, V

= 2.5V, V

= 0V; f

= 1000sps, External Clock = 8.192MHz; Continuous

AVDD

AVSS

DVDD

REFP

REFN

DATA

conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,

T

= T to T , unless otherwise noted. Typical values are at T = +25°C.)

A

MIN

MAX

A

64ksps NOISE HISTOGRAM

INL vs. INPUT VOLTAGE

toc09

toc10A

toc10B

450

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

Bypass Mode

Buffer Mode

400

350

300

250

200

150

100

50

T_A= +85°C

T_A= +25°C

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

T_A= +25°C

T_A= -40°C

BYPASS MODE

SINC FILTER

SHORTED INPUTS

T_A= -40°C

0.5

0

-80-70-60-50-40-30-20-10 0 10 20 30 40 50 60 70 80

NOISE (µV)

-2.5

-1.5

-0.5

0.5

1.5

2.5

-2.5

-1.5

-0.5

1.5

2.5

DIFFERENTIAL INPUT (V)

OFFSET ERROR

vs. TEMPERATURE

INL vs INPUT VOLTAGE

INL vs. INPUT VOLTAGE

toc10C

toc10D

toc11

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

10

5

CALIBRATED AT 25°C

BYPASS MODE

PGA = 4 LP Mode

T_A= +85°C

PGA = 4 LN Mode

T_A=+85°C

T_A= -40°C

T_A=+25°C

0

-5

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

-10

-15

-20

T_A= +25°C

T_A= -40°C

-50

0

50

100

150

-0.65

-0.325

0

0.325

0.65

-0.65

-0.325

0

0.325

0.65

TEMPERATURE (°C)

DIFFERENTIAL INPUT (V)

OFFSET ERROR

vs. AVDD

OFFSET ERROR

vs. V_REFP- V_REFN

toc12

toc13

8

6

150

100

50

CALIBRATED AT V_AVDD= 3.15V,

BYPASS MODE

CALIBRATED AT V_REF= 2.5V

BYPASS MODE

4

2

0

-2

-4

-6

-8

-50

-100

-150

2.5

3

3.5

4

1

2

3

4

V_AVDD(V)

V_REFP- V_REFN(V)

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Typical Operating Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V, V

= 2.5V, V

= 0V; f

= 1000sps, External Clock = 8.192MHz; Continuous

AVDD

AVSS

DVDD

REFP

REFN

DATA

conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,

T

= T

to T , unless otherwise noted. Typical values are at T = +25°C.)

MAX A

A

MIN

OUTPUT SPECTRUM

SHORTED INPUTS

SNR

vs. TEMPERATURE

toc15

toc14A

0

115

114

113

112

111

110

109

108

107

106

105

BYPASS MODE

SINGLE-CYCLE CONTINUOUS

SINC FILTER

BYPASS MODE

FULL SCALE = ±3.6V

-20

-40

-60

-80

-100

-120

-140

-160

-180

-50

0

50

TEMPERATURE (ºC)

100

150

0

100

200

300

400

500

FREQUENCY (Hz)

OFFSET HISTOGRAM OF 200 PARTS

SNR vs. VREF

toc16

toc15b

35

30

25

20

15

10

5

120

118

116

114

112

110

108

106

104

102

100

BYPASS MODE

AFTER CALIBRATION

SHORTED INPUTS

BYPASS MODE

SHORTED INPUTS

0

1

2

3

4

-3.0 -1.0 1.0 3.0 5.0 7.0 9.0 11.0 13.0

OFFSET (nV)

V_REFP- V_REFN(V)

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Typical Operating Characteristics (continued)

(V

= 3.6V, V

= 0V, V

= 2.0V, V

= 2.5V, V

= 0V; f

= 1000sps, External Clock = 8.192MHz; Continuous

AVDD

AVSS

DVDD

REFP

REFN

DATA

conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,

T

= T

to T , unless otherwise noted. Typical values are at T = +25°C.)

MAX A

A

MIN

NEGATIVE FULL-SCALE

GAIN ERROR HISTOGRAM OF 200 PARTS

POSITIVE FULL SCALE

GAIN ERROR HISTOGRAM OF 200 PARTS

toc17A

toc17B

50

45

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

BYPASS MODE

AFTER CALIBRATION

BYPASS MODE

AFTER CALIBRATION

0

-1.4

-1

-0.6

-0.2

0.2

0.6

1

1.4

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

GAIN ERROR (ppm)

V_REFCURRENT vs. TEMPERATURE

toc18A

toc18B

30

25

20

15

10

5

120

119

118

117

116

115

114

113

112

111

110

CALIBRATED AT 25°C

SLEEP

MODE

STANDBY

MODE

0

-50

0

50

100

150

-50

0

50

TEMPERATURE (°C)

100

150

TEMPERATURE (°C)

Maxim Integrated

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Pin Conﬁguration

TOP VIEW

+

1

24

23

22

21

20

19

18

17

16

15

14

DIN

DOUT

DGND

SYNC

RSTB

GPIO3

GPIO2

GPIO1

AVDD

AVSS

AINN

SCLK

CSB

2

3

DVDD

CAPREG

DGND

CLK

4

MAX11270

5

6

7

RDYB

AVSS

CAPP

CAPN

REFP

8

9

10

11

12

AINP

13 REFN

TSSOP

Pin Description

NAME

FUNCTION

Serial Data Input. Data is clocked into DIN on the rising edge of SCLK. DIN conﬁgures the internal

register writes or a command operation.

1

DIN

Serial Data Output or Real-Time Modulator MB0 Output. DOUT outputs 32 or 24 bits of ﬁltered data in

normal data mode. DOUT transitions on the falling edge of SCLK.

2

DOUT

DGND

3, 20

Digital Ground

SYNC Reset. SYNC resets both the digital ﬁlter and the modulator.

Connect SYNC from multiple MAX11270s in parallel to synchronize more than one ADC to an external

trigger. This is a digital input pin and is not internally pulled down. For normal operation drive or pull this

pin low.

4

SYNC

The RSTB function is a complete reset of all digital functions resulting in a power-on reset default state.

This is a digital input pin and is not internally pulled up. For normal operation drive or pull this pin high.

5

6

RSTB

General-Purpose I/O 3 or Modulator Sync Output. GPIO3 is conﬁgurable as a digital input or output.

GPIO pins have weak pull ups and do not require external bias if unused. For lowest power operation

do not connect or drive high with GPIO conﬁgured as input (default).

GPIO3

General-Purpose I/O 2. Register controllable via SPI. GPIO pins have weak pull ups and do not require

external bias if unused. For lowest power operation do not connect or drive high with GPIO conﬁgured

as input (default).

7

8

GPIO2

GPIO1

General-Purpose I/O 1. Register controllable via SPI. GPIO pins have weak pull ups and do not require

external bias if unused. For lowest power operation do not connect or drive high with GPIO conﬁgured

as input (default).

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Pin Description (continued)

NAME

FUNCTION

Analog Positive Supply Voltage. In single-supply mode, V

= 2.7V to 3.6V with V

AVSS

= 0V. In

= 0V in

AVDD

dual-supply mode, AVDD and AVSS can range from ±1.35V to ±1.8V

9

AVDD

Analog Negative Supply Voltage. Connect AVSS to the most negative supply. Connect V

single-supply mode. Connect AVSS between -1.8V and 0V for dual-supply mode.

AVSS

10, 17

11

AVSS

AINN

AINP

REFN

REFP

Negative Analog Input. The analog inputs can measure both unipolar and bipolar ranges, depending on

the AVDD and AVSS voltages.

Positive Analog Input. The analog inputs can measure both unipolar and bipolar ranges, depending on

the AVDD and AVSS voltages.

12

Negative Reference Input. REFN must be less than REFP. REFN voltage must be between AVDD and

AVSS.

13

Positive Reference Input. REFP must be greater than REFN. REFP voltage must be between AVDD

and AVSS.

14

15

16

CAPN

CAPP

PGA Filter Negative Capacitor Output. Connect a 10nF COG capacitor between CAPN and CAPP.

PGA Filter Positive Capacitor Output. Connect a 10nF COG capacitor between CAPN and CAPP.

Active-Low Data Ready Output or Internal Clock Output. RDYB asserts low when the data is ready.

When in continuous conversion mode, a SYNC or POR event inhibits output of the ﬁrst 4 data values to

allow for ﬁlter settling when the SINC ﬁlter is selected. A SYNC or POR event inhibits output of the ﬁrst

63 data values to allow for ﬁlter settling when using the FIR ﬁlters.

18

19

RDYB

CLK

External Clock Input. For external clock mode, set the EXTCLK bit = 1 and provide a digital clock signal

at CLK. The MAX11270 is speciﬁed with a clock frequency of 8.192MHz. Other clock frequencies may

be used, but the data rate and digital ﬁlter notch frequencies will scale accordingly. This is a digital input

pin and is not internally pulled down. When external clock is disabled drive this pin low.

Internal 1.8V Subregulator Reservoir Output. Bypass with a 10µF capacitor to DGND. Minimum

capacitor value required for stability is 220nF.

21

22

CAPREG

DVDD

Digital Supply Voltage. Supply DVDD with 2.0V to 3.6V, with respect to DGND.

Active-Low Chip-Select Input. Set CSB low to access the serial interface. CSB is used for frame

synchronization for communications when SCLK is continuous. Drive CSB high to reset the SPI

interface.

23

24

CSB

Serial Clock Input. Apply an external serial clock at SCLK to issue commands or access data from the

MAX11270.

SCLK

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Functional Diagram

REFP

REFN

DVDD

AVDD

GPIO1

GPIO2

GPIO3

1.8V

REGULATOR

CAPREG

RSTB

MAX11270

SYNC

RDYB

BUFFER

AIN+

DIN

CAPP

SCLK

DOUT

CSB

SIGMA DELTA

MODULATOR

SERIAL

INTERFACE

PGA

SINC FILTER

CAPN

AIN-

BUFFER

CLOCK

GENERATOR

CLK

TIMING

AVSS

DGND

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Programmable Gain Ampliﬁer (PGA)

Detailed Description

The integrated PGA provides gain settings from 1x to

128x. See the Control 2 Register (Read/Write) section for

enabling and programming the PGA. The PGA configura-

tion is shown in Figure 1. Direct connection is available

to bypass the PGA enabling direct connection to the

modulator. The PGA’s absolute input voltage range is

The MAX11270 is an ultra-low power ADC that resolves a

very high dynamic range. This ADC is capable of resolv-

ing microvolt-level changes to the analog input, making it

a good fit for seismic, instrumentation, and ATE applica-

tions. The user can select between programmable gain

amplifier, unity-gain buffer or connect directly to the delta-

sigma sampling network.

CMIRNG and the PGA output voltage range is VOUT

RNG

as specified in the Electrical Characteristics. The PGA

output common-mode voltage is the same as the input

common-mode voltage.

The MAX11270 includes a high-accuracy internal oscil-

lator that requires no external components. Data is

output through a serial interface at sample rates up to

12.8ksps with no data latency and 64ksps continuous.

The MAX11270 has a fifth-order digital SINC filter.

Note that linearity and performance degrade when the

usable input common-mode voltage of the PGA is

exceeded. The usable input common-mode range and

output common-mode range are shown in Figure 2. The

following equations describe the relationship between the

analog inputs and PGA output.

The MAX11270 is highly configurable via the internal reg-

isters, which can be accessed via the SPI interface. This

includes PGA gain selection, offset and gain calibration,

and a scalable sample rate to optimize performance.

System Clock

AINP = Positive input to the PGA

AINN = Negative input to the PGA

CAPP = Positive output of PGA

CAPN = Negative output of PGA

The MAX11270 incorporates a highly stable internal oscil-

lator that provides the system clock. The system clock is

trimmed to 8.192MHz and is divided further down to run

the digital and analog timing.

Voltage Reference Inputs

V

= Input common mode

CM

The MAX11270 provide differential inputs REFP and

REFN for an external reference voltage. Connect the

external reference directly across the REFP and REFN

pins to obtain the differential reference voltage. The

GAIN = PGA gain

V

= ADC reference input voltage

REF

= V

- V

AINN

IN

AINP

V

REFP

should always be greater than V

and the

Note: Input voltage range is limited by the reference volt-

REFN

common-mode voltage range is between 1V and V_AVDD

- 1V.

age as described by V ≤ ±V

/GAIN

IN

REF

Analog Inputs

V

+ V

AINN

2

(

)

AINP

V

=

CM

The MAX11270 measures a pair of differential analog

inputs (AINP, AINN) in buffered, direct connect or PGA.

See the Control 2 Register (Read/Write) section for pro-

gramming and enabling the PGA, buffers, or direct con-

nect. The default configuration is direct connect, with both

PGA and input buffers powered down.

V

= V

+ GAIN× V

− V

CM

(

)

CAPP

CM

AINP

− V

AINN

V

− GAIN× V

)

CAPN

CM

Input Buffers

The input buffer isolates the inputs from the capacitive

load presented by the modulator, allowing for high source-

impedance analog transducers.

Bypass/Direct Connect

The MAX11270 offers the option to bypass both buffers

and PGA and route the analog inputs directly to the modu-

lator. This option lowers the power of the part since both

buffers and PGA are shut off.

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Input Voltage Range

The ADC input range is programmable for bipolar (-V

REF

to +V

) or unipolar (0 to V

) ranges. The U/B bit in

REF

the CTRL1 register configures the MAX11270 for unipolar

or bipolar transfer functions. See Figure 2.

AINP

R3

CAPP

A1

Noise Performance vs. Data Rate

The MAX11270 offers software-selectable output data

rates in order to optimize data rate and noise. The RATE

bits in the command byte determines the ADC’s output

data rate. The MAX11270 offers zero latency in single-

cycle conversion mode. Set SCYCLE = 0 in the CTRL1

register to run in continuous conversion mode and

SCYCLE = 1 for single-cycle conversion mode.

R1

C

CAPP/N

R2

(COG capacitor)

R1

Single-cycle conversion mode gives an output result with

no data latency for up to 12.8ksps. In continuous conver-

sion mode, the maximum output data rate is 64ksps. In

continuous conversion mode, the output data requires

four additional 24-bit cycles to settle from an input step.

For optimal SNR vs. power, it is recommended to use

different PGA modes. For gain settings 8 and below, use

low-power PGA mode, for gain setting above 8, use low-

noise PGA mode.

R3

CAPN

A2

AINN

Figure 1. PGA Structure

ANALOG INPUTS

PGA OUTPUT

V

AVDD

V

– 0.3V

AVDD

OUTPUT VOLTAGE RANGE = GAIN

x INPUT VOLTAGE RANGE

V

– 1.3V

AVDD

COMMON-MODE

INPUT VOLTAGE

≤ V

REF

INPUT VOLTAGE RANGE

V

+ 0.3V

AVSS

V

AVSS

Figure 2. Usable Input and Output Common-Mode Range

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Table 1. Continuous Mode SNR (dB) vs Data Rate and PGA Gain with Sinc Filter^*

PGA ENABLED: GAIN SETTING

16

DATA

RATE

(sps)

1

2

4

8

32

64

128

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

1.9

3.9

129.8

129.4

129.3

125.5

123.4

119.9

117.9

114.1

112.0

108.1

106.1

102.2

100.2

96.2

130.2

129.9

129.8

129.5

125.6

123.6

119.9

118.0

114.2

112.1

108.2

106.2

102.3

100.3

96.3

128.8

128.6

128.4

128.2

124.4

122.3

118.7

116.7

113.0

110.9

106.9

104.9

101.0

99.0

128.7

128.5

128.3

128.2

124.2

122.1

118.6

116.7

112.9

110.8

106.9

104.9

101.0

99.0

130.0

130.1

129.9

129.5

125.7

123.6

120.0

118.0

114.2

112.2

108.3

106.2

102.4

100.3

96.4

129.5

129.9

129.6

129.5

125.5

123.4

120.0

118.0

114.2

112.2

108.3

106.2

102.4

100.4

96.4

129.8

130.0

129.7

129.6

125.7

123.5

119.9

117.9

114.1

112.0

108.2

106.1

102.3

100.3

96.3

129.8

129.7

129.6

129.5

125.5

123.5

119.9

117.9

114.1

112.0

108.2

106.1

102.3

100.3

96.4

130.0

129.9

129.5

129.2

125.2

123.2

119.7

117.7

114.0

111.9

108.1

106.0

102.2

100.2

96.3

130.0

129.7

129.5

129.0

125.2

123.2

119.7

117.8

114.0

111.9

108.1

106.0

102.2

100.2

96.3

129.7

129.4

129.5

128.7

124.9

122.8

119.4

117.3

113.6

111.5

107.8

105.6

102.0

100.0

96.2

129.7

129.4

129.3

127.8

124.7

122.7

119.3

117.1

113.5

111.2

107.5

105.3

101.7

99.9

130.0

129.6

128.6

127.9

123.9

121.6

118.4

116.1

112.6

110.3

106.8

104.5

101.2

99.4

129.5

128.8

127.7

126.5

123.5

121.2

117.8

115.4

112.0

109.5

106.1

103.8

100.6

99.0

128.7

127.9

126.6

124.8

121.3

118.8

115.7

113.1

110.0

107.3

104.2

101.8

99.0

127.6

126.9

125.4

123.4

120.2

117.5

114.3

111.6

108.4

105.7

102.6

100.2

97.6

126.1

124.3

122.3

119.7

116.6

113.8

110.8

108.0

105.0

102.2

99.2

124.0

122.6

120.2

117.0

114.7

111.9

108.8

105.9

102.9

100.0

97.1

7.8

15.6

31.2

62.5

125

250

500

1000

2000

4000

8000

16000

32000

64000

96.7

94.6

94.4

92.4

97.5

96.3

93.2

91.3

95.1

96.0

95.7

95.3

94.1

93.0

90.2

88.4

94.2

93.0

92.9

94.3

94.4

94.2

94.1

93.9

93.6

93.2

91.9

90.8

87.9

86.2

*V = 0V. V

= 3.6V, V

= 0V, V

= 3.6V, T = +25°C, external clock. Data taken with PGA output 150mV from AVDD

IN

AVDD

AVSS

REF A

and AVSS. This table is not tested and is based on characterization data.

Maxim Integrated

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Table 2. Continuous Mode Input-Referred Noise (µV

with Sinc Filter^*

) vs. Data Rate and PGA Gain

RMS

PGA ENABLED: GAIN SETTING

DATA

RATE

(sps)

1

2

4

8

16

32

64

128

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

1.9

3.9

0.825

0.824

0.866

0.868

1.350

1.717

2.580

3.238

5.031

6.385

9.980

0.805

0.833

0.844

0.865

1.368

1.717

2.611

3.283

5.084

6.439

10.059

0.837

0.857

0.875

0.893

1.391

1.766

2.658

3.346

5.177

6.586

10.352

13.146

20.455

25.751

40.563

51.554

0.838

0.865

0.878

1.412

1.800

2.682

3.370

5.211

0.451

0.446

0.452

0.476

0.741

0.938

1.418

1.786

2.758

3.500

5.454

6.956

10.814

13.670

21.501

27.340

0.475

0.455

0.471

0.476

0.750

0.957

1.427

1.790

2.764

3.501

5.484

6.932

10.830

13.602

21.502

27.206

0.220

0.215

0.221

0.224

0.352

0.455

0.684

0.860

1.333

1.692

2.633

3.339

5.198

6.556

10.328

13.142

0.217

0.222

0.223

0.225

0.357

0.453

0.686

0.865

1.332

1.693

2.637

3.353

5.204

6.568

10.287

13.149

0.109

0.111

0.116

0.120

0.190

0.239

0.355

0.447

0.686

0.878

1.360

1.723

2.674

3.364

5.260

6.729

0.110

0.113

0.117

0.123

0.189

0.238

0.355

0.449

0.690

0.886

1.370

1.743

2.695

3.373

5.292

6.740

0.058

0.060

0.065

0.101

0.129

0.191

0.243

0.370

0.476

0.728

0.931

1.421

1.773

2.758

3.519

0.057

0.060

0.061

0.072

0.103

0.131

0.194

0.249

0.378

0.490

0.747

0.963

1.456

1.808

2.807

3.590

0.029

0.030

0.034

0.037

0.058

0.076

0.111

0.144

0.214

0.281

0.420

0.545

0.799

0.980

1.510

1.920

0.031

0.034

0.038

0.044

0.062

0.080

0.119

0.156

0.232

0.309

0.456

0.594

0.857

1.036

1.579

2.023

0.017

0.018

0.021

0.026

0.039

0.052

0.075

0.101

0.145

0.197

0.282

0.372

0.512

0.607

0.905

1.165

0.019

0.021

0.024

0.031

0.044

0.060

0.087

0.120

0.172

0.236

0.335

0.445

0.599

0.698

1.017

1.313

0.011

0.013

0.016

0.022

0.032

0.043

0.061

0.085

0.120

0.166

0.232

0.311

0.403

0.465

0.659

0.855

0.020

0.016

0.021

0.030

0.039

0.054

0.077

0.108

0.153

0.212

0.295

0.395

0.510

0.576

0.811

1.040

7.8

15.6

31.2

62.5

125

250

500

1000

2000

4000

8000

16000

32000

64000

6.600

10.315

13.073

20.371

25.728

40.547

51.724

12.674 12.749

19.739 19.953

24.895 25.179

39.335 39.649

49.899 50.430

*V = 0V. V

IN

ization data.

= 3.6V, V

= 0V, V

= 3.6V, T = +25°C, external clock. This table is not tested and is based on character-

AVDD

AVSS

REF A

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Table 3. Single-Cycle Mode SNR (dB) vs. Data Rate and PGA Gain with Sinc Filter*

PGA ENABLED: GAIN SETTING

DATA

RATE

(sps)

1

2

4

8

16

32

64

128

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

50

62.5

100

123.9

124.0

120.1

120.2

118.2

118.0

114.2

112.0

108.1

107.9

106.0

105.8

101.9

101.4

123.6

123.4

119.8

119.9

117.6

113.8

113.7

111.7

111.6

107.7

107.5

105.6

105.4

101.5

100.9

119.0

115.3

115.2

113.0

109.1

107.0

103.1

103.0

101.0

100.8

96.9

119.0

115.2

115.1

113.0

109.1

107.1

106.9

103.1

102.9

101.0

100.8

96.9

121.9

121.7

118.1

116.0

115.9

112.1

112.0

109.9

106.0

105.9

103.9

103.7

99.8

121.9

121.7

118.1

116.0

115.9

112.0

110.0

109.8

106.0

105.8

103.9

103.7

99.8

123.3

123.1

119.5

119.4

117.3

113.5

113.4

111.3

111.2

107.4

107.2

105.2

105.0

101.2

100.6

123.3

123.1

119.6

119.3

117.3

113.5

113.4

111.3

111.2

107.3

107.2

105.2

105.0

101.2

100.5

123.2

123.0

119.3

117.3

117.1

113.4

113.2

111.2

111.1

107.3

107.1

105.1

104.8

101.0

100.3

123.2

123.0

119.2

117.2

117.1

113.3

113.2

111.1

110.9

107.1

106.9

105.0

104.7

100.9

100.1

123.0

122.8

119.2

119.0

116.9

116.8

113.1

112.9

110.8

110.6

106.8

106.5

104.6

104.2

100.5

99.5

122.7

122.3

118.9

118.8

116.7

116.4

112.8

112.5

110.5

110.1

106.5

106.1

104.2

103.7

100.1

98.9

122.0

121.5

118.0

115.8

115.4

112.2

111.8

109.6

109.1

105.6

105.0

103.2

102.4

99.0

121.1

120.5

117.5

117.1

115.0

114.5

111.5

110.9

108.7

108.0

104.8

103.9

102.2

101.3

98.0

119.1

118.7

115.7

115.2

112.9

112.3

109.6

108.8

106.6

105.8

102.7

101.5

99.9

117.6

116.7

114.4

113.5

111.4

110.6

108.0

107.3

105.0

103.9

101.1

99.8

114.1

113.1

111.0

110.1

107.9

107.2

104.8

103.7

101.4

100.3

97.5

112.1

111.2

108.9

108.1

105.7

104.9

102.6

101.6

99.2

125

200

250

400

500

800

1000

1600

2000

3200

4000

6400

12800

98.2

95.3

96.2

94.0

98.2

94.6

92.4

98.8

97.0

93.2

91.1

95.7

93.9

90.2

88.2

96.4

96.3

99.2

97.5

96.4

93.7

91.9

88.1

86.0

*V = 0V. V

= 3.6V, V

= 0V, V

= 3.6V, T = +25°C, external clock. Data taken with PGA output 150mV from AVDD

IN

AVDD

AVSS

REF A

and AVSS. This table is not tested and is based on characterization data.

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24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Table 4. Single-Cycle Mode Input-Referred Noise (µVRMS) vs. Data Rate and PGA Gain

with Sinc Filter*

PGA ENABLED: GAIN SETTING

DATA

RATE

(sps)

1

2

4

8

16

32

64

128

LN

1.620 1.614 1.655

1.604 1.652 1.648

2.502 2.517 2.524

2.479 2.493 2.566

3.136 3.232 3.298

3.204 3.248 3.297

4.961 5.031 5.144

4.976 5.076 5.153

6.371 6.380 6.556

6.381 6.480 6.597

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

LN

LP

50

62.5

100

1.643

1.633

2.571

2.580

3.234

3.301

5.151

5.095

6.533

6.628

0.835

0.850

1.298

1.296

1.655

1.669

2.580

2.603

3.302

3.337

0.833 0.423 0.420 0.219 0.219 0.115 0.120 0.067 0.074 0.046 0.055 0.038 0.048

0.847 0.432 0.433 0.225 0.224 0.118 0.125 0.071 0.079 0.049 0.061 0.043 0.054

1.285 0.653 0.651 0.344 0.346 0.179 0.186 0.105 0.112 0.068 0.080 0.055 0.070

1.293 0.666 0.670 0.343 0.347 0.183 0.187 0.105 0.117 0.073 0.088 0.061 0.077

1.644 0.842 0.834 0.432 0.435 0.232 0.240 0.136 0.150 0.094 0.112 0.078 0.101

1.649 0.847 0.844 0.439 0.441 0.237 0.248 0.142 0.158 0.101 0.122 0.085 0.111

2.601 1.311 1.310 0.675 0.684 0.361 0.374 0.206 0.224 0.138 0.165 0.112 0.144

2.612 1.326 1.331 0.688 0.690 0.368 0.388 0.216 0.238 0.151 0.179 0.127 0.162

3.298 1.682 1.691 0.869 0.881 0.469 0.487 0.277 0.307 0.194 0.234 0.165 0.212

3.344 1.710 1.710 0.883 0.899 0.484 0.509 0.294 0.333 0.214 0.264 0.187 0.240

5.227 2.648 2.658 1.367 1.390 0.743 0.771 0.440 0.484 0.306 0.368 0.260 0.333

5.299 2.699 2.708 1.403 1.434 0.772 0.809 0.473 0.534 0.350 0.425 0.303 0.389

6.649 3.391 3.406 1.764 1.786 0.963 1.006 0.583 0.649 0.419 0.511 0.363 0.466

6.795 3.464 3.474 1.815 1.843 1.010 1.071 0.634 0.723 0.478 0.591 0.425 0.544

125

200

250

400

500

800

1000

1600

2000

3200

4000

6400

12800

9.983 10.128 10.317 10.336 5.197

10.201 10.312 10.479 10.516 5.283

12.812 12.905 13.183 13.192 6.664

12.996 13.159 13.416 13.415 6.764

20.411 20.637 21.067 21.080 10.571 10.598 5.395 5.426 2.816 2.842 1.546 1.617 0.940 1.056 0.686 0.837 0.600 0.758

21.755 21.988 22.412 22.461 11.320 11.330 5.806 5.855 3.051 3.129 1.724 1.847 1.114 1.277 0.860 1.056 0.769 0.975

*V = 0V. V

= 3.6V, V

= 0V, V

= 3.6V, T = +25°C, external clock. Data taken with PGA output 150mV from AVDD

IN

AVDD

AVSS

REF A

and AVSS. This table is not tested and is based on characterization data.

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MAX11270

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ADC with Integrated PGA

Sleep Mode: The sleep mode can be set by writing 01 to

the PD[1:0] bits. In this state the internal subregulator that

powers the digital core is powered off. This is the lowest

power state for the device.

Power-On Reset

The MAX11270 contains power-on reset (POR) supply

monitoring circuitry on both the digital supply (DVDD) and

the positive analog supply (AVDD). The POR circuitry

ensures proper device default conditions after either a

digital or analog power-sequencing event.

Standby Mode (10): The standby mode is set by writ-

ing 10 to the PD[1:0] bits. In this mode the device is not

active, but the internal subregulator is still powered on.

This allows conversions to start immediately after receiv-

ing a start conversion command.

The digital POR trigger threshold is typically 1.2V with

respect to V

and has 100mV of hysteresis. The ana-

DGND

log POR trigger threshold is typically 1.25V with respect to

and has 100mV of hysteresis. Both POR circuits

V

AVSS

have lowpass filters that prevent high-frequency supply

glitches from triggering the POR.

Power-Down Modes

The MAX11270 can be powered down via the IMPD bit

in the command byte. The PD[1:0] bits of the CTRL1

register are used to select the power-down state. The SPI

remains fully functional in all power-down states.

Table 5. MAX11270 Command Behavior from Pin (RSTB, SYNC) and SPI (RESET, SYNC_SPI)

STATE

BEFORE

COMMAND

STATE

AFTER

COMMAND

ISSUED

COMMAND-

ISSUED VIA

TRANSITION

TIME (MAX)

COMMAND INTERPRETATION AND

RESULTING CHIP STATE

STBY

SLEEP

STBY

SLEEP

STBY

—

5ms

—

Chip POR

RESET

SPI or PIN

SPI, PIN

Calibration

Conversion

STBY

Calibration stops, chip POR

Conversion stops, chip POR

Chip changes from STBY to SLEEP

Chip remains in SLEEP

—

IMPD

CTRL1:PD=’01’

SLEEP Mode

SLEEP

—

SPI

Calibration

Conversion

STBY

—

Calibrations stop

—

Conversion stop

—

Chip remains in standby

IMPD

CTRL1:PD=’10’

STBY Mode

SLEEP

—

Chip changes from SLEEP to standby

Calibrations stop, chip changes to standby

Conversions stop, chip changes to standby

SPI

Calibration

Conversion

—

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Table 5. MAX11270 Command Behavior from Pin (RSTB, SYNC) and SPI (RESET, SYNC_SPI)

(continued)

STATE

BEFORE

COMMAND

STATE

AFTER

COMMAND

ISSUED

COMMAND-

ISSUED VIA

TRANSITION

TIME (MAX)

COMMAND INTERPRETATION AND

RESULTING CHIP STATE

STBY

—

SYNC ignored, chip remains in STBY mode

SYNC ignored

Calibration

Conversion

Calibration

Conversion

Pulse SYNC mode, conversions restart

Continuous SYNC mode, 1^stSYNC rising

edge set clock counter, subsequent rising

edges are compared against clock counter.

If count is off by more than ±1 clock counts

then restart conversions otherwise do nothing

and continue conversions in progress. If a

SYNC rising edge occurs before the ﬁrst

RDYB asserts after conversions are started

then SYNC is ignored. Once the ﬁrst RDYB

asserts, all subsequent SYNC rising edges

are evaluated.

SYNC

SPI, PIN

Conversion

—

STBY

SLEEP

STBY

SLEEP

—

Chip remains in standby

Chip remains in SLEEP

CMD Register

Write

SPI

Calibration

Conversion

STBY

Calibration stops, chip goes to STBY mode

Conversion stops, chip goes to STBY mode

Exit standby, conversion starts

STBY

Conversion

Convert

Command

Write

SLEEP (SPI)

Calibration

Conversion

Exit SLEEP mode, conversion starts

Calibration stops then a new conversion starts

Conversion stops and a new conversion starts

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MAX11270

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ADC with Integrated PGA

is clocked into the device from DIN on the rising edge of

SCLK. Data is clocked out of DOUT on the falling edge of

SCLK. When CSB is high, SCLK and DIN are ignored and

DOUT is high impedance allowing DOUT to be shared

with other devices.

Digital Filters

The digital filter is a mode-configurable digital filter and

decimator that processes a one-bit data stream from the

fourth order delta-sigma modulator and implements a fifth

order SINC function with an averaging function to produce

a 24-bit wide data stream.

SCLK (Serial Clock)

The serial clock (SCLK) is used to synchronize data com-

munication between the host device and the MAX11270.

Data is shifted in on the rising edge of SCLK and data is

shifted out on the falling edge of SCLK. SCLK remains

low when not active.

SINC Filter

The SINC filter allows MAX11270 to achieve very high

SNR. One feature of the fifth order SINC filter is a band-

width that is about twenty percent of the data rate. The

following example shows 3dB BW of about 3kHz for

16ksps data rate.

DIN (Serial Data Input)

Data present on DIN is clocked into internal registers on

the rising edge of SCLK.

Serial Interface

The MAX11270 interface is fully compatible with SPI,

QSPI™, and MICROWIRE®-standard serial interfaces.

The SPI interface provides access to on-chip registers

that are 8 bits to 24 bits wide.

Chip Select (CSB)

CSB is an active-low chip-select input to communicate

with the MAX11270. CSB transitioning from low to high

is used to reset the SPI interface. When CSB is low, data

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National Semiconductor Corp.

Figure 3a. SINC Magnitude Response

Figure 3b. SINC Mag Response Zoomed-In

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DOUT (Serial Data Output)

SPI Incomplete Write Command Termination

The DOUT pin is actively driven when CSB is low and

high impedance when CSB is high. Data are shifted out

on DOUT on the falling edge of SCLK.

In case of register writes, the register values get updated

every 8th clock cycle with a byte of data starting from the

MSB. A minimum of 16 SCLKs are needed to write the first

byte of data in a multibyte register or for an 8-bit register.

For example, a 24-bit register write requires 8 SCLKs for

register access byte and 24 SCLKs (data bits to be writ-

ten). If only 15 SCLKs were issued out of 32 expected,

the register value will not be updated. At least 16 SCLKs

are required to update the MSB byte. For example, when

the user issues a write command for a 24-bit register write

and terminates after 16 SCLKs, only the MSB byte, bits

23 to 16 of the register are updated. Bits 15 to 0 retain the

old value of the register.

Data Ready (RDYB)

The RDYB output displays the conversion status. RDYB

is forced low when a conversion result is ready for read-

out and remains low until the user reads the conversion

result. RDYB returns high after SCLK is pulled high, fol-

lowing a complete read of the data register. RDYB also

resets high for 4 master clock cycles prior to DATA regis-

ter update (see Figure 4).

When the modulator is in one of the continuous operat-

ing modes and the part has either experienced a RESET,

SYNC, or POR event, then the RDYB pin will remain

high until the selected filter is settled. If the SINC filter is

selected then RDYB remains high for five t

times and

CNV

afterwards data appears at each t

.

CNV

The conversion status can also be determined by reading

the MSTAT bit in the STAT1 register.

CONVERT COMMANDS

CSB/SCLK/DIN

t

CNV

t

CNV

DATA NOT RETRIEVED

SCYCLE=’1',

CONTSC=’0',

RDYB

t

CNV

DATA

RETRIEVED

SCYCLE=’1',

CONTSC=’1',

RDYB

5 t

t

CNV

SCYCLE=’0',

CONTSC=’x',

Figure 4. DATA Ready Timing for All Conversion Modes

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SPI Incomplete Read Command Termination

SPI Timing Characteristics

The SPI interface stays in read mode for as long as CSB

stays low independent of the number of SCLKs issued.

The CSB pin must be toggled high to remove the device

from the bus and reset the internal SPI controller. Any

activity on the DIN pin is ignored while in the register read

mode. The read operation is terminated if the CSB pin

is toggled high before the maximum number of SCLK is

issued.

The SPI timing diagrams illustrating command byte and

register access operations are shown in Figure 4 to

Figure 7. The MAX11270 timing allows for the input data

to be changed by the user at both rising and falling edges

of SCLK. The data read out by the device on SCLK falling

edges can be sampled by the user on subsequent rising

or falling edges.

When reading from DATA registers, the behavior of RDYB

will depend on how many bits are read. If at least 23 bits

are read, the read operation is complete and RDYB resets

to high. If the user reads less than 23 bits, internally the

logic considers the read incomplete, and RDYB stays

low. The user can initiate a new read within the same

conversion cycle and the new 24-bit read must complete

before the next DATA register update.

SPI 8b REGISTER WRITE

RDYB

‘X’

t

CSW

t

CSS0

t

CSH1

CSB

SCLK

DIN

t

CL

t

CH

t

CSS1

t

CP

1

8

16

t

DH

DS

‘X’

‘1’ ‘1’ ‘X’ RS3 RS2 RS1 RS0 ‘0’ D7 D6 D5 D4 D3 D2 D1 D0

‘X’

t

DOD

DOE

HIGH-Z

DOUT

‘X’

Figure 5. SPI Register Write Timing Diagram

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SPI 8b REGISTER READ

RDY

‘X’

t_CSW

t_CSS0

t_CSH1

CS

SCLK

DIN

t_CH

t_CL

t_CP

t_CSS1

1

8

16

8b data

‘X’

t_DS

t_DH

‘X’

‘1’ ‘1’ RS4 RS3 RS2 RS1 RS0 ‘1’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’

t_DOTt_DOH

D7 D6 D5 D4 D3 D2 D1 D0

t_DOD

HIGH-Z

t_DOE

HIGH-Z

DOUT

‘X’

Figure 6. SPI Register Read Timing Diagram

RDY

t

R1

t

CSW

t

CSS0

t

CSH1

CS

SCLK

DIN

t

CSS1

CH

CL

CP

23

31

39

16b data

24b data

32b data

1

8

9

t

DH

DS

‘x’

‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’ ‘1’

t

DOD

DOE

DOT

DOH

HIGH-Z

DOUT

‘x’

MSB

LSB

Figure 7. SPI Data Readout Timing Diagram

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SPI COMMAND BYTE

RDY

CS

‘X’

t

CSW

t

CSS0

t

CSH1

t

CSS1

CH

CL

CP

SCLK

DIN

1

8

t

DS

DH

‘X’

‘1’

‘0’

CAL IMPD RT3 RT2 RT1 RT0

t

DOD

t

DOE

HIGH-Z

DOUT

‘X’

Figure 8. SPI Command Byte Timing Diagram

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MAX11270

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Modes and Registers

The MAX11270 interface operates in two modes, conversion mode or register access mode, which is selected by the

command byte. Every SPI transaction to the MAX11270 starts with a command byte. The command byte begins with a

START bit (B7), which must be set to 1. The next bit is the MODE bit (B6), which selects between conversion mode or

register access mode. Based on the mode selection the remaining bits in the command byte get decoded accordingly.

If the command byte is for a register read/write request, hold CSB low for the entire read or write operation and pull CSB

high at the end of the command. For example, if the command is to read a 24-bit data register; hold CSB low for 32 SCLK

cycles (8 cycles of command plus 24 cycles of data). CSB transitions must not occur near the rising edge of SCLK and

must conform to the setup and hold timing detailed in the timing section.

Pulling CSB from low to high ends the current SPI transaction. If CSB is pulled high in the middle of a register write com-

mand, the registers will retain any partially written data. This does not cause a change in state of any internal register

that was being accessed for read or write

Conversion Mode (MODE = 0)

Table 6. Command Byte for Conversion Modes (MODE = 0)

BIT

B7 (MSB)

B6

B5

B4

B3

B2

B1

B0

BIT NAME

START = 1

MODE = 0

CAL

IMPD

RATE3

RATE2

RATE1

RATE0

Set the MODE bit to 0 to: start a conversion with a rate defined by RATE[3:0], immediately power down the part or per-

form a calibration.

The CAL bit (B5) determines if a calibration is to be performed. Set CAL = 1 to perform a calibration, for all other opera-

tions set CAL = 0. The calibration is done based on the setting of the calibration bits CTRL 5. Also see discussion on

calibration in the following sections.

The IMPD bit (B4) controls the software power-down. Set IMPD = 1 to power down the MAX11270 and enter sleep mode

or standby mode, based on the setting of the PD Bits in CTRL1, once the command byte is complete. The power-down

status does not change until another command byte is received that is interpreted as a conversion byte (MODE = 0, IMPD

= 0). Set IMPD = 0 for normal operation.

The data rate bits RATE[3:0] determine the conversion speed. The speed table is shown later in Table 7.

Register Access Mode (MODE = 1)

Table 7. Command Byte for Register Access Mode (MODE = 1)

BIT

B7 (MSB)

B6

B5

B4

B3

B2

B1

B0

BIT NAME

START =1

MODE = 1

RS4

RS3

RS2

RS1

RS0

R/W

MODE 1 or Register Access Mode is used for reading from and writing to the registers of the MAX11270. Set the MODE

bit (B6) = 1 to configure the command byte for Register Access Modes.

The bits RS[4:0] determine the register that is addressed as shown in Table 6.

The R/W bit enables either a read or a write of the register. Set R/W = 0 to write to the selected register and R/W = 1 to

read from the selected register.

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Register Map

Register Address Map

There are 14 registers that can be accessed in the MAX11270. The majority of registers can be both written to and read

from, but the STAT and DATA registers are read only. The RAM and SYNC are not physical registers, but addresses to

enable special operating modes.

Table 8. Register Address Map

ADDRESS

REGISTER

NAME

R/W

SELECT

RS[3:0]

B7

B6

B5

B4

B3

B2

B1

B0

INRESET

RATE3

EXTCK

DGAIN1

—

ERROR

RATE2

SYNCMODE

DGAIN0

—

PDSTAT1

SYSGOR

U/~B

PDSTAT0

DOR

RDERR

MSTAT

SCYCLE

PGAG1

—

AOR

RDY

STAT

R

0x0

RATE1

PD1

RATE0

PD0

CTRL1

CTRL2

R/W

R

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

FORMAT

PGAG2

—

CONTSC

PGAG0

—

BUFEN

LPMODE

PGAEN

DATA32

—

CTRL3

ENMSYNC MODBITS

CTRL4

—

DIR3

DIR2

—

DIR1

—

DIO3

DIO2

DIO1

CTRL5

CAL1

CAL0

NOSYSG

NOSYSO

NOSCG

NOSCO

DATA

D[23:0]

SOC_SPI

SGC_SPI

SCOC_SPI

SCGC_SPI

R/W

B[23:0]

Address space only, not a physical register. Please contact factory for instructions on using internal RAM

function.

RAM

R/W

0xC

0xD

Address space only, not a physical register. Please contact factory for instructions on using internal RAM

function.

SYNC_SPI

W

SOC_ADC

SGC_ADC

SCOC_ADC

SCGC_ADC

R

0x15

0x16

0x17

0x18

B[23:0]

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Status Register (Read Only)

The 16-bit status register is a read-only register that indicates the following: power-down status, if the modulator was

reset or overloaded, the data rate, overrange condition, when a measurement is in progress and when a measurement

is complete.

BIT

B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

BIT NAME

DEFAULT

0

1

0

1

0

1

0

BIT

DEFAULT

LABEL

FUNCTION

Ready bit. RDY = 1 when a new conversion result is available. A read of the DATA register

resets RDY = 0. The function of the RDY bit is redundant and is duplicated by RDYB pin.

00

0

RDY

Measurement status bit. MSTAT = 1 indicates that a conversion, self-calibration, or system

01

0

MSTAT

DOR

calibration is in progress and that the modulator is busy. When the modulator is not converting,

MSTAT = 0.

Data overrange bit. DOR = 1 indicates that the conversion result has exceeded the maximum

or minimum value and that the result has been clipped or limited to the maximum value. DOR

= 0 when the conversion result is within the full-scale range.

02

03

0

System gain overrange bit. SYSGOR = 1 indicates that a system gain calibration was

overranged. The SGC calibration coefﬁcient maximum value is 1.9999999.

SYSGOR

04

05

06

07

1

0

1

RATE0

RATE1

RATE2

RATE3

Data rate bits. See Table 13. The RATE bits indicate the conversion rate that corresponds to

the result in the DATA register or the rate that was used for calibration coefﬁcient calculation.

Note: RATE bits always show the rate of previous conversion and not the rate of the

conversion in progress.

Analog overrange bit. AOR = 1 when the modulator detects that the analog input voltage

exceeds 1.3 x full-scale range.

08

09

10

11

0

1

AOR

Data read error bit. RDERR = 1 when new result is being written to the DATA register while

user is reading from the DATA register. RDERR = 0 otherwise.

RDERR

PDSTAT0

PDSTAT1

00: ADC is converting

01: Device is fully powered down

10: In standby mode with modulator powered OFF but subregulator powered ON.

11: Reserved.

12

13

14

15

1

0

—

ERROR

INRESET

Error bit. ERROR = 1 when CAL[1:0] bits are set to invalid setting of 11.

In reset bit. INRESET = 1 when software reset is initiated till the part exits reset mode.

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Table 9. Programmable Conversion Rates

CONTINUOUS DATA RATE, SCYCLE = 0

SCYCLE = 1 SINGLE-CYCLE

CONTINUOUS DATA RATE (sps)

RATE[3:0]

SINC FILTER (sps)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1.9

3.9

50

62.5

100

7.8

15.6

31.2

62.5

125

200

250

400

250

500

800

1000

2000

4000

8000

16000

32000

64000

1000

1600

2000

3200

4000

6400

12800

*Continuous data rate with SCYCLE = 0, single cycle with CONTSC = 1, SCYCLE = 1.

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Control Registers

These are registers reserved for configuring the MAX11270.

Control 1 Register (Read/Write)

The CTRL1 register is an 8-bit read/write register. The byte written to the CTRL1 register determines the clock setting,

synchronization mode, power-down or reset state, input range is unipolar or bipolar, data output is two’s complement or

offset binary, and conversion mode is in single cycle or continuous.

B07

EXTCK

0

B06

SYNC

0

B05

PD1

0

B04

PD0

0

B03

U/B

0

B02

FORMAT

0

B01

SCYCLE

1

B00

CONTSC

0

BIT

BIT NAME

DEFAULT

BIT

00

DEFAULT

LABEL

FUNCTION

Continuous single-cycle bit. Set CONTSC = 1 to select continuous conversions. Set CONTSC

= 0 to select a single conversion.

0

CONTSC

Single-cycle control bit. Set SCYCLE = 1 to select single-cycle mode. The MAX11270

completes one no-latency conversion and then powers down into a leakage-only state. Set

SCYCLE = 0 to select continuous conversion mode.

01

1

SCYCLE

Bipolar range format bit. When reading bipolar data, set FORMAT = 0 to select two’s

complement and FORMAT = 1 to select offset binary. The data from unipolar range is always

formatted in offset binary format.

02

03

0

FORMAT

U/B: Unipolar/bipolar bit. Set U/B = 1 to select the unipolar input range (0 to V ). Set U/B = 0

REF

U/B

to select the bipolar input range (±V ).

REF

00

Normal power-up state. This is the default state.

04

05

0

PD0

PD1

Sleep Mode—Powers down the subregulator and the entire digital circuitry. Upon

resumption of power to the digital the PD[1:0] reverts to the default state of ‘00’.

01

10

11

Standby power—Powers down the analog blocks leaving the subregulator powered up.

Resets all registers to POR state leaving the subregulator powered. The PD[1:0] bits

are reset to ‘00’. The operation of this state is identical to the RSTB pin.

Set SYNC = 1 to select continuous synchronization mode. Set SYNC = 0 to select pulse

synchronization mode.

06

07

0

SYNC

External clock bit. Set EXTCLK = 1 to selects the external clock as the system clock. Set

EXTCLK = 0 to select the internal oscillator as the system clock.

EXTCK

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Control 2 Register (Read/Write)

The CTRL2 register is an 8-bit read/write register. The byte written to the CTRL2 register determines the digital and

analog gain settings, and whether the buffers or PGA is enabled.

BIT

B07

DGAIN1

0

B06

DGAIN0

0

B05

BUFEN

0

B04

LPMODE

0

B03

PGAEN

0

B02

PGAG2

0

B01

PGAG1

0

B00

PGAG0

0

BIT NAME

DEFAULT

BIT

DEFAULT

LABEL

FUNCTION

000

001

010

011

100

101

110

111

X1 PGA Gain-Setting bits

X2

X4

X8

X16

X32

X64

X128

00

01

02

0

PGA0

PGA1

PGA2

0

03

04

0

PGAEN

PGA Enable Bit. Set PGAEN = 1 to enable the PGA. Set PGAEN = 0 to disable the PGA.

PGA Low Power. Set LPMODE = 1 for lower power. Set LPMODE = 0 for standard power.

LPMODE

Analog input buffer enable bit. Set BUFEN = 1 to enable the analog input buffers. Set BUFEN

= 0 to disable the analog input buffers.

05

06

0

BUFEN

DGAIN0

00

01

10

11

x1 Modulator Digital Gain Bits

x2

x4

x8

07

0

DGAIN1

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Control 3 Register (Read/Write)

The CTRL3 register is an 8-bit read/write register. The byte written to the CTRL3 register determines the operation of

the modulator output.

BIT

B07

—

B06

—

B05

ENMSYNC

1

B04

MODBITS

0

B03

DATA32

0

B02

—

B01

—

B00

—

BIT NAME

DEFAULT

0

1

0

1

BIT

00

DEFAULT

LABEL

—

FUNCTION

1

0

Reserved bit

01

—

Reserved bit

02

—

32-bit data mode bit. Set DATA32 = 1 to read 32 bits of data at DOUT. Set DATA32 = 0 for 24-

bit data reads at DOUT. See the Data Register section.

03

04

0

DATA32

Modulator output mode enable bit. Set MODBITS = 1 to enable the modulator output on

DOUT and GPIO1. Set MODBITS = 0 for standard data output mode on DOUT.

MODBITS

ENMSYNC

Modulator sychronization pulse enable bit. Set ENMSYNC = 1 to enable the synchronization

pulse for modulator output mode. Set ENMSYNC = 0 to disable the synchronization pulse for

modulator output mode.

05

1

06

07

1

0

—

Reserved bit

Control 4 Register (Read/Write)

The CTRL4 register is an 8-bit read/write register. The byte written to the CTRL4 register determines whether the GPIOs

are inputs or outputs, and whether they are enabled.

BIT

B07

—

B06

DIR3

0

B05

DIR2

0

B04

DIR1

0

B03

—

B02

DIO3

1

B01

DIO2

1

B00

DIO1

1

BIT NAME

DEFAULT

0

1

BIT

00

01

02

03

04

05

06

07

DEFAULT

LABEL

FUNCTION

1

0

DIO1

DIO2

DIO3

—

GPIO bit values. When GPIO is conﬁgured as an output, set the DIO bits = 0 to set the

associated GPIO output as a 0. When GPIO are conﬁgured as inputs, these bits indicate the pin

status.

DIR1

DIR2

DIR3

—

GPIO direction bits. Set the DIR bits = 0 to conﬁgure the associated GPIO as an input. The

value returned by a read of the DIO bit is the value being driven on the pin. Set the DIR bits =

1 to conﬁgure the associated GPIO as an output. The GPIO is driven to the logic value of the

associated DIO bit.

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Control 5 Register (Read/Write)

The CTRL5 register is an 8-bit read/write register. The byte written to the CTRL5 register determines the MAX11270’s

reset, data overflow, and calibration modes.

BIT

B07

CAL1

0

B06

CAL0

0

B05

—

B04

—

B03

NOSYSG

1

B02

NOSYSO

1

B01

NOSCG

0

B00

NOSCO

0

BIT NAME

DEFAULT

0

BIT

00

DEFAULT

LABEL

FUNCTION

No self-calibration offset bit. Set NOSCO = 1 to disable the use of the self-calibration offset

value when computing the ﬁnal offset and gain-corrected data value. Set NOSCO = 0 to

enable the use of the self-calibration offset value when computing the ﬁnal offset and gain-

corrected data value.

0

NOSCO

NOSCG

No self-calibration gain bit. Set NOSCG = 1 to disable the use of the self-calibration gain value

when computing the ﬁnal offset and gain-corrected data value. Set NOSCG = 0 to enable the

use of the self-calibration gain value when computing the ﬁnal offset and gain-corrected data

value.

01

No system offset bit. Set NOSYSO = 1 to disable the use of the system offset value when

computing the ﬁnal offset and gain-corrected data value. Set NOSYSO = 0 to enable the use

of the system offset value when computing the ﬁnal offset-corrected data value.

02

03

1

NOSYSO

NOSYSG

No system gain bit. Set NOSYSG = 1 to disable the use of the system gain value when

computing the ﬁnal offset and gain-corrected data value. Set NOSYSG = 0 to enable the use

of the system gain value when computing the ﬁnal gain-corrected data value.

04

05

0

—

Reserved

00 Perform Self Calibration

06

07

0

CAL0

CAL1

01 Perform System-Level Offset Calibration

10 Perform System-Level Full-Scale Calibration

11 Reserved

Data Register (Read Only)

The data register is a 32-bit or 24-bit read-only register. Any attempt to write data to the data register has no effect. The

data from this register is clocked out MSB first. The data register holds the conversion result. The result is stored in either

two’s complement or offset binary format, depending on the FORMAT bit in CTRL1 register.

The data format in unipolar mode is always offset binary. In bipolar mode, set the FORMAT bit = 1 for offset binary or

FORMAT = 0 for two’s compliment. Any input exceeding the available input range is limited to the minimum or maximum

data value. Attempts to read this register while data is being updated (4 system clocks before RDYB asserts low) will

result in invalid data being read, see Figure 13. Note that the STATUS register RDERR bit is set when this condition is

detected.

BIT

B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

DEFAULT

0

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Table 10. ADC Output Code Data Format

DIGITAL OUTPUT CODE (Hex)

OFFSET BINARY TWO’s COMPLEMENT

32-BIT

CODE

TRANSITION

ANALOG INPUT

(AINP - AINN) (V)

24-BIT

FFFFFF

FFFFFE

800001

800000

7FFFFF

000001

000000

32-BIT

24-BIT

7FFFFF

7FFFFE

000001

000000

FFFFFF

800001

800000

≥ FS

FS – 1 LSB

Midscale + 1 LSB

Midscale

≥ V

REF

FFFFFFFF

FFFFFFFE

80000001

80000000

7FFFFFFF

00000001

00000000

7FFFFFFF

7FFFFFFE

00000001

00000000

FFFFFFFF

80000001

80000000

N

V

x (1 – (1/2 – 1))

N

REF

V

/2 - 1

N

REF

V

/2

REF

N

Midscale - 1 LSB

ZS + 1 LSB

≤ ZS

-V

/2 -1

REF

x (1 – (1/2 – 1))

N

-V

REF

≤ -V

REF

N = number of data bits, 32 or 24.

= V - V

V

.

REFN

REF

REFP

Calibration

Two types of calibration are available: self-calibration and system calibration. Self-calibration is used to reduce the

MAX11270 gain and offset errors during changing operating conditions such as supply voltages, ambient temperature,

and time. System calibration is used to reduce the gain and offset of the entire signal path. This enables calibration of

board level components and the integrated PGA. System calibration requires the MAX11270 inputs to be reconfigured

for zero scale and full scale during calibration. See Figure 9 for details of the calibration signal flow.

The on-chip calibration registers are enabled or disabled by programming the NOSYSG, NOSYSO, NOSCG, and

NOSCO bits in the CTRL5 register. See Table 6

Self-Calibration

The self-calibration is an internal operation and does not disturb the analog inputs. Self-calibration is accomplished in two

independent phases, offset and gain. The first phase disconnects the inputs to the modulator and shorts them together

internally to develop a zero-scale signal. A conversion is then completed and the results are post-processed to generate

an offset coefficient which cancels all internally generated offsets. The second phase connects the inputs to the reference

to develop a full-scale signal. A conversion is then completed and the results are post-processed to generate a full-scale

coefficient, which scales the converters full-scale analog range to the full-scale digital range.

The entire self-calibration sequence requires two independent conversions, one for offset and one for full scale.

The conversion rate is 50sps which provides the lowest noise and most accurate calibrations. The self-calibration opera-

tion excludes the PGA. A system-level calibration is available in order to calibrate the PGA signal path.

The calibration operations are controlled with the CAL bit in the command byte. Request a self-calibration by setting

the CAL bit to 1, with the CTRL5:CAL[1:0] = 00. A self-calibration requires 200ms to complete, and both the SCOC and

SCGC registers contain the values that correct the chip output for zero scale and full scale.

System Calibration

This mode is used when board level components and the integrated PGA calibration is desired. A system calibration

requires the user to configure the input to the proper level for the calibration operation. The offset and full-scale system

calibrations are performed using separate command bytes by configuring the CTRL5:CAL [1:0] bits. The system offset

and system full scale require setting these CAL bits appropriately before issuing the calibration command byte.

Request a system zero-scale calibration by setting the CAL bit to 1 and the CTRL5:CAL[1:0] bit = 01 and connect a

system zero-level signal to the input pins. The system zero calibration requires 100ms to complete, and the SOC register

contains values that correct the chip zero scale.

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Request a system full-scale calibration by setting the CAL bit to 1 and the CTRL5:CAL[1:0] = 10 and connect a system

full-scale signal level to the input pins. The system full-scale calibration requires 100ms to complete, and the SGC

register contains values that correct for the chip full-scale value.

A third level of calibration allows a write to the internal calibration registers through the SPI interface to achieve any

digital offset or scaling with the following restrictions. The range of digital offset correction is ±V

/4. The resolution

REF

of offset correction is 0.5 LSB. The range of digital gain correction is from 0.75 to 2. The resolution of gain is less than

1ppm.

SPI System Offset Calibration Register (SOC_SPI)

The system offset calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked

in/out MSB first. The format is always in two’s complement. This register temporarily holds the system offset calibra-

tion value from the user. This value gets copied into the SOC_ADC register. The value written to this register remains

until it is overwritten. This value gets invalidated for calibration after a system-calibration operation is requested. Any

attempt to write to this register during an active calibration operation will be ignored.

ADC System Offset Calibration Register (SOC_ADC)

This is 24-bit read only register. There are two ways this register value is updated. One way is if a system offset calibra-

tion operation is requested. Another way is if a user writes a value to SOC_SPI register, the value will then get copied

into SOC_ADC from SOC_SPI.

The system offset calibration value is subtracted from each conversion result if NOSYSO = 0 in the CTRL5 register.

The system offset calibration value is subtracted from the conversion result after self-calibration, but before system

gain correction. It is also applied prior to the 1x or 2x scale factor associated with bipolar and unipolar modes. Attempts

to read this register while data is being updated (4 system clocks before RDYB asserts low) will result in invalid data

being read, see Figure 13. Note that the STATUS register RDERR bit is set when this condition is detected.

SPI System Gain Calibration Register (SGC_SPI)

The system gain calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked

in/out MSB first. The format is unsigned binary. This register temporarily holds the system gain calibration value from

the user. This value gets copied into the SGC_ADC register. The value written to this register remains until it is over-

written. This value gets invalidated for calibration after a system-calibration operation is requested. Any attempt to write

to this register during an active calibration operation will be ignored.

ADC System Gain Calibration Register (SGC_ADC)

This is 24-bit read only register. There are two ways this register value is updated. One way is if a system gain calibra-

tion operation is requested. Another way is if a user writes a value to SGC_SPI register, the value will then get copied

into SGC_ADC from SGC_SPI.

The system gain calibration value is used to scale the offset-corrected conversion result if NOSYSG = 0 in the CTRL5

register. The system gain calibration value scales the gain corrected result by up to 2x or can correct a gain error

of approximately 50%. The amount of positive gain error that can be corrected is determined by modulator overload

characteristics which may be as much as +125%. The gain will be corrected to within 1ppm. Attempts to read this

register while data is being updated (4 system clocks before RDYB asserts low) will result in invalid data being read,

see Figure 13. Note that the STATUS register RDERR bit is set when this condition is detected.

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SPI Self-Cal Offset Calibration Register (SCOC_SPI)

The Self-Cal Offset register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out

MSB first. The format is always in two’s complement format. This register temporarily holds the self-cal offset calibration

value from the user. This value gets copied into the SCOC_ADC register. The value written to this register remains until

it is overwritten. This value gets invalidated for calibration after a system-calibration operation is requested. Any attempt

to write to this register during an active calibration operation will be ignored.

ADC Self-Cal Offset Calibration Register (SCOC_ADC)

This is a 24-bit read-only register. There are two ways this register value is updated. One way is if a self-cal operation is

requested. Another way is if a user writes a value to SCOC_SPI register, the value will then get copied into SCOC_ADC

from SCOC_SPI.

The self-cal offset value is subtracted from each conversion result if NOSCO = 0 in the CTRL5 register. The self-cal offset

value is subtracted from the conversion result before the self-calibration gain correction and before the system offset and

gain correction. It is also applied prior to the 2x scale factor associated with unipolar mode. Attempts to read this register

while data is being updated (4 system clocks before RDYB asserts low) will result in invalid data being read, see Figure

13. Note that the STATUS register RDERR bit is set when this condition is detected.

SPI Self-Cal Gain Calibration Register (SCGC_SPI)

The self-cal gain calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked

in/out MSB first. The format is unsigned binary. This register temporarily holds the self-cal gain calibration value from the

user. This value gets copied into the SCGC_ADC register. The value written to this register remains until it is overwritten.

This value gets invalidated for calibration after a system-calibration operation is requested. Any attempt to write to this

register during an active calibration operation will be ignored.

ADC Self-Cal Gain Calibration Register (SCGC_ADC)

This is a 24-bit read only register. There are two ways this register value is updated. One way is if a self-cal operation is

requested. Another way is if a user writes a value to SCGC_SPI register, the value will then get copied into SCGC_ADC

from SCGC_SPI.

The self-cal gain calibration value is used to scale the self-cal offset corrected conversion result before the system offset

and gain calibration values have been applied – provided NOSCG = 0 in the CTRL5 register. The self-cal gain calibration

value scales the self-cal offset corrected conversion result by up to 2x or can correct a gain error of approximately 50%.

The gain will be corrected to within 1ppm. Attempts to read this register while data is being updated (4 system clocks

before RDYB asserts low) will result in invalid data being read, see Figure 13. Note that the STATUS register RDERR bit

is set when this condition is detected.

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RAW RESULT

SPI BLOCK

CAL BLOCK

F

NOSCO=0

T

SCOC

SUBTRACT

SCOC_ADC

SCGC_ADC

SOC_ADC

24

F

NOSCG=0

T

SCGC

MULTIPLY

NOSYSO=0

T

SOC

SUBTRACT

NOSYSG=0

T

SGC

MULTIPLY

SGC_ADC

F

FINAL

RESULT

UNIPOLAR

DATA

T

STATUS REG

x2

LIMITER

Figure 9. Calibration Flow Diagram

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GPIOs

The MAX11270 provides three general-purpose input/output ports that are programmable through the CTRL4 register.

Set the DIR bits in the CTRL4 register to select the pins to be configured as inputs or outputs. All pins are inputs by

default. When programmed as output, set the DIO bits in the CTRL4 register to set pin state to 0 or 1.

Conversion Synchronization Using SYNC Pin or SYNC_SPI Function

The SYNC pin can be used to synchronize the data conversions to external events. This can be done by either pulling

the SYNC pin high or addressing the SYNC_SPI register in a SPI command byte. There are two methods available in

the device to synchronize conversion results using external signals on the SYNC pin: continuous mode or pulse mode.

Continuous Mode

Continuous synchronization mode is used to detect if the current conversions are synchronized to a continuous syn-

chronization pulse with a period greater than the data rate. This synchronization mode compares the number of device

master clocks between the RDYB assertion to the rising edge of the SYNC pin. The relative edges should stay aligned

within 1 master clock period of the initial SYNC pulse and remain within integer multiples of the data rate. If the rising

edge of the SYNC pin occurs after an integer multiple of the data rate and is greater than plus or minus 1 master clock

from the initial SYNC rising edge then the chip resets the conversion in progress, flushes the digital filter contents and

starts a new conversion. The conversion reset process incurs the full digital filter latency before valid results are available.

See Figure 10 for timing waveform relationships between the chip master clock and the SYNC pin. Due to startup delays,

any SYNC pin assertions before the first RDYB assertion are ignored. The first SYNC pin assertion after a RDYB asser-

tion establishes the relationship between the SYNC pin and the conversion ready, timed in master clock units. This

relationship is defined as n, which constitutes the number of clocks that occur between the assertion of RDYB and the

rising edge of the SYNC pin.

FIRST VALID

SYNC

IGNORED

t

SYNC2

t

SYNC1

SYNC PIN

t

CNV

t

5 t

CNV

R2

RDYB

FIRST

CONVERSION

READY

n

CLK

...

(N + n)

PART INITIATES A RESET AND RESTARTS CONVERSIONS WHEN THE RELATIONSHIP OF (clk n to clk N+n) IS

MISALIGNED BY MORE THAN ±1 CLK COUNT. IF THE SYNC PIN RISING EDGE IS COINCIDENT WITH CLOCK COUNT

(N+n) THEN THE SOFT_SYNC COMMAND IS IGNORED AND CONVERSIONS CONTINUE UNINTERRUPTED).

Figure 10. Synchronization Using Continuous Sync Mode Showing Relationship Between SYNC Pin and CLK Pin

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TOP VIEW

+

1

24

23

22

21

20

19

18

17

16

15

14

DIN

DOUT/MB0

DGND

SCLK

t

SYNC2

SYNC1

2

3

CSB

SYNC PIN

DVDD

CAPREG

DGND

CLK

SYNC

4

MAX11270

t

CNV

5 t

CNV

RSTB

5

SINC FILTER,

RDYB

GPIO3/MSYNC

GPIO2

6

...

7

RDYB/ICLK

AVSS

ST

1

CONVERSION READY

AFTER PULSE SYNCHRONIZATION

...

GPIO1/MB1

AVDD

8

CLK

9

CAPP

CAPN

REFP

t

R2

AVSS

10

11

12

RISING EDGE OF SYNC PIN INITIATES A RESET, ABORTING THE CURRENT

CONVERSION AND STARTS A NEW CONVERSION

AINN

AINP

13 REFN

TSSOP

Figure 11. Synchronization Using Pulse Sync Mode Showing

Relationship Between SYNC, RDYB, and CLK Pins

Figure 12. Pin Configuration with MODBITS

Pulse Mode

Initializing MODBITS Mode

Pulse or single event synchronization mode starts a new

conversion upon the rising edge of the SYNC pin. When

the SYNC pin is asserted the chip begins conversions

using the speed settings from the previous convert com-

mand, if no previous convert command was issued prior

to the SYNC pin asserting then the default conversion

speed of 1ksps is used. Note that convert start and SYNC

pin rising edge cannot be applied at the same time. Any

activity on the SYNC pin is ignored until after the first

RDYB assertion following a convert start. This is required

due to convert start overhead which delays the first con-

version result by 32 master clocks.

Set the CTRL3: MODBITS to 1 to enter the MODBITS

mode and read the real-time modulator output data. After

setting the control bits, a conversion command must be

issued. This starts the modulator without running the rest

of the digital logic needed for a full conversion. Setting

CTRL3: ENMSYNC = 1 enables the modulator SYNC puls-

es to shift out onto GPIO3/MSYNC. The modulator mode

can be run even if this bit is disabled. If ENMSYNC = 0,

the SYNC pulses will not be shifted out on GPIO3/MSYNC.

Exiting MODBITS Mode

To go back to normal conversion mode, set MODBITS = 0.

If MODBITS = 0, ENMSYNC is a don’t care. After setting

MODBITS = 0, issue a conversion command to activate

the MAX11270 in normal data read mode.

Modulator MODBITS Mode

The MODBITS mode bypasses the MAX11270’s internal

filters and outputs the real-time 5-bit modulator data to the

DOUT and GPIO pins.

MODBITS Mode Pin Conﬁgurations

The DOUT/MB0, GPIO3/MSYNC, and GPIO1/MB1 pins

offer dual functionality, depending on whether MODBITS

real-time modulator data mode or normal data output

mode is selected.

MODBITS mode is controlled by the MODBITS and

ENMSYNC bits in the CTRL3 register.

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DOUT/MB0

GPIO1/MB1

In MODBIT mode, the DOUT/MB0 outputs the real-time

modulatordata(MB0). WhentheENMSYNCbit=0, DOUT/

MB0 outputs the first MSYNC pulse and shifts out the

even bits of the modulator data (bit 4, bit 2, and bit 0). The

first SYNC pulse (indicating valid modulator data) will be

shifted out on the positive clock edge (referred to as clock

edge 1) for initial synchronization. For all other data cycles,

the clock edge 1 will output 0 on this pin (as well as 0 on

GPIO1/MB1) indicating the end of a current data stream.

On clock edge 2, 3, and 4 DOUT/MB0 shifts out the even

data bits as described earlier.

In MODBIT mode, the GPIO1/MB1 functions as a real-

time modulator data output. On clock edge 1, GPIO1/MB1

always outputs 0 (irrespective of the state of ENMSYNC).

On clock edge 2 and 3, this pin will shift out the odd bits

of the modulator data (bit 3 and bit 1). GPIO1/MB1 is 0 on

clock edge 3 as well.

RDYB/ICLK

When the MODBITS bit = 1, the internal system clock

(running at 8.192MHz) is output on RDYB/ICLK. This

enables aligning the data to the clock edge.

The description of the data shift described above is

detailed in the Figure 13. It shows both cases with

ENMSYNC = 0 or 1 and the difference in the behavior of

GPIO3/MSYNC and DOUT/MB0. RDYB and GPIO1/MB1

are unaffected by the ENMSYNC bit.

GPIO3/MSYNC

When ENMSYNC = 1 in the MODBIT mode, GPIO3/

MSYNC functions as the modulator sync (MSYNC) out-

put. The SYNC pulse from the modulator is shifted out on

the positive clock edge. When the sync signal shifts out

on the GPIO3/MSYNC pin, the data is “00” on both the

DOUT/MB0 and GPIO1/MB1 pins and marks the starting

point of the next modulator data.

Table 11. MODBITS Mode Pins

NORMAL FUNCTION

MODBITS FUNCTION

DESCRIPTION

ENMSYNC=0, output MSYNC ﬁrst followed by even bits of

modulator data. ENMSYNC=1, output even bits of modulator data

only

DOUT

MB0

GPIO1

GPIO3

RDYB

MB1

MSYNC

ICLK

Odd bits (bits 1 and 3) of modulator data

Shifts SYNC pulses from the modulator

Internal clock

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WRITE TO

CTRL3[5:4]=01

OR 11

WRITE TO

CTRL3[5:4]=00

OR 10

ISSUE A

CONVERSION

COMMAND

ISSUE A

CONVERSION

COMMAND

MCLK

EN_MODBITS

(INTERNAL SIGNAL)

1

2

3

4

1

2

3

4

RDYB_ICLK

SYNC1

SYNC2

CASE1: ENMSYNC (CTRL3[5]=1)

GPIO3_MSYNC

(SYNC PULSES OUT)

0

MDATA4

MDATA3

MDATA2

MDATA1

MDATA0

0

MDATA4

MDATA3

MDATA2

MDATA1

MDATA0

0

DOUT_MB0

GPIO1_MB1

0

CASE2: ENMSYNC (CTRL3[5]=0)

OVRRNG=0

1

DOUT_MB0

GPIO1_MB1

MDATA4

MDATA3

MDATA2

MDATA1

MDATA0

0

MDATA4

MDATA3

MDATA2

MDATA1

MDATA0

0

(1^stSYNC)

0

Figure 13. Timing Diagram for MODBITS Mode

Maxim Integrated

│ 45

www.maximintegrated.com

MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma

ADC with Integrated PGA

Ordering Information

Package Information

For the latest package outline information and land patterns

PART

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

24 TSSOP

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

MAX11270EUG+

+Denotes a lead(Pb)-free/RoHS-compliant package.

PACKAGE

TYPE

PACKAGE

CODE

LAND

PATTERN NO.

OUTLINE NO.

21-0066

Chip Information

PROCESS: BiCMOS

24 TSSOP

U24+2

90-0118

Maxim Integrated

│ 46

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MAX11270

24-Bit, 10mW, 130dB SNR, 64ksps Delta Sigma

ADC with Integrated PGA

Revision History

REVISION REVISION

PAGES

DESCRIPTION

CHANGED

NUMBER

DATE

0

8/14

Initial release

—

1, 6, 7, 9, 11–13,

16–18, 25, 30, 34,

37, 39, 40

Corrected errors in data sheet, changed Reference Voltage range speciﬁcation.

Revised Typical Operating Characteristics, register tables and descriptions.

1

5/15

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2015 Maxim Integrated Products, Inc.

│ 47


型号：	MAX11270EUG+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	ADC, Delta-Sigma, 24-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO24, ROHS COMPLIANT, TSSOP-24 信息通信管理光电二极管转换器
文件：	总47页 (文件大小：722K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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