MAX11312_V01 [MAXIM]
PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO;
| 型号： | MAX11312_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO |
| 文件： | 总54页 (文件大小：2836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
General Description
Benefits and Features
● 12 Configurable Mixed-Signal Ports Maximize Design
Flexibility Across Platforms
The MAX11312 integrates a PIXI™, 12-bit, multichannel,
analog-to-digital converter (ADC) and a 12-bit, multichannel,
buffered digital-to-analog converter (DAC) in a single
integrated circuit. This device offers 12 mixed-signal high-
voltage, bipolar ports, which are configurable as an ADC
analog input, a DAC analog output, a general purpose
input (GPI), a general-purpose output (GPO), or an analog
switch terminal. One internal and two external temperature
sensors track junction and environmental temperature.
Adjacent pairs of ports are configurable as a logic-level
translator for open-drain devices or an analog switch.
• Up to 12 12-Bit ADC Inputs
- Single-Ended, Differential, or Pseudo-Differential
- Range Options: 0 to 2.5V, ±5V, 0 to +10V, -10V to 0V
- Programmable Sample Averaging Per ADC Port
- Unique Voltage Reference for Each ADC PIXI Port
• Up to 12 12-Bit DAC Outputs
- Range Options: ±5V, 0 to +10V, -10V to 0V
- 25mA Current Drive Capability with Overcurrent
Protection
PIXI ports provide highly flexible hardware configuration
for 12-bit mixed-signal applications. The MAX11312 is best
suited for applications that demand a mixture of analog
and digital functions. Each port is individually configurable
with up to four selectable voltage ranges within the -10V
to +10V range.
• Up to 12 General-Purpose Digital I/Os
- 0 to +5V GPI Input Range
- 0 to +2.5V GPI Programmable Threshold Range
- 0 to +10V GPO Programmable Output Range
- Logic-Level-Shifting Between Any Two Pins
The device allows for the averaging of 2, 4, 8, 16, 32,
64, or 128 ADC samples from each ADC-configured
port to improve noise performance. A DAC-configured output
port can drive up to 25mA. The GPIO ports can be
programmed to user-defined logic levels, and a GPI
coupled with a GPO forms a logic-level translator.
• 60Ω Analog Switch Between Adjacent PIXI Ports
• Internal/External Temperature Sensors, ±1°C Accuracy
● Adapts to Specific Application Requirements and Allows
for Easy Reconfiguration as System Needs Change
● Configurability of Functions Enables Optimized PCB Layout
Internal and external temperature measurements monitor
programmable conditions of minimum and maximum
temperature limits, using the interrupt to notify the host if one
or more conditions occur. The temperature measurement
results are made available through the serial interface.
● Reduces BOM Cost with Fewer Components in a
Small Footprint
2
• 25mm 32-Pin TQFN
The device features an internal, low-noise 2.5V voltage
reference and provides the option to use external voltage
references with separate inputs for the DAC and ADC.
2
Ordering Information appears at end of data sheet.
The MAX11312 uses a 400kHz I C-compatible serial
interface, operating from a 5V analog supply and a 1.8V
to 5.0V digital supply. The PIXI port supply voltages operate
from a wide -12.0V to +12.0V.
The MAX11312 is available in a 32-pin TQFN, 5mm x 5mm
package specified over the -40°C to +105°C temperature
range.
Applications
● Base-Station RF Power Device Bias Controllers
● System Supervision and Control
● Power-Supply Monitoring
● Industrial Control and Automation
● Control for Optical Components
PIXI is a trademark of Maxim Integrated Products, Inc.
19-7945; Rev 1; 7/19
MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Functional Diagram
DVDD
DAC_REF
ADC_INT_REF
AVDD
AVDDIO
CLOCK
GENERATOR
D1P
2.5V
D1N
D0P
INTERNAL
REFERENCE
TEMPERATURE
MONITORS
EXT AND INT
TEMP SENSORS
MAX11312
2.5V
D0N
REFERENCE
(0 ≤ x ≤ 5)
MUX
PORT[x+1]
12
12
ADC
SEQUENCER
CNVT
ADC
PORT[x]
AD1
12
PIXI PORT
MANAGER
DAC
SEQUENCER
SERIAL
INTERFACE
AND
DIGITAL
DAC
GPI
PORT[y+1]
PORT[y]
AD0
12
12
SCL
CORE
GPO
(6 ≤ y ≤ 11)
SDA
INT
DGND
AGND1
AGND
AVSSIO
Maxim Integrated
│ 2
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Absolute Maximum Ratings
DVDD to DGND.......................................................-0.3V to +6V
AVDD to AGND .......................................................-0.3V to +6V
AVDDIO to AVSSIO...............................................-0.3V to +25V
AVDDIO to AGND..................................................-0.3V to +17V
AVSSIO to AGND..................................................-14V to +0.3V
AGND to AGND1..................................................-0.3V to +0.3V
AGND to DGND ...................................................-0.3V to +0.3V
AGND1 to DGND .................................................-0.3V to +0.3V
(AD0, AD1) to DGND ....-0.3V to min of (V
DAC and ADC Reference Pins to AGND (DAC_REF,
ADC_INT_REF,) .......... -0.3V to min of (V
Temperature Sensor Pins
(D0N, D0P, D1N, D1P) to AGND..........................-0.3V to min of
(V + 0.3V) or +6V
+ 0.3V) or +6V
DVDD
+0.3V) or +4V
AVDD
AVDD
Current into Any PORT Pin ..............................................100mA
Current into Any Other Pin Except Supplies
(PORT0 to PORT11) to AGND ............max of (V
- 0.3V)
and Ground.....................................................................50mA
AVSSIO
or -14V to min of (V
+ 0.3V) or +17V
Continuous Power Dissipation (T = +70°C) (Multilayer board)
AVDDIO
A
(PORT0 to PORT11) to AGND (GPI and Bidirectional Level
TQFN (derate 34.5mW/°C above +70°C) .............2758.6mW
Operating Temperature Range..........................-40ºC to +105°C
Storage Temperature Range.............................-65ºC to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
Translator Modes) ........-0.3V to min of (V
+ 0.3V) or +6V
AVDD
CNVT to DGND.............-0.3V to min of (V
+ 0.3V) or +6V
DVDD
INT to DGND...........................................................-0.3V to +6V
(SDA, SCL) to DGND..............................................-0.3V to +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TQFN
Junction-to-Case Thermal Resistance (θ )..............1.7°C/W
Junction-to-Ambient Thermal Resistance (θ ) ..........29°C/W
JA
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
ADC Electrical Specifications
(V
= 4.75V to 5.25V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V,
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF
V
= 2.5V (Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise
ADCREF
S
A
noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
DC ACCURACY (Note 3)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
±2.5
±1
DNL
No missing codes over temperature
LSB
±0.5
±8
LSB
Offset Error Drift
Gain Error
±0.002
LSB/°C
LSB
±11
Gain Error Drift
±0.01
1
LSB/°C
Channel-to-Channel Offset
Matching
LSB
LSB
Channel-to-Channel Gain
Matching
2
Maxim Integrated
│ 3
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Electrical Characteristics (continued)
ADC Electrical Specifications
(V
= 4.75V to 5.25V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V,
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF
V
= 2.5V (Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise
ADCREF
S
A
noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (SINGLE-ENDED INPUTS)
Signal-to-Noise Plus Distortion
Signal to Noise
SINAD
SNR
f
S
f
S
f
S
f
S
= 400ksps, f = 10kHz
70
71
dB
dB
dB
dB
dB
IN
= 400ksps, f = 10kHz
IN
Total Harmonic Distortion
Spurious-Free Dynamic Range
Crosstalk
THD
= 400ksps, f = 10kHz
-75
75
IN
SFDR
= 400ksps, f = 10kHz
IN
-85
DYNAMIC PERFORMANCE (DIFFERENTIAL INPUTS)
Signal-to-Noise Plus Distortion
Signal to Noise
SINAD
SNR
f
S
f
S
f
S
f
S
= 400ksps, f = 10kHz
71
72
dB
dB
dB
dB
dB
IN
= 400ksps, f = 10kHz
IN
Total Harmonic Distortion
Spurious-Free Dynamic Range
Crosstalk
THD
= 400ksps, f = 10kHz
-82
82
IN
SFDR
= 400ksps, f = 10kHz
IN
-85
CONVERSION RATE
ADCCONV[1:0] = 00
ADCCONV[1:0] = 01
ADCCONV[1:0] = 10
ADCCONV[1:0] = 11
ADCCONV[1:0] = 00
ADCCONV[1:0] = 01
ADCCONV[1:0] = 10
ADCCONV[1:0] = 11
200
250
333
400
3.5
2.5
1.5
1.0
Throughput (Note 4)
ksps
Acquisition Time
t
μs
ACQ
ANALOG INPUT (All Ports)
Absolute Input Voltage (Note 5)
Range 1
Range 2
Range 3
Range 4
Range 1, 2, 3
Range 4
0
-5
10
+5
V
V
PORT
-10
0
0
2.5
130
100
70
50
100
75
kΩ
kΩ
Input Resistance
Maxim Integrated
│ 4
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
REF Electrical Characteristics
(V
= 4.75V to 5.25V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V, V
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF ADCREF
= 2.5V (Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise noted.
S
A
Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC INTERNAL REFERENCE
Reference Output Voltage
REF Output Tempco (Note 6)
Internal references at T = +25°C
2.494
2.5
2.506
±25
V
A
T
±10
ppm/°C
C-VREF
C-VREF
Capacitor Bypass at ADC_INT_
REF
4.7
10
µF
DAC INTERNAL REFERENCE
Reference Output Voltage
Internal references at T = +25°C
2.494
4.7
2.5
2.506
±25
10
V
ppm/°C
µF
A
REF Output Tempco (Note 6)
Capacitor Bypass at DAC_REF
DAC EXTERNAL REFERENCE
Reference Input Range
T
±10
1.25
2.5
V
GPIO Electrical Specifications
(V
= 5.0V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V, V
= 2.5V
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF
ADCREF
(Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise noted. Typical
S
A
values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GPIO EXCEPT IN BIDIRECTIONAL LEVEL TRANSLATION MODE
Programmable Input Logic
Threshold
V
V
DACREF
0.3
V
ITH
V
V
ITH
Input High Voltage
Input Low Voltage
Hysteresis
+
0.3
V
V
IH
V
V
- 0.3
ITH
IL
±30
mV
Programmable Output
Logic Level
4 x
V
0
V
OLVL
V
DACREF
Propagation Delay from GPI Input
to GPO Output in Unidirectional
Level Translating Mode
Midscale threshold-5V logic swing
2
µs
BIDIRECTIONAL LEVEL TRANSLATION PATH AND ANALOG SWITCH
V
Input High Voltage
Input Low Voltage
On-Resistance
1
V
V
Ω
IH
V
0.2
60
IL
From V
+ 2.50V to V
-2.50V
AVSSIO
AVDDIO
10kΩ pullup resistors to rail in each side.
Midvoltage to midvoltage when driving
side goes from high to low
Propagation Delay
1
µs
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
GPIO Electrical Specifications (continued)
(V
= 5.0V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V, V
= 2.5V
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF
ADCREF
(Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise noted. Typical
S
A
values are at T = +25°C.) (Note 2)
A
PARAMETER
ANALOG SWITCH
Turn-On Delay
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 7)
(Note 7)
(Note 7)
(Note 7)
400
400
ns
ns
µs
µs
Turn-Off Delay
On-Time Duration
Off-Time Duration
1
1
From V
+ 2.50V to
- 2.50V
AVSSIO
On-Resistance
60
Ω
V
AVDDIO
DAC Electrical Specifications
(V
= 4.75V to 5.25V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V, V
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF ADCREF
= 2.5V (Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise noted.
S
A
Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
V
Resolution
N
12
0
Range 1
Range 2
Range 3
+10
+5
V
Output Range (Note 5)
-5
PORT
-10
0
Integral Linearity Error
Differential Linearity Error
Offset Voltage
INL
From code 100 to code 3996
±0.5
±0.5
±1.5
±1
LSB
LSB
DNL
At code 100
±20
LSB
Offset Voltage Tempco
Gain Error
15
ppm/°C
% of FS
From code 100 to code 3996
From code 100 to code 3996
-0.6
+0.6
ppm of
FS/°C
Gain Error Tempco
4
Power-Supply Rejection
Ratio
PSRR
0.4
mV/V
DYNAMIC CHARACTERISTICS
Output Voltage Slew Rate
SR
1.6
40
V/µs
µs
To ±1 LSB, from 0 to full scale, output load
capacitance of 250pF (Note 8)
Output Settling Time
Settling TimeAfter Current-
Limit Condition
6
µs
mV
P-P
Noise
f = 0.1Hz to 300kHz
3.8
Maxim Integrated
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
DAC Electrical Specifications (continued)
(V
AVDD
= 4.75V to 5.25V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V, V
= 2.5V
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF
ADCREF
(Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise noted. Typical
S
A
values are at T = +25°C.) (Note 2)
A
PARAMETER
TRACK-AND-HOLD
Digital Feedthrough
Hold Step
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5
1
nV·s
mV
(Note 6)
(Note 6)
6
Droop Rate
0.3
15
mV/s
Interface Digital IO Electrical Specifications
(V
= 5.0V, V
= 1.62V to 5.50V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V, V
= 2.5V
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF
ADCREF
(Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise noted. Typical
S
A
values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C IO DC SPECIFICATION
0.7 x
V
DVDD
V
DVDD
V
DVDD
V
DVDD
= 2.5V to 5.5V
V
DVDD
Input Logic-High Voltage
(SDA, SCL, AD0, AD1, CNVT)
V
0.85 x
= 1.62V to 2.5V
= 2.5V to 5.5V
= 1.62V to 2.5V
V
DVDD
0.3 x
V
DVDD
Input Logic-Low Voltage
(SDA, SCL, AD0, AD1, CNVT)
V
0.15 x
V
DVDD
+10
Input Leakage Current
(SDA, SCL, AD0, AD1, CNVT)
-10
µA
pF
V
Input Capacitance
(SDA, SCL, AD0, AD1, CNVT)
10
Output Logic-Low Voltage
(SDA)
I
= 3mA
0.4
SNK
I
I
= 5mA, V
= 2mA, V
= 2.5V to 5.5V
= 1.62V to 2.5V
0.4
0.2
SNK
DVDD
Output Logic-Low Voltage (INT)
V
SNK
DVDD
2
I C TIMING REQUIREMENTS (Fast Mode) (See Figure 1)
Serial Clock Frequency
f
0
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Condition
t
1.3
BUF
Hold Time (Repeated) START
Condition
After this period, first clock pulse is
generated
t
0.6
1.3
µs
µs
HD;STA
SCL Pulse-Width Low
t
LOW
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Interface Digital IO Electrical Specifications (continued)
(V
= 4.75V to 5.25V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V, V
= 2.5V
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF
ADCREF
(Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise noted. Typical
S
A
values are at T = +25°C.) (Note 2)
A
SCL Pulse-Width High
t
0.6
µs
HIGH
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Setup Time for Repeated
START Condition
t
0.6
µs
SU;STA
Data Hold Time
Data Setup Time
t
0
900
ns
ns
HD;DAT
t
100
SU;DAT
12 x
SDA and SCL Receiving Rise
Time
t
(Note 6)
(Note 6)
(V
300
300
250
ns
ns
ns
r
DVDD
/5.5V)
12 x
SDA and SCL Receiving Fall
Time
t
(V
f
DVDD
/5.5V)
12 x
SDA Transmitting Fall Time
t
(V
of
DVDD
/5.5V)
Setup Time for STOP Condition
Bus Capacitance Allowed
t
0.6
µs
pF
SU;STO
C
b
V
= 2.5V to 5.5V
400
DVDD
Pulse Width of Suppressed
Spike
t
50
ns
SP
SDA
tf
tSU;DAT
tHD;STA
tr
tf
tr
tBUF
tSP
tLOW
SCL
tSU;STO
tHD;DAT
tHIGH
tSU;STA
tHD;STA
Sr
P
S
S
2
Figure 1. I C Timing
Maxim Integrated
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Electrical Characteristics
Internal and External Temperature Sensor Specifications
(V
= 4.75V to 5.25V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V, V
= 2.5V
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF
ADCREF
(Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise noted. Typical
S
A
values are at T = +25°C.) (Note 2)
A
PARAMETER
ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0°C ≤ T ≤ +80°C
±0.3
±0.7
±0.3
±1.0
±2.0
±5
°C
°C
°C
°C
Accuracy of Internal Sensor
(Notes 6, 9)
J
-40°C ≤ T ≤ +125°C
J
0°C ≤ T ≤ +80°C
±2.0
±5
Accuracy of External Sensor
(Notes 6, 9)
RJ
-40°C ≤ T ≤ +150°C
RJ
Temperature Measurement
Resolution
0.125
°C
High
Low
High
Low
68
4
μA
μA
μA
μA
External Sensor Junction
Current
Series resistance cancellation mode
Series resistance cancellation mode
136
8
External Sensor Junction
Current
Remote Junction Current
Conversion Ratio
17
D0N/D1N Voltage
Internally generated
0.5
V
Power-Supply Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.25
5.50
15.75
0
UNITS
V
V
V
V
V
4.75
1.62
V
V
V
V
V
AVDD
DVDD
V
AVDDIO
AVSSIO
AVDDIO
AVDD
-12.0
to V
V
24
AVSSIO
AVDD
All ports in high impedance
LPEN = 1
14
11
17
18
18
I
mA
AVDD
All ports in ADC-related modes
All ports in DAC-related modes
Serial interface in idle mode
All ports in mode 0
I
I
I
2
μA
μA
μA
DVDD
150
AVDDIO
AVSSIO
All ports in mode 0
-400
Maxim Integrated
│ 9
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Recommended VDDIO/VSSIO Supply Selection
ADC RANGE
0V TO +10V
= +10V
-10V TO 0V
-5V TO +5V
0 TO 2.5V
V
V
= +5V
V
V
= +5V
V
V
V
= +5V
AVDDIO
AVDDIO
AVDDIO
AVDDIO
-10V TO 0V
-5V TO +5V
0V TO +10V
= -12V
= -12V
V
= -12V
= -12V
AVSSIO
AVSSIO
AVSSIO
AVSSIO
V
V
= +7V
V
= +7V
= -7V
V
V
= +10V
= -7V
V
AVDDIO
= +7V
= -7V
AVDDIO
AVDDIO
AVDDIO
= -10V
V
V
AVSSIO
AVSSIO
AVSSIO
AVSSIO
V
V
= +12V
= -10V
V
= +12V
= -5V
V
V
= +12V
= -2V
V
AVDDIO
= +12V
= -2V
AVDDIO
AVDDIO
AVDDIO
V
V
AVSSIO
AVSSIO
AVSSIO
AVSSIO
The values of V
and V
supply voltages depend on the application circuit and the device configuration.
AVSSIO
AVDDIO
V
needs to be the maximum of those four values:
AVDDIO
● If one or more ports are in mode 3, 4, 5, 6, or 10 (DAC-related modes), V
must be set, at minimum, to the
AVDDIO
value of the largest voltage driven by any of the ports set in those modes. For improved linearity, it is recommended
to set V 2.0V above the largest voltage value.
AVDDIO
● If one or more ports are in mode 7, 8, or 9 (ADC-related modes), V
must be set, at minimum, to the value of
AVDDIO
the largest voltage applied to any of the ports set in those modes.
● If one or more ports are in mode 11 or 12 (Analog switch-related modes), V
must be set, at minimum, to
AVDDIO
2.0V above the value of the largest voltage applied to any of the ports functioning as analog switch terminals.
● V cannot be set lower than V
.
AVDD
AVDDIO
V
needs to be the minimum of those four values:
AVSSIO
● If one or more ports are in mode 3, 4, 5, 6, or 10 (DAC-related modes), V
must be set, at maximum, to the
AVSSIO
value of the lowest voltage driven by any of the ports set in those modes. For improved linearity, it is recommended
to set V 2.0V below the lowest voltage value.
AVSSIO
● If one or more ports are in mode 7, 8, or 9 (ADC-related modes), V
must be set, at maximum, to the value
AVSSIO
of the lowest voltage applied to any of the ports set in those modes.
● If one or more ports are in mode 11 or 12 (Analog Switch-related modes), V
must be set, at maximum, to
AVSSIO
2.0V below the value of the lowest voltage applied to any of the ports functioning as analog switch terminals.
● V cannot be set higher than V
.
AGND
AVSSIO
For example, the MAX11312 can operate with only one voltage supply of 5V (±5%) connected to AVDD, AVDDIO, and
DVDD, and one ground of 0V connected to AGND, DGND, and AVSSIO. However, the level of performance presented
in the electrical specifications requires the setting of the supplies connected to AVDDIO and AVSSIO, as previously
described.
Maxim Integrated
│ 10
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Common PIXI Electrical Specifications
(V
= 4.75V to 5.25V, V
= 3.3V, V
= +12.0V, V
= V
= 0V, V
= -2.0V, V
= 2.5V, V
= 2.5V
AVDD
DVDD
AVDDIO
AGND
DGND
AVSSIO
DACREF
ADCREF
(Internal), f = 400ksps, 10V analog input range set to range 1 (0 to +10V). T = -40°C to +105°C, unless otherwise noted. Typical
S
A
values are at T = +25°C.) (Note 2)
A
PARAMETER
PIXI PORTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
Input Resistance
All PIXI ports
12
75
pF
All PIXI input pins except ADC mode
50
100
100
kΩ
Between stable supplies and accessing
registers
Startup Time
ms
HIGH-VOLTAGE OUTPUT DRIVER CHARACTERISTICS
Maximum Output Capacitance
250
pF
V
Sinking 25mA, V
= 0V,
V
V
AVSSIO
AVSSIO
+ 1.0
Output Low Voltage, DAC Mode
Output High Voltage, DAC Mode
Output Low Voltage, GPO Mode
Output High Voltage, GPO Mode
V
= 10V
AVDDIO
Sourcing 25mA, V
= 0V,
V
V
AVSSIO
AVDDIO
- 1.5
V
V
= 10V
AVDDIO
Sinking 2mA, V
= 0V,
AVSSIO
AVSSIO
+ 0.4
V
V
= 10V
AVDDIO
Sourcing 2mA, V
= 0V,
AVSSIO
AVDDIO
- 0.4
V
V
= 10V
AVDDIO
Short to AVDDIO
Short to AVSSIO
75
75
mA
mA
Current Limit
Note 2: Electrical specifications are production tested at T = +25°C. Specifications over the entire operating temperature range are
A
guaranteed by design and characterization. Typical specifications are at T = +25°C.
A
Note 3: DC accuracy specifications are tested for single-ended ADC inputs only.
Note 4: The effective ADC sample rate for port X configured in mode 6, 7, or 8 is:
#
[ADC sample rate per ADCCONV]/(([number of ports in modes 6,7,8] + [1 if TMPSEL ≠ 000]) x [2 OF SAMPLES for port X])
Note 5: See the Recommended VDDIO/VSSIO Supply Selection table for each range. For ports in modes 6, 7, 8, or 9, the voltage
applied to those ports must be within the limits of their selected input range, whether in single-ended or differential mode.
Note 6: Specification is guaranteed by design and characterization.
Note 7: Switch controlled by GPI-configured port. One switch terminal connected to 0V, the other terminal connected to 5V through a 5mA
current source. Timing is measured at the 2.5V transition point. Turn-on and turn-off delays are measured from the edge of the
control signal to the 2.5V transition point. Turn-on and turn-off durations are measured between control signal transitions.
Note 8: In DAC-related modes, the rate, at which PIXI ports configured in mode 1, 3, 4, 5, 6, or 10 are refreshed, is as follows:
1/(40µs x [number of ports in modes 1, 3, 4, 5, 6, 10])
Note 9: Typical (typ) values represent the errors at the extremes of the given temperature range.
Maxim Integrated
│ 11
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
ADC INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTERNAL REFERENCE
ADC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTERNAL REFERENCE
ADC INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
EXTERNAL REFERENCE
toc01
toc02
toc03
2.5
1
0.8
0.6
0.4
0.2
0
2.5
2
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.2
-0.4
-0.6
-0.8
-1
-0.5
-1
-1.5
-1.5
-2
RANGE 0V TO 10V
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
RANGE -5V TO +5V
-2
RANGE -10V TO 0V
-2.5
-2.5
0
1000
2000
3000
4000
0
1000
2000
3000
4000
0
1000
2000
3000
4000
DIGITAL OUPUT CODE (DECIMAL)
DIGITAL OUPUT CODE (DECIMAL)
DIGITAL OUPUT CODE (DECIMAL)
ADC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
EXTERNAL REFERENCE
ADC OFFSET ERROR
vs. TEMPERATURE
ADC GAIN ERROR
vs. TEMPERATURE
toc05
toc06
toc04
1
0
1
0.8
0.6
0.4
0.2
0
1.5
0.5
-1
-2
-3
-4
-5
-6
-7
-8
-9
-0.5
-1.5
-2.5
-3.5
-4.5
-0.2
-0.4
-0.6
-0.8
-1
RANGE 0-10V
RANGE 0-10V
RANGE -5V - +5V
RANGE 0 - 2.5V
RANGE -5V - +5V
RANGE -10 - 0V
RANGE 0 - 2.5V
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
RANGE -10 - 0V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
0
1000
2000
3000
4000
TEMPERATURE (°C)
TEMPERATURE (°C)
DIGITAL OUPUT CODE (DECIMAL)
SUPPLY CURRENT
vs. TEMPERATURE
ADC RANGE 0V TO 10V
ADC OFFSET ERROR
vs. SUPPLY VOLTAGE
ADC GAIN ERROR
vs. SUPPLY VOLTAGE
toc07
toc08
toc9a
1
0
100000
10000
1000
100
1
0
-1
-2
-3
-4
-5
-6
-7
-8
IAVDD
IAVSSIO
-1
-2
-3
-4
IAVDDIO
10
IAVDDIO
RANGE 0-10V
RANGE -5V - +5V
RANGE 0 - 2.5V
1
RANGE 0-10V
RANGE -10 - 0V
RANGE -5V - +5V
RANGE 0 - 2.5V
RANGE -10 - 0V
0.1
4.7
4.8
4.9
5
5.1
5.2
5.3
4.7
4.8
4.9
5
5.1
5.2
5.3
-50
-25
0
25
50
75
100 125
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Maxim Integrated
│ 12
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. TEMPERATURE
ADC RANGE -5V TO +5V
SUPPLY CURRENT
vs. TEMPERATURE
ADC RANGE -10V TO 0V
IAVDD
vs. ADC CHANNELS
toc10
toc9b
toc9c
16
15.8
15.6
15.4
15.2
15
100000
100000
10000
1000
100
ADC RANGE
-5V TO +5V
10000
IAVDD
IAVDD
IAVSSIO
IAVSSIO
1000
100
10
IAVDDIO
IAVDDIO
ADC RANGE
-10V TO 0V
14.8
14.6
14.4
14.2
14
10
IAVDDIO
IAVDDIO
ADC RANGE
0V TO 10V
1
1
0.1
0.1
0
2
4
6
8
10
12
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
NO. OF ADC CONFIGURED PORTS
TEMPERATURE (°C)
TEMPERATURE (°C)
DAC INTEGRAL NONLINEARITY
vs. DIGITAL CODE
DAC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTERNAL REFERENCE
toc13
ADC INTERNAL REFERENCE
vs. TEMPERATURE
INTERNAL REFERENCE
toc11
toc12
1.5
1
1
2.506
2.504
2.502
2.500
2.498
2.496
2.494
0.8
0.6
0.4
0.2
0
0.5
0
-0.2
-0.4
-0.6
-0.8
-1
-0.5
-1
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
-1.5
0
1000
2000
3000
4000
0
1000
2000
3000
4000
-50
-25
0
25
50
75
100 125
DAC CODE (DECIMAL)
DAC CODE (DECIMAL)
TEMPERATURE (°C)
DAC INTEGRAL NONLINEARITY
vs. DIGITAL CODE
DAC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
EXTERNAL REFERENCE
DAC OFFSET ERROR
vs. TEMPERATURE
EXTERNAL REFERENCE
toc14
toc15
toc16
1.5
1
1
0.8
0.6
0.4
0.2
0
3.5
2.5
0.5
0
1.5
0.5
-0.2
-0.4
-0.6
-0.8
-1
-0.5
-1
-0.5
-1.5
-2.5
RANGE 0V TO 10V
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
RANGE -5V TO +5V
RANGE -10V TO 0V
-1.5
0
1000
2000
3000
4000
0
1000
2000
3000
4000
-50
-25
0
25
50
75
100
125
DAC CODE (DECIMAL)
DAC CODE (DECIMAL)
TEMPERATURE (°C)
Maxim Integrated
│ 13
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
DAC GAIN ERROR
vs. TEMPERATURE
DAC OFFSET ERROR
vs. SUPPLY VOLTAGE
DAC GAIN ERROR
vs. SUPPLY VOLTAGE
toc17
toc18
toc19
2
4
3
-0.1
-0.3
-0.5
-0.7
-0.9
-1.1
-1.3
-1.5
1.5
1
2
0.5
0
1
-0.5
0
-1
RANGE 0V TO 10V
RANGE 0V TO 10V
RANGE 0V TO 10V
-1
-2
RANGE -5V TO +5V
-1.5
RANGE -5V TO +5V
RANGE -5V TO +5V
RANGE -10V TO 0V
RANGE -10V TO 0V
RANGE -10V TO 0V
-2
-50
-50
0
-25
0
25
50
75
100
125
4.7
-50
0
4.8
4.9
5
5.1
5.2
5.3
4.7
-50
0
4.8
4.9
5
5.1
5.2
5.3
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT
vs. TEMPERATURE
DAC RANGE -5V TO +5V
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
DAC RANGE -10V TO 0V
DAC RANGE 0V TO 10V
toc20a
toc20b
toc20c
100000
10000
1000
100
100000
10000
1000
100
100000
10000
1000
100
IAVSSIO
IAVSSIO
IAVSSIO
IAVDD
IAVDD
IAVDD
IAVDDIO
IAVDDIO
IAVDDIO
10
10
10
IAVDDIO
IAVDDIO
IAVDDIO
1
1
1
0.1
0.1
0.1
-25
0
25
50
75
100 125
-25
0
25
50
75
100 125
-25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
IAVSSIO
IAVDDIO
IAVDD
vs. DAC CHANNELS
vs. DAC CHANNELS
vs. DAC CHANNELS
toc21b
toc21c
toc21a
5
4.5
4
7
6
5
4
3
2
1
0
19
18
17
16
15
14
13
ADC RANGE
-5V TO +5V
ADC RANGE
-5V TO +5V
3.5
3
ADC RANGE
-5V TO +5V
ADC RANGE
0V TO 10V
ADC RANGE
-10V TO 0V
ADC RANGE
0V TO 10V
2.5
2
1.5
1
ADC RANGE
-10V TO 0V
ADC RANGE
-10V TO 0V
ADC RANGE
0V TO 10V
0.5
0
2
4
6
8
10
12
2
4
6
8
10
12
2
4
6
8
10
12
NO. OF DAC-CONFIGURED PORTS
NO. OF DAC-CONFIGURED PORTS
NO. OF DAC-CONFIGURED PORTS
Maxim Integrated
│ 14
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
DAC SETTLING TIME
CHANGE FROM
PSV1 TO PSV2
DAC SETTLING TIME
CHANGE FROM MIN TO MAX
NO LOAD
DAC INTERNAL REFERENCE
vs. TEMPERATURE
toc23
toc24a
toc22
2.506
PSV1 = 0X000
PSV2 = 0XFFF
2.504
2.502
2.500
2.498
2.496
2.494
2V/div
2V/div
-50
-25
0
25
50
75
100 125
5µs/div
2.5µs/div
TEMPERATURE (°C)
DAC SETTLING TIME
CHANGE FROM MAX TO MIN
NO LOAD
DAC SETTLING TIME
CHANGE FROM MIN TO MAX
1µF CAP LOAD
DAC SETTLING TIME
CHANGE FROM MAX TO MIN
1µF CAP LOAD
toc24b
toc24c
toc24d
2V/div
2V/div
2V/div
2.5µs/div
50µs/div
50µs/div
DAC DROOP RATE
vs. TEMPERATURE
DAC DROOP RATE
vs. TEMPERATURE
(DAC RANGE 0 TO 10V)
(DAC RANGE -5V TO +5V)
toc25a
toc25b
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
AVDD = 4.75V
VAVDD = 4.75V
AVDD = 5V
V
V
= 5V
AVDD
AVDD = 5.25V
AVDD = 5.25V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Maxim Integrated
│ 15
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
DAC VOH AND VOL
vs. TEMPERATURE
(ILOAD = 25mA)
DAC DRIVE CURRENT LIMIT
vs. TEMPERATURE
DAC = 0V, SHORTED TO VDDIO
DAC DROOP RATE
vs. TEMPERATURE
(DAC RANGE -10V TO 0)
toc25c
toc26
toc27
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
1.000
0.900
0.800
0.700
0.600
0.500
0.400
0.300
0.200
0.100
0.000
62.0
61.8
61.6
61.4
61.2
61.0
60.8
60.6
60.4
60.2
60.0
VAVDD = 4.75V
A
V
= 5V
A
AVDD
A
VAVDD = 5.25V
VOL
VOH
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
DAC DRIVE CURRENT LIMIT
vs. TEMPERATURE
DAC = 10V, SHORTED TO VSSIO
DAC OUTPUT NOISE
INTERNAL REFERENCE
(0.1Hz TO 10Hz)
MAJOR-CODE TRANSITION GLITCH
DAC CODE FROM 0x7FF TO 0x800
toc29
toc30
toc28
62.0
61.8
61.6
61.4
61.2
61.0
60.8
60.6
60.4
60.2
60.0
CS
5V/div
20µV/div
DAC VOUT
AC-
COUPLED
1mV/div
-50
-25
0
25
50
75
100 125
10µs/div
1s/div
TEMPERATURE (°C)
DAC OUTPUT NOISE
EXTERNAL REFERENCE
(0.1Hz TO 10Hz)
GPI OFFSET
vs. SUPPLY VOLTAGE
toc31
toc32
4.5
4
3.5
3
2.5
2
20µV/div
1.5
1
V
= 0.9V
TH
V
= 1.65V
TH
0.5
V
= 2.5V
TH
0
4.7
4.8
4.9
5
5.1
5.2
5.3
1s/div
SUPPLY VOLTAGE (V)
Maxim Integrated
│ 16
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
GPI HYSTERESIS
vs. TEMPERATURE
GPI OFFSET
vs. TEMPERATURE
toc34
toc33
40
38
36
34
32
30
28
26
24
22
20
6
5
4
3
2
1
0
VTH = 0.9V
VTH = 0.9V
TH = 1.65V
V
V=1.65V
TH
TH = 2.5V
V
V=2.5V
TH
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
EXTERNAL TEMPERATURE
SENSOR ERROR
INTERNAL TEMPERATURE
SENSOR ERROR
vs. TEMPERATURE
vs. TEMPERATURE
toc36
toc35
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Maxim Integrated
│ 17
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
PORT7
D1N
D1P
AGND1
PORT0
AGND
AVDDIO
PORT8
PORT9
PORT10
PORT11
DGND
MAX11312
AVDD
D0N
D0P
+
DAC_REF
1
2
3
4
5
6
7
8
TQFN
5mm x 5mm
Pin Description
PIN
1
NAME
DVDD
SDA
FUNCTION
Positive Digital Supply
Serial Interface Input and Output
Serial Interface Clock Input
Slave Address Bit 0
2
3
SCL
4
AD0
5
AD1
Slave Address Bit 1
6
INTINT
CNVT
Interrupt Open-Drain Output. Active-low.
ADC Trigger Control Input. Active-low.
7
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Pin Description (continued)
PIN
NAME
FUNCTION
ADC Internal Voltage Reference Output. Connect a bypass capacitor at this pin
(4.7µF to 10µF).
8
ADC_INT_REF
DAC External/Internal Voltage Reference Input. Connect a bypass capacitor at this pin
(4.7µF to 10µF).
9
DAC_REF
st
10
11
D0P
D0N
1
1
External Temperature Sensor Positive Input
External Temperature Sensor Negative Input
st
12
13
14
15
16
17
18,27
19
20
21
22
23
24
25
26
28
29
30
31
32
—
AVDD
Positive Analog Supply
Analog Ground
AGND
PORT0
D1P
Configurable Mixed-Signal Port 0
nd
2
2
External Temperature Sensor Positive Input
External Temperature Sensor Negative Input
nd
D1N
PORT1
AVDDIO
PORT2
PORT3
PORT4
PORT5
AVSSIO
PORT6
PORT7
AGND1
PORT8
PORT9
PORT10
PORT11
DGND
EP
Configurable Mixed-Signal Port 1
Analog Positive Supply For Mixed-Signal Ports. Connect both pins to AVDDIO.
Configurable Mixed-Signal Port 2
Configurable Mixed-Signal Port 3
Configurable Mixed-Signal Port 4
Configurable Mixed-Signal Port 5
Analog Negative Supply for Mixed-Signal Ports.
Configurable Mixed-Signal Port 6
Configurable Mixed-Signal Port 7
Analog Ground
Configurable Mixed-Signal Port 8
Configurable Mixed-Signal Port 9
Configurable Mixed-Signal Port 10
Configurable Mixed-Signal Port 11
Digital Ground
Exposed Pad. Connect EP to AVSSIO.
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│ 19
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Control and Monitoring Application Circuit—PA Biasing—PIXI Solution
SCL_5V
SDA_5V
SCL_3V3
SDA_3V3
LEVEL
TRANSLATOR
RS
4 – 20mA
0V TO +10V
4-20mA
OUTPUT
ADC
DAC
ADC
ADC
RLOAD
CSA
MAX44285
COOLING
FAN
SPEED
CONTROLLER
DAC
HEATER
THERMAL
CONTROL
THERMAL
PROBE
MAX11312
10V
RS
TEMPERATURE
SENSOR AND
MONITOR
CSA
MAX44285
CURRENT
REGULATION
DAC
ADC
ADC
CURRENT
SENSE
VOLTAGE
SENSE
USB
SPI
MINIQUSB
PC
Maxim Integrated
│ 20
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
ADC Control
Detailed Description
The ADC can be triggered using an external signal CNVT
or from a control bit. CNVT is active-low and must remain
Functional Overview
The MAX11312 has 12 configurable mixed-signal I/O
ports. Each port is independently configured as a DAC
output, an ADC, a GPI input, a GPO, or an analog switch
terminal. User-controllable parameters are available for each
of those configurations. The device offers one internal and
two external temperature sensors. The serial interface
low for a minimal duration of 0.5µs to trigger a conversion.
Four configurations are available:
● Idle mode (default setting).
● Single sweep mode. The ADC sweeps sequentially
the ADC-configured ports, from the lowest index port
to the highest index port, once CNVT is asserted.
2
operates as a Fast Mode I C-compatible interface.
● Single conversion mode. The ADC performs a single
conversion at the current port in the series of ADC-
configured ports when CNVT is asserted.
The DAC is used to drive out a voltage defined by the
DAC data register of the DAC-configured ports. The DAC
uses either an internal or external voltage reference. The
selection of the voltage reference is set for all the ports
and cannot be configured on a port-by-port basis.
● Continuous sweep mode. The ADC continuously
sweeps the ADC-configured ports. The CNVT port
has no effect in this mode.
The ADC converts voltages applied to the ADC-configured
ports. The ADC can operate in single-ended mode or in
differential mode, by which any two ports can form a
differential pair. The port configured as the negative
input of the ADC can be used by more than one differential
ADC input pairs. The ADC uses an internal voltage
reference. In some configurations, the ADC uses the DAC
voltage reference. The ADC voltage reference selection
can be configured on a port-by-port basis.
ADC Averaging Function
ADC-configured ports can be configured to average
blocks of 2, 4, 8, 16, 32, 64, or 128 conversion results.
The corresponding ADC data register is updated only
when the averaging is completed, thus decreasing the
throughput proportionally. If the number of samples to
average is modified for a given port, the content of the
ADC data register for that port is cleared before starting
to average the new block of samples.
Interrupts provide the host with the occurrence of user-
selected events through the configuration of an interrupt
mask register.
ADC Mode Change
When users change the ADC active mode (continuous
sweep, single sweep, or single conversion), the ADC data
registers are reset. However, ADC data registers retain
content when the ADC is changed to idle mode.
ADC Operations
The ADC is a 12-bit, low-power, successive approximation
analog-to-digital converter, capable of sampling a single
input at up to 400ksps. The ADC’s conversion rate can be
programmed to 400ksps, 333ksps, 250ksps, or 200ksps.
The default conversion rate setting is 200ksps. Each
ADC-configured port can be programmed for one of five
input voltage ranges: 0 to +10V, -5V to +5V, -10V to 0V,
and 0 to +2.5V. The ADC uses the internal ADC 2.5V
voltage reference or in some cases, the DAC voltage
reference. The voltage reference can be selected on a
port-by-port basis.
ADC Configurations
The ADC can operate in single-ended, differential, or
pseudo-differential mode. In single-ended mode, the PIXI
port is the positive input to the ADC while the negative
input is grounded internally (Figure 2). In differential mode
(Figure 3), any pair of PIXI ports can be configured as
inputs to the differential ADC. In pseudo-differential mode
(Figure 4), one PIXI port produces the voltage applied
to the negative input of the ADC, while another PIXI port
forms the positive input.
The ADC data format is straight binary in single-ended
mode, and two’s complement in differential and pseudo-
differential modes.
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
By default, the DAC updates the DAC-configured ports
sequentially. However, users can configure the DAC so
DAC Operations
The MAX11312 uses a 12-bit DAC, which operates at the
rate of 40µs per port. Since up to 12 ports can be configured
in DAC-related modes, the minimum refresh rate per port
is 2.083KHz.
that its sequence can jump to update the port that just
received new data to convert. After having updated this
port, the DAC continues its default sequence from that
port. In that mode, users should allow a minimum of 80µs
between DAC data register updates for subsequent jump
operations.
No external component is required to set the offset and
gain of the DAC drivers. The PIXI port driver features a
wide output voltage range of ±10V and high-current capability
with dedicated power supplies (AVDDIO, AVSSIO).
In addition to port-specific DAC data registers, the host
can also use the same data for all DAC-related ports
using one of two preset DAC data registers.
The DAC uses either the internal or external voltage
reference. Unlike the ADC, the DAC voltage reference
cannot be configured on a port-by-port basis. DAC mode
configuration is illustrated in Figure 5.
All DAC output drivers are protected by overcurrent limit
circuitry. In case of overcurrent, the MAX11312 generates
an interrupt. Detailed status registers are offered to the
host to determine which ports are current limited.
DAC operations can be monitored by the ADC. In such a
mode, the ADC samples the DAC-configured port to allow
the host to monitor that the voltage at the port is within
expectations given the accuracy of the ADC and DAC.
This ADC monitoring mode is shown in Figure 6.
ADC_INT_REF
CNVT
SCALING
BLOCK
SERIAL
INTERFACE
DIGITAL
CORE
I2C
PORT
SEQUENCER
ADC
12 BITS
UP TO 400ksps
INT
Figure 2. ADC with Single-Ended Input
ADC_INT_REF
SCALING
BLOCK
CNVT
ANY
PORT
DIGITAL
CORE
SERIAL
INTERFACE
I2C
SCALING
BLOCK
SEQUENCER
ADC
ANY OTHER
PORT
12 BITS
UP TO 400ksps
INT
Figure 3. ADC with Differential Inputs
Maxim Integrated
│ 22
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
ADC_INT_REF
ADC_EXT_REF
SCALING
BLOCK
REFERENCE
CNVT
MUX
ANY
PORT
DIGITAL
CORE
SERIAL
INTERFACE
I2C
SCALING
BLOCK
SEQUENCER
ADC
ANY OTHER
PORT
INT
DAC_REF
INTERNAL OR
EXTERNAL FOR
ALL PORTS
SCALING
BLOCK
SEQUENCER
DAC
Figure 4. ADC with Pseudo-Differential Input Set by DAC
DAC_REF
INTERNAL OR
EXTERNAL FOR
ALL PORTS
SCALING
BLOCK
SERIAL
INTERFACE
DIGITAL
CORE
I2C
SEQUENCER
DAC
PORT
0mA 25mA
CURRENT LIMIT at
50mA
40µs to 1 LSB
INT
Figure 5. DAC Configuration
level is four times the DAC reference voltage. The logic-
zero level is always 0V. The host can set the logic state
of GPO-configured ports through the corresponding GPO
data registers.
General-Purpose Input and Output
Each PIXI port can be configured as a GPI or a GPO. The
GPI threshold is adjusted by setting the DAC data register
of that GPI port to the corresponding voltage. If the DAC
data register is set at 0x0FFF, the GPI threshold is the DAC
reference voltage. The amplitude of the input signal must
Unidirectional and Bidirectional
Level Translator Operations
By combining GPI and GPO-configured ports, unidirectional
level translator paths can be formed. The signaling at the
input of the path can be different from the signaling at the
end (Figure 9). For example, a unidirectional path could
convert a signal from 1.8V logic level to 3.3V logic level.
be contained within 0V to V
. The GPI-configured port
AVDD
can be set to detect rising edges, falling edges, either rising
or falling edges, or none.
When a port is configured as GPO (Figure 8), the amplitude
of its logic-one level is set by its DAC data register. If the
DAC data register is set at 0x0FFF, the GPO logic-one
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
CNVT
DAC_REF
INTERNAL OR EXTERNAL
FOR ALL PORTS
SCALING
BLOCK
SERIAL
INTERFACE
DIGITAL
CORE
I2C
SEQUENCER
PORT
DAC
ADC_INT_REF
DAC_REF
REFERENCE
MUX
SCALING
BLOCK
SEQUENCER
ADC
INT
Figure 6. DAC Configuration with ADC Monitoring
The unidirectional path configuration allows for the
transmission of signals received on a GPI-configured port
to one or more GPO-configured ports.
Power-Supply Brownout Detection
The MAX11312 features a brownout detection circuit that
monitors AVDDIO and AVDD pins. When AVDDIO goes
below approximately 4.0V, an interrupt is registered, and
the interrupt port is asserted if not masked. When AVDD
goes below approximately 4.0V, the device resets.
Pairs of adjacent PIXI ports can also form bidirectional
level translator paths that are targeted to operate with
open-drain drivers (Figure 10). In this configuration,
adjacent PIXI ports must be from the same six-channel
group: PORT0 to PORT5 or PORT6 to PORT11. When
used as a bidirectional level translator, the pair of PIXI
ports must be accompanied with external pullup resistors
to meet proper logic levels.
2
I C Operations
2
The MAX11312 serial interface is compatible with the I C
Fast Mode (SCL at 400kHz).
The MAX11312 has a configurable 7-bit slave address.
The first four bits of all MAX11312 slave addresses are
always 0111. Slave address bits A2, A1, and A0 are
shown in Table 1. The AD0 and AD1 inputs are connected
to any of three signals: DGND, DVDD, SDA, or SCL giving
eight possible slave addresses, and allowing up to eight
MAX11312 devices to share the bus.
Internally or Externally Controlled
Analog Switch Operation
Two adjacent PIXI ports from the same group of ports (PORT0
to PORT5 or PORT6 to PORT11) can form a 60Ω analog
switch that is controlled by two different configurations. Analog
switches cannot be configured between programmable ports
in different groups, such as between PORT5 and PORT6
or between PORT0 and PORT11. In one configuration, the
switch is dynamically controlled by any other GPI-configured
PIXI port, as illustrated in Figure 11. The signal applied to that
GPI-configured port can be inverted.
Basic write and read transactions are structured as shown
in Table 2 and Table 3, respectively. For write transactions,
the targeted register content is modified only after the
third byte has been fully received. A burst transaction
would simply be the extension of the single register transaction,
where the address is automatically incremented from one
data word to the next (Table 4 and Table 5). Each time a
new data sample is read or written, the register address
is incremented by one until it reaches the last register
In the other configuration, the switch is programmed to be
permanently “ON” by configuring the corresponding PIXI
port. To turn the switch “OFF”, the host must set that PIXI
port in high-impedance configuration.
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│ 24
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Table 1. MAX11312 Slave Addresses
SLAVE ADDRESS
PIN AD1
PIN AD0
A6
0
A5
1
A4
1
A3
1
A2
0
A1
0
A0
0
DGND
DGND
DGND
DGND
DVDD
DVDD
DVDD
DVDD
DGND
SDA
0
1
1
1
0
0
1
SCL
0
1
1
1
0
1
0
DVDD
DGND
SDA
0
1
1
1
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
0
1
SCL
0
1
1
1
1
1
0
DVDD
0
1
1
1
1
1
1
2
Table 2. Single Register I C Write Transaction Format
B7
B6
B5
B4
B3
B2
B1
B0
N/ACK
START
st
1
2
3
4
byte
byte
byte
byte
7-Bit Slave Address[6:0]
Address[6:0]
R/WB
ACK
ACK
ACK
ACK
nd
rd
th
0
Data[15:8]
Data[7:0]
STOP
2
Table 3. Single Register I C Read Transaction Format
B7
B6
B5
B4
B3
B2
B1
B0
N/ACK
START
st
1
2
byte
byte
7-Bit Slave Address[6:0]
Address[6:0]
R/WB
R/WB
ACK
ACK
nd
0
RESTART
st
1
3
4
byte
byte
byte
7-Bit Slave Address[6:0]
Data[15:8]
ACK
ACK
rd
th
Data[7:0]
NACK (from host)
STOP
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
2
Table 4. Multiple Register I C Write Transaction Format
B7
B6
B5
B4
B3
B2
B1
B0
N/ACK
START
st
1
byte
byte
byte
byte
byte
byte
byte
byte
byte
7-Bit Slave Address[6:0]
Address_N[6:0]
R/WB
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
nd
2
3
4
5
6
7
8
9
0
rd
th
th
th
th
th
th
Data_N[15:8]
Data_N[7:0]
Data_N+1[15:8]
Data_N+1[7:0]
Data_N+2[15:8]
Data_N+2[7:0]
Data_N+3[15:8]
Data_N+3[7:0]
th
10 byte
th
11 byte
…
…
th
25 byte
Data_N+11[15:8]
Data_N+11[7:0]
ACK
ACK
th
26 byte
STOP
2
Table 5. Multiple Register I C Read Transaction Format
B7
B6
B5
B4
B3
B2
B1
B0
N/ACK
START
st
1
2
byte
byte
7-Bit Slave Address[6:0]
Address_N[6:0]
R/WB
ACK
ACK
nd
0
RESTART
st
1
3
4
5
6
7
8
9
byte
byte
byte
byte
byte
byte
byte
byte
7-Bit Slave Address[6:0]
Data_N[15:8]
Data_N[7:0]
R/WB
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
rd
th
th
th
th
th
th
Data_N+1[7:0]
Data_N+1[15:8]
Data_N+1[7:0]
Data_N+2[15:8]
Data_N+2[7:0]
Data_N+3[15:8]
Data_N+3[7:0]
…
th
10 byte
th
11 byte
…
th
25 byte
Data_N+11[15:8]
ACK
NACK
(from host)
th
26 byte
Data_N+11[7:0]
STOP
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│ 26
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
address. The RESTART shown in Tables 3 and 5 could
be replaced by a STOP followed by a START.
Burst Transaction Address
Incrementing Modes
With a burst transaction, the address of the initial register
is entered once. The data of the targeted register can then
be written or read. If the serial clock keeps running without
issuing RESTART, the device increments the address
pointer and writes or reads the next data after the next
If a transaction targets an unused address, nothing is
written within the MAX11312 for write transactions, and
all zeros are read back for read transactions. Similarly, if
a write transaction targets a read-only register, nothing is
written to the device.
DAC_REF INTERNAL OR
EXTERNAL FOR ALL PORTS
SEQUENCER
DAC
SERIAL
INTERFACE
DIGITAL
CORE
I2C
PORT
GPI
30mV
HYSTERESIS
INT
Figure 7. GPI Mode
DAC_REF INTERNAL OR
EXTERNAL FOR ALL PORTS
SCALING
BLOCK
SEQUENCER
DAC
SERIAL
INTERFACE
DIGITAL
CORE
I2C
PORT
GPO
CURRENT LIMIT at 50mA
INT
Figure 8. GPO Mode
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│ 27
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
two bytes. This scheme goes on until the host produces a
NACK (read transactions) or a STOP (write transactions).
additional serial clock cycle results in looping back to the
first DAC-configured port.
There are two address incrementing modes. In one mode,
the address is simply incremented by one (default mode),
while in the other, the address is incremented contextually.
When writing DAC data registers in a burst fashion using
contextual addressing, the host would write the address
of the first port that is DAC-configured (starting from the
lowest port index). As long as the host does not issue a
STOP and another two bytes are received, the next DAC-
configured port is written. This scheme continues until the
last DAC-configured port is reached. At that point, any
The contextual addressing scheme is only valid for writing
DAC data registers, as described above, and reading
ADC data registers.
Interrupt Operations
The device issues interrupts to alert the host of various
events. All events are recorded by the interrupt register.
The assertion of an interrupt register bit results in the
assertion of the interrupt port (INT) if that interrupt bit is
DAC_REF INTERNAL OR
EXTERNAL FOR ALL PORTS
SCALING
BLOCK
SEQUENCER
SEQUENCER
DAC
DAC
ANY OTHER
PORT
DIGITAL
CORE
ANY
PORT
GPI
GPO
SERIAL
INTERFACE
I2C
INT
Figure 9. Unidirectional Level Translator Path Mode
VDD1
VDD2
CHIP1 WITH VDD1
LOGIC LEVEL
CHIP2 WITH VDD2
LOGIC LEVEL
MAX11312
PORT[i]
PORT[i+1]
LOGIC
LOGIC
CONTROLLER
CONTROLLER
Figure 10. Bidirectional Level Translation Application Diagram
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
not masked. By default, all interrupts are masked upon
power-up or reset. The interrupts are listed hereafter.
the next event. This interrupt must be used in conjunction
with the GPIER interrupt bit to operate properly. GPIEM
is cleared after the interrupt register and both GPI status
registers are read subsequently.
The ADCFLAG (ADC Flag) interrupt indicates that the
ADC just completed a conversion or set of conversions.
It is asserted either at the end of a conversion when the
ADC is in single-conversion mode or at the end of a
sweep when the ADC is either in single-sweep mode or
continuous-sweep mode. ADCFLAG is cleared when the
interrupt register is read.
The DACOI (DAC Overcurrent) interrupt indicates that
a DAC-configured port current exceeded approximately
50mA. This limit is not configurable. A DAC overcurrent
status register allows the host to identify which DAC-
configured port exceeded the 50mA current limit. DACOI
is cleared after the interrupt register is read, and both
DAC overcurrent status registers are read subsequently.
The ADCDR (ADC Data Ready) interrupt is asserted
when at least one ADC data register is refreshed. Since
one conversion per ADC-configured port is performed
per sweep, many sweeps may be required before refreshing
the data register of a given ADC-configured port that
utilizes the averaging function. (See the ADC Averaging
Function section) To determine which ADC-configured
port received a new data sample, the host must read
the ADC status registers. ADCDR is cleared after the
interrupt register and both ADC status registers are read
subsequently.
The TMPINT[2:0] (Internal Temperature Monitor)
interrupt has three sources of interrupt, each independently
controllable: a new internal temperature data is ready, the
internal temperature value exceeds the maximum limit, or
the internal temperature value is below the minimum limit.
TMPINT is cleared after the interrupt register is read.
The TMPEXT1[2:0] (1st External Temperature Monitor)
interrupt has three sources of interrupt, each independently
controllable: a new first external temperature data is
ready, the first external temperature value exceeds the
maximum limit, or the first external temperature value is
below the minimum limit. TMPEXT1 is cleared after the
interrupt register is read.
The ADCDM (ADC Data Missed) interrupt is asserted when
any ADC data register is not read by the host before new
data is stored in that ADC data register. ADCDM is cleared
after the interrupt register is read.
The GPIER (GPI Event Received) interrupt indicates that
an event has been received on one of the GPI-configured
ports. Each GPI port can be configured to generate an
interrupt for an event such as detecting a rising edge, a
falling edge, or either edge at the corresponding port. If
the GPI port is configured to detect no edge, it is equivalent
to masking the interrupt related to that port. A GPI status
register allows the host to identify which port detected the
event. GPIER is cleared after the interrupt register and
both GPI status registers are read subsequently.
The TMPEXT2[2:0] (2nd External Temperature Monitor)
interrupt has three sources of interrupt, each independently
controllable: a new second external temperature data is
ready, the second external temperature value exceeds
the maximum limit, or the second external temperature
value is below the minimum limit. TMPEXT2 is cleared
after the interrupt register is read.
(High-Voltage Supply Monitor) Supply Voltage
The V
MON
Failure) interrupt is triggered when AVDDIO supply voltage
falls below 4V, approximately. V
interrupt register is read.
is cleared after the
MON
The GPIEM (GPI Event Missed) interrupt informs the
host that it did not service the GPI interrupt caused by the
occurrence of an event recorded by GPI status registers
before another event was received on the same port. The
host must read the interrupt register and the GPI status
registers whenever a GPI event received interrupt occurs;
otherwise, the GPIEM register is asserted upon receiving
GPI
ANY OTHER PORT
PIXI PORT[i+1]
PIXI PORT[i]
Figure 11. PIXI Ports as a Controllable Analog Switch
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Ohm of resistance. The MAX11312 features a series resistance
cancellation mode (RS_CANCEL) that eliminates this error
Temperature Sensors Overview
The device integrates one internal and two external
temperature sensors. The external sensors are diode-
connected transistors, typically a low-cost, easily mounted
2N3904 NPN type, that replace conventional thermistors
or thermocouples. The external sensors’ accuracy is typically
±1°C over the -40°C to +150°C temperature range with
no calibration necessary. Use of a transistor with a different
ideality factor produces a proportionate difference in the
absolute measured temperature. Parasitic series resistance
results in a temperature reading error of about 0.25°C per
for resistances up to 10Ω. The external sensors can
also measure the die temperature of other ICs, such as
microprocessors, that contain a substrate-connected diode
available for temperature-sensing purposes. Temperature
data can be read from the temperature data registers. The
temperature data format is in two’s complement, with one
LSB representing 0.125°C.
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Maxim Integrated
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Register Detailed Description
Device ID Register (Read)
BIT
FIELD NAME
DESCRIPTION
Device ID
0001_0100_0010_0100
15:0
DEVID[15:0]
Interrupt Register (Read)
BIT
FIELD NAME
DESCRIPTION
ADC flag interrupt
•ꢀ Asserted when the ADC completes a conversion (ADC set in single-conversion mode) or when
the ADC completes a sweep (ADC set in single-sweep or continuous-sweep mode).
•ꢀ No interrupt is generated when the ADC is in idle mode.
0
ADCFLAG
•ꢀ Cleared after the interrupt register is read.
ADC data ready interrupt
•ꢀ Asserted when any ADC data register receives a new data sample. If a port is configured to
N
N
average 2 samples, it takes 2 sweeps for that port data register to be refreshed and assert
ADCDR.
1
ADCDR
•ꢀ Data registers are refreshed either at the end of a conversion (ADC set in single-conversion
mode) or at the end of a sweep (ADC set in single-sweep or continuous-sweep mode).
•ꢀ Cleared after the interrupt register is read, and after both ADCST[10:0] and ADCST[11] registers
are read subsequently.
ADC data missed interrupt
•ꢀ Asserted when the host missed reading a port’s ADC data register by the time that port’s ADC
data register is overwritten by new data.
•ꢀ Cleared after the interrupt register is read.
2
3
ADCDM
GPIDR
GPI event ready interrupt
•ꢀ Asserted when a new event is captured by GPI-configured ports. The type of event is set by the
corresponding GPI IRQ mode register. The host can then consult GPIST[10:0] and GPIST[11]
registers to identify the port that caused the interrupt.
•ꢀ Cleared after the interrupt register is read, and after both GPIST[10:0] and GPIST[11] are read
subsequently.
GPI event missed interrupt
•ꢀ Asserted when the host missed reading the GPI status register by the time that register is
overwritten.
4
5
GPIDM
DACOI
•ꢀ Must be used in conjunction with GPIDR for proper operation.
•ꢀ Cleared after the interrupt register is read, and after both GPIST[10:0] and GPIST[11] are read
subsequently.
DAC driver overcurrent interrupt
•ꢀ Asserted when the DAC driver current exceeds approximately 50mA. The host can then read
DACOIST[10:0] and DACOIST[11] to identify the port that caused the interrupt.
•ꢀ Cleared after the interrupt register is read, and after both DACOIST[10:0] and DACOIST[11]
registers are read subsequently.
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Interrupt Register (Read) (continued)
BIT
FIELD NAME
DESCRIPTION
Internal temperature interrupts
•ꢀ TMPINT[2]: Asserted when the internal temperature value is larger than the value stored in
TMPINTHI[11:0]. Cleared after the interrupt register is read.
8:6
TMPINT[2:0]
•ꢀ TMPINT[1]: Asserted when the internal temperature value is lower than the value stored in
TMPINTLO[11:0]. Cleared after the interrupt register is read.
•ꢀ TMPINT[0]: Asserted when a new temperature value is available. Cleared after the interrupt
register is read.
1st external temperature interrupts
•ꢀ TMPEXT1[2]: Asserted when the 1st external temperature value is larger than the value stored in
TMPEXT1HI[11:0]. Cleared after the interrupt register is read.
11:9
TMPEXT1[2:0]
•ꢀ TMPEXT1[1]: Asserted when the 1st external temperature value is lower than the value stored in
TMPEXT1LO[11:0]. Cleared after the interrupt register is read.
•ꢀ TMPEXT1[0]: Asserted when a new temperature value is available. Cleared after the interrupt
register is read.
2nd external temperature interrupts
•ꢀ TMPEXT2[2]: Asserted when the 2nd external temperature value is larger than the value stored in
TMPEXT2HI[11:0]. Cleared after the interrupt register is read.
14:12
TMPEXT2[2:0]
•ꢀ TMPEXT2[1]: Asserted when the 2nd external temperature value is lower than the value stored in
TMPEXT2LO[11:0]. Cleared after the interrupt register is read.
•ꢀ TMPEXT2[0]: Asserted when a new temperature value is available. Cleared after the interrupt
register is read.
High-voltage supply monitor interrupt
15
VMON
•ꢀ Asserted when the high voltage supply (AVDDIO) falls below approximately 4V.
•ꢀ Cleared after the interrupt register is read.
ADC Status Registers (Read)
BIT
FIELD NAME
DESCRIPTION
Status of ADC data received for ports 0 to 11
•ꢀ Once new data is written in anADC data register, the corresponding ADCST bit is asserted.
The new data is written only after the set of samples to average is collected when the averaging
function is enabled.
•ꢀ This register content is not affected by any related interrupt mask. Activity onADC-configured
ports is recorded by this register regardless of the mask interrupt register setting.
•ꢀ Cleared after the interrupt register is read, and after bothADCST[10:0] andADCST[11] registers
are read, subsequently.
7:2
15:11
0
ADCST[5:0]
ADCST[10:6]
ADCST[11]
Overcurrent Status Registers (Read)
BIT
FIELD NAME
DESCRIPTION
Status of DAC drivers overcurrent for ports 0 to 11
•ꢀ Once a port driver exceeds approximately 50mA, the host can identify which driver caused the
7:2
DACOIST[5:0]
interrupt by reading DACOIST[10:0] and DACOIST[11].
15:11 DACOIST[10:6] •ꢀ This register content is not affected by any related interrupt mask. Activity on overcurrent
0
DACOIST[11]
detection is recorded by these registers regardless of the mask interrupt register setting.
•ꢀ Cleared after the interrupt register is read, and after both DACOIST[10:0] and DACOIST[11]
registers are read, subsequently.
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Internal Temperature Data Register (Read)
BIT
FIELD NAME
DESCRIPTION
Internal temperature measurement data
11:0
TMPINTDAT[11:0]
•ꢀ Temperature measurement produced by the internal temperature sensor.
•ꢀ The data sample is represented in two’s complement, and one LSB represents 0.125°C.
1st External Temperature Data Register (Read)
BIT
FIELD NAME
DESCRIPTION
1st external temperature measurement data
11:0
TMPEXT1DAT[11:0]
•ꢀ Temperature measurement produced by the first external temperature sensor.
•ꢀ The data sample is represented in two’s complement, and one LSB represents 0.125°C.
2nd External Temperature Data Register (Read)
BIT
FIELD NAME
DESCRIPTION
2nd external temperature measurement data
•ꢀ Temperature measurement produced by the second external temperature sensor.
•ꢀ The data sample is represented in two’s complement, and one LSB represents 0.125°C.
11:0
TMPEXT2DAT[11:0]
GPI Status Registers (Read)
BIT
FIELD NAME
DESCRIPTION
Status of GPI event detection for ports 0 to 11
•ꢀ Asserted when an event is detected on a GPI-configured port. The type of event to detect is
set by the corresponding GPI IRQ register.
•ꢀ Once a GPIDT interrupt is generated, the host can identify which GPI port(s) caused the
interrupt by reading GPIST[10:0] and GPIST[11] registers.
•ꢀ GPIST content is not affected by any related interrupt mask. Activity on GPI-configured
ports is recorded by GPIST regardless of the mask interrupt register setting.
•ꢀ Cleared after the interrupt register is read, and after both GPIST[10:0] and GPIST[11]
registers are read, subsequently.
7:2
15:11
0
GPIST[5:0]
GPIST[10:6]
GPIST[11]
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Interrupt Mask Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
ADC flag interrupt mask
•ꢀ MasksADCFLAG interrupt bit when asserted.
•ꢀ In ADC continuous-sweep mode, INT is asserted for 100nS at the end of each sweep
whether ADCFLAG interrupt is cleared or not.
0
ADCFLAGMSK
•ꢀ 1: Prevents the assertion of ADCFLAG interrupt bit from pulling INT low.
•ꢀ 0: Allows the assertion of ADCFLAG interrupt bit to pull INT low.
ADC data ready interrupt mask
•ꢀ MasksADCDR interrupt bit when asserted.
•ꢀ 1: Prevents the assertion ofADCDR interrupt bit from pulling INT low.
•ꢀ 0:Allows the assertion ofADCDR interrupt bit to pull INT low.
1
2
ADCDRMSK
ADCDMMSK
ADC data missed interrupt mask
•ꢀ MasksADCDM interrupt bit when asserted.
•ꢀ 1: Prevents the assertion ofADCDM interrupt bit from pulling INT low.
•ꢀ 0:Allows the assertion ofADCDM interrupt bit to pull INT low.
GPI event ready interrupt
•ꢀ Masks GPIDR interrupt bit when asserted.
•ꢀ Supersedes the settings in the GPI IRQ Mode registers.
•ꢀ 1: Prevents the assertion of GPIDR interrupt bit from pulling INT low.
•ꢀ 0:Allows the assertion of GPIDR interrupt bit to pull INT low.
3
4
GPIDRMSK
GPIDMMSK
GPI event missed interrupt mask
•ꢀ Masks GPIDM interrupt bit when asserted.
•ꢀ Can be deasserted only if GPIDRMSK is deasserted.
•ꢀ 1: Prevents the assertion of GPIDM interrupt bit from pulling INT low.
•ꢀ 0:Allows the assertion of GPIDM interrupt bit to pull INT low.
DAC driver overcurrent interrupt mask
•ꢀ Masks DACOI interrupt bit when asserted.
•ꢀ 1: Prevents the assertion of DACOI interrupt bit from pulling INT low.
•ꢀ 0:Allows the assertion of DACOI interrupt bit to pull INT low.
5
DACOIMSK
Internal temperature interrupt mask
•ꢀ Masks TMPINT[2:0] interrupt bits when asserted on a bit-by-bit basis.
•ꢀ 1: Prevents the assertion of TMPINT[i] interrupt bit from pulling INT low (0≤i≤2).
•ꢀ 0:Allows the assertion of TMPINT[i] interrupt bit to pull INT low (0≤i≤2).
8:6
TMPINTMSK[2:0]
TMPEXT1MSK[2:0]
TMPEXT2MSK[2:0]
1st external temperature interrupt mask
•ꢀ Masks TMPEXT1[2:0] interrupt bits when asserted on a bit-by-bit basis.
•ꢀ 1: Prevents the assertion of TMPEXT1[i] interrupt bit from pulling INT low (0≤i≤2).
•ꢀ 0:Allows the assertion of TMPEXT1[i] interrupt bit to pull INT low (0≤i≤2).
11:9
14:12
2nd external temperature interrupt mask
•ꢀ Masks TMPEXT2[2:0] interrupt bits when asserted on a bit-by-bit basis.
•ꢀ 1: Prevents the assertion of TMPEXT2[i] interrupt bit from pulling INT low (0≤i≤2).
•ꢀ 0:Allows the assertion of TMPEXT2[i] interrupt bit to pull INT low (0≤i≤2).
High-voltage supply monitor mask
•ꢀ Masks VMON interrupt bit when asserted.
•ꢀ 1: Prevents the assertion of VMON interrupt bit from pulling INT low.
•ꢀ 0:Allows the assertion of VMON interrupt bit to pull INT low.
15
VMONMSK
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
GPI IRQ Mode Registers (Read/Write)
BIT
5:4
7:6
FIELD NAME
GPIMD_0[1:0]
GPIMD_1[1:0]
GPIMD_2[1:0]
GPIMD_3[1:0]
GPIMD_4[1:0]
GPIMD_5[1:0]
GPIMD_6[1:0]
GPIMD_7[1:0]
GPIMD_8[1:0]
GPIMD_9[1:0]
GPIMD_10[1:0]
GPIMD_11[1:0]
DESCRIPTION
GPI interrupt request mode for ports 0 to 11
•ꢀ Each input port is controlled by GPIMD, a 2-bit code.
9:8
•ꢀ For a given port i (0≤i≤11):
11:10
13:12
15:14
7:6
•ꢀ GPIMD_i[1:0] = 00: GPIST[i] is never asserted
•ꢀ GPIMD_i[1:0] = 01: GPIST[i] is asserted upon detection of a positive edge
•ꢀ GPIMD_i[1:0] = 10: GPIST[i] is asserted upon detection of a negative edge
•ꢀ GPIMD_i[1:0] = 11: GPIST[i] is asserted upon detection of a positive or a negative edge
9:8
11:10
13:12
15:14
1:0
Device Control Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
ADC conversion mode selection
•ꢀ 00: Idle mode – TheADC does not perform any conversion.
•ꢀ 01: Single sweep – TheADC performs one conversion for each of theADC-configured
ports sequentially. The assertion of CNVT triggers the single sweep. The sweep starts with
theADC-configured port of lowest index and stops with theADC-configured port of highest
index.
1:0
ADCCTL[1:0]
•ꢀ 10: Single conversion – TheADC performs one conversion for the current port. It starts with
the lowest index port that isADC-configured, and it progresses to higher index ports as
CNVT is asserted.
•ꢀ 11: Continuous sweep – This mode is not controlled by CNVT. TheADC continuously
sweeps theADC-configured ports.
DAC mode selection
•ꢀ 00: Sequential update mode for DAC-configured ports.
•ꢀ 01: Immediate update mode for DAC-configured ports. The DAC-configured port that
received new data is the next port to be updated. After updating that port, the DAC-
configured port update sequence continues from that port onward. Aminimum of 80µs must
be observed before requesting another immediate update.
•ꢀ 10:All DAC-configured ports use the same data stored in DACPRSTDAT1[11:0].
•ꢀ 11:All DAC-configured ports use the same data stored in DACPRSTDAT2[11:0].
3:2
5:4
DACCTL[1:0]
ADC conversion rate selection
•ꢀ 00:ADC conversion rate of 200ksps (default)
•ꢀ 01:ADC conversion rate of 250ksps
•ꢀ 10:ADC conversion rate of 333ksps
•ꢀ 11:ADC conversion rate of 400ksps
ADCCONV[1:0]
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Device Control Register (Read/Write) (continued)
BIT
FIELD NAME
DESCRIPTION
DAC voltage reference selection
•ꢀ 0: External reference voltage
•ꢀ 1: Internal reference voltage
6
DACREF
Thermal shutdown enable
•ꢀ 0: Thermal shutdown function disabled.
7
THSHDN
•ꢀ 1: Thermal shutdown function enabled. If the internal temperature monitor is enabled, and
if the internal temperature is measured to be larger than 145°C, the device is reset, thus
bringing all channels to high-impedance mode and setting all registers to their default value.
Temperature monitor selection
•ꢀ TMPCTL[0]: Internal temperature monitor (0: disabled; 1: enabled)
•ꢀ TMPCTL[1]: 1st external temperature monitor (0: disabled; 1: enabled)
•ꢀ TMPCTL[2]: 2nd external temperature monitor (0: disabled; 1: enabled)
10:8
TMPCTL[2:0]
Temperature conversion time control
•ꢀ 0: Default conversion time setting. Selected for junction capacitance filter < 100pF.
11
12
TMPPER
•ꢀ
1: Extended conversion time setting. Selected for junction capacitance filter from 100pF to
390pF
Temperature sensor series resistor cancellation mode
•ꢀ 0: Temperature sensor series resistance cancellation disabled.
•ꢀ 1: Temperature sensor series resistance cancellation enabled.
RS_CANCEL
Power mode selection
•ꢀ 0: Default power mode for normal operations
13
LPEN
•ꢀ 1: Lower power mode. The analog ports are in high-impedance mode. The device can be
brought out of the lower power mode by deasserting this bit. The device would then undergo
the regular power-on sequence.
Serial interface burst-mode selection
•ꢀ 0: Default address incrementing mode. The address is automatically incremented by “1” in
burst mode.
•ꢀ 1: Contextual address incrementing mode. In burst mode, the address automatically points
to the next ADC- or DAC-configured port data register. Specifically, when reading ADC data
(writing DAC data), the serial interface reads (writes to) only the data registers of those ports
that are ADC-configured (DAC-configured). This mode applies to ADC data read and DAC
data write, not DAC data read.
14
15
BRST
Soft reset control
•ꢀ Self-clearing soft reset register, equivalent to power-on reset.
RESET
GPI Data Registers (Read)
BIT
FIELD NAME
DESCRIPTION
Data received on GPI ports 0 to 11
•ꢀ The data received on GPI-configured ports can be read by the host.
•ꢀ For a given port i (0≤i≤11)
7:2
15:11
0
GPIDAT[5:0]
GPIDAT[10:6]
GPIDAT[11]
•ꢀ GPIDAT[i] = 0:Alogic zero level is received at GPI port i
•ꢀ GPIDAT[i] = 1:Alogic one level is received at GPI port i
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
GPO Data Registers (Read/Write)
BIT
FIELD NAME
DESCRIPTION
Data transmitted through GPO ports 0 to 11
•ꢀ Data written by the host to be transmitted through the GPO-configured ports
•ꢀ For a given port i (0 ≤ I ≤ 11):
7:2
15:11
0
GPODAT[5:0]
GPODAT[10:6]
GPODAT[11]
•ꢀ GPIDAT[i] = 0:Alogic zero level is transmitted through GPO port i
•ꢀ GPIDAT[i] = 1:Alogic one level is transmitted through GPO port i
DAC Preset Data Registers (Read/Write)
BIT
FIELD NAME
DESCRIPTION
DAC preset data register 1 and 2
•ꢀ DAC data used by all ports configured in a DAC-related mode (1, 3, 4, 5, 6, and 10)
•ꢀ Writing to these registers does not alter the contents of the DAC data registers
11:0
11:0
DACPRSTDAT1[11:0]
DACPRSTDAT2[11:0]
Temperature Monitor Configuration Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
Number of samples averaged for calculating the internal temperature
•ꢀ 00: 4 samples
•ꢀ 01: 8 samples
•ꢀ 10: 16 samples
•ꢀ 11: 32 samples
1:0
TMPINTMONCFG[1:0]
Number of samples averaged for calculating the 1st external temperature
•ꢀ 00: 4 samples
•ꢀ 01: 8 samples
•ꢀ 10: 16 samples
•ꢀ 11: 32 samples
3:2
5:4
TMPEXT1MONCFG[1:0]
TMPEXT2MONCFG[1:0]
Number of samples averaged for calculating the 2nd external temperature
•ꢀ 00: 4 samples
•ꢀ 01: 8 samples
•ꢀ 10: 16 samples
•ꢀ 11: 32 samples
Internal Temperature Monitor High Threshold Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
Internal temperature monitor high threshold
•ꢀ Maximum temperature value beyond which TMPINT[2] is asserted.
•ꢀ This value is represented in two’s complement; one LSB represents 0.125°C.
11:0
TMPINTHI[11:0]
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Internal Temperature Monitor Low Threshold Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
Internal temperature monitor low threshold
11:0
TMPINTLO[11:0]
•ꢀ Minimum temperature value below which TMPINT[1] is asserted.
•ꢀ This value is represented in two’s complement; one LSB represents 0.125°C.
1st External Temperature Monitor High Threshold Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
1st external temperature monitor high threshold
11:0
TMPEXT1HI[11:0]
•ꢀ Maximum temperature value beyond which TMPEXT1[2] is asserted.
•ꢀ This value is represented in two’s complement; one LSB represents 0.125°C.
1st External Temperature Monitor Low Threshold Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
1st external temperature monitor low threshold
11:0
TMPEXT1LO[11:0]
•ꢀ Minimum temperature value below which TMPEXT1[1] is asserted.
•ꢀ This value is represented in two’s complement; one LSB represents 0.125°C.
2nd External Temperature Monitor High Threshold Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
2nd external temperature monitor high threshold
11:0
TMPEXT2HI[11:0]
•ꢀ Maximum temperature value beyond which TMPEXT2[2] is asserted.
•ꢀ This value is represented in two’s complement; one LSB represents 0.125°C.
2nd External Temperature Monitor Low Threshold Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
2nd external temperature monitor low threshold
11:0
TMPEXT2LO[11:0]
•ꢀ Minimum temperature value below which TMPEXT2[1] is asserted.
•ꢀ This value is represented in two’s complement; one LSB represents 0.125°C.
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Port Configuration Registers (Read/Write)
BIT
FIELD NAME
DESCRIPTION
FUNCPRM_i[4:0]: ASSOCIATED PORT
•ꢀ Defines the port to use in conjunction with a port configured in mode 4, 8, or 11.
•ꢀ The associated port addresses are :
FUNCPRM_i[7:5]: # OF SAMPLES (for ADC-related functional modes only)
•ꢀ Defines the number of samples to be captured and averaged before loading the result in the
port’sADC data register. The coding of the number of samples is 2# OF SAMPLES.
The number of samples to average can be 1, 2, 4, 8, 16, 32, 64, or 128.
Associated Port Name
Corresponding Address
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
0x02
0x03
0x04
0x05
0x06
0x07
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
FUNCPRM_0[11:0]
FUNCPRM_1[11:0]
FUNCPRM_2[11:0]
FUNCPRM_3[11:0]
FUNCPRM_4[11:0]
FUNCPRM_5[11:0]
FUNCPRM_6[11:0]
FUNCPRM_7[11:0]
FUNCPRM_8[11:0]
FUNCPRM_9[11:0]
FUNCPRM_10[11:0]
FUNCPRM_11[11:0]
11:0
FUNCPRM_i[10:8]: RANGE
•ꢀ Determines the input voltage range of ports configured in input modes, or the output voltage
range of ports configured in output modes.
•ꢀ InADC- or DAC-related modes, RANGE cannot be set to 000.
VOLTAGE RANGE CODES
ADC VOLTAGE RANGE (V)
No Range Selected
0 to +10
DAC VOLTAGE RANGE (V)
No Range Selected
0 to +10
000
001
010
011
100
101
110
111
-5 to +5
-5 to +5
-10 to 0
-10 to 0
0 to +2.5
-5 to +5
Reserved
Reserved
0 to +2.5
0 to +10
Reserved
Reserved
FUNCPRM_i[11]: AVR (for mode 6 only)
•ꢀ ADC voltage reference selection
•ꢀ 0:ADC internal voltage reference
•ꢀ 1: ADC DAC voltage reference determined by DACREF
FUNCPRM_i[11]: INV (for GPI-controlled functional modes only)
•ꢀ Asserted to invert the data received by the GPI-configured port.
•ꢀ 0: Data received from GPI-configured port is not inverted
•ꢀ 1: Data received from GPI-configured port is inverted
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Port Configuration Registers (Read/Write) (continued)
BIT
FIELD NAME
DESCRIPTION
Functional mode for port i (0≤i≤11)
•ꢀ When switching from one mode to another, it is recommended to first switch to the high-
impedance mode. The duration for which the device may need to stay in the transitional high-
impedance mode depends on the application and hardware configuration.
•ꢀ 0000: Mode 0 - High impedance
•ꢀ The port is configured in high-impedance mode.
FUNCID_0[3:0]
FUNCID_1[3:0]
FUNCID_2[3:0]
FUNCID_3[3:0]
FUNCID_4[3:0]
FUNCID_5[3:0]
FUNCID_6[3:0]
FUNCID_7[3:0]
FUNCID_8[3:0]
FUNCID_9[3:0]
FUNCID_10[3:0]
FUNCID_11[3:0]
•ꢀ 0001: Mode 1 - Digital input with programmable threshold, GPI (Figure 7)
•ꢀ The port is configured as a GPI whose threshold is set through the DAC data register.
The DAC data register for that port needs to be set to the value corresponding to the
intended input threshold voltage. Any input voltage above that programmed threshold is
reported as a logic one. The input voltage must be between 0V and 5V.
15:12
•ꢀ
To avoid false interrupts, the port’s GPIERMSK register bit must be asserted. The DAC
data register can then be set for the desired threshold voltage. It may take up to 1ms for
the threshold voltage to be effective. The port’s GPIMD register bit is set next. At that
point, GPIERMSK can be deasserted for the port to start detecting events. The data
resulting from the comparison between the threshold voltage and the voltage at the port
can be read from the corresponding GPIDAT register bit.
•ꢀ 0010: Mode 2 - Bidirectional level translator terminal (Figure 10)
•ꢀ Any pair of adjacent ports can form a bidirectional level translator path. Only the lower
index port of the pair needs to be configured to enable this mode. The other port (index
+ 1) must be set in high-impedance mode.
•ꢀ Ports 5 and 11 cannot be set in mode 2.
•ꢀ The activity on this port is observable through its GPI path. The GPI-related registers are
configured as described for mode 1.
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Port Configuration Registers (Read/Write) (continued)
BIT
FIELD NAME
DESCRIPTION
•ꢀ 0011: Mode 3 - Register-driven digital output with DAC-controlled level, GPO (Figure 8)
•ꢀ
The port is configured as a GPO driven by the corresponding GPODAT register bit.
The logic one level is set by the DAC data register of that port.
•ꢀ The port’s DAC data register needs to be set first. It may require up to 1ms for the
port to be ready to produce the desired logic one level. At that point, the port can
be set in mode 3. The logic level at the port is then controlled by the corresponding
GPODAT register bit.
•ꢀ 0100: Mode 4 - Unidirectional path output with DAC-controlled level, GPO (Figure 9)
•ꢀ The port is configured as a GPO forming the output of a unidirectional level
translator path. The input port of that path is specified by the functional parameter,
ASSOCIATED PORT, and that port must be separately configured in GPI mode. The
port’s DAC data register defines the logic one level. The data received by the GPI-
configured port is transmitted by this port configured in mode 4.
•ꢀ The data from the associated GPI-configured port can be inverted by asserting the
functional parameter INV.
•ꢀ Multiple ports configured in mode 4 can refer to the same GPI-configured port
through the functional parameter, ASSOCIATED PORT. Therefore, one GPI-
configured port can transmit its data to multiple ports configured in mode 4.
•ꢀ
To avoid false interrupts and unexpected activity at the port configured in mode 4,
the GPI port must be configured before this port is configured in mode 4.
•ꢀ Functional parameters to be set: INV, ASSOCIATED PORT
•ꢀ 0101: Mode 5 - Analog output for DAC (Figure 5)
The port’s DAC data register must be set for the desired voltage at the port. It may
take up to 1ms for the port to reflect the data written in the DAC data register.
•ꢀ Functional parameters to be set: RANGE (codes 001, 010, and 011 apply to this
mode).
•ꢀ 0110: Mode 6 - Analog output for DAC with ADC monitoring (Figure 6)
•ꢀ In addition to the functionality of mode 5, the port is sampled by theADC. The result
of theADC conversion is stored in the port’sADC data register. The host can access
that register to monitor the voltage at the port.
•ꢀ When theADC input voltage range is set from 0V to 2.5V, (RANGE = 100 or 110), the
DAC data register value must be limited to the range of values corresponding to 0V
to 2.5V at the port. Internally, the DAC data register value is clipped, so that the PIXI
port voltage is contained within a range from 0V to 5V to prevent device damage.
•ꢀ Functional parameters to be set:AVR, RANGE
•ꢀ 0111: Mode 7 - Positive analog input to single-ended ADC (Figure 2)
•ꢀ The port is configured as a single-ended ADC input.
•ꢀ Functional parameters to be set: RANGE, # OF SAMPLES
•ꢀ 1000: Mode 8 - Positive analog input to differential ADC (Figure 3)
•ꢀ The port is configured as a differentialADC positive input.
•ꢀ Functional parameters to be set: RANGE, # OF SAMPLES,ASSOCIATED PORT
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Port Configuration Registers (Read/Write) (continued)
BIT
FIELD NAME
DESCRIPTION
•ꢀ 1001: Mode 9 - Negative analog input to differential ADC
•ꢀ The port is configured as a differentialADC negative input.
•ꢀ The number of samples to average is defined by the associated positive port. The
functional parameter RANGE must be identical to that used by the corresponding
positive port.
•ꢀ Aport configured in mode 9 can be associated to more than one port configured in
mode 8.
•ꢀ Functional parameter to be set: RANGE
•ꢀ 1010: Mode 10 - Analog output for DAC and negative analog input to differential ADC
(Figure 4)
•ꢀ While this port drives the voltage corresponding to its DAC data register, it also
operates as the negative input for theADC.
•ꢀ The number of samples to average is defined by the associated positive port. The
functional parameter RANGE must be identical to that used by the corresponding
positive port.
•ꢀ Aport configured in mode 10 can be associated to more than one port configured in
mode 8.
•ꢀ When theADC input voltage range is set from 0V to 2.5V (RANGE = 100 or 110), the
DAC data register value must be limited to the range of values corresponding to 0V
to 2.5V at the port. Internally, the DAC data register value is clipped, so that the PIXI
port voltage is contained within a range from 0V to 5V to prevent device damage.
•ꢀ Functional parameter to be set: RANGE
•ꢀ 1011: Mode 11 - Terminal to GPI-controlled analog switch (Figure 11)
•ꢀ In this mode, two adjacent ports can be connected together through an analog
switch controlled by a GPI-configured port (designated by the functional parameter
ASSOCIATED PORT). This function involves three ports. The switch controlling port
needs to be separately configured in GPI mode. Only the port with the lower index
needs to be configured in mode 11. The port with the higher index can be configured
in any other mode, except mode 2. If the port of higher index operates in anADC-
related mode (mode 6, 7, 8, or 9), the signals applied to the port in mode 11 must
comply with the input voltage range for which the port of higher index is configured.
•ꢀ Ports 5 and 11 cannot be configured in mode 11, as there is no switch between ports
5and6 andbetweenports11and 0.
•ꢀ Functional parameters to be set: INV, ASSOCIATED PORT
•ꢀ 1100: Mode 12 - Terminal to register-controlled analog switch
•ꢀ This mode is identical to Mode 11, except that the switch remains closed as long as this
port is configured in mode 12.
Maxim Integrated
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Table 7. Port Functional Modes
FUNCID[3:0]
FUNCPRM[11:0]
MODE
DESCRIPTION
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
High impedance
Digital input with
programmable
threshold, GPI
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
1
2
3
4
Bidirectional level
translator terminal
Register-driven digital
output with DAC-
controlled level, GPO
Unidirectional path
output with DAC-
INV
ASSOCIATED PORT*
controlled level, GPO
0
0
1
1
0
1
1
0
RANGE
RANGE
5
6
Analog output for DAC
Analog output for DAC
withADC monitoring
0
0
0
0
Positive analog input to
single-endedADC
0
1
1
1
0
0
1
0
0
1
0
1
RANGE
RANGE
RANGE
# OF SAMPLES
# OF SAMPLES
7
8
Positive analog input to
differentialADC
ASSOCIATED PORT*
Negative analog input
to differentialADC
9
Analog output for DAC
and negative analog
input to differentialADC
(pseudo-differential
mode)
1
0
1
0
0
RANGE
10
Terminal to GPI-
controlled analog
switch
1
1
0
1
1
0
1
0
INV
ASSOCIATED PORT*
11
Terminal to register-
controlled analog
switch
12
*Port must be configured separately to a compatible mode.
Maxim Integrated
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
ADC Data Registers (Read)
BIT
FIELD NAME
DESCRIPTION
11:0
ADCDAT_0[11:0]
ADCDAT_1[11:0]
ADCDAT_2[11:0]
ADCDAT_3[11:0]
ADCDAT_4[11:0]
ADCDAT_5[11:0]
ADCDAT_6[11:0]
ADCDAT_7[11:0]
ADCDAT_8[11:0]
ADCDAT_9[11:0]
ADCDAT_10[11:0]
ADCDAT_11[11:0]
ADC data for port i (0≤i≤11)
•ꢀ 12-bit data produced by theADC when converting the analog input signal on port i.
•ꢀ The conversion result is represented in straight binary for ports configured in single-
ended mode (modes 6, 7), and in two’s complement for ports configured as an ADC
positive input (mode 8) in differential or pseudo-differential mode (mode 9). The ADC
data register of the port configured as an ADC negative input in differential (mode 9) or
pseudo-differential mode (mode 10) contains 0x0000.
DAC Data Registers
BIT
FIELD NAME
DESCRIPTION
DACDAT_0[11:0]
DACDAT_1[11:0]
DACDAT_2[11:0]
DACDAT_3[11:0]
DACDAT_4[11:0]
DACDAT_5[11:0]
DACDAT_6[11:0]
DACDAT_7[11:0]
DACDAT_8[11:0]
DACDAT_9[11:0]
DACDAT_10[11:0]
DACDAT_11[11:0]
DAC data for port i (0≤i≤11)
•ꢀ 12-bit DAC data for port i.
•ꢀ The data is represented in straight binary.
11:0
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Figure 12. Flow Chart for Initial Configuration of PIXI Ports
Maxim Integrated
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Configuration Software (GUI)
To simplify use of the MAX11312, Maxim has created a GUI for customers to easily configure the device for unique
application needs with a simple drag and drop. The software generates register addresses and corresponding register
values. Figure 13 shows an example of this software with a few function connections.
Figure 13. Example of GUI to Develop Configuration File
Maxim Integrated
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Configuration Software Output File
SUPPLY
VOLTAGE
AVSSIO
AVDDIO
DVDD
-2.5
12.5
3.3
5
AVDD
DAC_REF
2.5
2.5
ADC_EXT_REF
NAME
ADDRESS
0x0D
0x0E
0x10
0x11
VALUE
0x0000
0x0000
0x00c0
0xffff
DESCRIPTION
GPO data for PIXI ports P10 to P6 and P5 to P0
GPO data for PIXI port P11
gpo_data_P10P6_P5P0
gpo_data_P11
device_control
Device main control register
interrupt_mask
Interrupt mask register
gpi_irqmode_P5_P0
gpi_irqmode_P10_P6
gpi_irqmode_P11
dac_preset_data_1
dac_preset_data_2
tmp_mon_cfg
0x12
0x13
0x14
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x07ff
GPI ports P5 to P0 mode register
GPI ports P10 to P6 mode register
GPI port P11 mode register
DAC preset data #1
DAC preset data #2
Temperature monitor configuration
tmp_mon_int_hi_thresh
tmp_mon_int_lo_thresh
tmp_mon_ext1_hi_thresh
tmp_mon_ext1_lo_thresh
tmp_mon_ext2_hi_thresh
tmp_mon_ext2_lo_thresh
reserved_20
Internal temperature monitor high threshold
Internal temperature monitor low threshold
1st external temperature monitor high threshold
1st external temperature monitor low threshold
2nd external temperature monitor high threshold
2nd external temperature monitor low threshold
Configuration register for (reserved) N.C.
Configuration register for (reserved) N.C.
Configuration register for PIXI port P0 Single Ended ADC
Configuration register for PIXI port P1 DAC
Configuration register for PIXI port P2 Differential ADC (+)
Configuration register for PIXI port P3 Differential ADC (-)
Configuration register for PIXI port P4 DAC with ADC Monitoring
Configuration register for PIXI port P5 GPI
Configuration register for (reserved) N.C.
Configuration register for (reserved) N.C.
0x0800
0x07ff
0x0800
0x07ff
0x0800
0x0000
0x0000
0x7100
0x5100
0x9100
0x9100
0x6100
0x1000
0x0000
0x0000
reserved_21
port_cfg_p0
port_cfg_p1
port_cfg_p2
port_cfg_p3
port_cfg_p4
port_cfg_p5
reserved_28
reserved_29
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Configuration Software Output File (continued)
NAME
reserved_2A
ADDRESS
0x2A
VALUE
0x0000
0x3000
DESCRIPTION
Configuration register for (reserved) N.C.
Configuration register for PIXI port P6 GPO
port_cfg_p6
port_cfg_p7
0x2B
Configuration register for PIXI port P7 Software Controlled
Analog Switch
0x2C
0x2D
0x0000
0x0000
Configuration register for PIXI port P8 Software Controlled
Analog Switch
port_cfg_p8
port_cfg_p9
0x2E
0x2F
0x30
0x31
0x32
0x33
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x1000
0x4009
0x5100
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0666
0x0000
0x0000
0x0000
0x0666
Configuration register for PIXI port P9 Level Translator
Configuration register for PIXI port P10 Level Translator
Configuration register for PIXI port P11 DAC
Configuration register for (reserved) N.C.
Configuration register for (reserved) N.C.
Configuration register for (reserved) N.C.
DAC data register for (reserved) N.C.
port_cfg_p10
port_cfg_p11
reserved_31
reserved_32
reserved_33
reserved_60
reserved_61
DAC data register for (reserved) N.C.
dac_data_port_p0
dac_data_port_p1
dac_data_port_p2
dac_data_port_p3
dac_data_port_p4
dac_data_port_p5
reserved_68
DAC data register for PIXI port P0 Single Ended ADC
DAC data register for PIXI port P1 DAC
DAC data register for PIXI port P2 Differential ADC (+)
DAC data register for PIXI port P3 Differential ADC (-)
DAC data register for PIXI port P4 DAC with ADC Monitoring
DAC data register for PIXI port P5 GPI
DAC data register for (reserved) N.C.
reserved_69
DAC data register for (reserved) N.C.
reserved_6A
DAC data register for (reserved) N.C.
dac_data_port_p6
DAC data register for PIXI port P6 GPO
DAC data register for PIXI port P7 Software Controlled
Analog Switch
dac_data_port_p7
dac_data_port_p8
0x6C
0x6D
0x0000
0x0000
DAC data register for PIXI port P8 Software Controlled
Analog Switch
dac_data_port_p9
dac_data_port_p10
dac_data_port_p11
reserved_71
0x6E
0x6F
0x70
0x71
0x72
0x73
0x0666
0x0666
0x0000
0x0000
0x0000
0x0000
DAC data register for PIXI port P9 Level Translator
DAC data register for PIXI port P10 Level Translator
DAC data register for PIXI port P11 DAC
DAC data register for (reserved) N.C.
reserved_72
DAC data register for (reserved) N.C.
reserved_73
DAC data register for (reserved) N.C.
Maxim Integrated
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
10µF bypass capacitors. Bypass ADC_INT_REF and
DAC_REF to ground with capacitors whose values are
Layout, Grounding, Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the MAX11312 package. Noise in AVDD,
AGND, AVDDIO, AVSSIO, ADC_REF_INT, and DAC_
REF affects the device performance. Bypass AVDD,
DVDD, AVDDIO, and AVSSIO to ground with 0.1µF and
shown in the REF Electrical Characteristics table. Place
the bypass capacitors as close as possible to the respective
pins and minimize capacitor lead and trace lengths for
best supply-noise rejection. For optimum heat dissipation,
connect the exposed pad (EP) to a large copper area,
such as a ground plane.
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
-40°C to +105°C
-40°C to +105°C
PIN-PACKAGE
32 TQFN-EP*
32 TQFN-EP*
MAX11312GTJ+
MAX11312GTJ+T
+Denotes a lead(Pb)-free/RoHS-compliant package.
EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
LAND
PATTERN NO.
NO.
*T = Tape and reel.
32 TQFN-EP
T3255+9
21-0140
90-100015
Chip Information
PROCESS: BiCMOS
Maxim Integrated
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
2/16
7/19
Initial release
Updated TOC5–8
—
12
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 54
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