MAX11327ATJ+ [MAXIM]
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access;
| 型号： | MAX11327ATJ+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access 转换器 |
| 文件： | 总37页 (文件大小：1801K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
General Description
Benefits and Features
The MAX11321–MAX11328 are 12-/10-bit with external
reference and 500kHz, full-linear-bandwidth, high-speed,
low-power, serial-output successive approximation reg-
ister (SAR) analog-to-digital converters (ADCs). The
MAX11321–MAX11328 provide external access to the
output of the integrated mux and ADC input, to simplify
conditioning. The MAX11321–MAX11328 include both
internal and external clock modes. These devices feature
scan mode in both internal and external clock modes. The
internal clock mode features internal averaging to increase
SNR. The external clock mode features the SampleSetK
technology, a user-programmable analog input channel
sequencer. The SampleSet approach provides greater
sequencing flexibility for multichannel applications while
alleviating significant microcontroller or DSP (controlling
unit) communication overhead.
S Highly Integrated Precision ADC Saves Space
While Retaining Flexibility
ꢀ±± ꢀSꢁ IꢂꢀL ±± ꢀSꢁ DꢂꢀL ꢂo ꢃissing Codes
ꢀ70dꢁ SIꢂAD at ±00kHz
ꢀ±ꢃsps Conversion Rate with ꢂo Pipeline Delay
S
Analog ꢃultiplexer with True Differential Track/Hold:
Any Combination of Single-EndedL Differential and
Pseudo-Differential Input Pin Pairs Allowed
ꢀ±6-/8-/4-Channel Single-Ended
ꢀ±2-/8-/4-Channel Fully-Differential Pairs
ꢀ±5-/8-/4-Channel Pseudo-Differential Relative to
a Common Input
S Two Software-Selectable ꢁipolar Input Ranges:
±ꢄ +/2L ±ꢄ
+
REF
REF
S External Differential Reference (±ꢄ to ꢄ
S 32-PinL 5mm x 5mm TQFꢂ Package
)
DD
External pins provide access to the output of the
multiplexer and ADC inputs to simplify multichannel sig-
nal conditioning. The internal clock mode features an inte-
grated FIFO allowing data to be sampled at high speeds
and then held for readout at any time or at a lower clock
rate. Internal averaging is also supported in internal clock
mode improving SNR for noisy input signals. The devices
feature analog input channels that can be configured to
be single-ended inputs, fully differential pairs, or pseudo-
differential inputs with respect to one common input. The
MAX11321–MAX11328 operate from a 2.35V to 3.6V sup-
ply and consume only 5.4mW at 1Msps.
S SampleSet™ Technology ꢁrings Extreme
Flexibility to Program Input Configurations Per
Channel and Sampling Sequence to Optimize
Interface to the ꢃicrocontroller
ꢀUser-Defined Channel Sequence with ꢃaximum
ꢀength of 256
ꢀScan ꢃodesL Internal AveragingL and Internal Clock
ꢀ±6-Entry First-In/First-Out (FIFO)
S Post-ꢃux Signal Access Allows for External
Signal Conditioning ꢁetween the ꢃux and the
ADC Even for Differential Signals
The MAX11321–MAX11328 include AutoShutdownK,
fast wake-up, and a high-speed 3-wire serial interface.
The devices feature full power-down mode for optimal
power management. The 48MHz, 3-wire serial interface
ꢀExternally Accessible ꢃultiplex Output and ADC Input
S ꢀow-Power Consumption Extends ꢁattery ꢀife for
Portable Applications
M
directly connects to SPI, QSPIK, and MICROWIRE
ꢀ±.5ꢄ to 3.6ꢄ Digital I/O Supply ꢄoltage
ꢀ2.35ꢄ to 3.6ꢄ Supply ꢄoltage
ꢀ5.4mW at ±ꢃsps with 3ꢄ Supplies
ꢀ2μA Full-Shutdown Current
devices without external logic.
Excellent dynamic performance, low voltage, low power,
ease of use, and small package size make these convert-
ers ideal for portable battery-powered data-acquisition
applications, and for other applications that demand low
power consumption and small space.
S Easy to Interface with ꢃost ꢃicrocontrollers
ꢀ±6ꢃHzL 3-Wire SPI-/QSPI-/ꢃICROWIRE-/DSP-
Compatible Serial Interface
The MAX11321–MAX11328 are available in 32-pin, 5mm
x 5mm, TQFN packages and operate over the -40NC to
+125NC temperature range.
Applications
High-Speed Data
Medical Instrumentation
Acquisition Systems
SampleSet and AutoShutdown are trademarks of Maxim
Integrated Products, Inc.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor
Corp.
Battery-Powered
Instruments
High-Speed Closed-Loop
Systems
Portable Systems
Industrial Control Systems
Ordering Information appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6467; Rev 1; 12/14
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
AꢁSOꢀUTE ꢃAXIꢃUꢃ RATIꢂGS
DD
V
to GND.............................................................-0.3V to +4V
Continuous Power Dissipation (T = +70NC)
A
AOP, AON, AIP, AIN, OVDD, AIN0–AIN13, CNVST/AIN14, REF+,
REF-/AIN15 to GND....................................... -0.3V to the lower of
TQFN (derate 34.4mW/NC above +70NC)..................2758mW
Operating Temperature Range........................ -40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
(V
+ 0.3V) and +4V
DD
CS, SCLK, DIN, DOUT, EOC TO GND .......-0.3V to the lower of
(V + 0.3V) and +4V
OVDD
DGND to GND......................................................-0.3V to +0.3V
Input/Output Current (all pins) ...........................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERꢃAꢀ CHARACTERISTICS (ꢂote ±)
TQFN
Junction-to-Ambient Thermal Resistance (B )...........29NC/W
JA
Junction-to-Case Thermal Resistance (B )...............1.7NC/W
JC
ꢂote ±: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
EꢀECTRICAꢀ CHARACTERISTICS (ꢃAX±±322/ꢃAX±±325/ꢃAX±±328)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAꢃETER
DC ACCURACY (ꢂotes 3 and 4)
Resolution
SYꢃꢁOꢀ
COꢂDITIOꢂS
ꢃIꢂ
TYP
ꢃAX
UꢂITS
RES
INL
12 bit
12
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Q1.0
Q1.0
Q3.0
Q5.5
DNL
No missing codes
(Note 5)
LSB
1.2
0.02
Q2
LSB
Gain Error
LSB
Offset Error Temperature Coefficient
OE
GE
ppm/NC
TC
Gain Temperature Coefficient
Channel-to-Channel Offset Matching
Line Rejection
Q0.8
Q0.5
0.3
ppm/NC
LSB
TC
PSR
(Note 6)
Q2
LSB/V
DYꢂAꢃIC PERFORꢃAꢂCE (±00kHzL Input Sine Wave) (ꢂotes 3 and 7)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
70
70
71.9
72.3
dB
dB
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-83
-76
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
SFDR
IMD
77
84
-85
30
5
dB
dB
f = 99.2432kHz, f = 69.2139kHz
1
2
-3dB
Full-Power Bandwidth
Full-Linear Bandwidth
MHz
MHz
-0.1dB
SINAD ≥ 70dB
0.5
Maxim Integrated
2
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
EꢀECTRICAꢀ CHARACTERISTICS (ꢃAX±±322/ꢃAX±±325/ꢃAX±±328) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAꢃETER
SYꢃꢁOꢀ
COꢂDITIOꢂS
ꢃIꢂ
TYP
ꢃAX
UꢂITS
-0.5dB below full-scale of 99.2432kHz
sine wave input to the channel being
sampled, apply full-scale 69.2139kHz
sine wave signal to all 15 nonselected
input channels.
Crosstalk
-88
dB
COꢂꢄERSIOꢂ RATE
Power-Up Time
t
Conversion cycle, external clock
Internally clocked (Note 8)
2
Cycles
ns
PU
Acquisition Time
t
156
5.9
ACQ
µs
Conversion Time
t
CONV
Externally clocked, f
16 cycles (Note 8)
= 16MHz,
SCLK
1000
0.16
ns
External Clock Frequency
Aperture Delay
f
16
MHz
ns
SCLK
8
Aperture Jitter
RMS
30
ps
AꢂAꢀOG IꢂPUT
Unipolar, (single ended and pseudo-
differential)
0
V
REF+
Input Voltage Range
V
V
INA
Range bit set to 0
Range bit set to 1
-V
/2
V
/2
Bipolar
(Note 9)
REF+
REF+
-V
V
REF+
REF+
Absolute Input Voltage Range
Static Input Leakage Current
AIN+, AIN- relative to GND
= V , GND
-0.1
V
+ 0.1
V
REF+
I
V
-0.1
Q1.5
FA
ILA
AIN
DD
During acquisition time;
RANGE bit = 0 (Note 10)
15
Input Capacitance
C
pF
AIN
During acquisition time;
RANGE bit = 1 (Note 10)
7.5
EXTERꢂAꢀ REFEREꢂCE IꢂPUT
REF- Input Voltage Range
V
-0.3
1
+1
V
V
REF-
REF+ Input Voltage Range
V
V
+ 50mV
REF+
DD
V
V
= 2.5V, f
= 2.5V, f
= 1Msps
= 0Msps
36.7
0.1
REF+
SAMPLE
REF+ Input Current
I
FA
REF+
REF+
SAMPLE
DIGITAꢀ IꢂPUTS (SCꢀKL DIꢂL CSL CNVST)
V
OVDD
Input Voltage Low
Input Voltage High
Input Hysteresis
V
V
V
IL
O0.25
V
OVDD
V
IH
O0.75
V
OVDD
V
mV
HYST
O0.15
Maxim Integrated
3
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
EꢀECTRICAꢀ CHARACTERISTICS (ꢃAX±±322/ꢃAX±±325/ꢃAX±±328) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAꢃETER
Input Leakage Current
Input Capacitance
SYꢃꢁOꢀ
COꢂDITIOꢂS
= 0V or V
ꢃIꢂ
TYP
Q0.09
3
ꢃAX
UꢂITS
FA
I
V
Q1.0
IN
AIN
DD
C
pF
IN
DIGITAꢀ OUTPUTS (DOUTL EOC)
V
OVDD
Output Voltage Low
V
I
I
= 200FA
V
V
OL
SINK
O0.15
V
OVDD
Output Voltage High
V
= 200FA
SOURCE
OH
O0.85
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREꢃEꢂTS
Positive Supply Voltage
I
-0.3
4
Q1.5
FA
CS = V
CS = V
L
DD
C
pF
OUT
DD
V
2.35
1.5
3.0
3.0
1.8
1
3.6
3.6
2.5
V
V
DD
Digital I/O Supply Voltage
V
OVDD
f
f
= 1Msps
SAMPLE
SAMPLE
Positive Supply Current
I
= 0Msps (1Msps devices)
mA
DD
Full shutdown
0.0015 0.006
V
= 3V,
DD
5.4
Normal mode
(External
Reference)
f
= 1Msps
SAMPLE
V
= 2.35V,
DD
3.8
2.6
1.6
f
= 1Msps
SAMPLE
mW
V
= 3V,
DD
Power Dissipation
f
= 1Msps
SAMPLE
AutoStandby
V
= 2.35V,
DD
f
= 1Msps
SAMPLE
V
= 3V
4.5
2.1
Full/
AutoShutdown
DD
DD
FW
V
= 2.35V
TIꢃIꢂG CHARACTERISTICS (Figure ±) (ꢂote ±±)
SCLK Clock Period
SCLK Duty Cycle
t
Externally clocked conversion
62.4
40
4
ns
%
CP
CH
t
60
16.5
15
V
V
= 1.5V to 2.35V
= 2.35V to 3.6V
C
10pF
=
OVDD
OVDD
LOAD
SCLK Fall to DOUT Transition
t
ns
DOT
4
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
t
C
C
C
= 10pF, channel ID on
= 10pF, channel ID off
= 10pF
15
ns
ns
ns
ns
ns
DOD
LOAD
LOAD
LOAD
16
t
14
DOE
t
4
1
DS
SCLK Rise to DIN Hold
t
DH
Maxim Integrated
4
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
EꢀECTRICAꢀ CHARACTERISTICS (ꢃAX±±322/ꢃAX±±325/ꢃAX±±328) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAꢃETER
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
SYꢃꢁOꢀ
COꢂDITIOꢂS
ꢃIꢂ
4
TYP
ꢃAX
UꢂITS
ns
t
CSS
t
1
ns
CSH
t
See Figure 6
See Figure 7, f
5
ns
CSW
CS or CNVST Rise to EOC Low
(Note 6)
t
= 1Msps
SAMPLE
5.3
6.2
Fs
CNV_INT
t
5
ns
CS Pulse Width
CSBW
EꢀECTRICAꢀ CHARACTERISTICS (ꢃAX±±32±/ꢃAX±±324/ꢃAX±±327)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAꢃETER
DC ACCURACY (ꢂotes 3 and 4)
Resolution
SYꢃꢁOꢀ
COꢂDITIOꢂS
ꢃIꢂ
TYP
ꢃAX
UꢂITS
RES
INL
10 bit
10
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
0.4
0.4
1.2
1.5
DNL
No missing codes
(Note 5)
0.7
0
Gain Error
Offset Error Temperature
Coefficient
OE
GE
2
0.8
0.5
0.2
ppm/NC
ppm/NC
LSB
TC
TC
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
Line Rejection
PSR
(Note 6)
1.0
-75
LSB/V
DYꢂAꢃIC PERFORꢃAꢂCE (±00kHzL Input Sine Wave) (ꢂotes 3 and 7)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
61
61
61.5
61.5
dB
dB
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-82.5
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
SFDR
IMD
76
83.4
-83
30
dB
dB
f = 99.2432kHz, f = 69.2139kHz
1
2
-3dB
MHz
MHz
MHz
Full-Power Bandwidth
Full-Linear Bandwidth
-0.1dB
5
SINAD ≥ 61dB
0.5
Maxim Integrated
5
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
EꢀECTRICAꢀ CHARACTERISTICS (ꢃAX±±32±/ꢃAX±±324/ꢃAX±±327) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAꢃETER
SYꢃꢁOꢀ
COꢂDITIOꢂS
ꢃIꢂ
TYP
ꢃAX
UꢂITS
-0.5dB below full-scale of 99.2432kHz
sine-wave input to the channel being
sampled; apply full-scale 69.2139kHz sine
wave signal to all 15 nonselected
input channels
Crosstalk
-88
dB
COꢂꢄERSIOꢂ RATE
Power-Up Time
t
Conversion cycle, external clock
2
Cycles
ns
PU
Acquisition Time
t
156
5.9
ACQ
Internally clocked, f
(Note 8)
= 1Msps,
= 16MHz,
SAMPLE
µs
ns
Conversion Time
t
CONV
Externally clocked, f
16 cycles (Note 8)
SCLK
1000
0.16
External Clock Frequency
Aperture Delay
f
16
MHz
ns
SCLK
8
Aperture Jitter
RMS
30
ps
AꢂAꢀOG IꢂPUT
Unipolar (single-ended and pseudo
differential)
0
V
REF+
Input Voltage Range
V
V
-V
REF+
/2
+V
INA
REF+
/2
RANGE bit set to 0
Bipolar (Note 9)
RANGE bit set to 1
-V
+V
REF+
REF+
V
+ 0.1
REF+
Absolute Input Voltage Range
Static Input Leakage Current
AIN+, AIN- relative to GND
-0.1
V
I
V
= V , GND
-0.1
1.5
FA
ILA
AIN_
DD
During acquisition time,
RANGE bit = 0 (Note 10)
15
Input Capacitance
C
pF
AIN
During acquisition time,
RANGE bit = 1 (Note 10)
7.5
EXTERꢂAꢀ REFEREꢂCE IꢂPUT
REF- Input Voltage Range
V
-0.3
1
+1
V
V
REF-
V
DD
REF+ Input Voltage Range
REF+ Input Current
V
REF+
+50mV
V
V
= 2.5V, f
= 2.5V, f
= 1Msps
= 0Msps
36.7
0.1
FA
FA
REF+
REF+
SAMPLE
I
REF+
SAMPLE
DIGITAꢀ IꢂPUTS (SCꢀKL DIꢂL CSL CNVST)
V
OVDD
Input Voltage Low
V
V
IL
O0.25
Maxim Integrated
6
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
EꢀECTRICAꢀ CHARACTERISTICS (ꢃAX±±32±/ꢃAX±±324/ꢃAX±±327) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAꢃETER
Input Voltage High
SYꢃꢁOꢀ
COꢂDITIOꢂS
ꢃIꢂ
TYP
ꢃAX
UꢂITS
V
OVDD
O0.75
V
V
IH
V
OVDD
Input Hysteresis
V
mV
HYST
O0.15
0.09
3
Input Leakage Current
I
V
= 0V or V
1.0
FA
IN
AIN_
DD
Input Capacitance
C
pF
IN
DIGITAꢀ OUTPUTS (DOUTL EOC)
V
OVDD
Output Voltage Low
Output Voltage High
V
I
I
= 200FA
V
V
OL
SINK
O0.15
V
OVDD
V
= 200FA
SOURCE
OH
O0.85
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREꢃEꢂTS
Positive Supply Voltage
I
-0.3
4
1.5
FA
CS = V
CS = V
L
DD
C
pF
OUT
DD
V
2.35
1.5
3.0
3.0
1.8
1
3.6
3.6
2.5
V
V
DD
Digital I/O Supply Voltage
V
OVDD
f
f
= 1Msps
SAMPLE
SAMPLE
Positive Supply Current
I
= 0Msps (1Msps devices)
mA
DD
Full shutdown
0.0015 0.006
V
= 3V,
DD
5.4
Normal mode
(external
reference)
f
= 1Msps
SAMPLE
V
= 2.35V,
DD
3.8
2.6
1.6
f
= 1Msps
SAMPLE
mW
V
= 3V,
DD
Power Dissipation
f
= 1Msps
SAMPLE
AutoStandby
V
= 2.35V,
DD
f
= 1Msps
SAMPLE
V
= 3V
4.5
2.1
Full/
AutoShutdown
DD
DD
FW
V
= 2.35V
TIꢃIꢂG CHARACTERISTICS (Figure ±) (ꢂote ±±)
SCLK Clock Period
SCLK Duty Cycle
t
Externally clocked conversion
62.4
40
4
ns
%
CP
CH
t
60
16.5
15
V
V
= 1.5V to 2.35V
= 2.35V to 3.6V
C
10pF
=
OVDD
LOAD
SCLK Fall to DOUT Transition
t
ns
DOT
4
OVDD
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
t
C
C
C
= 10pF, channel ID on
= 10pF, channel ID off
= 10pF
15
ns
ns
ns
DOD
LOAD
LOAD
LOAD
16
t
14
DOE
Maxim Integrated
7
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
EꢀECTRICAꢀ CHARACTERISTICS (ꢃAX±±32±/ꢃAX±±324/ꢃAX±±327) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAꢃETER
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
SYꢃꢁOꢀ
COꢂDITIOꢂS
ꢃIꢂ
4
TYP
ꢃAX
UꢂITS
ns
t
DS
t
1
ns
DH
t
t
4
ns
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
CSS
1
ns
CSH
CSW
t
See Figure 6
5
ns
CS or CNVST Rise to EOC Low
(Note 7)
t
See Figure 7, f
= 1Msps
5.3
6.2
Fs
CNV_INT
SAMPLE
t
5
ns
CS Pulse Width
CSBW
ꢂote 2: Limits are 100% production tested at T = +25NC. Limits over the operating temperature range are guaranteed by design.
A
Parts are tested with MUX externally connected to the ADC input.
ꢂote 3: Channel ID disabled.
ꢂote 4: Tested in single-ended mode.
ꢂote 5: Offset nulled.
ꢂote 6: Line rejection D(D
) with V
= 2.35V to 3.6V and V
= 2.35V.
OUT
DD
REF+
ꢂote 7: Tested and guaranteed with fully differential input.
ꢂote 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Maximum conversion time: 4.73Fs + N x 16 x t
OSC_MAX
t
= 88.2ns, t
= 75ns.
OSC_MAX
OSC_TYP
ꢂote 9: The operational input voltage range for each individual input of a differentially configured pair is from V
to GND. The
DD
operational input voltage difference is from -V
ꢂote ±0: See Figure 3 (Equivalent Input Circuit).
ꢂote ±±: Guaranteed by characterization.
/2 to +V
/2 or -V
to +V
.
REF+
REF+
REF+
REF+
t
CSBW
CS
t
t
t
CP
CSH
CSS
t
CH
1ST
CLOCK
SCLK
16TH
CLOCK
t
DH
t
DS
t
DOT
DIN
t
DOD
t
DOE
DOUT
Figure 1. Detailed Serial-Interface Timing Diagram
Maxim Integrated
8
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Typical Operating Characteristics
(MAX11322ATJ+/MAX11325ATJ+/MAX11328ATJ+, T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
OFFSET ERROR
vs. TEMPERATURE
1.0
0.8
1.0
0.5
0
3
2
f
= 1Msps
f
= 1Msps
SAMPLE
SAMPLE
0.6
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-0.5
-1.0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
DIGITAL OUTPUT CODE (DECIMAL)
DIGITAL OUTPUT CODE (DECIMAL)
HISTOGRAM FOR 30,000
CONVERSIONS
SNR AND SINAD
vs. ANALOG INPUT FREQUENCY
GAIN ERROR
vs. TEMPERATURE
35,000
30,000
25,000
20,000
15,000
10,000
5,000
0
3
2
74.0
73.5
73.0
72.5
72.0
71.5
71.0
f
= 1Msps
f
= 1Msps
SAMPLE
SAMPLE
30,000 CODE HITS
1
SNR
0
-1
-2
-3
SINAD
0
2046 2047 2048 2049 2050
OUTPUT CODE (DECIMAL)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
20
40
60
(kHz)
80
100
f
IN
THD vs. ANALOG INPUT FREQUENCY
SFDR vs. ANALOG INPUT FREQUENCY
-80
-85
-90
-95
96
f
= 1Msps
f
= 1Msps
SAMPLE
SAMPLE
94
92
90
88
86
84
82
80
0
20
40
60
(kHz)
80
100
0
20
40 60
f (kHz)
IN
80
100
f
IN
Maxim Integrated
9
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Typical Operating Characteristics (continued)
(MAX11322ATJ+/MAX11325ATJ+/MAX11328ATJ+, T = +25°C, unless otherwise noted.)
A
SNR vs. INPUT RESISTANCE
SINAD vs. INPUT RESISTANCE
THD vs. INPUT RESISTANCE
73.0
72.5
72.0
71.5
71.0
73
72
71
70
-70
-75
-80
-85
-90
f
= 1Msps
= 100kHz
SAMPLE
BUFFER BETWEEN AOP AND AIP
BUFFER BETWEEN AON AND AIN
f
IN
BUFFER BETWEEN AOP AND AIP
BUFFER BETWEEN AON AND AIN
AOP SHORTED TO AIP
AON SHORTED TO AIN
AOP SHORTED TO AIP
AON SHORTED TO AIN
AOP SHORTED TO AIP
AON SHORTED TO AIN
BUFFER BETWEEN AOP AND AIP
BUFFER BETWEEN AON AND AIN
f
= 1Msps
= 100kHz
f
= 1Msps
f = 100kHz
IN
SAMPLE
SAMPLE
f
IN
0
1000
2000
R
3000
4000
4500
5000
0
1000
2000
R
3000
4000
4500
5000
0
1000
2000
R
3000
4000
5000
500
1500
2500
3500
500
1500
2500
3500
500
1500
2500
3500
4500
(I)
(I)
(I)
IN
IN
IN
REFERENCE CURRENT
vs. SAMPLING RATE
100kHz SINE-WAVE INPUT
(8192 POINT FFT PLOT)
SFDR vs. INPUT RESISTANCE
90
85
80
75
50
40
30
20
10
0
0
-20
f
= 1Msps
SAMPLE
f
IN
= 100kHz
BUFFER BETWEEN AOP AND AIP
BUFFER BETWEEN AON AND AIN
-40
AHD3 = -86.69dB
f = 300kHz
-60
AOP SHORTED TO AIP
AON SHORTED TO AIN
A
= -102.99dB
HD2
f = 200kHz
-80
-100
-120
f
= 1Msps
= 100kHz
SAMPLE
f
IN
0
1000
2000
R
3000
4000
3500 4500
5000
0
500
1000
0
50 100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
500
1500
2500
f
(ksps)
SAMPLE
(I)
IN
SUPPLY CURRENT vs. TEMPERATURE
SNR vs. REFERENCE VOLTAGE
3.0
2.5
2.0
1.5
1.0
74
73
72
71
70
69
f
= 1Msps
SAMPLE
V
= 3.0V
DD
f = 1Msps
SAMPLE
= 100kHz
f
IN
68
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
1.0
1.4
1.8
2.2
2.6
3.0
3.4
V
REFP
(V)
Maxim Integrated
10
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Pin Configurations
TOP VIEW
24 23 22 21 20 19 18 17
24 23 22 21 20 19 18 17
16
15
16
15
DGND 25
OVDD 26
REF-
DGND 25
OVDD 26
REF-
CNVST
CNVST
14 AIN
14 AIN
27
28
29
30
31
32
27
28
29
30
31
32
DOUT
EOC
DOUT
EOC
AIP
AIP
13
12
13
12
MAX11321
MAX11322
MAX11324
MAX11325
AIN0
AIN1
AIN2
AIN3
AON
AIN0
AIN1
AIN2
AIN3
AON
11 AOP
11 AOP
10
9
10
9
GND
GND
GND
GND
+
+
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TQFN
4 CHANNEL
TQFN
8 CHANNEL
TOP VIEW
24 23 22 21 20 19 18 17
16
15
DGND 25
OVDD 26
REF-/AIN15
CNVST/AIN14
14 AIN
27
28
29
30
31
32
DOUT
EOC
AIP
13
12
MAX11327
MAX11328
AIN0
AIN1
AIN2
AIN3
AON
11 AOP
10
9
AIN13
AIN12
+
1
2
3
4
5
6
7
8
TQFN
16 CHANNEL
Maxim Integrated
11
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Pin Description
ꢃAX±±32±
ꢃAX±±322
ꢃAX±±324
ꢃAX±±325
ꢃAX±±327
ꢃAX±±328
ꢂAꢃE
FUꢂCTIOꢂ
(4 CHAꢂꢂEꢀ) (8 CHAꢂꢂEꢀ) (±6 CHAꢂꢂEꢀ)
1–10, 17, 19
5–10, 17, 19
17, 19
11
GND
AOP
AON
AIP
Ground
11
12
13
14
15
16
11
12
13
14
15
16
Positive Output from the Multiplexer
Negative Output from the Multiplexer
Positive Input to the ADC
12
13
14
AIN
Negative Input to the ADC
—
Active-Low Conversion Start Input
External Differential Reference Negative Input
CNVST
—
REF-
External Positive Reference Input. Apply a reference voltage at
REF+. Bypass to GND with a 0.47FF capacitor.
18
18
18
REF+
Power-Supply Input. Bypass to GND with a 10FF in parallel with
a 0.1FF capacitors.
20, 21
22
20, 21
22
20, 21
22
V
DD
SCLK
Serial Clock Input. Clocks data in and out of the serial interface.
Active-Low Chip Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high impedance
or three-state.
23
23
23
CS
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
24
25
26
24
25
26
24
25
26
DIN
DGND
OVDD
Digital I/O Ground
Digital Power-Supply Input. Bypass to GND with a 10FF in
parallel with a 0.1FF capacitors.
Serial Data Output. Data is clocked out on the falling edge of
SCLK. When CS is high, DOUT is high impedance or three-
state.
27
27
27
DOUT
End of Conversion Output. Data is valid after EOC is driven low
(internal clock mode only).
28
28
—
28
—
EOC
29–32
AIN0–AIN3 Analog Inputs
—
—
—
29–32 , 1–10
—
AIN0–AIN13 Analog Inputs
AIN0–AIN7 Analog Inputs
29–32, 1–4
CNVST/
AIN14
—
—
—
—
—
—
15
16
—
Active-Low Conversion Start Input/Analog Input 14
REF-/AIN15 External Differential Reference Negative Input /Analog Input 15
Exposed Pad. Connect EP directly to GND plane for guaranteed
performance.
EP
Maxim Integrated
12
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Functional Diagrams
HIGH-INPUT IMPEDANCE
PGA/FILTER/BUFFER
AOP AON
AIN AIP
REF+ REF-
AIN0
AIN1
AIN2
AIN3
REF+
ADC
REF-
CS
SCLK
SINGLE-
ENDED/
DIFFERENTIAL
BUS
OSCILLATOR
I/P
MUX
CS
SCLK
DIN
AIN(N-1)
AIN(N)
CONTROL LOGIC
AND
SEQUENCER
DOUT
CNVST
EOC
MAX11321–MAX11328
Maxim Integrated
13
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Functional Diagrams (continued)
AOP AON
AIN AIP
REF+ REF-
AIN0
AIN1
AIN2
AIN3
REF+
ADC
REF-
CS
SCLK
SINGLE-
ENDED/
OSCILLATOR
DIFFERENTIAL
BUS
I/P
MUX
CS
SCLK
DIN
AIN(N-1)
AIN(N)
CONTROL LOGIC
AND
SEQUENCER
DOUT
CNVST
EOC
MAX11321–MAX11328
is also supported in this mode improving SNR for noisy
input signals. All input channels are configurable for sin-
gle-ended, fully differential or pseudo-differential inputs
in unipolar or bipolar mode. The MAX11321–MAX11328
operate from a 2.35V to 3.6V supply and consume only
5.4mW at 1Msps.
Detailed Description
The MAX11321–MAX11328 are 12-/10-bit with external
reference and industry-leading 500kHz, full linear band-
width, high-speed, low-power, serial output successive
approximation register (SAR) analog-to-digital converters
(ADC). These devices feature scan mode, internal aver-
aging to increase SNR, and AutoShutdown.
The MAX11321–MAX11328 include AutoShutdown, fast
wake-up, and a high-speed 3-wire serial interface. The
devices feature full power-down mode for optimal power
management.
The external clock mode features the SampleSet technol-
ogy, a user-programmable analog input channel sequenc-
er. The user may define and load a unique sequencing
pattern into the ADC allowing both high- and low-frequen-
cy inputs to be converted without interface activity. This
feature frees the controlling unit for other tasks while lower-
ing overall system noise and power consumption.
Data is converted from analog voltage sources in a
variety of channel and data-acquisition configurations.
Microprocessor (FP) control is made easy through a 3-wire
SPI-/QSPI-/MICROWIRE-compatible serial interface.
AOP and AON are the output pins of the internal multi-
plexer while AIP and AIN are the ADC inputs which are all
accessible externally through pins. This allows flexibility
to the system designer to process all signals through one
PGA (programmable gain amplifier), filter or gain stage
The MAX11321–MAX11328 include internal clock. The
internal clock mode features an integrated FIFO, allowing
data to be sampled at high speed and then held for read-
out at any time or at a lower clock rate. Internal averaging
Maxim Integrated
14
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
in single-ended or differential configuration. The external
buffering stage should be designed to properly drive the
input sampling network of the ADC.
mode to generate the serial clock signal. Select the SCLK
frequency of 48MHz or less, and set clock polarity (CPOL)
and phase (CPHA) in the control registers to the same
value. The MAX11321–MAX11328 operate with SCLK
idling high, and thus operate with CPOL = CPHA = 1.
The external buffer should also have very high input
impedance (low-leakage current) to ensure best linearity.
If additional signal processing is not required, connect
AOP to AIP and AON to AIN. It is recommended to limit
the source impedance to not affect the sampling accu-
racy of the ADC causing degradation in linearity and total
harmonic distortion. See the SINAD vs. Input Resistance
graph in the Typical Operating Characteristics.
Set CS low to latch input data at DIN on the rising edge
of SCLK. Output data at DOUT is updated on the falling
edge of SCLK. A high-to-low transition on CS samples
the analog inputs and initiates a new frame. A frame is
defined as the time between two falling edges of CS.
There is a minimum of 16 bits per frame. The serial data
input, DIN, carries data into the control registers clocked
in by the rising edge of SCLK. The serial data output,
DOUT, delivers the conversion results and is clocked out
by the falling edge of SCLK. DOUT is a 16-bit data word
containing a 4-bit channel address, followed by a 12-bit
conversion result led by the MSB when CHAN_ID is set
to 1 in the ADC Mode Control register (Figure 2a). When
CHAN_ID is set to 1 keep the SCLK high for at least 25ns
before the CS falling edge (Figure 2b). When CHAN_ID is
set to 0 (external clock mode only), the 16-bit data word
includes a leading zero and the 12-bit conversion result
is followed by 3 trailing zeros (Figure 2c). In the 10-bit
conversion result is followed by 5 trailing zeros.
Input Bandwidth
The ADC’s input-tracking circuitry features a 500MHz
small-signal full-linear bandwidth to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. Anti-alias filtering of the input
signals is necessary to avoid high-frequency signals
aliasing into the frequency band of interest.
3-Wire Serial Interface
The MAX11321–MAX11328 feature a serial interface
compatible with SPI/QSPI and MICROWIRE devices. For
SPI/QSPI, ensure the CPU serial interface runs in master
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DI[15] DI[14]
DI[1] DI[0]
DOUT
Ch[3] Ch[2] Ch[1] Ch[0] MSB MSB-1
LSB+1 LSB
Figure 2a. External Clock Mode Timing Diagram with CHAN_ID=1
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
t
> t
QUIET SCLK
DI[15]
DI[1] DI[0]
DOUT
Ch[3] Ch[2] Ch[1] Ch[0] MSB MSB-1
LSB+1 LSB
Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance
Maxim Integrated
15
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DI[15] DI[14]
DI[1] DI[0]
0
MSB] MSB-1 MSB-2
LSB
0
DOUT
Figure 2c. External Clock Mode Timing Diagram with CHAN_ID=0
Single-Ended, Differential,
and Pseudo-Differential Input
The MAX11321–MAX11328 include up to 16 analog input
channels that can be configured on a pin-by-pin basis
to 16 single-ended inputs, 8 fully differential pairs, or 15
pseudo-differential inputs with respect to one common
input (REF-/AIN15 is the common input).
DAC
COMPARATOR
AIP
HOLD
The analog input range is 0V to V
and pseudo-differential mode (unipolar) and QV
in single-ended
REF+
AIN
(GND)
/2 or
REF+
QV
in fully differential mode (bipolar) depending on
REF+
DAC
the RANGE register settings. See Table 7 for the RANGE
register settings.
Unipolar mode sets the differential input range from 0
to V . If the positive analog input swings below the
REF+
Figure 3. Equivalent Input Circuit
negative analog input in unipolar mode, the digital output
code is zero. Selecting bipolar mode sets the differential
maximum value if the input signal exceeds this reference
range.
input range to QV
RANGE register settings (Table 7).
/2 or QV
depending on the
REF+
REF+
ADC Transfer Function
The output format of the MAX11321–MAX11328 is straight
binary in unipolar mode and two’s complement in bipolar
mode. The code transitions midway between successive
integer LSB values, such as 0.5 LSB, 1.5 LSB. Figure
4 and Figure 5 show the unipolar and bipolar transfer
function, respectively. Output coding is binary, with for
In single-ended mode, the ADC always operates in uni-
polar mode. The analog inputs are internally referenced
to GND with a full-scale input range from 0V to V
.
REF+
Single-ended conversions are internally referenced to
GND (Figure 3).
The MAX11321–MAX11328 feature up to 15 pseudo
differential inputs by setting the PDIFF_COM bits in the
Unipolar register to 1 (Table 10). The 15 analog input sig-
nals inputs are referenced to a DC signal applied to the
REF-/AIN15.
example, 1 LSB = V
as the MAX11322/MAX11325/MAX11328.
/4096 in the 12-bit devices such
REF+
Internal FIFO
The MAX11321–MAX11328 contain a FIFO buffer that can
hold up to 16 ADC results. This allows the ADC to handle
multiple internally clocked conversions without tying up
the serial bus. If the FIFO is filled and further conversions
are requested without reading from the FIFO, the oldest
ADC results are overwritten by the new ADC results. Each
Fully Differential Reference (REF+, REF-)
When the reference is used in fully differential mode
(REFSEL = 1), the full-scale range is set by the difference
between REF+ and REF-. The output code reaches its
Maxim Integrated
16
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
OUTPUT CODE (hex)
OUTPUT CODE (hex)
V
REF+
+FS =
7FF
FFF
FFE
FFD
FFC
FFB
FS = V
ZS = 0
1 LSB =
REF+
2
ZS = 0
7FE
-V
REF+
V
REF+
-FS =
2
V
4096
REF+
1 LSB =
001
000
FFF
FFE
4096
004
003
002
001
000
801
800
0
1
2
3
4
FS
-FS
0
+FS
FS -1.5 LSB
INPUT VOLTAGE (LSB)
-FS +0.5 LSB
+FS -1.5 LSB
INPUT VOLTAGE (LSB)
Figure 4. Unipolar Transfer Function for 12-Bit Resolution
Figure 5. Bipolar Transfer Function for 12-Bit Resolution
result contains 2 bytes, with the MSB preceded by four
leading channel address bits. After each falling edge of
CS, the oldest available byte of data is available at DOUT.
When the FIFO is empty, DOUT is zero.
Internal Clock
Apply a soft reset when changing from internal to exter-
nal clock mode: RESET [1:0] = 10. The MAX11321–
MAX11328 operate from an internal oscillator, which is
accurate within Q15% of the 13.33MHz nominal clock
rate. Request internally timed conversions by writing the
appropriate sequence to the ADC Mode Control register
(Table 2).
External Clock
Apply a soft reset when changing from internal to external
clock mode: RESET [1:0] = 10. The detailed operation
of external clock mode is dependent on the mode of
operation selected for the device using SCAN[3:0] bit
settings (see Table 3). In external clock mode the analog
inputs are sampled at the falling edge of CS. Serial clock
(SCLK) is used to perform the conversion.
The wake-up, acquisition, conversion, and shutdown
sequences are initiated through CNVST and are per-
formed automatically using the internal oscillator. Results
are added to the internal FIFO.
With CS high, initiate a scan by setting CNVST low for
at least 5ns before pulling it high (Figure 6). Then, the
MAX11321–MAX11328 wake up, scan all requested
channels, store the results in the FIFO, and shut down.
After the scan is complete, EOC is pulled low and the
results are available in the FIFO. Wait until EOC goes
low before pulling CS low to communicate with the serial
interface. EOC stays low until CS or CNVST is pulled low
again. Do not initiate a second CNVST before EOC goes
low; otherwise, the FIFO may become corrupted.
Depending on the mode selected, the sequencer reads
in the channel to be converted from the serial data input
(DIN) at each frame (e.g. manual mode). The conversion
results are sent to the serial output (DOUT) at the next
frame.
In other external clocked modes the sequence of channel
to be converted is determined by the mode (SCAN[3:0])
selected in Table 3. See the Applications Information for
more detail on programming modes.
Maxim Integrated
17
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
UP TO N INTERNALLY
CLOCKED ACQUISITIONS
AND CONVERSIONS
CNVST
CS
t
CSW
EOC
t
CNV_INT
1
16
1
16
SCLK
DIN
SET MODE REG
SET MODE REG
DOUT
INTERNAL
OSCILLATOR ON
READ DATA FROM FIFO
READ DATA FROM FIFO
SCAN OPERATION AND
RESULTS STORED IN FIFO
Figure 6. Internal Conversions with CNVST
UP TO N INTERNALLY
CLOCKED ACQUISITIONS
AND CONVERSIONS
t
CNV_INT
(N = 1)
CS
EOC
1
17
1
16
SCLK
SET MODE REG
SWCNV = 1
SET MODE REG
DIN
DOUT
MODE CONTROL
INTERNAL OSCILLATOR ON
READ DATA FROM FIFO
SCAN OPERATION AND
RESULTS STORED IN FIFO
Figure 7. Internal Conversions with SWCNV
Maxim Integrated
18
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Repeat Mode
Repeat scanning channel N for number of times and
store all the conversion results in the FIFO. The number of
scans is programmed in the ADC Configuration register.
The repeat mode works with the internal clock only.
Alternatively, set SWCNV to 1 in the ADC Mode Control
register (Figure 4) to initiate conversions with CS rising
edge instead of cycling CNVST (Table 2). For proper
operation, CS must be held low for 17 clock cycles to
guarantee that the device interprets the SWCNV setting.
Wait until EOC goes low before pulling CS low to com-
municate with the serial interface. Upon completing the
conversion, SWCNV is reset to 0 (Figure 7).
Custom_Int and Custom_Ext
In Custom_Int and Custom_Ext modes, the device scans
preprogrammed channels in ascending order. The chan-
nels to be scanned in sequence are programmed in the
Custom Scan0 or Custom Scan1 registers (see Table 12
and Table 13). A new I/P MUX is selected every frame
on the thirteenth falling edge of SCLK. Custom_Int works
with the internal clock. Custom_Ext works with the exter-
nal clock.
Analog Input
The MAX11321–MAX11328 produce a digital output that
corresponds to the analog input voltage as long as the
analog inputs are within the specified operating range.
Internal protection diodes confine the analog input volt-
age within the region of the analog power input rails
(V , GND) and allow the analog input voltage to swing
DD
Standard_Int and Standard_Ext
In Standard_Int and Standard_Ext modes, the device
scans channels 0 through N in ascending order where
N is the last channel specified in the ADC Mode Control
register. A new I/P MUX is selected every frame on the
thirteenth falling edge of SCLK. Standard_Int works with
the internal clock. Standard_Ext works with the external
clock.
from GND - 0.3V to V
device. Input voltages beyond GND - 0.3V and V
+ 0.3V without damaging the
DD
+
DD
0.3V forward bias the internal protection diodes. Limit the
forward diode current to less than 50mA to avoid dam-
age to the MAX11321–MAX11328.
ECHO
When writing to the ADC Configuration register, set
ECHO to 1 in ADC Configuration register to echo back
the configuration data onto DOUT at time n+1 (Figure 8,
Table 6).
Upper_Int and Upper_Ext
In Upper_Int and Upper_Ext modes, the device scans
channels N through 15/11/7/3 in ascending order where
N is the first channel specified in the ADC Mode Control
register. A new I/P MUX is selected every frame on the
thirteenth falling edge of SCLK. Upper_Int works with the
internal clock. Upper_Ext works with the external clock.
Scan Modes
The MAX11321–MAX11328 feature nine scan modes
(Table 3).
Manual Mode
The next channel to be selected is identified in each SPI
frame. The conversion results are sent out in the next
frame. The manual mode works with the external clock
only. The FIFO is unused.
SampleSet
The SampleSet mode of operation allows the definition
of a unique channel sequence combination with maxi-
mum length of 256. SampleSet is supported only in the
external clock mode. SampleSet is ideally suited for mul-
tichannel measurement applications where some analog
inputs must be converted more often than others.
t = n-1
t = n
t = n+1
t = n+2
CS
CONFIGURATION
DATA
CONFIGURATION
DATA
CONFIGURATION
DATA
DIN
TURN ON ECHO
CONFIGURATION
DATA
CONFIGURATION
DATA
DOUT
Figure 8. Echo Back the Configuration Data
Maxim Integrated
19
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
The SampleSet approach provides greater sequencing
flexibility for multichannel applications while alleviat-
ing significant microcontroller communication overhead.
SampleSet technology allows the user to exploit available
ADC input bandwidth without need for constant commu-
nication between the ADC and controlling unit. The user
may define and load a unique sequencing pattern into
the ADC allowing both high- and low-frequency inputs
to be converted appropriately without interface activity.
With the unique sequence loaded into ADC memory, the
pattern may be repeated indefinitely or changed at any
time.
For example, the maximum throughput of MAX11321–
MAX11328 is 1Msps. Traditional ADC scan modes allow
SampleSet REPEATS: LENGTH = 256
SAMPLE SET
(DEPTH = 256)
ST
ND
RD
TH
TH
TH
TH
TH
TH
9 CYCLE
1
CYCLE
2
CYCLE
3
CYCLE
4
CYCLE
5
CYCLE
6
CYCLE
7
CYCLE
8
CYCLE
POTENTIAL SampleSet PATTERN
AIN2/
AIN2/
AIN3
AIN2/
AIN3
AIN2/
AIN3
CHANNEL:
AIN0
2
AIN1
3
AIN0
4
AIN1
5
AIN0
AIN1
AIN3
AIN4
123
AIN5
124
AIN6
125
AIN7
126
AIN8
127
AIN9
128
AIN10 AIN11 AIN12 AIN13 AIN14 AIN15
129 130 131 132 133 134
AIN0
136
AIN1
137
AIN0
254
AIN1
255
1
120
121
122
135
256
ENTRY NO.:
120 CONVERSIONS:
AIN0 AND AIN1
120 CONVERSIONS:
AIN0 AND AIN1
ANALOG
INPUTS
AIN0
AIN1
100kHz
100 CYCLES
135
AIN2
FULLY
DIFFERENTIAL
10kHz
10 CYCLES
1
AIN3
122
123
124
125
256
1kHz
1 CYCLES
AIN4
AIN5
AIN6
t
= 1/f = 1/3Msps = 333.33ns
S
S
AIN7
CS
10
AIN8
8
AIN0
12
6
14
4
AIN9
16
32
2
18
10µs
30
T
S
5µs
AIN10
AIN11
AIN12
AIN13
20
28
22
f
= 100kHz
26
in
24
9
11
AIN1
7
13
5
15
3
17
31
19
5µs
10µs
T
S
29
21
27
23
25
Figure 9. SampleSet Use-Model Example
Maxim Integrated
20
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Scan Modes and Unipolar/Bipolar Setting
When the Unipolar or Bipolar registers are configured
as pseudo-differential or fully differential, the analog
input pairs are repeated in this automated mode. For
example, if N is set to 15 to scan all 16 channels and
all analog input pairs are configured for fully-differential
conversion, the ADC converts the channels twice. In this
case, the user may avoid dual conversions on input pairs
by implementing Manual mode or using Custom_Int or
Custom_Ext scan modes and only scan even (or odd)
channels (e.g. 0, 2, 4).
up to 16-channel conversions in ascending order. In this
case, the effective throughput per channel is 1Msps/16
channel or 62.5ksps. The maximum input frequency that
the ADC can resolve (Nyquist Theorem) is 31.25kHz.
If all 16 channels must be measured, with some chan-
nels having greater than 31.25kHz input frequency, the
user must revert back to manual mode requiring con-
stant communication on the serial interface. SampleSet
technology solves this problem. Figure 9 provides a
SampleSet use-model example.
Averaging Mode
In averaging mode, the device performs the specified
number of conversions and returns the average for each
requested result in the FIFO. The averaging mode works
with internal clock only.
Table ±. Register Access and Control
REGISTER IDEꢂTIFICATIOꢂ CODE
DIꢂ ≡ DATA IꢂPUTS
REGISTER ꢂAꢃE
ꢁIT ±5
ꢁIT ±4
ꢁIT ±3
ꢁIT ±2
ꢁIT ±±
ꢁIT [±0:0]
DIN
ADC Mode Control
ADC Configuration
Unipolar
0
1
1
1
1
1
1
1
1
DIN
0
DIN
0
DIN
0
DIN
0
DIN
0
0
0
1
DIN
Bipolar
0
0
1
0
DIN
RANGE
0
0
1
1
DIN
Custom Scan0
Custom Scan1
SampleSet
0
1
0
0
DIN
0
1
0
1
DIN
0
1
1
0
DIN
Reserved. Do not use.
1
1
1
1
DIN
Table 2. ADC ꢃode Control Register
DEFAUꢀT
STATE
ꢁIT ꢂAꢃE
ꢁIT
FUꢂCTIOꢂ
REG_CNTL
SCAN[3:0]
15
0
Set to 0 to select the ADC Mode Control register
ADC Scan Control register (Table 3)
14:11
0001
Analog Input Channel Select register (Table 4).
CHSEL[3:0]
10:7
6:5
0000
See Table 3 to determine which modes use CHSEL[3:0] for the channel scan
instruction.
RESET±
RESET0
FUꢂCTIOꢂ
0
0
1
1
0
1
0
1
No reset
RESET[1:0]
00
Reset the FIFO only (resets to zero)
Reset all registers to default settings (includes FIFO)
Unused
Maxim Integrated
21
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 2. ADC ꢃode Control Register (continued)
DEFAUꢀT
STATE
ꢁIT ꢂAꢃE
ꢁIT
FUꢂCTIOꢂ
Power Management Modes (Table 5). In external clock mode, PM[1:0] selects
between normal mode and various power-down modes of operation.
PM[1:0]
4:3
00
External Clock Mode. Channel address is always present in internal clock mode.
Set to 1, DOUT is a 16-bit data word containing a 4-bit channel address, followed by
a 12-bit conversion result led by the MSB.
CHAN_ID
2
0
Set to 1 to initiate conversions with the rising edge of CS instead of cycling CNVST
(internal clock mode only).
This bit is used for the internal clock mode only and must be reasserted in the ADC
mode control, if another conversion is desired.
SWCNV
—
1
0
0
0
Unused
Table 3. ADC Scan Control
SCAꢂ3 SCAꢂ2 SCAꢂ± SCAꢂ0
ꢃODE ꢂAꢃE
FUꢂCTIOꢂ
Continue to operate in the previously selected mode. Ignore data
on bits [10:0]. This feature is provided so that DIN can be held low
when no changes are required in the ADC Mode Control register.
Bits [6:3, 1] can be still written without changing the scan mode
properties.
0
0
0
0
0
0
0
1
Null
The next channel to be selected is identified in each SPI frame. The
conversion results are sent out in the next frame.
Clock mode: External clock only
Manual
Channel scan/sequence: Single channel per frame
Channel selection: See Table 4, CHSEL[3:0]
Averaging: No
Scans channel N repeatedly. The FIFO stores 4, 8, 12, or 16
conversion results for channel N.
Clock mode: Internal clock only
0
0
0
0
1
1
0
1
Repeat
Channel scan/sequence: Single channel per frame
Channel selection: See Table 4, CHSEL[3:0]
Averaging: Can be enabled
Scans channels 0 through N. The FIFO stores N conversion results.
Clock mode: Internal clock
Standard_Int
Channel scan/sequence: N channels in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: Can be enabled
Maxim Integrated
22
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 3. ADC Scan Control (continued)
SCAꢂ3 SCAꢂ2 SCAꢂ± SCAꢂ0
ꢃODE ꢂAꢃE
FUꢂCTIOꢂ
Scans channels 0 through N
Clock mode: External clock only
0
1
0
0
Standard_Ext
Channel scan/sequence: N channels in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: No
Scans channel N through the highest numbered channel. The FIFO
stores X conversion results where:
X = Channel 16–N
16-channel devices
8-channel devices
X = Channel 8–N
0
1
0
1
Upper_Int
Clock mode: Internal clock only
Channel scan/sequence: Channel N through the highest numbered
channel in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: Can be enabled
Scans channel N through the highest numbered channel
Clock mode: External clock only
Channel scan/sequence: Channel N through the highest numbered
channel in ascending order
0
0
1
1
1
1
0
1
Upper_Ext
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: No
Scans preprogrammed channels in ascending order. The FIFO
stores conversion results for this unique channel sequence.
Clock mode: Internal clock only
Channel scan/sequence: Unique ascending channel sequence
Maximum depth: 16 conversions
Custom_Int
Channel selection: See Table 12, Custom Scan0 register and Table
13, Custom Scan1 register
Averaging: Can be enabled
Scans preprogrammed channels in ascending order
Clock mode: External clock only
Channel scan/sequence: Unique ascending channel sequence
Maximum depth: 16 conversions
1
0
0
0
Custom_Ext
Channel selection: See Table 12, Custom Scan0 register and Table
13, Custom Scan1 register
Averaging: No
Maxim Integrated
23
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 3. ADC Scan Control (continued)
SCAꢂ3 SCAꢂ2 SCAꢂ± SCAꢂ0
ꢃODE ꢂAꢃE
FUꢂCTIOꢂ
Scans preprogrammed channel sequence with maximum length of
256. There is no restriction on the channel pattern.
Clock mode: External clock only
Channel scan/sequence: Unique channel sequence
Maximum depth: 256 conversions
Channel Selection: See Table 4
Averaging: No
1
0
0
1
SampleSet
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Null
Null
Null
Null
Null
Null
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Table 4. Analog Input Channel Select
CHSEꢀ3
CHSEꢀ2
CHSEꢀ±
CHSEꢀ0
SEꢀECTED CHAꢂꢂEꢀ (ꢂ)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Maxim Integrated
24
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
U Full shutdown where all circuitry is shutdown.
Register Descriptions
U Partial shutdown where all circuitry is powered down
The MAX11321–MAX11328 communicate between the
internal registers and the external circuitry through the
SPI-/QSPI-compatible serial interface. Table 1 details the
register access and control. Table 2 through Table 14
detail the various functions and configurations.
except for the internal bias generator.
AutoShutdown with External Clock Mode
When the PM_ bits in the ADC Mode Control register are
asserted (Table 5), the device shuts down at the rising
edge of CS in the next frame. The device powers up
again at the following falling edge of CS. There are two
available options:
For ADC mode control, set bit 15 of the register code
identification to zero. The ADC Mode Control register
determines when and under what scan condition the
ADC operates.
U AutoShutdown where all circuitry is shutdown.
U AutoStandby where all circuitry are powered down
To set the ADC data configuration, set the bit 15 of the
register code identification to one.
except for the internal bias generator.
AutoShutdown with Internal Clock Mode
The device shuts down after all conversions are complet-
ed. The device powers up again at the next falling edge
of CNVST or at the rising edge of CS after the SWCNV
bit is asserted.
Power-Down Mode
The MAX11321–MAX11328 feature three power-down
modes.
Static Shutdown
The devices shut down when the SPM bits in the ADC
Configuration register are asserted (Table 6). There are
two shutdown options:
Table 5. Power ꢃanagement ꢃodes
Pꢃ±
Pꢃ0
ꢃODE
FUꢂCTIOꢂ
0
0
Normal
All circuitry is fully powered up at all times.
The device enters full shutdown mode at the end of each conversion. All circuitry
is powered down. The device powers up following the falling edge of CS. It takes 2
cycles before valid conversions take place. The information in the registers is retained.
0
1
AutoShutdown
The device powers down all circuitry except for the internal bias generator. The part
powers up following the falling edge of CS. It takes 2 cycles before valid conversions
take place. The information in the registers is retained.
1
1
0
1
AutoStandby
—
Unused.
Table 6. ADC Configuration Register
DEFAUꢀT
STATE
ꢁIT ꢂAꢃE
ꢁIT
FUꢂCTIOꢂ
CONFIG_SETUP
15:11
N/A
Set to 10000 to select the ADC Configuration register.
REFSEꢀ
ꢄOꢀTAGE REFEREꢂCE
REF- COꢂFIGURATIOꢂ
REFSEL
AVGON
10
9
0
0
0
1
External single-ended
External differential
AIN15 (for the 16-channel devices)
REF-
Set to 1 to turn averaging on. Valid for internal clock mode only.
Set to 0 to turn averaging off.
Maxim Integrated
25
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 6. ADC Configuration Register (continued)
DEFAUꢀT
STATE
ꢁIT ꢂAꢃE
ꢁIT
FUꢂCTIOꢂ
Valid for internal clock mode only.
AꢄGOꢂ ꢂAꢄG±
ꢂAꢄG0
FUꢂCTIOꢂ
Performs 1 conversion for each requested
result.
0
1
1
1
1
X
0
0
1
1
X
Performs 4 conversions and returns the
average for each requested result.
0
1
0
1
NAVG[1:0]
8:7
00
Performs 8 conversions and returns the
average for each requested result.
Performs 16 conversions and returns the
average for each requested result.
Performs 32 conversions and returns the
average for each requested result.
Scans channel N and returns 4, 8, 12, or 16 results. Valid for repeat mode only.
ꢂSCAꢂ±
ꢂSCAꢂ0
FUꢂCTIOꢂ
0
0
1
1
0
1
0
1
Scans channel N and returns 4 results.
Scans channel N and returns 8 results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
NSCAN[1:0]
6:5
00
Static power-down modes
SPꢃ±
SPꢃ0
ꢃODE
Normal
Full
FUꢂCTIOꢂ
0
0
All circuitry is fully powered up at all times.
All circuitry is powered down. The information
0
1
Shutdown in the registers is retained.
SPM[1:0]
4:3
00
All circuitry is powered down except for
the reference and reference buffer. The
information in the registers is retained.
Partial
Shutdown
1
1
0
1
—
Reserved
Set to 0 to disable the instruction echo on DOUT.
ECHO
—
2
0
0
Set to 1 to echo back the DIN instruction given at time = n onto the DOUT line at
time = n + 1. It takes 1 full cycle for the echoing to begin (Figure 8).
1:0
Unused
Maxim Integrated
26
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 7. RAꢂGE Register (RAꢂGE Settings Only Applies to ꢁipolar Fully Differential
Analog Input Configurations)
DEFAUꢀT
STATE
ꢁIT ꢂAꢃE
RANGE_SETUP
RANGE0/1
ꢁIT
15:11
10
FUꢂCTIOꢂ
N/A
Set to 10011 to select the RANGE register
Set to 0 for AIN0/1: +V
Set to 1 for AIN0/1: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
0
0
0
0
0
0
0
S
Set to 0 for AIN2/3: +V
Set to 1 for AIN2/3: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
RANGE2/3
RANGE4/5
RANGE6/7
RANGE8/9
RANGE10/11
RANGE12/13
9
8
7
6
5
4
S
Set to 0 for AIN4/5: +V
Set to 1 for AIN4/5: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
S
Set to 0 for AIN6/7: +V
Set to 1 for AIN6/7: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
S
Set to 0 for AIN8/9: +V
Set to 1 for AIN8/9: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
S
Set to 0 for AIN10/11: +V
Set to 1 for AIN10/11: +V
/2, f = V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
, f = 2(V
S
Set to 0 for AIN12/13: +V
Set to 1 for AIN12/13: +V
/2, f = V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
, f = 2(V
S
Set to 0 for AIN14/15: +V
Set to 1 for AIN14/15: +V
/2, f = V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
RANGE14/15
—
3
0
, f = 2(V
S
2:0
000
Unused
Patterns are assembled in 4-bit channel identifier nib-
bles as described in Table 4. Figure 10 presents the
SampleSet timing diagram. Note that two CS frames are
required to configure the SampleSet functionality. The
first frame indicates the sequence length. The second
frame is used to encode the channel sequence pattern.
ADC Output as a Function
of Unipolar and Bipolar Modes
The ADC Scan Control register (Table 3) determines the
ADC mode of operation. The Unipolar and Bipolar regis-
ters in Table 10 and Table 11 determine output coding
and whether input configuration is single-ended or fully
differential.
After the SampleSet register has been coded (Table 14),
by the next falling edge of CS, the new SampleSet pattern
is activated (Figure 10). If the pattern length is less than
SEQ_LENGTH, the remaining channels default to AIN0. If
the select pattern length is greater than SEQ_LENGTH,
the additional data is ignored as the ADC waits for the ris-
ing edge of CS. If CS is asserted in the middle of a nibble,
the full nibble defaults to AIN0.
Table 9 details the conversion output for analog inputs,
AIN0 and AIN1. The truth table is consistent for any other
valid input pairs (AINn/AINn+1). Table 8 shows the appli-
cable input signal format with respect to analog input
configurations.
CHSEL[3:0] is used for MANUAL, REPEAT,
STANDARD_EXT, STANDARD_INT, UPPER_EXT,
UPPER_INT modes of operation. CHSCAN[15:0] is used
for CUSTOM_EXT and CUSTOM_INT modes of operation.
Upon receiving the SampleSet pattern, the user can
set the ADC Mode Control register to begin the conver-
sion process where data readout begins with the first
SampleSet entry. While the last conversion result is read,
the ADC can be instructed to enter AutoShutdown, if
desired. If the user wishes to change the SampleSet
length, a new pattern must be loaded into the ADC as
described in Figure 10.
SampleSet Mode of Operation
The SampleSet register stores the unique channel
sequence length. The sequence pattern is comprised of
up to 256 unique single-ended and/or differential conver-
sions with any order or pattern.
Maxim Integrated
27
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 8. Analog Input Configuration and Unipolar/ꢁipolar Waveforms
SUPPORTED WAꢄEFORꢃS
REFSEꢀ = 0 REFSEꢀ = ±
AꢂAꢀOG IꢂPUT
COꢂFIGURATIOꢂ
UꢂIPOꢀAR/ꢁIPOꢀAR
REGISTER SETTIꢂG
REF+
RANGE: 1V TO V
REF+
RANGE: 1V TO V
Table 10. Unipolar Register:
Set desired channel(s) to 0
or PDIFF_COM to 1.
DD
DD
V
IN+
V
IN+
Unipolar
(Binary
Coding)
REF+
REF+
Single-
Ended
1V
Counterpart Register
REF-
Table 11. Bipolar Register:
Set desired channel(s) to 0.
GND, AIN15
PDIFF_COM = 1
0V
-0.3V
REF+
REF+
RANGE: 1V TO V
RANGE: 1V TO V
DD
DD
V
IN+
Table 10. Unipolar Register:
Set desired channel(s) to 1.
V
IN+
Unipolar
(Binary
Coding)
REF+
REF+
Fully
Differential
V
IN-
V
IN-
Counterpart Register
Table 11. Bipolar Register:
Set desired channel(s) to 0.
V
IN-
(DC OFFSET
OR
SINUSOID)
1V
(DC OFFSET
OR
SINUSOID)
REF-
GND
0V
-0.3V
REF+
REF+
RANGE: 1V TO V
RANGE: 1V TO V
DD
DD
V
IN+
Table 11. Bipolar Register:
Set desired channel(s) to 1.
V
IN+
Bipolar
(2’s
Complement)
REF+
2
REF+
REF+
Fully
Differential
V
V
IN-
IN-
Counterpart Register
Table 10. Unipolar Register:
Set desired channel(s) to 0.
1V
REF-
GND
0V
-0.3V
Table 9. ADC Output as a Function of Unipolar/ꢁipolar Register Settings
CHAꢂꢂEꢀ SEꢀECTIOꢂ
ꢁIT ꢂAꢃE
UꢂIPOꢀAR REGISTER
UCH0/± PDIFF_COꢃ
ꢁIPOꢀAR REGISTER
FUꢂCTIOꢂ
ꢁCH0/±
0
0
1
0
0
0
0
1
0
AIN0 (binary, unipolar)
AIN0/1 pair (two’s complement, bipolar)
AIN0/1 pair (binary, unipolar)
AIN0 Selection:
CHSEL[3:0] = 0000
CHSCAN0 = 1
AIN0/1 pair (binary, unipolar); Unipolar register
takes precedence
1
0
1
X
0
0
1
1
0
0
0
X
0
1
0
AIN0 referred to REF-/AIN15 (binary, unipolar)
AIN1 (binary, unipolar)
AIN0/1 pair (two’s complement, bipolar)
AIN0/1 pair (binary, unipolar)
AIN1 Selection:
CHSEL[3:0] = 0001
CHSCAN1 = 1
AIN0/1 pair (binary, unipolar), Unipolar register
takes precedence
1
X
0
1
1
X
AIN1 referred to REF-/AIN15 (binary, unipolar)
Maxim Integrated
28
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table ±0. Unipolar Register
DEFAUꢀT
STATE
ꢁIT ꢂAꢃE
UNI_SETUP
UCH0/1
ꢁIT
15:11
10
FUꢂCTIOꢂ
Set to 10001 to select the Unipolar register.
—
Set to 1 to configure AIN0 and AIN1 for pseudo-differential conversion.
Set to 0 to configure AIN0 and AIN1 for single-ended conversion.
0
Set to 1 to configure AIN2 and AIN3 for pseudo-differential conversion.
Set to 0 to configure AIN2 and AIN3 for single-ended conversion.
Set to 1 to configure AIN4 and AIN5 for pseudo-differential conversion.
Set to 0 to configure AIN4 and AIN5 for single-ended conversion.
UCH2/3
UCH4/5
9
8
7
6
5
4
3
0
0
0
0
0
0
0
Set to 1 to configure AIN6 and AIN7 for pseudo-differential conversion.
Set to 0 to configure AIN6 and AIN7 for single-ended conversion.
UCH6/7
Set to 1 to configure AIN8 and AIN9 for pseudo-differential conversion.
Set to 0 to configure AIN8 and AIN9 for single-ended conversion.
Set to 1 to configure AIN10 and AIN11 for pseudo-differential conversion.
Set to 0 to configure AIN10 and AIN11 for single-ended conversion.
Set to 1 to configure AIN12 and AIN13 for pseudo-differential conversion.
Set to 0 to configure AIN12 and AIN13 for single-ended conversion.
Set to 1 to configure AIN14 and AIN15 for pseudo-differential conversion.
Set to 0 to configure AIN14 and AIN15 for single-ended conversion.
UCH8/9
UCH10/11
UCH12/13
UCH14/15
Set to 1 to configure AIN0–AIN14 to be referenced to one common DC voltage on
the REF-/AIN15. Set to 0 to disable the 15:1 pseudo differential mode.
PDIFF_COM
—
2
0
1:0
000
Unused.
Table ±±. ꢁipolar Register
DEFAUꢀT
STATE
ꢁIT ꢂAꢃE
BIP_SETUP
BCH0/1
ꢁIT
15:11
10
FUꢂCTIOꢂ
—
Set to 10010 to select the Bipolar register.
Set to 1 to configure AIN0 and AIN1 for bipolar fully differential conversion.
Set to 0 to configure AIN0 and AIN1 for unipolar conversion mod
0
e.
Set to 1 to configure AIN2 and AIN3 for bipolar fully differential conversion.
Set to 0 to configure AIN2 and AIN3 for unipolar conversion mode.
BCH2/3
BCH4/5
9
8
7
6
5
4
0
0
0
0
0
0
Set to 1 to configure AIN4 and AIN5 for bipolar fully differential conversion.
Set to 0 to configure AIN4 and AIN5 for unipolar conversion mode.
Set to 1 to configure AIN6 and AIN7 for bipolar fully differential conversion.
Set to 0 to configure AIN6 and AIN7 for unipolar conversion mode.
BCH6/7
Set to 1 to configure AIN8 and AIN9 for bipolar fully differential conversion.
Set to 0 to configure AIN8 and AIN9 for unipolar conversion mode.
BCH8/9
Set to 1 to configure AIN10 and AIN11 for bipolar fully differential conversion.
Set to 0 to configure AIN10 and AIN11 for unipolar conversion mode.
BCH10/11
BCH12/13
Set to 1 to configure AIN12 and AIN13 for bipolar fully differential conversion.
Set to 0 to configure AIN12 and AIN13 for unipolar conversion mode.
Set to 1 to configure AIN14 and AIN15 for bipolar fully differential conversion.
Set to 0 to configure AIN14 and AIN15 for unipolar conversion mode.
BCH14/15
—
3
0
2:0
000
Unused.
Maxim Integrated
29
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table ±2. Custom Scan0 Register
DEFAUꢀT
STATE
ꢁIT ꢂAꢃE
ꢁIT
FUꢂCTIOꢂ
CUST_SCAN0
CHSCAN15
CHSCAN14
CHSCAN13
CHSCAN12
CHSCAN11
CHSCAN10
CHSCAN9
CHSCAN8
—
15:11
—
0
Set to 10100 to select the Custom Scan0 register.
Set to 1 to scan AIN15. Set to 0 to omit AIN15.
Set to 1 to scan AIN14. Set to 0 to omit AIN14.
Set to 1 to scan AIN13. Set to 0 to omit AIN13.
Set to 1 to scan AIN12. Set to 0 to omit AIN12.
Set to 1 to scan AIN11. Set to 0 to omit AIN11.
Set to 1 to scan AIN10. Set to 0 to omit AIN10.
Set to 1 to scan AIN9. Set to 0 to omit AIN9.
Set to 1 to scan AIN8. Set to 0 to omit AIN8.
Unused.
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2:0
000
Table ±3. Custom Scan± Register
DEFAUꢀT
STATE
ꢁIT ꢂAꢃE
ꢁIT
FUꢂCTIOꢂ
CUST_SCAN1
CHSCAN7
CHSCAN6
CHSCAN5
CHSCAN4
CHSCAN3
CHSCAN2
CHSCAN1
CHSCAN0
—
15:11
—
0
Set to 10101 to select the Custom Scan1 register.
Set to 1 to scan AIN7. Set to 0 to omit AIN7.
Set to 1 to scan AIN6. Set to 0 to omit AIN6.
Set to 1 to scan AIN5. Set to 0 to omit AIN5.
Set to 1 to scan AIN4. Set to 0 to omit AIN4.
Set to 1 to scan AIN3. Set to 0 to omit AIN3.
Set to 1 to scan AIN2. Set to 0 to omit AIN2.
Set to 1 to scan AIN1. Set to 0 to omit AIN1.
Set to 1 to scan AIN0. Set to 0 to omit AIN0.
Unused.
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2:0
000
Table ±4. SampleSet Register
ꢁIT ꢂAꢃE
ꢁIT
DEFAUꢀT STATE
FUꢂCTIOꢂ
SMPL_SET
15:11
—
Set to 10110 to select the SampleSet register.
8-bit binary word indicating desired sequence length. The equation is:
Sequence length = SEQ_LENGTH + 1
00000000 = Sequence length = 1
11111111 = Sequence length = 256
Coding: Straight binary
SEQ_LENGTH
—
10:3
2:0
00000000
—
Maximum length: 256 ADC conversions
Unused.
Maxim Integrated
30
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
CS
SCLK
DIN
1
16
1
1
ENTRY 1
ENTRY 2
ENTRY N = (SEQ_LENGTH)
DOUT
WRITE SampleSet REGISTER
DEFINE SEQ_LENGTH
LOAD SampleSet PATTERN
TIME BETWEEN CS FALLING AND
RISING EDGE DEPENDS IN SEQ_LENGTH
WRITE ADC MODE CONTROL
OR CONTINUE WITH ADDITIONAL
CONFIGURATION SETTINGS
Figure 10. SampleSet Timing Diagram
OVDD, and REF affects the ADC’s performance. Bypass
Applications Information
the V , OVDD, and REF to ground with 0.1FF and 10FF
DD
bypass capacitors. Minimize capacitor lead and trace
lengths for best supply-noise rejection.
How to Program Modes
1) Configure the ADC (set the MSB on DIN to 1).
Choosing an Input Amplifier
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is the
interval between the application of an input voltage step
and the point at which the output signal reaches and
stays within a given error band centered on the result-
ing steady-state amplifier output level. The ADC input
sampling capacitor charges during the sampling cycle,
referred to as the acquisition period. During this acquisi-
tion period, the settling time is affected by the input resis-
tance and the input sampling capacitance. This error
can be estimated by looking at the settling of an RC time
constant using the input capacitance and the source
impedance over the acquisition time period. Figure 13
shows a typical application circuit. The MAX4430, offer-
ing a settling time of 37ns at 16-bit resolution, is an excel-
lent choice for this application.
2) Program ADC mode control (set the MSB on DIN to 0)
to begin the conversion process or to control power
management features.
•
If ADC mode control is written during a conversion
sequence, the ADC finishes the present conver-
sion and at the next falling edge of CS initiates its
new instruction.
•
If configuration data (MSB on DIN is a 1) is written
during a conversion sequence, the ADC finishes
the present conversion in the existing scan mode.
However, data on DOUT is not valid in following
frames until a new ADC mode control instruction
is coded.
Programming Sequence Flow Chart
See Figure 11 for programming sequence.
Layout, Grounding, and Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
Table 15 lists serveral recommended operational ampli-
fiers for MAX11321–MAX11328.
lines underneath the ADC package. Noise in the V
,
DD
Maxim Integrated
31
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
SELECT REFERENCE
EXTERNAL SINGLE-ENDED
EXTERNAL DIFFERENTIAL
SINGLE-ENDED
OR DIFFERENTIAL
SELECT ADC
CONFIGURATION REGISTER
SET REFSEL BIT TO 1
SELECT ADC
CONFIGURATION REGISTER
SET REFSEL BIT TO 0
FIGURE OUT NUMBER
OF CHANNELS TO USE (N)
FOR EACH ADC CHANNEL
SE, PsD/FD
SINGLE-ENDED
PSEUDO-
DIFFERENTIAL
FULLY-
DIFFERENTIAL
SINGLE-ENDED
PSEUDO-
DIFFERENTIAL
UNIPOLAR OR
BIPOLAR
PSEUDO-DIFFERENTIAL
SINGLE-ENDED
BIPOLAR
UNIPOLAR
SELECT UNIPOLAR AND
BIPOLAR REGISTER SET PER
CHANNEL UCH{X}/{X+1}
AND BCH{X}/{X+1} TO 0 FOR
SINGLE-ENDED SELECTION
SELECT BIPOLAR REGISTER
SET PER CHANNEL
BCH{X}/{X+1} TO 1
FOR BIPOLAR FULLY
DIFFERENTIAL
SELECT UNIPOLAR AND
REGISTER SET BIT PDIFF_COM
TO 1 FOR PSEUDO-
SELECT UNIPOLAR
REGISTER SET PER
CHANNEL UCH{X}/{X+1}
TO 1 FOR UNIPOLAR
DIFFERENTIAL SELECTION
1
SELECT RANGE REGISTER SET PER CHANNEL
RANGE SELECT
PAIR RANGE{X}/{X+1} TO 1 QV
REF+
0
SELECT RANGE REGISTER SET PER CHANNEL
FOR EACH ADC CHANNEL
PAIR RANGE{X}/{X+1} TO 0 QV
/2
REF+
NEXT CHANNEL
SEE FIGURE 12
Figure 11. ADC Programming Sequence
Maxim Integrated
32
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
INTERNAL
EXTERNAL
INTERNAL/EXTERNAL
CLOCK
ADC MODE CONTROL REGISTER
YES
NO
SET SCAN[3:0] TO 0001
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE PM[1:0] BITS
REPEAT
AVERAGE
MANUAL
YES
YES
YES
YES
YES
YES
NO
NO
ADC CONFIGURATION REGISTER
SET AVG ON BIT TO 1
SET NAVG[1:0] TO N
ADC CONFIGURATION REGISTER
SET NSCAN[1:0] FOR SCAN COUNT
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0100
SET CHSEL[3:0] TO CHANNEL NUMBER
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0010
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
STANDARD-EXT
NO
YES
NO
STANDARD-INT
AVERAGE
YES
NO
ADC CONFIGURATION REGISTER
SET AVG ON BIT TO 1
SET NAVG[1:0] TO N
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0110
SET CHSEL[3:0] TO CHANNEL NUMBER
UPPER-EXT
NO
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0011
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
YES
NO
UPPER-INT
AVERAGE
YES
NO
ADC CONFIGURATION REGISTER
SET AVG ON BIT TO 1
SET NAVG[1:0] TO N
SET CUSTOM Scan0 REGISTER
SET CUSTOM Scan1 REGISTER
CUSTOM-EXT
NO
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0101
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 1000
SET CHSEL[3:0] TO CHANNEL NUMBER
YES
NO
CUSTOM-INT
AVERAGE
YES
NO
ADC CONFIGURATION REGISTER
SET AVGON BIT TO 1
SET NAVG[1:0] TO N
SampleSet REGISTER
SET SEQ_DEPTH[7:0] TO SET
CHANNEL CAPTURE DEPTH
SampleSet
SET CUSTOM Scan0 REGISTER
SET CUSTOM Scan1 REGISTER
FOLLOW SampleSet REGISTER WITH
CHANNEL PATTERN OF THE SAME SIZE
AS SEQUENCE DEPTH
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0111
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 1001
SET CHSEL[3:0] TO CHANNEL NUMBER
Figure 12. ADC Mode Select Programming Sequence
Maxim Integrated
33
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
U Initial voltage accuracy
Choosing a Reference
For devices using an external reference, the choice of the
reference determines the output accuracy of the ADC.
An ideal voltage reference provides a perfect initial accu-
racy and maintains the reference voltage independent
of changes in load current, temperature, and time. The
following parameters need to be considered in selecting
a reference:
U Temperature drift
U Current source capability
U Current sink capability
U Quiescent current
U Noise. See Table 16.
+5V
0.1µF
10µF
V
V
OVDD
DD
100pF
V
OVDD
DD
0.1µF
10µF
0.1µF
10µF
500I
AGND
500I
AOP
AON
4
3
5
INPUT 1
MAX11321–MAX11328
AIN0
10I
AIP
AIN
1
MAX4430
470pF
470pF
COG
CAPACITOR
V
DC
SCLK
DOUT
SCLK
2
-5V
10µF
MISO
CPU
AIN1
0.1µF
+5V
COG
CAPACITOR
INPUT 2
CS
SS
AIN15
REF
MOSI
DIN
GND
10µF
0.1µF
10µF
+5V
100pF
7
6
2
OUTF
OUTS
IN
1µF
0.1µF
500I
MAX6126
0.1µF
500I
4
3
1
4
3
5
GNDS
GND
NR
INPUT 2
10I
0.1µF
1
MAX4430
V
DC
2
-5V
10µF
0.1µF
Figure 13. Typical Application Circuit
Maxim Integrated
34
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
Definitions
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
spectral components minus the fundamental, the first five
on an actual transfer function from a straight line. This
harmonics, and the DC offset.
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
Total Harmonic Distortion
once offset and gain errors have been nulled. The static
linearity parameters for the MAX11321–MAX11328 are
measured using the end-points method.
Total harmonic distortion (THD) is expressed as:
2
2
2
2
5
V
+ V + V + V
3 4
2
THD = 20 × log
V
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no miss-
ing codes and a monotonic transfer function.
1
where V is the fundamental amplitude, and V through V
5
1
2
are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
Signal-to-Noise Ratio
Signal-to-noise ratio is the ratio of the amplitude of the
desired signal to the amplitude of noise signals at a
given point in time. The larger the number, the better. The
theoretical minimum analog-to-digital noise is caused by
quantization error and results directly from the ADC’s
resolution (N bits):
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.
SNR = (6.02 x N + 1.76) dB
Table ±5. Recommended Input Amplifiers
REFEREꢂCE
MAX4430
MAX4432
MAX4454
MAX4418
MAX44263
CHAꢂꢂEꢀS
TYPICAꢀ APPꢀICATIOꢂ
1
2
4
4
2
Dual supply, low noise, low distortion, high bandwidth
Dual supply, low noise, low distortion, high bandwidth
Low power, single, supply, low cost
Low noise, low power, high bandwidth
Low power, precision, CMOS input, rail-to-rail I/O
Table ±6. Recommended References
REFEREꢂCE
TYPICAꢀ APPꢀICATIOꢂ
MAX6126
MAX6033
MAX6043
MAX6129B
MAX6003
Ultra-high precision, ultra-low noise, wide temperature range
Ultra-high precision, low noise, low power, wide temperature range
High precision, wide temperature range
Low cost, ultra-low power
Low cost, low power
Maxim Integrated
35
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the
signal-to-noise plus distortion (SINAD) is more than 70dB
(MAX11322/MAX11325/MAX11328).
Intermodulation Distortion
Any device with nonlinearities creates distortion products
when two sine waves at two different frequencies (f1 and
f2) are input into the device. Intermodulation distortion
(IMD) is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones, f1 and f2. The indi-
vidual input tone levels are at -6dBFS.
Ordering Information
PART
PIꢂ-PACKAGE
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
ꢁITS
10
SPEED (ꢃsps)
ꢂO. OF CHAꢂꢂEꢀS
ꢃAX±±32±ATJ+
ꢃAX±±322ATJ+
ꢃAX±±324ATJ+
ꢃAX±±325ATJ+
ꢃAX±±327ATJ+
ꢃAX±±328ATJ+
1
1
1
1
1
1
4
4
12
10
8
12
8
10
16
16
12
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE OUTꢀIꢂE
ꢀAꢂD
PATTERꢂ ꢂO.
CODE
ꢂO.
32 TQFN-EP
T3255+5
2±-0±40
90-00±3
Maxim Integrated
36
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Revision History
REꢄISIOꢂ
ꢂUꢃꢁER
REꢄISIOꢂ
DATE
PAGES
CHAꢂGED
DESCRIPTIOꢂ
0
1
9/12
Initial release
Updated Benefits and Features section
—
1
12/14
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
37
©
2014 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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MAXIM
MAX11328ATJ+T
ADC, Successive Approximation, 12-Bit, 1 Func, 16 Channel, Serial Access, 5 X 5 MM, ROHS COMPLIANT, TQFN-32
MAXIM
MAX11329
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access
MAXIM
MAX11329ATJ
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access
MAXIM
MAX11329ATJ+
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access
MAXIM
MAX11329_V1
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access
MAXIM
MAX1132BCAP
1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20, 5.30 MM, MO-150, SSOP-20
ROCHESTER
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