MAX11335_V01 [MAXIM]
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning AccessPost-Mux External Signal Conditioning Access;
| 型号： | MAX11335_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning AccessPost-Mux External Signal Conditioning Access |
| 文件： | 总37页 (文件大小：2219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
MAX11335–MAX11340
General Description
Benefits and Features
● Highly Integrated Precision ADC Saves Space while
The MAX11335–MAX11340 are 12-/10-bit with external
reference and 500kHz, full-linear-bandwidth, high-speed,
low-power, serial-output successive approximation reg-
ister (SAR) analog-to-digital converters (ADCs). The
MAX11335–MAX11340 provide external access to the
output of the integrated mux and ADC input, to simplify
conditioning. The MAX11335–MAX11340 include both
internal and external clock modes. These devices feature
scan mode in both internal and external clock modes. The
internal clock mode features internal averaging to increase
SNR. The external clock mode features the SampleSet™
technology, a user-programmable analog input channel
sequencer. The SampleSet approach provides greater
sequencing flexibility for multichannel applications while
alleviating significant microcontroller or DSP (controlling
unit) communication overhead.
Retaining Flexibility
• ±1 LSB INL, ±1 LSB DNL, No Missing Codes
• 70dB SINAD at 100kHz
• 500ksps Conversion Rate with No Pipeline Delay
● Analog Multiplexer with True Differential Track/Hold:
Any Combination of Single-Ended, Differential and
Pseudo-Differential Input Pin Pairs Allowed
• 16-/8-/4-Channel Single-Ended
• 12-/8-/4-Channel Fully-Differential Pairs
• 15-/8-/4-Channel Pseudo-Differential Relative to a
Common Input
● Two Software-Selectable Bipolar Input Ranges
(±V
+/2, ±V
+)
REF
REF
● External Differential Reference (1V to V
● 32-Pin, 5mm x 5mm TQFN Package
● SampleSet™ Technology Brings Extreme Flexibility
to Program Input Configurations Per Channel and
Sampling Sequence, Optimizes Interface to the
Microcontroller
)
DD
External pins provide access to the output of the
multiplexer and ADC inputs to simplify multichannel signal
conditioning. The internal clock mode features an inte-
grated FIFO allowing data to be sampled at high speeds
and then held for readout at any time or at a lower clock
rate. Internal averaging is also supported in internal clock
mode improving SNR for noisy input signals. The devices
feature analog input channels that can be configured to
be single-ended inputs, fully differential pairs, or pseudo-
differential inputs with respect to one common input.
The MAX11335–MAX11340 operate from a 2.35V to 3.6V
supply and consume only 4.2mW at 500ksps.
• User-Defined Channel Sequence with Maximum
Length of 256
• Scan Modes, Internal Averaging, and Internal Clock
• 16-Entry First-In/First-Out (FIFO)
● Post-Mux Signal Access Allows for External Signal
Conditioning Between the Mux and ADC For
Differential Signals
• Externally Accessible Multiplex Output and ADC
Input
● Low Power Consumption Extends Battery Life for
Portable Applications
The MAX11335–MAX11340 include AutoShutdown™, fast
wake-up, and a high-speed 3-wire serial interface. The
devices feature full power-down mode for optimal power
management. The 8MHz, 3-wire serial interface directly
connects to SPI, QSPI™, and MICROWIRE devices
without external logic.
®
• 1.5V to 3.6V Digital I/O Supply Voltage
• 2.35V to 3.6V Supply Voltage
• 4.2mW at 500ksps with 3V Supplies
• 2μA Full-Shutdown Current
Excellent dynamic performance, low voltage, low power,
ease of use, and small package size make these convert-
ers ideal for portable battery-powered data-acquisition
applications, and for other applications that demand low
power consumption and small space.
● Easy to Interface with Most Microcontrollers
• 16MHz, 3-Wire SPI-/QSPI-/MICROWIRE-/DSP-
Compatible Serial Interface
The MAX11335–MAX11340 are available in 32-pin, 5mm
x 5mm, TQFN packages and operate over the -40°C to
+125°C temperature range.
Applications
SampleSet and AutoShutdown are trademarks of Maxim
Integrated Products, Inc.
● High-Speed Data
● Medical Instrumentation
● Battery-Powered
Instruments
Acquisition Systems
High-Speed Closed-Loop
Systems
QSPI is a trademark of Motorola, Inc.
●
●
MICROWIRE is a registered trademark of National
Semiconductor Corp.
● Portable Systems
Industrial Control Systems
Ordering Information appears at end of data sheet.
19-6468; Rev 2; 6/21
©
2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A.
|
Tel: 781.329.4700
|
© 2021 Analog Devices, Inc. All rights reserved.
19-6468; Rev 1; 12/14
MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Absolute Maximum Ratings
V
to GND ............................................................-0.3V to +4V
Continuous Power Dissipation (T = +70°C)
A
DD
AOP, AON, AIP, AIN, OVDD, AIN0–AIN13, CNVST/AIN14,
TQFN (derate 34.4mW/°C above +70°C)...................2758mW
Operating Temperature Range............................-40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range..............................-65°C to +150°C
Lead Temperature (soldering, 10s)...................................+300°C
Soldering Temperature (reflow)........................................+260°C
REF+, REF-/AIN15 to GND......................-0.3V to the lower of
(V
+ 0.3V) and +4V
DD
CS, SCLK, DIN, DOUT, EOC TO GND...... -0.3V to the lower of
(V + 0.3V) and +4V
OVDD
DGND to GND......................................................-0.3V to +0.3V
Input/Output Current (all pins)............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TQFN
Junction-to-Ambient Thermal Resistance (θ )...........29°C/W
JA
Junction-to-Case Thermal Resistance (θ )...............1.7°C/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics (MAX11335/MAX11336/MAX11337)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 500ksps, f
= 8MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
REF+ DD A
DD
OVDD
SAMPLE
SCLK
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RES
INL
12 bit
12
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
±1.0
±1.0
±3.0
±5.5
DNL
No missing codes
(Note 5)
LSB
1.2
-0.02
±2
LSB
Gain Error
LSB
Offset Error Temperature Coefficient
OE
GE
ppm/°C
TC
Gain Temperature Coefficient
Channel-to-Channel Offset Matching
Line Rejection
±0.8
±0.5
±0.3
ppm/°C
LSB
TC
PSR
(Note 6)
±2
LSB/V
DYNAMIC PERFORMANCE (100kHz, Input Sine Wave) (Notes 3 and 7)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
70
70
71.9
72.3
dB
dB
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-83
-76
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
SFDR
IMD
77
84
-85
30
5
dB
dB
f = 99.2432kHz, f = 69.2139kHz
1
2
-3dB
Full-Power Bandwidth
Full-Linear Bandwidth
MHz
MHz
-0.1dB
SINAD ≥ 70dB
0.5
Analog Devices
│ 2
www.analog.com
MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Electrical Characteristics (MAX11335/MAX11336/MAX11337) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 500ksps, f
= 8MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-0.5dB below full-scale of 99.2432kHz
sine wave input to the channel being
sampled, apply full-scale 69.2139kHz
sine wave signal to all 15 nonselected
input channels.
Crosstalk
-88
dB
CONVERSION RATE
Power-Up Time
t
Conversion cycle, external clock
Internally clocked (Note 8)
2
8
Cycles
ns
PU
Acquisition Time
t
312
5.9
ACQ
µs
Conversion Time
t
CONV
Externally clocked, f
16 cycles (Note 8)
= 8MHz,
SCLK
2000
0.16
ns
External Clock Frequency
Aperture Delay
f
MHz
ns
SCLK
8
Aperture Jitter
RMS
30
ps
ANALOG INPUT
Unipolar, (single ended and pseudo-
differential)
0
V
REF+
Input Voltage Range
V
V
INA
Range bit set to 0
Range bit set to 1
-V
/2
V
/2
Bipolar
(Note 9)
REF+
REF+
-V
V
REF+
REF+
Absolute Input Voltage Range
Static Input Leakage Current
AIN+, AIN- relative to GND
= V , GND
-0.1
V
+ 0.1
V
REF+
I
V
-0.1
±1.5
µA
ILA
AIN
DD
During acquisition time;
RANGE bit = 0 (Note 10)
15
Input Capacitance
C
pF
AIN
During acquisition time;
RANGE bit = 1 (Note 10)
7.5
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
V
-0.3
1
+1
V
V
REF-
REF+ Input Voltage Range
V
V
+ 50mV
DD
REF+
V
V
= 2.5V, f
= 2.5V, f
= 500ksps
= 0Msps
36.7
0.1
REF+
SAMPLE
REF+ Input Current
I
µA
REF+
REF+
SAMPLE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
V
OVDD
Input Voltage Low
Input Voltage High
Input Hysteresis
V
V
V
IL
x 0.25
V
OVDD
V
IH
x 0.75
V
OVDD
V
mV
HYST
x 0.15
Analog Devices
│ 3
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Electrical Characteristics (MAX11335/MAX11336/MAX11337) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 500ksps, f
= 8MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
Input Leakage Current
SYMBOL
CONDITIONS
= 0V or V
MIN
TYP
±0.09
3
MAX
UNITS
µA
I
V
±1.0
IN
AIN
DD
Input Capacitance
C
pF
IN
DIGITAL OUTPUTS (DOUT, EOC)
V
OVDD
x 0.15
Output Voltage Low
V
I
I
= 200µA
V
V
OL
SINK
V
OVDD
Output Voltage High
V
= 200µA
OH
SOURCE
x 0.85
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
I
CS = V
CS = V
-0.3
4
±1.5
µA
pF
L
DD
C
OUT
DD
V
2.35
1.5
3.0
3.0
1.4
1
3.6
3.6
2
V
V
DD
Digital I/O Supply Voltage
V
OVDD
f
f
= 500ksps
SAMPLE
Positive Supply Current
I
= 0Msps (500ksps devices)
mA
DD
SAMPLE
Full shutdown
0.0015 0.006
4.2
V
= 3V,
DD
Normal mode
(External
Reference)
f
= 500ksps
SAMPLE
V
= 2.35V,
DD
3.1
1.5
0.9
f
= 500ksps
SAMPLE
mW
µW
V
= 3V,
DD
Power Dissipation
f
= 500ksps
SAMPLE
AutoStandby
V
= 2.35V,
DD
f
= 500ksps
SAMPLE
V
= 3V
4.5
2.1
Full/
AutoShutdown
DD
DD
V
= 2.35V
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
t
Externally clocked conversion
125
40
4
ns
%
CP
CH
t
60
16.5
15
V
V
= 1.5V to 2.35V
= 2.35V to 3.6V
C
10pF
=
OVDD
LOAD
SCLK Fall to DOUT Transition
t
ns
DOT
DOD
4
OVDD
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
t
C
C
C
= 10pF, channel ID on
= 10pF, channel ID off
= 10pF
15
ns
ns
ns
ns
ns
LOAD
LOAD
LOAD
16
t
14
DOE
t
4
1
DS
DH
SCLK Rise to DIN Hold
t
Analog Devices
│ 4
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Electrical Characteristics (MAX11335/MAX11336/MAX11337) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 500ksps, f
= 8MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
SYMBOL
CONDITIONS
MIN
4
TYP
MAX
UNITS
ns
t
CSS
t
1
ns
CSH
t
See Figure 6
See Figure 7, f
5
ns
CSW
CS or CNVST Rise to EOC Low
(Note 6)
t
= 500ksps
SAMPLE
5.3
6.2
µs
ns
CNV_INT
CS Pulse Width
t
5
CSBW
Electrical Characteristics (MAX11338/MAX11339/MAX11340)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 500ksps, f
= 8MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD A
DD
OVDD
SAMPLE
SCLK
REF+
MIN
10
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
SYMBOL
CONDITIONS
TYP
MAX
UNITS
RES
INL
10 bit
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
±0.4
±0.4
±1.2
±1.5
DNL
No missing codes
(Note 5)
0.7
0
Gain Error
Offset Error Temperature
Coefficient
OE
GE
±2
ppm/°C
ppm/°C
LSB
TC
Gain Temperature Coefficient
±0.8
±0.5
0.2
TC
Channel-to-Channel Offset
Matching
Line Rejection
PSR
(Note 6)
±1.0
-75
LSB/V
DYNAMIC PERFORMANCE (100kHz, Input Sine Wave) (Notes 3 and 7)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
61
61
61.5
61.5
dB
dB
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-82.5
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
SFDR
IMD
76
83.4
-83
30
dB
f = 99.2432kHz, f = 69.2139kHz
dB
1
2
-3dB
MHz
MHz
MHz
Full-Power Bandwidth
Full-Linear Bandwidth
-0.1dB
5
SINAD ≥ 61dB
0.5
Analog Devices
│ 5
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Electrical Characteristics (MAX11338/MAX11339/MAX11340) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 500ksps, f
= 8MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-0.5dB below full-scale of 99.2432kHz
sine-wave input to the channel being
sampled; apply full-scale 69.2139kHz sine
wave signal to all 15 nonselected
input channels
Crosstalk
-88
dB
CONVERSION RATE
Power-Up Time
t
Conversion cycle, external clock
Internally clocked (Note 8)
2
8
Cycles
PU
Acquisition Time
t
312
5.9
ns
µs
ACQ
Conversion Time
t
CONV
Externally clocked, f
16 cycles (Note 8)
= 8MHz,
SCLK
2000
0.16
ns
External Clock Frequency
Aperture Delay
f
MHz
ns
SCLK
8
Aperture Jitter
RMS
30
ps
ANALOG INPUT
Unipolar (single-ended and pseudo
differential)
0
V
REF+
Input Voltage Range
V
V
-V
+V
INA
REF+
/2
REF+
/2
RANGE bit set to 0
Bipolar (Note 9)
RANGE bit set to 1
-V
+V
REF+
REF+
V
+ 0.1
REF+
Absolute Input Voltage Range
Static Input Leakage Current
AIN+, AIN- relative to GND
-0.1
V
I
V
= V , GND
-0.1
15
±1.5
µA
ILA
AIN_
DD
During acquisition time,
RANGE bit = 0 (Note 10)
Input Capacitance
C
pF
AIN
During acquisition time,
RANGE bit = 1 (Note 10)
7.5
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
V
-0.3
1
+1
V
V
REF-
V
DD
REF+ Input Voltage Range
REF+ Input Current
V
REF+
+50mV
V
V
= 2.5V, f
= 2.5V, f
= 500ksps
= 0Msps
36.7
0.1
µA
µA
REF+
SAMPLE
I
REF+
REF+
SAMPLE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
V
OVDD
Input Voltage Low
V
V
V
IL
x 0.25
V
OVDD
Input Voltage High
V
IH
x 0.75
Analog Devices
│ 6
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Electrical Characteristics (MAX11338/MAX11339/MAX11340) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 500ksps, f
= 8MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
Input Hysteresis
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
OVDD
V
mV
HYST
x 0.15
±0.09
3
Input Leakage Current
I
V
= 0V or V
±1.0
µA
pF
IN
AIN_
DD
Input Capacitance
C
IN
DIGITAL OUTPUTS (DOUT, EOC)
V
OVDD
x 0.15
Output Voltage Low
V
I
I
= 200µA
V
V
OL
SINK
V
OVDD
Output Voltage High
V
= 200µA
SOURCE
OH
x 0.85
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
I
CS = V
CS = V
-0.3
4
±1.5
µA
pF
L
DD
C
OUT
DD
V
2.35
1.5
3.0
3.0
1.4
1
3.6
3.6
2
V
V
DD
Digital I/O Supply Voltage
V
OVDD
f
f
= 500ksps
SAMPLE
SAMPLE
Positive Supply Current
I
= 0Msps (500ksps devices)
mA
DD
Full shutdown
0.0015 0.006
4.2
V
= 3V,
DD
Normal mode
(external
reference)
f
= 500ksps
SAMPLE
V
= 2.35V,
DD
3.1
1.5
0.9
f
= 500ksps
SAMPLE
mW
µW
V
= 3V,
DD
Power Dissipation
f
= 500ksps
SAMPLE
AutoStandby
V
= 2.35V,
DD
f
= 500ksps
SAMPLE
V
V
= 3V
4.5
2.1
Full/
AutoShutdown
DD
DD
= 2.35V
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
t
Externally clocked conversion
125
40
4
ns
%
CP
CH
t
60
16.5
15
V
V
= 1.5V to 2.35V
= 2.35V to 3.6V
OVDD
OVDD
SCLK Fall to DOUT Transition
t
C
= 10pF
ns
DOT
LOAD
4
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
t
C
C
C
= 10pF, channel ID on
= 10pF, channel ID off
= 10pF
15
ns
ns
ns
ns
DOD
LOAD
LOAD
LOAD
16
t
14
DOE
t
4
DS
Analog Devices
│ 7
www.analog.com
MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Electrical Characteristics (MAX11338/MAX11339/MAX11340) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 500ksps, f
= 8MHz, 50% duty cycle, V
= V , T = -40°C to +125°C,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SCLK Rise to DIN Hold
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
SYMBOL
CONDITIONS
MIN
1
TYP
MAX
UNITS
ns
t
DH
t
t
4
ns
CSS
1
ns
CSH
t
See Figure 6
5
ns
CSW
CS or CNVST Rise to EOC Low
(Note 7)
t
See Figure 7, f
= 500ksps
SAMPLE
5.3
6.2
µs
ns
CNV_INT
CS Pulse Width
t
5
CSBW
Note 2: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
Parts are tested with MUX externally connected to the ADC input.
Note 3: Channel ID disabled.
Note 4: Tested in single-ended mode.
Note 5: Offset nulled.
Note 6: Line rejection ∆(D
) with V
= 2.35V to 3.6V and V
= 2.35V.
OUT
DD
REF+
Note 7: Tested and guaranteed with fully differential input.
Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Maximum conversion time: 4.73µs + N x 16 x t
OSC_MAX
t
= 88.2ns, t
= 75ns.
OSC_MAX
OSC_TYP
Note 9: The operational input voltage range for each individual input of a differentially configured pair is from V
to GND.
DD
The operational input voltage difference is from -V
Note 10: See Figure 3 (Equivalent Input Circuit).
Note 11: Guaranteed by characterization.
/2 to +V
/2 or -V
to +V
.
REF+
REF+
REF+
REF+
t
CSBW
CS
t
t
t
CP
CSH
CSS
t
CH
1ST
CLOCK
SCLK
16TH
CLOCK
t
DH
t
DS
t
DOT
DIN
t
DOD
t
DOE
DOUT
Figure 1. Detailed Serial-Interface Timing Diagram
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Typical Operating Characteristics
(MAX11335ATJ+/MAX11336ATJ+/MAX11337ATJ+, T = +25°C, unless otherwise noted.)
A
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.5
0
3
2
f
= 500ksps
f
= 500ksps
SAMPLE
SAMPLE
1
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-0.5
-1.0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
-40 -25 -10 5 20 35 50 65 80 95 110 125
DIGITAL OUTPUT CODE (DECIMAL)
DIGITAL OUTPUT CODE (DECIMAL)
TEMPERATURE (°C)
SNR AND SINAD
vs. ANALOG INPUT FREQUENCY
GAIN ERROR vs. TEMPERATURE
HISTOGRAM FOR 30,000 CONVERSIONS
74.0
73.5
73.0
72.5
72.0
71.5
71.0
3
35,000
30,000
25,000
20,000
15,000
10,000
5000
f
= 500ksps
SAMPLE
f
= 500ksps
SAMPLE
2
1
29,999 CODE HITS
SNR
0
-1
-2
-3
SINAD
1 CODE HIT
2047
0
0
20
40
f
60
(kHz)
80
100
-40 -25 -10
5
20 35 50 65 80 95 110 125
2046
2048
2049
2050
TEMPERATURE (°C)
OUTPUT CODE (DECIMAL)
IN
THD vs. ANALOG INPUT FREQUENCY
SFDR vs. ANALOG INPUT FREQUENCY
-80
-85
-90
94
92
90
88
86
84
f
= 500ksps
f
= 500ksps
SAMPLE
SAMPLE
0
20
40
f
60
(kHz)
80
100
0
20
40
60
(kHz)
IN
80
100
f
IN
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Typical Operating Characteristics (continued)
(MAX11335ATJ+/MAX11336ATJ+/MAX11337ATJ+, T = +25°C, unless otherwise noted.)
A
SINAD vs. INPUT RESISTANCE
THD vs. INPUT RESISTANCE
SNR vs. INPUT RESISTANCE
73
72
71
70
-70
-75
-80
-85
-90
73.0
72.5
72.0
71.5
71.0
f
f
= 500ksps
SAMPLE
= 100kHz
f
f
= 500ksps
= 100kHz
f
f
= 500ksps
= 100kHz
SAMPLE
SAMPLE
IN
IN
IN
AOP SHORTED TO AIP
AON SHORTED TO AIN
AOP SHORTED TO AIP
AON SHORTED TO AIN
AOP SHORTED TO AIP
AON SHORTED TO AIN
BUFFER BETWEEN AOP AND AIP
BUFFER BETWEEN AON AND AIN
BUFFER BETWEEN AOP AND AIP
BUFFER BETWEEN AON AND AIN
BUFFER BETWEEN AOP AND AIP
BUFFER BETWEEN AON AND AIN
0
1000
2000
3000
2500 3500
(Ω)
4000
5000
0
1000
500 1500
2000
3000
2500 3500
(Ω)
4000
5000
0
1000
2000
3000
2500 3500
(Ω)
4000 5000
4500
500
1500
500
1500
4500
4500
R
IN
R
R
IN
IN
REFERENCE CURRENT
vs. SAMPLING RATE
100kHz SINE-WAVE INPUT
(8192 POINT FFT PLOT)
SFDR vs. INPUT RESISTANCE
90
85
80
75
30
20
10
0
0
-20
f
f
= 500ksps
= 100kHz
f
= 500ksps
= 100kHz
SAMPLE
IN
SAMPLE
f
IN
BUFFER BETWEEN AOP AND AIP
BUFFER BETWEEN AON AND AIN
-40
A
= -102dB
HD2
f = 200.03kHz
-60
A
= -86.678dB
HD3
f = 205.399kHz
-80
AOP SHORTED TO AIP
AON SHORTED TO AIN
-100
-120
0
1000
2000
3000
2500 3500
(Ω)
4000
5000
0
100
200
300
400
500
0
50
100
150
200
250
500
1500
4500
f
(ksps)
FREQUENCY (kHz)
SAMPLE
R
IN
SNR vs. REFERENCE VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
74
2.5
2.0
1.5
1.0
0.5
f
= 500ksps
SAMPLE
= 100kHz
f
V
= 500ksps
SAMPLE
= 3.0V
f
IN
DD
73
72
71
70
69
68
1.0
1.4
1.8
2.2
2.6
(V)
3.0
3.4
-40 -25 -10
5
20 35 50 65 80 95 110 125
V
TEMPERATURE (°C)
REFP
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Pin Configurations
TOP VIEW
24 23 22 21 20 19 18 17
24 23 22 21 20 19 18 17
16
15
16
15
DGND 25
OVDD 26
REF-
DGND 25
OVDD 26
REF-
CNVST
CNVST
14 AIN
14 AIN
27
28
29
30
31
32
27
28
29
30
31
32
DOUT
EOC
AIN0
AIN1
AIN2
AIN3
DOUT
EOC
AIN0
AIN1
AIN2
AIN3
AIP
AIP
13
12
13
12
MAX11335
MAX11338
MAX11336
MAX11339
AON
AON
11 AOP
11 AOP
10
9
10
9
GND
GND
GND
GND
+
+
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TQFN
4 CHANNEL
TQFN
8 CHANNEL
24 23 22 21 20 19 18 17
16
15
14 AIN
DGND 25
OVDD 26
REF-/AIN15
CNVST/AIN14
27
28
29
30
31
32
DOUT
EOC
AIN0
AIN1
AIN2
AIN3
AIP
13
12
MAX11337
MAX11340
AON
11 AOP
10
9
AIN13
AIN12
+
1
2
3
4
5
6
7
8
TQFN
16 CHANNEL
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Pin Description
MAX11335
MAX11338
MAX11336
MAX11339
MAX11337
MAX11340
NAME
FUNCTION
(4 CHANNEL) (8 CHANNEL) (16 CHANNEL)
1–10, 17, 19
5–10, 17, 19
17, 19
11
GND
AOP
AON
AIP
Ground
11
12
13
14
15
16
11
12
13
14
15
16
Positive Output from the Multiplexer
Negative Output from the Multiplexer
Positive Input to the ADC
12
13
14
AIN
Negative Input to the ADC
—
CNVST
REF-
Active-Low Conversion Start Input
External Differential Reference Negative Input
—
External Positive Reference Input. Apply a reference voltage at
REF+. Bypass to GND with a 0.47µF capacitor.
18
18
18
REF+
Power-Supply Input. Bypass to GND with a 10µF in parallel with
a 0.1µF capacitors.
20, 21
22
20, 21
22
20, 21
22
V
DD
SCLK
Serial Clock Input. Clocks data in and out of the serial interface.
Active-Low Chip Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high impedance
or three-state.
23
23
23
CS
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
24
25
26
24
25
26
24
25
26
DIN
DGND
OVDD
Digital I/O Ground
Digital Power-Supply Input. Bypass to GND with a 10µF in
parallel with a 0.1µF capacitors.
Serial Data Output. Data is clocked out on the falling edge of
SCLK. When CS is high, DOUT is high impedance or three-state.
27
27
27
DOUT
End of Conversion Output. Data is valid after EOC is driven low
(internal clock mode only).
28
29–32
—
28
—
—
28
—
15
EOC
AIN0–AIN3 Analog Inputs
CNVST/
AIN14
Active-Low Conversion Start Input/Analog Input 14
—
—
—
—
—
16
29–32 , 1–10
—
REF-/AIN15 External Differential Reference Negative Input /Analog Input 15
AIN0–AIN13 Analog Inputs
29–32, 1–4
AIN0–AIN7 Analog Inputs
Exposed Pad. Connect EP directly to GND plane for guaranteed
performance.
—
—
—
EP
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Functional Diagrams
HIGH-INPUT IMPEDANCE
PGA/FILTER/BUFFER
AOP AON
AIN AIP
REF+ REF-
AIN0
AIN1
AIN2
AIN3
REF+ REF-
ADC
CS
SCLK
SINGLE-
ENDED/
DIFFERENTIAL
BUS
OSCILLATOR
I/P
MUX
CS
SCLK
DIN
AIN(N-1)
AIN(N)
CONTROL LOGIC
AND
SEQUENCER
DOUT
CNVST
EOC
MAX11335–MAX11340
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Functional Diagrams (continued)
AOP AON
AIN AIP
REF+ REF-
AIN0
AIN1
AIN2
AIN3
REF+ REF-
ADC
CS
SCLK
SINGLE-
ENDED/
OSCILLATOR
DIFFERENTIAL
BUS
I/P
MUX
CS
SCLK
DIN
AIN(N-1)
AIN(N)
CONTROL LOGIC
AND
SEQUENCER
DOUT
CNVST
EOC
MAX11335–MAX11340
is also supported in this mode improving SNR for noisy
input signals. All input channels are configurable for single-
ended, fully differential or pseudo-differential inputs in uni-
polar or bipolar mode. The MAX11335–MAX11340 operate
from a 2.35V to 3.6V supply and consume only 4.2mW at
500ksps.
Detailed Description
The MAX11335–MAX11340 are 12-/10-bit with external
reference and industry-leading 500kHz, full linear band-
width, high-speed, low-power, serial output successive
approximation register (SAR) analog-to-digital converters
(ADC). These devices feature scan mode, internal aver-
aging to increase SNR, and AutoShutdown.
The MAX11335–MAX11340 include AutoShutdown, fast
wake-up, and a high-speed 3-wire serial interface. The
devices feature full power-down mode for optimal power
management.
The external clock mode features the SampleSet technol-
ogy, a user-programmable analog input channel sequenc-
er. The user may define and load a unique sequencing
pattern into the ADC allowing both high- and low-fre-
quency inputs to be converted without interface activity.
This feature frees the controlling unit for other tasks while
lowering overall system noise and power consumption.
Data is converted from analog voltage sources in a
variety of channel and data-acquisition configurations.
Microprocessor (µP) control is made easy through a 3-wire
SPI-/QSPI-/MICROWIRE-compatible serial interface.
AOP and AON are the output pins of the internal multi-
plexer while AIP and AIN are the ADC inputs which are all
accessible externally through pins. This allows flexibility
to the system designer to process all signals through one
PGA (programmable gain amplifier), filter or gain stage
The MAX11335–MAX11340 include internal clock. The
internal clock mode features an integrated FIFO, allowing
data to be sampled at high speed and then held for read-
out at any time or at a lower clock rate. Internal averaging
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
in single-ended or differential configuration. The external
buffering stage should be designed to properly drive the
input sampling network of the ADC.
mode to generate the serial clock signal. Select the SCLK
frequency of 8MHz or less, and set clock polarity (CPOL)
and phase (CPHA) in the control registers to the same
value. The MAX11335–MAX11340 operate with SCLK
idling high, and thus operate with CPOL = CPHA = 1.
The external buffer should also have very high input
impedance (low-leakage current) to ensure best linearity.
If additional signal processing is not required, connect
AOP to AIP and AON to AIN. It is recommended to limit
the source impedance to not affect the sampling accu-
racy of the ADC causing degradation in linearity and total
harmonic distortion. See the SINAD vs. Input Resistance
graph in the Typical Operating Characteristics.
Set CS low to latch input data at DIN on the rising edge
of SCLK. Output data at DOUT is updated on the falling
edge of SCLK. A high-to-low transition on CS samples
the analog inputs and initiates a new frame. A frame is
defined as the time between two falling edges of CS.
There is a minimum of 16 bits per frame. The serial data
input, DIN, carries data into the control registers clocked
in by the rising edge of SCLK. The serial data output,
DOUT, delivers the conversion results and is clocked out
by the falling edge of SCLK. DOUT is a 16-bit data word
containing a 4-bit channel address, followed by a 12-bit
conversion result led by the MSB when CHAN_ID is set
to 1 in the ADC Mode Control register (Figure 2a). When
CHAN_ID is set to 1 keep the SCLK high for at least 25ns
before the CS falling edge (Figure 2b). When CHAN_ID
is set to 0 (external clock mode only), the 16-bit data word
includes a leading zero and the 12-bit conversion result
is followed by 3 trailing zeros (Figure 2c). In the 10-bit
conversion result is followed by 5 trailing zeros.
Input Bandwidth
The ADC’s input-tracking circuitry features a 500MHz
small-signal full-linear bandwidth to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. Anti-alias filtering of the input
signals is necessary to avoid high-frequency signals alias-
ing into the frequency band of interest.
3-Wire Serial Interface
The MAX11335–MAX11340 feature a serial interface
compatible with SPI/QSPI and MICROWIRE devices. For
SPI/QSPI, ensure the CPU serial interface runs in master
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DI[15] DI[14]
DI[1] DI[0]
DOUT
Ch[3] Ch[2] Ch[1] Ch[0] MSB MSB-1
LSB+1 LSB
Figure 2a. External Clock Mode Timing Diagram with CHAN_ID=1
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
t
> t
QUIET SCLK
DI[15]
DI[1]
DI[0]
DOUT
Ch[3] Ch[2] Ch[1] Ch[0] MSB MSB-1
LSB+1 LSB
Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DI[15] DI[14]
DI[1]
DI[0]
0
MSB] MSB-1 MSB-2
LSB
0
DOUT
Figure 2c. External Clock Mode Timing Diagram with CHAN_ID=0
Single-Ended, Differential,
and Pseudo-Differential Input
DAC
The MAX11335–MAX11340 include up to 16 analog input
channels that can be configured on a pin-by-pin basis
to 16 single-ended inputs, 8 fully differential pairs, or 15
pseudo-differential inputs with respect to one common
input (REF-/AIN15 is the common input).
COMPARATOR
AIP
HOLD
AIN
(GND)
The analog input range is 0V to V
and pseudo-differential mode (unipolar) and ±V
in single-ended
REF+
/2 or
REF+
DAC
±V
in fully differential mode (bipolar) depending on
REF+
the RANGE register settings. See Table 7 for the RANGE
register settings.
Figure 3. Equivalent Input Circuit
Unipolar mode sets the differential input range from 0
to V
. If the positive analog input swings below the
REF+
maximum value if the input signal exceeds this reference
range.
negative analog input in unipolar mode, the digital output
code is zero. Selecting bipolar mode sets the differential
input range to ±V
RANGE register settings (Table 7).
/2 or ±V
depending on the
REF+
REF+
ADC Transfer Function
The output format of the MAX11335–MAX11340 is straight
binary in unipolar mode and two’s complement in bipolar
mode. The code transitions midway between successive
integer LSB values, such as 0.5 LSB, 1.5 LSB. Figure 4
and Figure 5 show the unipolar and bipolar transfer func-
tion, respectively. Output coding is binary, with for example,
In single-ended mode, the ADC always operates in uni-
polar mode. The analog inputs are internally referenced
to GND with a full-scale input range from 0V to V
.
REF+
Single-ended conversions are internally referenced to
GND (Figure 3).
The MAX11335–MAX11340 feature up to 15 pseudo
differential inputs by setting the PDIFF_COM bits in the
Unipolar register to 1 (Table 10). The 15 analog input
signals inputs are referenced to a DC signal applied to
the REF-/AIN15.
1 LSB = V
MAX11335/MAX11336/MAX11337.
/4096 in the 12-bit devices such as the
REF+
Internal FIFO
The MAX11335–MAX11340 contain a FIFO buffer that can
hold up to 16 ADC results. This allows the ADC to handle
multiple internally clocked conversions without tying up
the serial bus. If the FIFO is filled and further conversions
are requested without reading from the FIFO, the oldest
ADC results are overwritten by the new ADC results. Each
Fully Differential Reference (REF+, REF-)
When the reference is used in fully differential mode
(REFSEL = 1), the full-scale range is set by the difference
between REF+ and REF-. The output code reaches its
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
OUTPUT CODE (hex)
OUTPUT CODE (hex)
V
REF+
+FS =
FFF
FFE
FFD
FFC
FFB
FS = V
ZS = 0
1 LSB =
7FF
7FE
REF+
2
ZS = 0
-FS =
-V
REF+
V
REF+
2
V
4096
REF+
1 LSB =
001
000
FFF
FFE
4096
004
003
002
001
000
801
800
0
1
2
3
4
FS
-FS
0
+FS
FS -1.5 LSB
INPUT VOLTAGE (LSB)
-FS +0.5 LSB
+FS -1.5 LSB
INPUT VOLTAGE (LSB)
Figure 4. Unipolar Transfer Function for 12-Bit Resolution
Figure 5. Bipolar Transfer Function for 12-Bit Resolution
result contains 2 bytes, with the MSB preceded by four
leading channel address bits. After each falling edge of
CS, the oldest available byte of data is available at DOUT.
When the FIFO is empty, DOUT is zero.
Internal Clock
Apply a soft reset when changing from internal to exter-
nal clock mode: RESET [1:0] = 10. The MAX11335–
MAX11340 operate from an internal oscillator, which is
accurate within ±15% of the 13.33MHz nominal clock
rate. Request internally timed conversions by writing the
appropriate sequence to the ADC Mode Control register
(Table 2).
External Clock
Apply a soft reset when changing from internal to external
clock mode: RESET [1:0] = 10. The detailed operation of
external clock mode is dependent on the mode of opera-
tion selected for the device using SCAN[3:0] bit settings
(see Table 3). In external clock mode the analog inputs
are sampled at the falling edge of CS. Serial clock (SCLK)
is used to perform the conversion.
The wake-up, acquisition, conversion, and shutdown
sequences are initiated through CNVST and are per-
formed automatically using the internal oscillator. Results
are added to the internal FIFO.
With CS high, initiate a scan by setting CNVST low for
at least 5ns before pulling it high (Figure 6). Then, the
MAX11335–MAX11340 wake up, scan all requested
channels, store the results in the FIFO, and shut down.
After the scan is complete, EOC is pulled low and the
results are available in the FIFO. Wait until EOC goes
low before pulling CS low to communicate with the serial
interface. EOC stays low until CS or CNVST is pulled low
again. Do not initiate a second CNVST before EOC goes
low; otherwise, the FIFO may become corrupted.
Depending on the mode selected, the sequencer reads
in the channel to be converted from the serial data input
(DIN) at each frame (e.g. manual mode). The conversion
results are sent to the serial output (DOUT) at the next
frame.
In other external clocked modes the sequence of channel
to be converted is determined by the mode (SCAN[3:0])
selected in Table 3. See the Applications Information for
more detail on programming modes.
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
UP TO N INTERNALLY
CLOCKED ACQUISITIONS
AND CONVERSIONS
CNVST
CS
t
CSW
EOC
t
CNV_INT
1
16
1
16
SCLK
DIN
SET MODE REG
SET MODE REG
DOUT
INTERNAL
OSCILLATOR ON
READ DATA FROM FIFO
READ DATA FROM FIFO
SCAN OPERATION AND
RESULTS STORED IN FIFO
Figure 6. Internal Conversions with CNVST
UP TO N INTERNALLY
CLOCKED ACQUISITIONS
AND CONVERSIONS
t
CNV_INT
(N = 1)
CS
EOC
1
17
1
16
SCLK
SET MODE REG
SWCNV = 1
SET MODE REG
DIN
DOUT
MODE CONTROL
INTERNAL OSCILLATOR ON
READ DATA FROM FIFO
SCAN OPERATION AND
RESULTS STORED IN FIFO
Figure 7. Internal Conversions with SWCNV
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Alternatively, set SWCNV to 1 in the ADC Mode Control
register (Figure 4) to initiate conversions with CS rising
edge instead of cycling CNVST (Table 2). For proper
operation, CS must be held low for 17 clock cycles to
guarantee that the device interprets the SWCNV setting.
Wait until EOC goes low before pulling CS low to com-
municate with the serial interface. Upon completing the
conversion, SWCNV is reset to 0 (Figure 7).
Repeat Mode
Repeat scanning channel N for number of times and store
all the conversion results in the FIFO. The number of
scans is programmed in the ADC Configuration register.
The repeat mode works with the internal clock only.
Custom_Int and Custom_Ext
In Custom_Int and Custom_Ext modes, the device scans
preprogrammed channels in ascending order. The chan-
nels to be scanned in sequence are programmed in the
Custom Scan0 or Custom Scan1 registers (see Table 12
and Table 13). A new I/P MUX is selected every frame on
the thirteenth falling edge of SCLK. Custom_Int works with
the internal clock. Custom_Ext works with the external
clock.
Analog Input
The MAX11335–MAX11340 produce a digital output that
corresponds to the analog input voltage as long as the
analog inputs are within the specified operating range.
Internal protection diodes confine the analog input voltage
within the region of the analog power input rails (V
,
DD
GND) and allow the analog input voltage to swing from
GND - 0.3V to V + 0.3V without damaging the device.
Standard_Int and Standard_Ext
DD
In Standard_Int and Standard_Ext modes, the device
scans channels 0 through N in ascending order where N
is the last channel specified in the ADC Mode Control reg-
ister. A new I/P MUX is selected every frame on the thir-
teenth falling edge of SCLK. Standard_Int works with the
internal clock. Standard_Ext works with the external clock.
Input voltages beyond GND - 0.3V and V
+ 0.3V for-
DD
ward bias the internal protection diodes. Limit the forward
diode current to less than 50mA to avoid damage to the
MAX11335–MAX11340.
ECHO
When writing to the ADC Configuration register, set
ECHO to 1 in ADC Configuration register to echo back
the configuration data onto DOUT at time n+1 (Figure 8,
Table 6).
Upper_Int and Upper_Ext
In Upper_Int and Upper_Ext modes, the device scans
channels N through 15/11/7/3 in ascending order where
N is the first channel specified in the ADC Mode Control
register. A new I/P MUX is selected every frame on the
thirteenth falling edge of SCLK. Upper_Int works with the
internal clock. Upper_Ext works with the external clock.
Scan Modes
The MAX11335–MAX11340 feature nine scan modes
(Table 3).
SampleSet
Manual Mode
The SampleSet mode of operation allows the definition of
a unique channel sequence combination with maximum
length of 256. SampleSet is supported only in the external
clock mode. SampleSet is ideally suited for multichannel
measurement applications where some analog inputs
must be converted more often than others.
The next channel to be selected is identified in each SPI
frame. The conversion results are sent out in the next
frame. The manual mode works with the external clock
only. The FIFO is unused.
t = n-1
t = n
t = n+1
t = n+2
CS
CONFIGURATION
DATA
CONFIGURATION
DATA
CONFIGURATION
DATA
DIN
TURN ON ECHO
CONFIGURATION
DATA
CONFIGURATION
DATA
DOUT
Figure 8. Echo Back the Configuration Data
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
The SampleSet approach provides greater sequencing
flexibility for multichannel applications while alleviat-
ing significant microcontroller communication overhead.
SampleSet technology allows the user to exploit available
ADC input bandwidth without need for constant commu-
nication between the ADC and controlling unit. The user
may define and load a unique sequencing pattern into the
ADC allowing both high- and low-frequency inputs to be
converted appropriately without interface activity. With the
unique sequence loaded into ADC memory, the pattern
may be repeated indefinitely or changed at any time.
For example, the maximum throughput of MAX11335–
MAX11340 is 500ksps. Traditional ADC scan modes
SampleSet REPEATS: LENGTH = 256
SAMPLE SET
(DEPTH = 256)
ST
ND
RD
3
TH
TH
5
TH
6
TH
7
TH
8
TH
9 CYCLE
1
CYCLE
2
CYCLE
CYCLE
4
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
POTENTIAL SampleSet PATTERN
AIN2/
AIN2/
AIN3
AIN2/
AIN3
AIN2/
AIN3
CHANNEL:
AIN0
2
AIN1
3
AIN0
4
AIN1
5
AIN0
AIN1
AIN3
AIN4
123
AIN5
124
AIN6
125
AIN7
126
AIN8
127
AIN9
128
AIN10 AIN11 AIN12 AIN13 AIN14 AIN15
129 130 131 132 133 134
AIN0
136
AIN1
137
AIN0
254
AIN1
255
1
120
121
122
135
256
ENTRY NO.:
120 CONVERSIONS:
AIN0 AND AIN1
120 CONVERSIONS:
AIN0 AND AIN1
ANALOG
INPUTS
AIN0
AIN1
100kHz
100 CYCLES
135
AIN2
FULLY
DIFFERENTIAL
10kHz
10 CYCLES
1
AIN3
122
123
124
125
256
1kHz
1 CYCLES
AIN4
AIN5
AIN6
t
= 1/f = 1/3Msps = 333.33ns
S
S
AIN7
CS
10
AIN8
8
AIN0
12
6
14
4
AIN9
16
32
10µs
2
18
30
T
S
5µs
AIN10
AIN11
AIN12
AIN13
20
28
22
f
= 100kHz
in
26
24
9
11
AIN1
7
13
5
15
3
17
31
19
5µs
10µs
T
S
29
21
27
23
25
Figure 9. SampleSet Use-Model Example
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
allow up to 16-channel conversions in ascending order.
In this case, the effective throughput per channel is
500ksps/16 channel or 31.25ksps. The maximum input
frequency that the ADC can resolve (Nyquist Theorem)
is 15.625kHz. If all 16 channels must be measured, with
some channels having greater than 15.625kHz input
frequency, the user must revert back to manual mode
requiring constant communication on the serial interface.
SampleSet technology solves this problem. Figure 9 pro-
vides a SampleSet use-model example.
Scan Modes and Unipolar/Bipolar Setting
When the Unipolar or Bipolar registers are configured
as pseudo-differential or fully differential, the analog
input pairs are repeated in this automated mode. For
example, if N is set to 15 to scan all 16 channels and
all analog input pairs are configured for fully-differential
conversion, the ADC converts the channels twice. In this
case, the user may avoid dual conversions on input pairs
by implementing Manual mode or using Custom_Int or
Custom_Ext scan modes and only scan even (or odd)
channels (e.g. 0, 2, 4).
Averaging Mode
In averaging mode, the device performs the specified
number of conversions and returns the average for each
requested result in the FIFO. The averaging mode works
with internal clock only.
Table 1. Register Access and Control
REGISTER IDENTIFICATION CODE
DIN ≡ DATA INPUTS
REGISTER NAME
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT [10:0]
DIN
ADC Mode Control
ADC Configuration
Unipolar
0
1
1
1
1
1
1
1
1
DIN
0
DIN
0
DIN
0
DIN
0
DIN
0
0
0
1
DIN
Bipolar
0
0
1
0
DIN
RANGE
0
0
1
1
DIN
Custom Scan0
Custom Scan1
SampleSet
0
1
0
0
DIN
0
1
0
1
DIN
0
1
1
0
DIN
Reserved. Do not use.
1
1
1
1
DIN
Table 2. ADC Mode Control Register
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
REG_CNTL
SCAN[3:0]
15
0
Set to 0 to select the ADC Mode Control register
ADC Scan Control register (Table 3)
14:11
0001
Analog Input Channel Select register (Table 4).
CHSEL[3:0]
10:7
6:5
0000
See Table 3 to determine which modes use CHSEL[3:0] for the channel scan
instruction.
RESET1
RESET0
FUNCTION
0
0
1
1
0
1
0
1
No reset
RESET[1:0]
00
Reset the FIFO only (resets to zero)
Reset all registers to default settings (includes FIFO)
Unused
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 2. ADC Mode Control Register (continued)
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
Power Management Modes (Table 5). In external clock mode, PM[1:0] selects
between normal mode and various power-down modes of operation.
PM[1:0]
4:3
00
External Clock Mode. Channel address is always present in internal clock mode.
Set to 1, DOUT is a 16-bit data word containing a 4-bit channel address, followed by a
12-bit conversion result led by the MSB.
CHAN_ID
2
0
Set to 1 to initiate conversions with the rising edge of CS instead of cycling CNVST
(internal clock mode only).
This bit is used for the internal clock mode only and must be reasserted in the ADC
mode control, if another conversion is desired.
SWCNV
—
1
0
0
0
Unused
Table 3. ADC Scan Control
SCAN3 SCAN2 SCAN1 SCAN0
MODE NAME
FUNCTION
Continue to operate in the previously selected mode. Ignore data on
bits [10:0]. This feature is provided so that DIN can be held low when
no changes are required in the ADC Mode Control register. Bits [6:3,
1] can be still written without changing the scan mode properties.
0
0
0
0
Null
The next channel to be selected is identified in each SPI frame.
The conversion results are sent out in the next frame.
Clock mode: External clock only
0
0
0
1
Manual
Channel scan/sequence: Single channel per frame
Channel selection: See Table 4, CHSEL[3:0]
Averaging: No
Scans channel N repeatedly. The FIFO stores 4, 8, 12, or 16
conversion results for channel N.
Clock mode: Internal clock only
0
0
0
0
1
1
0
1
Repeat
Channel scan/sequence: Single channel per frame
Channel selection: See Table 4, CHSEL[3:0]
Averaging: Can be enabled
Scans channels 0 through N. The FIFO stores N conversion results.
Clock mode: Internal clock
Standard_Int
Channel scan/sequence: N channels in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: Can be enabled
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 3. ADC Scan Control (continued)
SCAN3 SCAN2 SCAN1 SCAN0
MODE NAME
FUNCTION
Scans channels 0 through N
Clock mode: External clock only
0
1
0
0
Standard_Ext
Channel scan/sequence: N channels in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: No
Scans channel N through the highest numbered channel. The FIFO
stores X conversion results where:
X = Channel 16–N
16-channel devices
8-channel devices
X = Channel 8–N
0
1
0
1
Upper_Int
Clock mode: Internal clock only
Channel scan/sequence: Channel N through the highest numbered
channel in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: Can be enabled
Scans channel N through the highest numbered channel
Clock mode: External clock only
Channel scan/sequence: Channel N through the highest numbered
channel in ascending order
0
1
1
0
Upper_Ext
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: No
Scans preprogrammed channels in ascending order. The FIFO stores
conversion results for this unique channel sequence.
Clock mode: Internal clock only
Channel scan/sequence: Unique ascending channel sequence
Maximum depth: 16 conversions
0
1
1
1
Custom_Int
Channel selection: See Table 12, Custom Scan0 register and Table
13, Custom Scan1 register
Averaging: Can be enabled
Scans preprogrammed channels in ascending order
Clock mode: External clock only
Channel scan/sequence: Unique ascending channel sequence
Maximum depth: 16 conversions
1
0
0
0
Custom_Ext
Channel selection: See Table 12, Custom Scan0 register and Table
13, Custom Scan1 register
Averaging: No
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 3. ADC Scan Control (continued)
SCAN3 SCAN2 SCAN1 SCAN0
MODE NAME
FUNCTION
Scans preprogrammed channel sequence with maximum length of
256. There is no restriction on the channel pattern.
Clock mode: External clock only
Channel scan/sequence: Unique channel sequence
Maximum depth: 256 conversions
Channel Selection: See Table 4
Averaging: No
1
0
0
1
SampleSet
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Null
Null
Null
Null
Null
Null
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Continue to operate in the previously selected mode. Ignore data on
bits [10:0].
Table 4. Analog Input Channel Select
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SELECTED CHANNEL (N)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
● Full shutdown where all circuitry is shutdown.
Register Descriptions
● Partial shutdown where all circuitry is powered down
The MAX11335–MAX11340 communicate between the
internal registers and the external circuitry through the
SPI-/QSPI-compatible serial interface. Table 1 details
the register access and control. Table 2 through Table 14
detail the various functions and configurations.
except for the internal bias generator.
AutoShutdown with External Clock Mode
When the PM_ bits in the ADC Mode Control register
are asserted (Table 5), the device shuts down at the ris-
ing edge of CS in the next frame. The device powers up
again at the following falling edge of CS. There are two
available options:
For ADC mode control, set bit 15 of the register code
identification to zero. The ADC Mode Control register
determines when and under what scan condition the ADC
operates.
● AutoShutdown where all circuitry is shutdown.
To set the ADC data configuration, set the bit 15 of the
register code identification to one.
● AutoStandby where all circuitry are powered down
except for the internal bias generator.
Power-Down Mode
The MAX11335–MAX11340 feature three power-down
modes.
AutoShutdown with Internal Clock Mode
The device shuts down after all conversions are complet-
ed. The device powers up again at the next falling edge
of CNVST or at the rising edge of CS after the SWCNV
bit is asserted.
Static Shutdown
The devices shut down when the SPM bits in the ADC
Configuration register are asserted (Table 6). There are
two shutdown options:
Table 5. Power Management Modes
PM1
PM0
MODE
FUNCTION
0
0
Normal
All circuitry is fully powered up at all times.
The device enters full shutdown mode at the end of each conversion. All circuitry is
powered down. The device powers up following the falling edge of CS. It takes 2 cycles
before valid conversions take place. The information in the registers is retained.
0
1
AutoShutdown
The device powers down all circuitry except for the internal bias generator. The part
powers up following the falling edge of CS. It takes 2 cycles before valid conversions
take place. The information in the registers is retained.
1
1
0
1
AutoStandby
—
Unused.
Table 6. ADC Configuration Register
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
CONFIG_SETUP
15:11
N/A
Set to 10000 to select the ADC Configuration register.
REFSEL
VOLTAGE REFERENCE
External single-ended
External differential
REF- CONFIGURATION
AIN15 (for the 16-channel devices)
REF-
REFSEL
AVGON
10
9
0
0
0
1
Set to 1 to turn averaging on. Valid for internal clock mode only.
Set to 0 to turn averaging off.
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 6. ADC Configuration Register (continued)
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
Valid for internal clock mode only.
AVGON NAVG1
NAVG0
FUNCTION
Performs 1 conversion for each requested
result.
0
1
1
1
1
X
0
0
1
1
X
Performs 4 conversions and returns the
average for each requested result.
0
1
0
1
NAVG[1:0]
8:7
00
Performs 8 conversions and returns the
average for each requested result.
Performs 16 conversions and returns the
average for each requested result.
Performs 32 conversions and returns the
average for each requested result.
Scans channel N and returns 4, 8, 12, or 16 results. Valid for repeat mode only.
NSCAN1
NSCAN0
FUNCTION
0
0
1
1
0
1
0
1
Scans channel N and returns 4 results.
Scans channel N and returns 8 results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
NSCAN[1:0]
6:5
00
Static power-down modes
SPM1
SPM0
MODE
Normal
Full
FUNCTION
0
0
All circuitry is fully powered up at all times.
All circuitry is powered down. The information
0
1
SPM[1:0]
4:3
00
Shutdown in the registers is retained.
All circuitry is powered down except for
the reference and reference buffer. The
information in the registers is retained.
Partial
Shutdown
1
1
0
1
—
Reserved
Set to 0 to disable the instruction echo on DOUT.
ECHO
—
2
0
0
Set to 1 to echo back the DIN instruction given at time = n onto the DOUT line at
time = n + 1. It takes 1 full cycle for the echoing to begin (Figure 8).
1:0
Unused
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 7. RANGE Register (RANGE Settings Only Applies to Bipolar Fully Differential
Analog Input Configurations)
DEFAULT
STATE
BIT NAME
RANGE_SETUP
RANGE0/1
BIT
15:11
10
FUNCTION
N/A
Set to 10011 to select the RANGE register
Set to 0 for AIN0/1: +V
Set to 1 for AIN0/1: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
0
0
0
0
0
0
0
S
Set to 0 for AIN2/3: +V
Set to 1 for AIN2/3: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
RANGE2/3
RANGE4/5
RANGE6/7
RANGE8/9
RANGE10/11
RANGE12/13
9
8
7
6
5
4
S
Set to 0 for AIN4/5: +V
Set to 1 for AIN4/5: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
S
Set to 0 for AIN6/7: +V
Set to 1 for AIN6/7: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
S
Set to 0 for AIN8/9: +V
Set to 1 for AIN8/9: +V
/2, f = V
, f = 2(V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
S
Set to 0 for AIN10/11: +V
Set to 1 for AIN10/11: +V
/2, f = V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
, f = 2(V
S
Set to 0 for AIN12/13: +V
Set to 1 for AIN12/13: +V
/2, f = V
- V
- V
-
-)
REF+
REF+
S
REF+
REF
REF
, f = 2(V
S
REF+
Set to 0 for AIN14/15: +V
Set to 1 for AIN14/15: +V
/2, f = V
- V
- V
-
-)
REF+
REF+
S
REF+
REF+
REF
REF
RANGE14/15
—
3
0
, f = 2(V
S
2:0
000
Unused
Patterns are assembled in 4-bit channel identifier nib-
bles as described in Table 4. Figure 10 presents the
SampleSet timing diagram. Note that two CS frames are
required to configure the SampleSet functionality. The first
frame indicates the sequence length. The second frame is
used to encode the channel sequence pattern.
ADC Output as a Function
of Unipolar and Bipolar Modes
The ADC Scan Control register (Table 3) determines the
ADC mode of operation. The Unipolar and Bipolar reg-
isters in Table 10 and Table 11 determine output coding
and whether input configuration is single-ended or fully
differential.
After the SampleSet register has been coded (Table 14),
by the next falling edge of CS, the new SampleSet pattern
is activated (Figure 10). If the pattern length is less than
SEQ_LENGTH, the remaining channels default to AIN0.
If the select pattern length is greater than SEQ_LENGTH,
the additional data is ignored as the ADC waits for the ris-
ing edge of CS. If CS is asserted in the middle of a nibble,
the full nibble defaults to AIN0.
Table 9 details the conversion output for analog inputs,
AIN0 and AIN1. The truth table is consistent for any
other valid input pairs (AINn/AINn+1). Table 8 shows the
applicable input signal format with respect to analog input
configurations.
CHSEL[3:0] is used for MANUAL, REPEAT, STANDARD_
EXT, STANDARD_INT, UPPER_EXT, UPPER_INT modes
of operation. CHSCAN[15:0] is used for CUSTOM_EXT
and CUSTOM_INT modes of operation.
Upon receiving the SampleSet pattern, the user can
set the ADC Mode Control register to begin the conver-
sion process where data readout begins with the first
SampleSet entry. While the last conversion result is
read, the ADC can be instructed to enter AutoShutdown,
if desired. If the user wishes to change the SampleSet
length, a new pattern must be loaded into the ADC as
described in Figure 10.
SampleSet Mode of Operation
The SampleSet register stores the unique channel
sequence length. The sequence pattern is comprised of
up to 256 unique single-ended and/or differential conver-
sions with any order or pattern.
Analog Devices
│ 27
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 8. Analog Input Configuration and Unipolar/Bipolar Waveforms
SUPPORTED WAVEFORMS
REFSEL = 0 REFSEL = 1
ANALOG INPUT
CONFIGURATION
UNIPOLAR/BIPOLAR
REGISTER SETTING
REF+
RANGE: 1V TO V
REF+
RANGE: 1V TO V
Table 10. Unipolar Register:
Set desired channel(s) to 0
or PDIFF_COM to 1.
DD
DD
V
IN+
V
IN+
Unipolar
(Binary
Coding)
Single-
Ended
REF+
REF+
Counterpart Register
1V
Table 11. Bipolar Register:
Set desired channel(s) to 0.
REF-
GND, AIN15
PDIFF_COM = 1
0V
-0.3V
REF+
REF+
RANGE: 1V TO V
RANGE: 1V TO V
DD
DD
V
Table 10. Unipolar Register:
Set desired channel(s) to 1.
IN+
V
IN+
Unipolar
(Binary
Coding)
Fully
Differential
REF+
REF+
V
IN-
Counterpart Register
Table 11. Bipolar Register:
Set desired channel(s) to 0.
V
IN-
V
IN-
(DC OFFSET
OR
1V
(DC OFFSET
OR
SINUSOID)
REF-
SINUSOID)
GND
0V
-0.3V
REF+
REF+
RANGE: 1V TO V
RANGE: 1V TO V
DD
DD
V
Table 11. Bipolar Register:
Set desired channel(s) to 1.
IN+
V
IN+
Bipolar
(2’s
Complement)
REF+
2
Fully
Differential
REF+
REF+
V
IN-
V
IN-
Counterpart Register
Table 10. Unipolar Register:
Set desired channel(s) to 0.
1V
REF-
GND
0V
-0.3V
Table 9. ADC Output as a Function of Unipolar/Bipolar Register Settings
CHANNEL SELECTION
UNIPOLAR REGISTER
BIPOLAR REGISTER
FUNCTION
BIT NAME
UCH0/1 PDIFF_COM
BCH0/1
0
0
1
0
0
0
0
1
0
AIN0 (binary, unipolar)
AIN0/1 pair (two’s complement, bipolar)
AIN0/1 pair (binary, unipolar)
AIN0 Selection:
CHSEL[3:0] = 0000
CHSCAN0 = 1
AIN0/1 pair (binary, unipolar); Unipolar register
takes precedence
1
0
1
X
0
0
1
1
0
0
0
X
0
1
0
AIN0 referred to REF-/AIN15 (binary, unipolar)
AIN1 (binary, unipolar)
AIN0/1 pair (two’s complement, bipolar)
AIN0/1 pair (binary, unipolar)
AIN1 Selection:
CHSEL[3:0] = 0001
CHSCAN1 = 1
AIN0/1 pair (binary, unipolar), Unipolar register
takes precedence
1
0
1
1
X
X
AIN1 referred to REF-/AIN15 (binary, unipolar)
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 10. Unipolar Register
DEFAULT
STATE
BIT NAME
UNI_SETUP
UCH0/1
BIT
15:11
10
FUNCTION
—
0
Set to 10001 to select the Unipolar register.
Set to 1 to configure AIN0 and AIN1 for pseudo-differential conversion.
Set to 0 to configure AIN0 and AIN1 for single-ended conversion.
Set to 1 to configure AIN2 and AIN3 for pseudo-differential conversion.
Set to 0 to configure AIN2 and AIN3 for single-ended conversion.
UCH2/3
UCH4/5
9
8
7
6
5
4
3
0
0
0
0
0
0
0
Set to 1 to configure AIN4 and AIN5 for pseudo-differential conversion.
Set to 0 to configure AIN4 and AIN5 for single-ended conversion.
Set to 1 to configure AIN6 and AIN7 for pseudo-differential conversion.
Set to 0 to configure AIN6 and AIN7 for single-ended conversion.
UCH6/7
Set to 1 to configure AIN8 and AIN9 for pseudo-differential conversion.
Set to 0 to configure AIN8 and AIN9 for single-ended conversion.
UCH8/9
Set to 1 to configure AIN10 and AIN11 for pseudo-differential conversion.
Set to 0 to configure AIN10 and AIN11 for single-ended conversion.
UCH10/11
UCH12/13
UCH14/15
Set to 1 to configure AIN12 and AIN13 for pseudo-differential conversion.
Set to 0 to configure AIN12 and AIN13 for single-ended conversion.
Set to 1 to configure AIN14 and AIN15 for pseudo-differential conversion.
Set to 0 to configure AIN14 and AIN15 for single-ended conversion.
Set to 1 to configure AIN0–AIN14 to be referenced to one common DC voltage on
the REF-/AIN15. Set to 0 to disable the 15:1 pseudo differential mode.
PDIFF_COM
—
2
0
1:0
000
Unused.
Table 11. Bipolar Register
DEFAULT
STATE
BIT NAME
BIP_SETUP
BCH0/1
BIT
15:11
10
FUNCTION
—
0
Set to 10010 to select the Bipolar register.
Set to 1 to configure AIN0 and AIN1 for bipolar fully differential conversion.
Set to 0 to configure AIN0 and AIN1 for unipolar conversion mode.
Set to 1 to configure AIN2 and AIN3 for bipolar fully differential conversion.
Set to 0 to configure AIN2 and AIN3 for unipolar conversion mode.
BCH2/3
BCH4/5
9
8
7
6
5
4
0
0
0
0
0
0
Set to 1 to configure AIN4 and AIN5 for bipolar fully differential conversion.
Set to 0 to configure AIN4 and AIN5 for unipolar conversion mode.
Set to 1 to configure AIN6 and AIN7 for bipolar fully differential conversion.
Set to 0 to configure AIN6 and AIN7 for unipolar conversion mode.
BCH6/7
Set to 1 to configure AIN8 and AIN9 for bipolar fully differential conversion.
Set to 0 to configure AIN8 and AIN9 for unipolar conversion mode.
BCH8/9
Set to 1 to configure AIN10 and AIN11 for bipolar fully differential conversion.
Set to 0 to configure AIN10 and AIN11 for unipolar conversion mode.
BCH10/11
BCH12/13
Set to 1 to configure AIN12 and AIN13 for bipolar fully differential conversion.
Set to 0 to configure AIN12 and AIN13 for unipolar conversion mode.
Set to 1 to configure AIN14 and AIN15 for bipolar fully differential conversion.
Set to 0 to configure AIN14 and AIN15 for unipolar conversion mode.
BCH14/15
—
3
0
2:0
000
Unused.
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 12. Custom Scan0 Register
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
CUST_SCAN0
CHSCAN15
CHSCAN14
CHSCAN13
CHSCAN12
CHSCAN11
CHSCAN10
CHSCAN9
CHSCAN8
—
15:11
—
0
Set to 10100 to select the Custom Scan0 register.
Set to 1 to scan AIN15. Set to 0 to omit AIN15.
Set to 1 to scan AIN14. Set to 0 to omit AIN14.
Set to 1 to scan AIN13. Set to 0 to omit AIN13.
Set to 1 to scan AIN12. Set to 0 to omit AIN12.
Set to 1 to scan AIN11. Set to 0 to omit AIN11.
Set to 1 to scan AIN10. Set to 0 to omit AIN10.
Set to 1 to scan AIN9. Set to 0 to omit AIN9.
Set to 1 to scan AIN8. Set to 0 to omit AIN8.
Unused.
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2:0
000
Table 13. Custom Scan1 Register
DEFAULT
STATE
BIT NAME
BIT
FUNCTION
CUST_SCAN1
CHSCAN7
CHSCAN6
CHSCAN5
CHSCAN4
CHSCAN3
CHSCAN2
CHSCAN1
CHSCAN0
—
15:11
—
0
Set to 10101 to select the Custom Scan1 register.
Set to 1 to scan AIN7. Set to 0 to omit AIN7.
Set to 1 to scan AIN6. Set to 0 to omit AIN6.
Set to 1 to scan AIN5. Set to 0 to omit AIN5.
Set to 1 to scan AIN4. Set to 0 to omit AIN4.
Set to 1 to scan AIN3. Set to 0 to omit AIN3.
Set to 1 to scan AIN2. Set to 0 to omit AIN2.
Set to 1 to scan AIN1. Set to 0 to omit AIN1.
Set to 1 to scan AIN0. Set to 0 to omit AIN0.
Unused.
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2:0
000
Table 14. SampleSet Register
BIT NAME
BIT
DEFAULT STATE
FUNCTION
SMPL_SET
15:11
—
Set to 10110 to select the SampleSet register.
8-bit binary word indicating desired sequence length. The equation is:
Sequence length = SEQ_LENGTH + 1
00000000 = Sequence length = 1
11111111 = Sequence length = 256
Coding: Straight binary
SEQ_LENGTH
10:3
2:0
00000000
—
Maximum length: 256 ADC conversions
—
Unused.
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
CS
SCLK
DIN
1
16
1
1
ENTRY 1
ENTRY 2
ENTRY N = (SEQ_LENGTH)
DOUT
WRITE SampleSet REGISTER
DEFINE SEQ_LENGTH
LOAD SampleSet PATTERN
TIME BETWEEN CS FALLING AND
RISING EDGE DEPENDS IN SEQ_LENGTH
WRITE ADC MODE CONTROL
OR CONTINUE WITH ADDITIONAL
CONFIGURATION SETTINGS
Figure 10. SampleSet Timing Diagram
the V , OVDD, and REF to ground with 0.1µF and 10µF
DD
bypass capacitors. Minimize capacitor lead and trace
lengths for best supply-noise rejection.
Applications Information
How to Program Modes
1) Configure the ADC (set the MSB on DIN to 1).
2) Program ADC mode control (set the MSB on DIN to
0) to begin the conversion process or to control power
management features.
Choosing an Input Amplifier
It is important to match the settling time of the input ampli-
fier to the acquisition time of the ADC. The conversion
results are accurate when the ADC samples the input
signal for an interval longer than the input signal’s worst-
case settling time. By definition, settling time is the interval
between the application of an input voltage step and the
point at which the output signal reaches and stays within
a given error band centered on the resulting steady-state
amplifier output level. The ADC input sampling capaci-
tor charges during the sampling cycle, referred to as
the acquisition period. During this acquisition period, the
settling time is affected by the input resistance and the
input sampling capacitance. This error can be estimated
by looking at the settling of an RC time constant using
the input capacitance and the source impedance over
the acquisition time period. Figure 13 shows a typical
application circuit. The MAX4430, offering a settling time
of 37ns at 16-bit resolution, is an excellent choice for this
application.
• If ADC mode control is written during a conversion
sequence, the ADC finishes the present conversion
and at the next falling edge of CS initiates its new
instruction.
• If configuration data (MSB on DIN is a 1) is written
during a conversion sequence, the ADC finishes
the present conversion in the existing scan mode.
However, data on DOUT is not valid in following
frames until a new ADC mode control instruction is
coded.
Programming Sequence Flow Chart
See Figure 11 for programming sequence.
Layout, Grounding, and Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
Table 15 lists several recommended operational ampli-
fiers for MAX11335–MAX11340.
lines underneath the ADC package. Noise in the V
,
DD
OVDD, and REF affects the ADC’s performance. Bypass
Analog Devices
│ 31
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
SELECT REFERENCE
EXTERNAL SINGLE-ENDED
EXTERNAL DIFFERENTIAL
SINGLE-ENDED
OR DIFFERENTIAL
SELECT ADC
SELECT ADC
CONFIGURATION REGISTER
SET REFSEL BIT TO 0
CONFIGURATION REGISTER
SET REFSEL BIT TO 1
FIGURE OUT NUMBER
OF CHANNELS TO USE (N)
FOR EACH ADC CHANNEL
SINGLE-ENDED
PSEUDO-
DIFFERENTIAL
FULLY-
DIFFERENTIAL
SINGLE-ENDED
PSEUDO-
DIFFERENTIAL
UNIPOLAR OR
BIPOLAR
SE, PsD/FD
PSEUDO-DIFFERENTIAL
SINGLE-ENDED
BIPOLAR
UNIPOLAR
SELECT UNIPOLAR AND
BIPOLAR REGISTER SET PER
CHANNEL UCH{X}/{X+1}
AND BCH{X}/{X+1} TO 0 FOR
SINGLE-ENDED SELECTION
SELECT BIPOLAR REGISTER
SET PER CHANNEL
BCH{X}/{X+1} TO 1
FOR BIPOLAR FULLY
DIFFERENTIAL
SELECT UNIPOLAR AND
REGISTER SET BIT PDIFF_COM
TO 1 FOR PSEUDO-
SELECT UNIPOLAR
REGISTER SET PER
CHANNEL UCH{X}/{X+1}
TO 1 FOR UNIPOLAR
DIFFERENTIAL SELECTION
SELECT RANGE REGISTER SET
1
PER CHANNEL PAIR RANGE{X}/{X+1}
TO 1 ±V
RANGE SELECT
0
REF+
SELECT RANGE REGISTER SET
FOR EACH ADC CHANNEL
PER CHANNEL PAIR RANGE{X}/{X+1}
TO 0 ±V
/2
REF+
NEXT CHANNEL
SEE FIGURE 12
Figure 11. ADC Programming Sequence
Analog Devices
│ 32
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
INTERNAL
EXTERNAL
INTERNAL/EXTERNAL
CLOCK
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0001
SET CHSEL[3:0] TO CHANNEL NUMBER
YES
NO
REPEAT
NO
AVERAGE
YES
MANUAL
YES
SELECT THE PM[1:0] BITS
NO
ADC CONFIGURATION REGISTER
SET AVG ON BIT TO 1
SET NAVG[1:0] TO N
ADC CONFIGURATION REGISTER
SET NSCAN[1:0] FOR SCAN COUNT
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0100
SET CHSEL[3:0] TO CHANNEL NUMBER
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0010
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
STANDARD-EXT
NO
YES
YES
YES
YES
NO
STANDARD-INT
NO
AVERAGE
YES
ADC CONFIGURATION REGISTER
SET AVG ON BIT TO 1
SET NAVG[1:0] TO N
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0110
SET CHSEL[3:0] TO CHANNEL NUMBER
UPPER-EXT
NO
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0011
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
YES
NO
UPPER-INT
NO
AVERAGE
YES
ADC CONFIGURATION REGISTER
SET AVG ON BIT TO 1
SET NAVG[1:0] TO N
SET CUSTOM Scan0 REGISTER
SET CUSTOM Scan1 REGISTER
CUSTOM-EXT
NO
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0101
SET CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 1000
SET CHSEL[3:0] TO CHANNEL NUMBER
YES
NO
CUSTOM-INT
NO
AVERAGE
YES
ADC CONFIGURATION REGISTER
SET AVGON BIT TO 1
SET NAVG[1:0] TO N
SampleSet REGISTER
SET SEQ_DEPTH[7:0] TO SET
CHANNEL CAPTURE DEPTH
SampleSet
SET CUSTOM Scan0 REGISTER
SET CUSTOM Scan1 REGISTER
YES
FOLLOW SampleSet REGISTER WITH
CHANNEL PATTERN OF THE SAME
SIZE AS SEQUENCE DEPTH
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 0111 SET
CHSEL[3:0] TO CHANNEL NUMBER
SELECT THE RIGHT SWCNV BIT
ADC MODE CONTROL REGISTER
SET SCAN[3:0] TO 1001 SET
CHSEL[3:0] TO CHANNEL NUMBER
Figure 12. ADC Mode Select Programming Sequence
Analog Devices
│ 33
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
● Initial voltage accuracy
Choosing a Reference
For devices using an external reference, the choice of the
reference determines the output accuracy of the ADC.
An ideal voltage reference provides a perfect initial accu-
racy and maintains the reference voltage independent
of changes in load current, temperature, and time. The
following parameters need to be considered in selecting
a reference:
● Temperature drift
● Current source capability
● Current sink capability
● Quiescent current
● Noise. See Table 16.
+5V
0.1µF
10µF
V
V
OVDD
DD
100pF
V
DD
OVDD
0.1µF
10µF
0.1µF
10µF
500Ω
AGND
500Ω
AON
AOP
4
3
5
INPUT 1
MAX11335–MAX11340
10Ω
AIP
AIN
1
AIN0
MAX4430
470pF
470pF
COG
CAPACITOR
V
DC
SCLK
DOUT
SCLK
2
-5V
10µF
MISO
CPU
AIN1
0.1µF
+5V
COG
CAPACITOR
INPUT 2
AIN15
CS
SS
MOSI
REF
DIN
GND
10µF
0.1µF
10µF
+5V
100pF
7
2
1
OUTF
OUTS
IN
1µF
0.1µF
6
500Ω
MAXꢀ1ꢁꢀ
0.1µF
500Ω
4
3
4
3
5
GNDS
GND
NR
INPUT 2
10Ω
0.1µF
1
MAX4430
V
DC
2
-5V
10µF
0.1µF
Figure 13. Typical Application Circuit
Analog Devices
│ 34
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nulled. The static
linearity parameters for the MAX11335–MAX11340 are
measured using the end-points method.
Total Harmonic Distortion
Total harmonic distortion (THD) is expressed as:
2
2
2
2
V
+ V + V + V
3 4 5
Differential Nonlinearity
2
THD = 20 × log
V
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
1
where V is the fundamental amplitude, and V through V
5
are the amplitudes of the 2nd- through 5th-order harmonics.
1
2
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
Signal-to-noise ratio is the ratio of the amplitude of the
desired signal to the amplitude of noise signals at a given
point in time. The larger the number, the better. The
theoretical minimum analog-to-digital noise is caused
by quantization error and results directly from the ADC’s
resolution (N bits):
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.
SNR = (6.02 x N + 1.76) dB
Table 15. Recommended Input Amplifiers
REFERENCE
MAX4430
MAX4432
MAX4454
MAX4418
MAX44263
CHANNELS
TYPICAL APPLICATION
1
2
4
4
2
Dual supply, low noise, low distortion, high bandwidth
Dual supply, low noise, low distortion, high bandwidth
Low power, single, supply, low cost
Low noise, low power, high bandwidth
Low power, precision, CMOS input, rail-to-rail I/O
Table 16. Recommended References
REFERENCE
TYPICAL APPLICATION
MAX6126
MAX6033
MAX6043
MAX6129B
MAX6003
Ultra-high precision, ultra-low noise, wide temperature range
Ultra-high precision, low noise, low power, wide temperature range
High precision, wide temperature range
Low cost, ultra-low power
Low cost, low power
Analog Devices
│ 35
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Full-Linear Bandwidth
Chip Information
PROCESS: BiCMOS
Full-linear bandwidth is the frequency at which the sig-
nal-to-noise plus distortion (SINAD) is more than 70dB
(MAX11335/MAX11336/MAX11337).
Intermodulation Distortion
Any device with nonlinearities creates distortion products
when two sine waves at two different frequencies (f1 and
f2) are input into the device. Intermodulation distortion
(IMD) is the total power of the IM2 to IM5 intermodula-
tion products to the Nyquist frequency relative to the total
input power of the two input tones, f1 and f2. The indi-
vidual input tone levels are at -6dBFS.
Ordering Information
PART
PIN-PACKAGE
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
BITS
12
SPEED (ksps)
NO. OF CHANNELS
MAX11335ATJ+
MAX11336ATJ+
MAX11337ATJ+
MAX11338ATJ+
MAX11339ATJ+
MAX11340ATJ+
500
500
500
500
500
500
4
8
12
12
16
4
10
10
8
10
16
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE OUTLINE
LAND
PATTERN NO.
CODE
NO.
32 TQFN-EP
T3255+5
21-0140
90-0013
Analog Devices
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MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
9/12
12/14
6/21
Initial release
—
Revised Benefits and Features section
1
Updated Figure 13
34
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use.Specifications subject to change without notice. No license is granted by implicationor
otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the
property of their respective owners.
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相关型号：
MAX11337ATJ+T
ADC, Successive Approximation, 12-Bit, 1 Func, 16 Channel, Serial Access, BICMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-32
MAXIM
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