MAX1151BIZS_技术文档

19-1170; Rev 0; 12/96

8 -Bit , 7 5 0 Ms p s Fla s h ADC

MAX51

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

The MAX1151 is a parallel flash analog-to-digital con-

verter (ADC) capable of digitizing full-scale (0V to -2V)

inp uts into 8-b it d ig ita l word s a t a n up d a te ra te of

750Msps. The ECL-compatible outputs are demuxed

into two separate output banks, each with differential

data-ready outputs to ease the task of data capture.

The MAX1151’s wide input bandwidth and low capaci-

tance eliminate the need for external track/hold amplifi-

e rs for mos t a p p lic a tions . A p rop rie ta ry d e c od ing

scheme reduces metastable errors to 1LSB. This device

operates from a single -5.2V supply, with a nominal

power dissipation of 5.5W.

♦ 1:2 Demuxed ECL-Compatible Outputs

♦ Wide Input Bandwidth: 900MHz

♦ Low Input Capacitance: 15pF

♦ Metastable Errors Reduced to 1LSB

♦ Single -5.2V Supply

________________________Ap p lic a t io n s

Digital Oscilloscopes

Data Acquisition

Transient-Capture Applications

Radar, EW, ECM

______________Ord e rin g In fo rm a t io n

PART

TEMP. RANGE

-20°C to +85°C

PIN-PACKAGE

80 MQUAD

Direct RF/IF Downconversion

Pin Configuration appears on last page.

MAX1151AIZS

MAX1151BIZS

80 MQUAD

_________________________________________________________Fu n c t io n a l Dia g ra m

CLK NCLK

CLOCK

BUFFER

DEMUX

CLOCK BUFFER

ANALOG

INPUT

VRT

COMPARATOR

255

MAX1151

PREAMP

254

D8B

D8

(OVR)

D7B

•

NDRB (NOT DATA READY)

152

151

DRB (DATA READY)

D7

(MSB)

D5B

D8B (OVR)

•

D7B (MSB)

D6B

D6

D5

D2B

BANK B

D5B

D4B

D1B

D0B

D8A

D3B

128

127

D2B

VRM

D1B

D0B (LSB)

NDRA (NOT DATA READY)

D4

DRA (DATA READY)

D8A (OVR)

D7A (MSB)

D6A

D7A

•

64

63

•

D3

D2

•

BANK A

D5A

D4A

•

D3A

•

D2A

D1A

D2A

2

1

D0A (LSB)

D1

D1A

D0A

D0

(LSB)

VFB

________________________________________________________________ Maxim Integrated Products

1

For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

8 -Bit , 7 5 0 Ms p s Fla s h ADC

ABSOLUTE MAXIMUM RATINGS

Supply Voltages

Negative Supply Voltage (V to GND) .............-7.0V to +0.5V

Ground Voltage Differential.................................-0.5V to +0.5V

Input Voltages

Analog Input Voltage .............................................+0.5V to V

Digital Output Current ...........................................0mA to -28mA

Operating Temperature Range ...........................-20°C to +85°C

Case Temperature ...........................................................+125°C

Junction Temperature ......................................................+150°C

Lead Temperature (soldering, 10sec). ............................+300°C

Storage Temperature Range .............................-65°C to +150°C

EE

Reference Input Voltage ........................................+0.5V to V

Digital Input Voltage ..............................................+0.5V to V

EE

Reference Current (V to V )........................................35mA

RT

RB

MAX51

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V = -5.2V, V = -2.00V, V = -1.00V, V = 0.00V, f

= 750MHz, duty cycle = 50%, typical thermal impedance (θ ) = 4°C/W,

JC

EE

RB

RM

RT

CLK

T = T = T = +25°C.) (Note 1)

j

C

A

TEST

LEVEL

MAX1151A

TYP

MAX1151B

TYP

PARAMETER

CONDITIONS

UNITS

MIN

MAX

MIN

MAX

Resolution

8

Bits

DC ACCURACY

Integral Nonlinearity

Differential Nonlinearity

No Missing Codes

ANALOG INPUT

Input Voltage Range

Input Bias Current

Input Resistance

Input Capacitance

f

= 100kHz

I

-1.0

1.0

-1.5

1.5

LSB

CLK

f

-0.85

0.95

-0.95

CLK

Guaranteed

I

V

RB

V

RT

V

RB

V

RT

V

= 0V

I

0.75

15

2.0

0.75

15

2.0

mA

kΩ

pF

IN

V

IV

V

Over full input range

Small signal

15

900

500

900

500

Input Bandwidth

MHz

Large signal

Offset Error V

-30

30

-30

30

mV

RT

Offset Error V

RB

Input Slew Rate

5

V/ns

REFERENCE INPUT

Ladder Resistance

I

60

80

30

60

80

30

Ω

Reference Bandwidth

TIMING CHARACTERISTICS

Maximum Sample Rate

Aperture Jitter

V

MHz

I

750

MHz

ps

V

2

Acquisition Time

V

250

1.4

250

1.4

ps

CLK to DATA READY Delay

Clock to Data Delay

IV

0.9

1.9

0.9

1.9

ns

1.25

1.75

2.25

1.25

1.75

2.25

ns

2

_______________________________________________________________________________________

8 -Bit , 7 5 0 Ms p s Fla s h ADC

MAX51

ELECTRICAL CHARACTERISTICS (continued)

(V = -5.2V, V = -2.00V, V = -1.00V, V = 0.00V, f

= 750MHz, duty cycle = 50%, typical thermal impedance (θ ) = 4°C/W,

JC

EE

RB

RM

RT

CLK

T = T = T = +25°C.) (Note 1)

j

C

A

TEST

LEVEL

MAX1151A

TYP

MAX1151B

TYP

PARAMETER

CONDITIONS

UNITS

MIN

MAX

MIN

MAX

DYNAMIC PERFORMANCE

f

= 50MHz

= 250MHz

= 50MHz

= 250MHz

= 50MHz

= 250MHz

= 50MHz

= 250MHz

I

46

44

-45

-37

43

36

48

40

44

42

-43

-35

41

34

44

36

IN

Signal-to-Noise Ratio

(without harmonics)

dB

dBc

dB

f

IN

f

IN

Total Harmonic Distortion

f

IN

f

IN

Signal-to-Noise and

Distortion

f

IN

f

IN

Spurious-Free Dynamic

Range

dB

f

IN

DIGITAL INPUTS

Input High Voltage

(CLK, NCLK)

I

-1.1

-0.7

-1.8

0.5

2

-1.1

-0.7

-1.8

0.5

2

V

Input Low Voltage

(CLK, NCLK)

-1.5

Clock Pulse Width High

I

0.67

ns

µA

(t

PWH

)

Clock Pulse Width Low

(t

I

)

PWL

Clock Synchronous

Input Currents

V

DIGITAL OUTPUTS

Logic "1" Voltage

Logic "0" Voltage

I

-1.1

-0.9

-1.8

2.4

-1.1

-0.9

-1.8

2.4

V

-1.5

POWER-SUPPLY REQUIREMENTS

Supply Voltage (V

V

IV

I

)

-4.95

-5.2

1.05

5.5

-5.45

1.2

-4.95

-5.2

1.05

5.5

-5.45

1.2

V

A

EE

Supply Current (I

)

EE

Power Dissipation

I

6.25

W

Note 1: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually

performed during production and Quality Assurance inspection. Unless otherwise noted, all tests are pulsed tests; therefore,

T = T = T .

j

C

A

TEST LEVEL TEST PROCEDURE

I

100% production tested at the specified temperature.

II

100% production tested at T = +25°C, and sample tested at the specified temperatures.

A

III

IV

V

QA sample tested only at the specified temperatures.

Parameter is guaranteed (but not tested) by design and characterization data.

Parameter is a typical value for information purposes only.

VI

100% production tested at T = +25°C. Parameter is guaranteed over specified temperature range.

A

_______________________________________________________________________________________

3

8 -Bit , 7 5 0 Ms p s Fla s h ADC

______________________________________________________________P in De s c rip t io n

NAME

FUNCTION

Data Output Bank, Bits 2, 3, and 4

1, 2, 3

D2B, D3B, D4B

4, 5, 19, 20, 22, 23, 27, 28, 38, 39,

40, 46, 47, 49, 60, 67, 79

V

Negative Supply, nominally -5.2V

Data Output Bank B, Bit 5

Digital Ground

EE

6

D5B

7, 9, 11, 54, 56, 58,

69, 71, 73, 75, 77

MAX51

DGND

8

D6B

D7B

D8B

N.C.

Data Output Bank B, Bit 6

10

Data Output Bank B, Bit 7 (MSB)

Data Output Bank B, Bit 8 (OVR)

No Connection. Not internally connected.

12

13, 14, 31, 34, 41, 63, 64

15-18, 25, 26, 29, 30, 36,

37, 44, 45, 51, 52

AGND

Analog Ground

21

VRBF

VRBS

VIN

Reference-Voltage Force Bottom

Reference-Voltage Sense Bottom

Analog Input Voltage. Can be either voltage or sense.

Reference-Voltage Middle, nominally -1V

Reference-Voltage Force Top

Reference-Voltage Sense Top

Inverse Clock Input

24

32, 33

35

VRM

42

VRTF

VRTS

NCLK

CLK

43

48

50

Clock Input

53

DRA

Data Ready Bank A

55

NDRA

D0A

Not Data Ready Bank A

57

Data Output Bank A, Bit 0 (LSB)

Data Output Bank A, Bits 1–6

Data Output Bank A, Bit 7 (MSB)

Data Output Bank A, Bit 8 (OVR)

Not Data Ready Bank B

59, 61, 62, 65, 66, 68

D1A–D6A

D7A

70

72

74

76

78

80

D8A

NDRB

DRB

Data Ready Bank B

D0B

Data Output Bank B, Bit 0 (LSB)

Data Output Bank B, Bit 1

D1B

signal’s dynamic state on the input comparators’ latching

characteristics. The preamplifiers act as buffers to stabi-

lize the input capacitance so that it remains constant over

different input voltage and frequency ranges, making the

part easier to drive than previous flash converters. The

preamplifiers also add a gain of +2 to the input signal, so

that each comparator has a wider overdrive or threshold

range to trip into or out of the active state. This gain

reduces metastable states that can cause errors at the

output.

_______________De t a ile d De s c rip t io n

The MAX1151 is one of the fastest monolithic, 8-bit, paral-

lel, flash analog-to-digital converters (ADCs) available

today. The nominal conversion rate is 750Msps, and the

a na log ba ndwidth is in e xc e ss of 900MHz. A ma jor

advance over previous flash converters is the inclusion of

255 input preamplifiers between the reference ladder and

input comparators (see Functional Diagram). This not

only reduces clock transient kickback to the input and

reference ladder but also reduces the effect of the input

4

_______________________________________________________________________________________

8 -Bit , 7 5 0 Ms p s Fla s h ADC

MAX51

The MAX1151 has true differential analog and digital

data paths from the preamplifiers to the output buffers

(current-mode logic) for reducing potential missing

codes while rejecting common-mode noise.

Table 1. Output Coding

V

(V)

D8

D7 . . . D0

IN

0

1

10000000

10000001

Signature errors are also reduced by careful layout of the

analog circuitry. The device’s output drive capability can

provide full ECL swings into 50Ω loads.

10000011

•

10100001

Typ ic a l In t e rfa c e Circ u it

The circuit of Figure 1 shows a method of achieving the

least error by correcting for integral linearity, input-

induced distortion, and power-supply/ground noise. This

is achieved with the use of external reference-ladder tap

connections, an input buffer, and supply decoupling.

Contact the factory for the MAX1150/MAX1151 evalua-

tion kit manual, which contains more details on interfac-

ing the MAX1151. The function of each pin and external

connections to other components are described in the fol-

lowing sections.

-0.5

-1.0

-1.5

0

10100000

11100000

•

11000001

11000000

01000000

•

01100001

01100000

00100000

•

V , AGND, DGND

EE

•

V

EE

is the supply pin with AGND as ground for the

00000011

00000001

00000000

device. The power-supply pins should be bypassed as

close to the device as possible with at least a 0.01µF

ceramic capacitor. A 1µF tantalum can also be used for

low-frequency suppression. DGND is the ground for the

ECL outputs, and should be referenced to the output

pulldown voltage and appropriately bypassed, as shown

in Figure 1.

-2.0

0

VRBF, VRBS, VRTF, VRTS, VRM

(Reference Inputs)

There are two reference inputs and one external refer-

ence voltage tap. These are -2V (VRB force and sense),

mid-tap (VRM), and AGND (VRT force and sense). The

reference pins and tap can be driven by op amps (as

shown in Figure 1), or VRM can be bypassed for limited

temperature operation. These voltage inputs can be by-

p a s s e d to AGND for furthe r nois e s up p re s s ion, if

desired.

VIN (Analog Input)

There are two analog input pins that are tied to the same

point internally. Either one may be used as an analog

input sense, while the other is used for input force. This is

convenient for testing the source signal to see if there is

sufficient drive capability. The pins can also be tied to-

gether and driven by the same source. The MAX1151 is

superior to similar devices due to a preamplifier stage

before the comparators. This makes the device easier to

drive because it has constant capacitance and induces

less slew-rate distortion.

Th e rm a l Ma n a g e m e n t

The typical thermal impedance (θ ) for the MQUAD

CA

package has been measured at θ

CA

= 17°C/W, in still

air with no heatsink.

CLK, NCLK (Clock Inputs)

The clock inputs are designed to be driven differentially

with ECL levels. The duty cycle of the clock should be

kept at 50%, to avoid causing larger second harmonics.

If this is not important to the intended application, duty

cycles other than 50% may be used.

To ensure rated performance, we highly recommend

using this device with a heatsink that can provide ade-

quate air flow. We have found that a Thermalloy 17846

heatsink with a minimum air flow of 1 meter/second

(200 linear feet per minute) provides adequate thermal

performance under laboratory tests. Application-specif-

ic conditions should be taken into account to ensure

that the device is properly heat sinked.

D0 to D8, DR, NDR (A and B)

The digital outputs can drive 50Ω to ECL levels when

pulled down to -2V. When pulled down to -5.2V, the out-

puts can drive 130Ω to 1kΩ loads. All digital outputs are

gray code, with the coding as shown in Table 1.

_______________________________________________________________________________________

5

8 -Bit , 7 5 0 Ms p s Fla s h ADC

V

IN

VIN

NDRB (NOT DATA READY)

DRB (DATA READY)

D8B (OVR)

50Ω

VIN

D7B (MSB)

D6B

MAX51

D5B

VRTF

D4B

D3B

D2B

R

MAX1151

VRTS

VRM

D1B

D0B (LSB)

NDRA (NOT DATA READY)

DRA (DATA READY)

D8A (OVR)

D7A (MSB)

D6A

22Ω

U1

**

D5A

R

D4A

D3A

D2A

VRBS

VRBF

1N2907

22Ω

D1A

-2.0V

U1

U2

REFERENCE

**

D0A (LSB)

-5.2V

*

CLK

CLOCK IN

*

NCLK

-2.0V

PULL-DOWN

(DIGITAL)

50Ω

0.1µF

V

EE

AGND

DGND

-2V

PULL-DOWN

(ANALOG)

L = Ferrite bead, DIGIKEY P98208BK or equivalent

L

* = 50Ω resistor

**

* * = 10µF tantalum capacitor and 0.1µF chip capacitor

-5.2V

U1 = OP220 or equivalent with low offset/noise

R = 1kΩ; 0.1% matched

= AGND

= DGND

U2 = Motorola ECLinPS Lite, MC10EL16, differential receiver

with 250ps (typ) propagation delay

Figure 1. Typical Interface Circuit

6

_______________________________________________________________________________________

8 -Bit , 5 0 0 Ms p s Fla s h ADC

MAX51

Op e ra t io n

The MAX1151 has 255 preamplifier/comparator pairs;

each is supplied with the voltage from VRT to VRB,

divided equally by the resistive ladder as shown in the

Functional Diagram. This voltage is applied to the posi-

tive input of each preamplifier/comparator pair. An ana-

log input voltage applied at VIN is connected to the

negative inputs of each preamplifier/comparator pair.

The comparators are then clocked through each one’s

individual clock buffer. When the CLK pin is in the low

state, the master or input stage of the comparators

compares the analog input voltage to the respective

reference voltage. When CLK changes from low to

high, the comparators are latched to the state prior to

the clock transition and output logic codes in sequence

from the top comparators, closest to VRT (0V), down to

the p oint whe re the ma g nitud e of the inp ut s ig na l

changes sign (thermometer code). The output of each

comparator is then registered into four 64-to-6 bit de-

coders when CLK is changed from high to low. At the

output of the decoders is a set of four 7-bit latches that

are enabled (track) when the clock changes from high

to low. From here, the output of the latches is coded

into six LSBs from four columns, and four columns are

coded into two MSBs. Finally, eight ECL output latches

and buffers are used to drive the external loads. The

conversion takes one clock cycle from the input to the

data outputs.

N + 5

N

N + 1

N + 6

N + 4

1.3ns

VIN

N + 7

N + 3

N + 2

CLK

NCLK

DRA

NDRA

1.4ns

TYP

DATA BANK A

N - 2

N

N + 2

N + 4

1.75ns

TYP

DRB

NDRB

1.4ns

TYP

DATA BANK B

N + 1

N + 3

N - 1

1.75ns

TYP

Figure 2. Timing Diagram

INPUT CIRCUIT

OUTPUT CIRCUIT

CLOCK INPUT

AGND

DGND

CLK

VIN

V

R

NCLK

DATA OUT

V

EE

V

EE

Figure 3. Subcircuit Schematics

_______________________________________________________________________________________

7

8 -Bit , 7 5 0 Ms p s Fla s h ADC

____________________________________________________________P in Co n fig u ra t io n

TOP VIEW

D2B

D3B

D4B

1

2

3

4

5

6

7

8

9

64 N.C.

63 N.C.

62 D3A

61 D2A

MAX51

V

EE

V

EE

60

V

EE

D5B

DGND

D6B

59 D1A

58 DGND

57 D0A

DGND

56 DGND

55 NDRA

54 DGND

53 DRA

52 AGND

51 AGND

50 CLK

D7B 10

DGND 11

D8B 12

MAX1151

N.C. 13

N.C. 14

AGND 15

AGND 16

49

48

47

46

45

44

43

42

41

V

EE

AGND

NCLK

17

18

19

20

21

22

23

24

V

EE

V

EE

V

EE

V

EE

AGND

VRTS

VRTF

N.C.

V

RBF

V

EE

V

EE

V

RBS

MQUAD

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

8

___________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0


型号：	MAX1151BIZS
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	8-Bit, 750Msps Flash ADC 8位， 750Msps ADC闪光
文件：	总8页 (文件大小：81K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1151BIZS [MAXIM]

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