MAX11606_V01 [MAXIM]
Low-Power, 4-/8-/12-Channel, I2C, 10-Bit ADCs in Ultra-Small Packages;
| 型号： | MAX11606_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Power, 4-/8-/12-Channel, I2C, 10-Bit ADCs in Ultra-Small Packages |
| 文件： | 总22页 (文件大小：964K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
Click here for production status of specific part numbers.
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
General Description
The MAX11606–MAX11611 low-power, 10-bit, multichannel,
Benefits and Features
● Reduce Cost with Highly Integrated ADCs
analog-to-digital converters (ADCs) feature internal track/
hold (T/H), voltage reference, clock, and an I C-
• Internal Reference
2
• 2.048V (MAX11607/MAX11609/MAX11611)
• 4.096V (MAX11606/MAX11608/MAX11610)
• External Reference Option: 1V to V
• Internal Clock
• 4-Channel Single-Ended or 2-Channel Fully
Differential (MAX11606/MAX11607)
• 8-Channel Single-Ended or 4-Channel Fully
Differential (MAX11608/MAX11609)
compatible 2-wire serial interface. These devices oper-
ate from a single supply of 2.7V to 3.6V (MAX11607/
MAX11609/MAX11611) or 4.5V to 5.5V (MAX11606/
MAX11608/MAX11610) and require only 670µA at the
maximum sampling rate of 94.4ksps. Supply current
falls below 230µA for sampling rates under 46ksps.
AutoShutdown™ powers down the devices between
conversions, reducing supply current to less than 1µA at
low throughput rates. The MAX11606/MAX11607 have 4
analog input channels each, the MAX11608/MAX11609
have 8 analog input channels each, while the MAX11610/
MAX11611 have 12 analog input channels each. The
fully differential analog inputs are software configurable
for unipolar or bipolar, and single ended or differential
operation.
DD
• 12-Channel Single-Ended or 6-Channel Fully
Differential (MAX11610/MAX11611)
• Internal FIFO with Channel-Scan Mode
• Software-Configurable Unipolar/Bipolar
2
• High-Speed I C-Compatible Serial Interface
• 400kHz Fast Mode
• 1.7MHz High-Speed Mode
● Simplify Power-Supply Design with Single-Supply
Operation
The full-scale analog input range is determined by
the internal reference or by an externally applied
• 2.7V to 3.6V (MAX11607/MAX11609/MAX11611)
• 5V to 5.5V (MAX11606/MAX11608/MAX11610)
• Low Power
reference voltage ranging from 1V to V . The MAX11607/
DD
MAX11609/MAX11611 feature
a
2.048V internal
reference and the MAX11606/MAX11608/MAX11610
feature a 4.096V internal reference.
• 670µA at 94.4ksps
• 230µA at 40ksps
• 60µA at 10ksps
• 6µA at 1ksps
The MAX11606/MAX11607 are available in an 8-pin
µMAX package. The MAX11607 is also available in
®
• 0.5µA in Power-Down Mode
● Reduce Size with Ultra-Small Packages
• 8-Pin µMAX (MAX11606/MAX11607)
• 12-Pin 1.9mm x 2.2mm, Wafer-Level Package
(MAX11607)
an ultra-small 1.9mm x 2.2mm WLP package. The
MAX11608–MAX11611 are available in a 16-pin QSOP
package. The MAX11606–MAX11611 are guaranteed
over the extended temperature range (-40°C to +85°C).
For pin-compatible 12-bit parts, refer to the MAX11612–
MAX11617 data sheet. For pin-compatible 8-bit parts,
refer to the MAX11600–MAX11605 data sheet.
● 16-Pin QSOP (MAX11608–MAX11611)
Ordering Information
Applications
● Handheld Portable
2
PIN-
PACKAGE
I C SLAVE
ADDRESS
PART
TEMP RANGE
● Solar-Powered Remote
Systems
● Received-Signal-Strength
Indicators
Applications
MAX11606EUA+ -40°C to +85°C 8 µMAX
MAX11607EUA+ -40°C to +85°C 8 µMAX
MAX11607EWC+ -40°C to +85°C 12 WLP
0110100
0110100
0110100
0110011
0110011
0110101
0110101
● Medical Instruments
● Battery-Powered Test
Equipment
● System Supervision
MAX11608EEE+
MAX11609EEE+
MAX11610EEE+
MAX11611EEE+
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
Pin Configurations, Typical Operating Circuit, and Selector
Guide appear at end of data sheet.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
+Denotes a lead(Pb)-free/RoHs-compliant package.
μMAX is a registered trademark of Maxim Integrated Products, Inc.
19-4560; Rev 5; 2/19
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Absolute Maximum Ratings
V
to GND ............................................................-0.3V to +6V
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
DD
AIN0–AIN11,
REF to GND .........-0.3V to the lower of (V
+ 0.3V) and 6V
DD
SDA, SCL to GND...................................................-0.3V to +6V
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (T = +70°C)
A
8-Pin µMAX (derate 5.9mW/°C above +70°C).........470.6mW
12-Pin WLP (derate 16.1mW/°C above +70°C)........1288mW
16-Pin QSOP (derate 8.3mW/°C above +70°C).......666.7mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
DD
(V
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
= 2.048V
DD
REF
(MAX11607/MAX11609/MAX11611), V
= 4.096V (MAX11606/MAX11608/MAX11610), f
= 1.7MHz, T = T
to T , unless
MAX
REF
SCL
A
MIN
otherwise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.) (Note 1)
A
PARAMETER
DC ACCURACY (Note 2)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
Bits
LSB
LSB
LSB
Relative Accuracy
Differential Nonlinearity
Offset Error
INL
(Note 3)
±1
±1
±1
DNL
No missing codes over temperature
Offset-Error Temperature
Coefficient
Relative to FSR
0.3
ppm/°C
Gain Error
(Note 4)
±1
LSB
Gain-Temperature Coefficient
Relative to FSR
0.3
ppm/°C
Channel-to-Channel Offset
Matching
±0.1
LSB
LSB
Channel-to-Channel Gain
Matching
±0.1
DYNAMIC PERFORMANCE (f
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious Free Dynamic Range
Full-Power Bandwidth
= 10kHz, V
= V
, f
= 94.4ksps)
IN(SINE-WAVE)
IN(P-P)
REF SAMPLE
SINAD
60
-70
70
dB
dB
THD
Up to the 5th harmonic
SFDR
dB
SINAD > 57dB
-3dB point
3.0
5.0
MHz
MHz
Full-Linear Bandwidth
CONVERSION RATE
Internal clock
6.8
Conversion Time (Note 5)
t
µs
CONV
External clock
10.6
800
Internal clock, SCAN[1:0] = 01
53
53
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX11610/MAX11611)
External clock
Throughput Rate
f
ksps
ns
SAMPLE
94.4
Track/Hold Acquisition Time
Maxim Integrated
│ 2
www.maximintegrated.com
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Electrical Characteristics (continued)
DD
(V
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
= 2.048V
DD
REF
(MAX11607/MAX11609/MAX11611), V
= 4.096V (MAX11606/MAX11608/MAX11610), f
= 1.7MHz, T = T
to T , unless
MAX
REF
SCL
A
MIN
otherwise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2.8
60
MAX
UNITS
Internal Clock Frequency
MHz
External clock, fast mode
Aperture Delay (Note 6)
t
ns
AD
External clock, high-speed mode
30
ANALOG INPUT (AIN0–AIN11)
Unipolar
Bipolar
0
0
V
REF
Input-Voltage Range, Single-
Ended and Differential (Note 7)
V
±V
/2
REF
Input Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V
= 0V or V
±0.01
22
±1
µA
pF
AIN_
DD
C
IN
INTERNAL REFERENCE (Note 8)
MAX11607/MAX11609/MAX11611
MAX11606/MAX11608/MAX11610
1.968
3.939
2.048
4.096
2.128
4.256
Reference Voltage
V
T
= +25°C
V
REF
A
Reference-Voltage Temperature
Coefficient
TCVREF
25
ppm/°C
REF Short-Circuit Current
REF Source Impedance
EXTERNAL REFERENCE
REF Input-Voltage Range
REF Input Current
2
mA
1.5
kΩ
V
(Note 9)
1
V
V
REF
DD
I
f
= 94.4ksps
40
µA
REF
SAMPLE
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
x
x
Input High Voltage
Input Low Voltage
Input Hysteresis
V
0.7
0.1
V
V
V
V
IH
DD
x
V
DD
V
0.3
IL
V
V
HYST
DD
Input Current
I
V
= 0 to V
DD
±10
0.4
µA
pF
V
IN
IN
Input Capacitance
Output Low Voltage
POWER REQUIREMENTS
C
15
IN
V
I
= 3mA
OL
SINK
MAX11607/MAX11609/MAX11611
MAX11606/MAX11608/MAX11610
2.7
4.5
3.6
5.5
Supply Voltage
Supply Current
V
V
DD
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
900
670
530
230
380
60
1150
900
f
= 94.4ksps
SAMPLE
external clock
f
= 40ksps
SAMPLE
internal clock
I
μA
f
= 10ksps
DD
SAMPLE
internal clock
330
6
f
=1ksps
SAMPLE
internal clock
Shutdown (internal reference off)
0.5
10
Maxim Integrated
│ 3
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Electrical Characteristics (continued)
DD
(V
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
= 2.048V
DD
REF
(MAX11607/MAX11609/MAX11611), V
= 4.096V (MAX11606/MAX11608/MAX11610), f
= 1.7MHz, T = T
to T , unless
MAX
REF
SCL
A
MIN
otherwise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Power-Supply Rejection Ratio
PSRR
Full-scale input (Note 10)
±0.01
±0.5
LSB/V
Timing Characteristics (Figure 1)
DD
(V
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V = 2.048V
REF
DD
(MAX11607/MAX11609/MAX11611), V
otherwise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.) (Note 1)
= 4.096V (MAX11606/MAX11608/MAX11610), f
= 1.7MHz, T = T
to T , unless
REF
SCL
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
f
400
kHz
µs
SCL
Bus Free Time Between a
STOP (P) and a
t
1.3
BUF
START (S) Condition
Hold Time for START (S) Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t
t
0.6
1.3
0.6
µs
µs
µs
HD,STA
t
LOW
t
HIGH
Setup Time for a Repeated
START Condition (Sr)
0.6
µs
SU,STA
Data Hold Time
Data Setup Time
t
(Note 11)
0
900
ns
ns
HD,DAT
t
100
SU,DAT
Rise Time of Both SDA and SCL
Signals, Receiving
t
Measured from 0.3V
Measured from 0.3V
to 0.7V
to 0.7V
20 + 0.1C
B
300
300
ns
R
DD
DD
DD
Fall Time of SDA Transmitting
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
(Note 12) 20 + 0.1C
0.6
ns
µs
pF
ns
F
DD
B
t
SU,STO
C
400
50
B
t
SP
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C = 400pF, Note 13)
B
Serial-Clock Frequency
f
(Note 14)
1.7
MHz
ns
SCLH
Hold Time, Repeated START
Condition (Sr)
t
160
HD,STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
320
120
ns
ns
LOW
t
HIGH
Setup Time for a Repeated
START Condition (Sr)
t
160
ns
SU,STA
Data Hold Time
Data Setup Time
t
(Note 11)
0
150
ns
ns
HD,DAT
t
10
SU,DAT
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Timing Characteristics (Figure 1) (continued)
(V
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
= 2.048V
DD
DD
REF
(MAX11607/MAX11609/MAX11611), V
otherwise noted. Typical values are at T = +25°C. See Tables 1–5 for programming notation.) (Note 1)
= 4.096V (MAX11606/MAX11608/MAX11610), f
= 1.7MHz, T = T
to T , unless
MAX
REF
SCL
A
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time of SCL Signal
(Current Source Enabled)
t
Measured from 0.3V
Measured from 0.3V
to 0.7V
to 0.7V
20
80
ns
RCL
DD
DD
DD
Rise Time of SCL Signal after
Acknowledge Bit
t
20
160
ns
RCL1
DD
Fall Time of SCL Signal
t
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
to 0.7V
to 0.7V
to 0.7V
20
20
80
ns
ns
ns
ns
pF
ns
FCL
DD
DD
DD
DD
DD
DD
Rise Time of SDA Signal
t
160
160
RDA
Fall Time of SDA Signal
t
(Note 12)
20
FDA
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
160
SU,STO
C
400
10
B
t
(Notes 11 and 14)
0
SP
Note 1: All WLP devices are 100% production tested at T = +25°C. Specifications over temperature limits are guaranteed by design
A
and characterization.
Note 2: For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at V
= 5V and the MAX11607/MAX11609/MAX11611 are
DD
tested at V
= 3V. All devices are configured for unipolar, single-ended inputs.
DD
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets
have been calibrated.
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion time
does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
.
DD
Note 8: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.1μF
capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).
Note 9: ADC performance is limited by the converter’s noise floor, typically 300μV
Note 10: Measured as follows for the MAX11607/MAX11609/MAX11611:
.
P-P
2N − 1
V
(3.6V ) − V (2.7V ) ×
FS
FS
V
REF
(3.6V − 2.7V )
and for the MAX11606/MAX11608/MAX11610, where N is the number of bits:
2N − 1
V
(5.5V ) − V (4.5V ) ×
FS
FS
V
REF
(5.5V − 4.5V )
Note 11: A master device must provide a data hold time for SDA (referred to V of SCL) to bridge the undefined region of SCL’s falling
IL
edge (see Figure 1).
Note 12: The minimum value is specified at T = +25°C.
A
Note 13: C = total capacitance of one bus line in pF.
B
Note 14: f
must meet the minimum clock low time plus the rise/fall times.
SCL
Maxim Integrated
│ 5
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Typical Operating Characteristics
DD
(V
= 3.3V (MAX11607/MAX11609/MAX11611), V
= 5V (MAX11606/MAX11608/MAX11610), f
= 1.7MHz, external clock,
DD
SCL
f
= 94.4ksps, single-ended, unipolar, T = +25°C, unless otherwise noted.)
SAMPLE
A
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
FFT PLOT
0.5
0.4
0.3
0.2
0.1
0
0
-20
0.3
0.2
0.1
0
f
f
= 94.4ksps
SAMPLE
= 10kHz
IN
-40
-60
-80
-0.1
-0.2
-0.3
-0.4
-0.5
-100
-120
-140
-160
-0.1
-0.2
-0.3
0
200
400
600
800
1000
0
200
400
600
800
1000
0
10k
20k
30k
40k
50k
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
FREQUENCY (Hz)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
800
750
700
650
600
550
500
450
400
350
300
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.6
0.5
0.4
0.3
0.2
0.1
0
SDA = SCL = V
MAX11610/MAX11608/
MAX11606
DD
INTERNAL REFERENCE
MAX11610/MAX11608/MAX11606
MAX11611/MAX11609/MAX11607
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
MAX11611/MAX11609/
MAX11607
INTERNAL REFERENCE
MAX11610/MAX11608/
MAX11606
EXTERNAL REFERENCE
MAX11611/MAX11609/
MAX11607
EXTERNAL REFERENCE
-40 -25 -10
5
20 35 50 65 80
2.7
3.2
3.7
4.2
4.7
5.2
-40
-10
5
20 35 50 65 80
-25
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE (EXTERNAL CLOCK)
800
800
750
700
650
600
550
500
450
400
350
300
250
200
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
A
700
600
500
A
B
B
400
300
200
MAX11611/MAX11609/MAX11607
MAX11610/MAX11608/MAX11606
0
10 20 30 40 50 60 70 80 90 100
CONVERSION RATE (ksps)
0
20
40
60
80
100
CONVERSATION RATE (ksps)
Maxim Integrated
│
6
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Typical Operating Characteristics (continued)
(V
= 3.3V (MAX11607/MAX11609/MAX11611), V
= 5V (MAX11606/MAX11608/MAX11610), f
= 1.7MHz, external clock,
DD
DD
SCL
f
= 94.4ksps, single-ended, unipolar, T = +25°C, unless otherwise noted.)
SAMPLE
A
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
1.00010
1.0010
1.0008
1.0006
1.0004
1.0002
1.0000
0.9998
0.9996
0.9994
0.9992
0.9990
NORMALIZED TO REFERENCE VALUE
= +25°C
MAX11610/11608/MAX11606,
NORMALIZED TO
REFERENCE VALUE AT
1.00008
1.00006
1.00004
1.00002
1.00000
0.99998
0.99996
0.99994
0.99992
0.99990
T
A
MAX11610/MAX11608/MAX11606
V
DD
= 5V
MAX11611/11609/MAX11607,
NORMALIZED TO
REFERENCE VALUE AT
MAX11611/MAX11609/MAX11607
V
DD
= 3.3V
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
(V)
-40 -25 -10
5
20 35 50 65 80
V
DD
TEMPERATURE (°C)
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
(V)
-40 -25 -10
5
20 35 50 65 80
V
DD
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
-40 -25 -10
5
20 35 50 65 80
V
DD
TEMPERATURE (°C)
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Pin Description
PIN
MAX11606
MAX11607
MAX11608
MAX11609
MAX11610
MAX11611
MAX11607
NAME
FUNCTION
µMAX
1, 2, 3
—
WLP
A1, A2, A3
—
QSOP
5, 6, 7
8–12
—
5, 6, 7
8–12
AIN0, AIN1, AIN2
AIN3–AIN7
Analog Inputs
—
—
4, 3, 2
AIN8, AIN9, AIN10
Analog Input 3/Reference Input or Output.
Selected in the setup register (see Tables 1 and 6).
4
A4
—
—
—
1
—
—
1
AIN3/REF
REF
Reference Input or Output. Selected in the setup
register (see Tables 1 and 6).
—
—
Analog Input 11/Reference Input or Output.
Selected in the setup register (see Tables 1 and 6).
—
AIN11/REF
5
6
C4
C3
13
14
13
14
15
16
—
SCL
SDA
GND
Clock Input
Data Input/Output
7
B1–B4, C2
C1
15
Ground
8
16
V
Positive Supply. Bypass to GND with a 0.1µF capacitor.
No Connection. Not internally connected.
DD
—
—
2, 3, 4
N.C.
A. F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
t
R
t
F
t
SDA
t
t
HD:DAT
SU:DAT
t
t
BUF
HD:STA
t
LOW
t
t
SU:STO
SU:STA
SCL
t
HD:STA
t
HIGH
t
R
t
F
S
Sr
A
P
S
B. HS-MODE 2-WIRE SERIAL-INTERFACE TIMING
t
t
RDA
FDA
SDA
t
t
HD:DAT
SU:DAT
t
BUF
t
HD:STA
t
LOW
t
SU:STO
t
SU:STA
SCL
t
t
HIGH
HD:STA
t
t
FCL
t
RCL
RCL1
S
Sr
A
S
F/S MODE
P
HS MODE
Figure 1. 2-Wire Serial-Interface Timing
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
SDA
SCL
INPUT SHIFT REGISTER
SETUP REGISTER
V
DD
INTERNAL
OSCILLATOR
CONTROL
LOGIC
GND
CONFIGURATION REGISTER
AIN0
AIN1
OUTPUT SHIFT
REGISTER
AND RAM
10-BIT
ADC
AIN2
T/H
AIN3
AIN4
ANALOG
INPUT
MUX
AIN5
REF
AIN6
AIN7
AIN8
REFERENCE
4.096V (MAX11610)
2.048V (MAX11611)
MAX11610
MAX11611
AIN9
AIN10
AIN11/REF
Figure 2. MAX11610/MAX11611 Functional Diagram
Power Supply
V
DD
The MAX11606–MAX11611 operates from a single
supply and consumes 670µA (typ) at sampling rates
up to 94.4ksps. The MAX11607/MAX11609/MAX11611
feature a 2.048V internal reference and the MAX11606/
I
OL
MAX11608/MAX11610 feature
reference. All devices can be configured for use with an
external reference from 1V to V
a
4.096V internal
V
SDA
OUT
400pF
.
DD
Analog Input and Track/Hold
I
OH
The MAX11606–MAX11611 analog-input architecture
contains an analog-input multiplexer (mux), a fully dif-
ferential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
Figure 3. Load Circuit
Detailed Description
In single-ended mode, the analog-input multiplexer con-
The MAX11606–MAX11611 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) circuitry
to capture and convert an analog signal to a serial 12-bit
digital output. The MAX11606/MAX11607 are 4-channel
ADCs, the MAX11608/MAX11609 are 8-channel ADCs,
and the MAX11610/MAX11611 are 12-channel ADCs.
These devices feature a high-speed 2-wire serial inter-
face supporting data rates up to 1.7MHz. Figure 2 shows
the simplified internal structure for the MAX11610/
MAX11611.
nects C
between the analog input selected by CS[3:0]
T/H
(see the Configuration/Setup Bytes (Write Cycle) section)
and GND (Table 3). In differential mode, the analog- input
multiplexer connects C
selected by CS[3:0] (Table 4).
to the + and - analog inputs
T/H
During the acquisition interval, the T/H switches are in
the track position and C
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
charges to the analog input
T/H
on C
as a stable sample of the input signal.
T/H
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage
to 0V within the limits of 10-bit resolution. This action
requires 10 conversion clock cycles and is equivalent to
during the shifting out of the first byte of the result. The
conversion is performed during the next 10 clock cycles.
The time required for the T/H circuitry to acquire an input
signal is a function of the input sample capacitance. If the
analog-input source impedance is high, the acquisition
time constant lengthens and more time must be allowed
transferring a charge of 11pF x (V
- V ) from C
IN+
IN- T/H
to the binary weighted capacitive DAC, forming a digital
representation of the analog input signal.
between conversions. The acquisition time (t
) is the
ACQ
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larger
source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
minimum time needed for the signal to be acquired. It is
calculated by:
t
≥ 9 x (R
+ R ) x C
SOURCE IN IN
ACQ
where R
is the analog-input source impedance,
is 1.5/f for internal
SOURCE
R
= 2.5kΩ, and C = 22pF. t
IN
IN
ACQ
SCL
clock mode and t
= 2/f
for external clock mode.
ACQ
SCL
Analog Input Bandwidth
The MAX11606–MAX11611 feature input-tracking cir-
cuitry with a 5MHz small-signal bandwidth. The 5MHz
input bandwidth makes it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
under sampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte (see the Slave Address section). The
T/H circuitry enters hold mode on the falling clock edge
of the acknowledge bit of the address byte (the ninth
clock pulse). A conversion or a series of conversions is
then internally clocked and the MAX11606–MAX11611
holds SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising edge
of the clock during the read (R/W = 1) bit. Hold mode is
then entered on the rising edge of the second clock pulse
Analog Input Range and Protection
Internal protection diodes clamp the analog input to V
DD
and GND. These diodes allow the analog inputs to swing
from (V
- 0.3V) to (V
+ 0.3V) without causing
GND
DD
HOLD
ANALOG INPUT MUX
REF
C
T/H
AIN0
AIN1
TRACK
CAPACITIVE
DAC
AIN2
V /2
DD
AIN3/REF
GND
CAPACITIVE
DAC
TRACK
MAX11606
MAX11607
C
T/H
REF
HOLD
Figure 4. Equivalent Input Circuit
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
damage to the device. For accurate conversions the
on SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is stable are
considered control signals (see the START and STOP
Conditions section). Both SDA and SCL remain high when
the bus is not busy.
inputs must not go more than 50mV below V
or
GND
above V
.
DD
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX11606–MAX11611 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are the
difference between the analog input selected by CS[3:0]
and GND (Table 3). In differential mode (SGL/DIF = 0), the
digital conversion results are the difference between the +
and the - analog inputs selected by CS[3:0] (Table 4).
START and STOP Conditions
The master initiates a transmission with a START condition
(S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the mode unchanged (see the HS Mode section).
Unipolar/Bipolar
Acknowledge Bits
When operating in differential mode, the BIP/UNI bit
of the setup byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input range
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master and
the MAX11606–MAX11611 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep it
low during the high period of the clock pulse (Figure 6). To
generate a not-acknowledge, the receiver allows SDA to
be pulled high before the rising edge of the acknowledge-
related clock pulse and leaves SDA high during the high
period of the clock pulse. Monitoring the acknowledge bits
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer happens if a receiving device
is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
from 0 to V
. A negative differential analog input in
REF
unipolar mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to ±V
/2. The digital output code is binary in unipolar
REF
mode and two’s complement in bipolar mode. See the
Transfer Functions section.
In single-ended mode, the MAX11606–MAX11611
always operate in unipolar mode irrespective of BIP/UNI.
The analog inputs are internally referenced to GND with a
full-scale input range from 0 to V
.
REF
2-Wire Digital Interface
The MAX11606–MAX11611 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock
line (SCL). SDA and SCL facilitate bidirectional com-
munication between the MAX11606–MAX11611 and the
master at rates up to 1.7MHz. The MAX11606–MAX11611
are slaves that transfer and receive data. The master
(typically a microcontroller) initiates data transfer on the
bus and generates the SCL signal to permit that transfer.
S
Sr
P
SDA
SCL
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Figure 5. START and STOP Conditions
Operating Circuit). Series resistors (R ) are optional.
S
They protect the input architecture of the MAX11606–
MAX11611 from high voltage spikes on the bus lines,
minimize crosstalk, and undershoot of the bus signals.
S
NOT ACKNOWLEDGE
Bit Transfer
SDA
One data bit is transferred during each SCL clock cycle.
A minimum of 18 clock cycles are required to transfer the
data in or out of the MAX11606–MAX11611. The data
ACKNOWLEDGE
8 9
1
2
SCL
Figure 6. Acknowledge Bits
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
DEVICE
SLAVE ADDRESS
0110100
MAX11606/MAX11607
MAX11608/MAX11609
MAX11610/MAX11611
0110011
0110101
SLAVE ADDRESS
MAX11606/MAX11607
S
0
1
1
0
1
0
0
R/W
A
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 7. MAX11606/MAX11607 Slave Address Byte
up to 94.4ksps. Figure 1 shows the bus timing for the
MAX11606–MAX11611’s 2-wire interface.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a slave
address. When idle, the MAX11606–MAX11611 continu-
ously wait for a START condition followed by their slave
address. When the MAX11606–MAX11611 recognize
their slave address, they are ready to accept or send
data. The slave address has been factory programmed
and is always 0110100 for the MAX11606/MAX11607,
0110011 for the MAX11608/MAX11609, and 0110101 for
MAX11610/MAX11611 (Figure 7). The least significant
bit (LSB) of the address byte (R/W) determines whether
the master is writing to or reading from the MAX11606–
MAX11611 (R/W = 0 selects a write condition, R/W = 1
selects a read condition). After receiving the address, the
MAX11606–MAX11611 (slave) issues an acknowledge by
pulling SDA low for one clock cycle.
HS Mode
At power-up, the MAX11606–MAX11611 bus timing is
set for F/S mode. The bus master selects HS mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After success-
fully receiving the HS-mode master code, the MAX11606–
MAX11611 issue a not-acknowledge, allowing SDA to
be pulled high for one clock cycle (Figure 8). After the
not-acknowledge, the MAX11606–MAX11611 are in HS
mode. The bus master must then send a repeated START
followed by a slave address to initiate HS-mode commu-
nication. If the master generates a STOP condition the
MAX11606–MAX11611 returns to F/S mode.
Bus Timing
At power-up, the MAX11606–MAX11611 bus timing is set
for fast mode (F/S mode), allowing conversion rates up
to 22.2ksps. The MAX11606–MAX11611 must operate in
high-speed mode (HS mode) to achieve conversion rates
HS-MODE MASTER CODE
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
F/S MODE
HS MODE
Figure 8. F/S-Mode to HS-Mode Transfer
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
byte (Table 2). The master can write either one or two
bytes to the slave in any order (setup byte then configuration
byte; configuration byte then setup byte; setup byte or
configuration byte only; Figure 9). If the slave receives a
byte successfully, it issues an acknowledge. The master
ends the write cycle by issuing a STOP condition or a
repeated START condition. When operating in HS mode,
a STOP condition returns the bus into F/S mode (see the
HS Mode section).
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a START
condition followed by seven address bits (Figure 7) and
a write bit (R/W = 0). If the address byte is successfully
received, the MAX11606–MAX11611 (slave) issues an
acknowledge. The master then writes to the slave. The
slave recognizes the received byte as the setup byte
(Table 1) if the most significant bit (MSB) is 1. If the MSB
is 0, the slave recognizes that byte as the configuration
MASTER TO SLAVE
SLAVE TO MASTER
A. ONE-BYTE WRITE CYCLE
1
7
1
1
8
1
1
NUMBER OF BITS
SETUP OR
CONFIGURATION BYTE
S
SLAVE ADDRESS
W
A
A P or Sr
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. TWO-BYTE WRITE CYCLE
1
7
1
1
8
1
8
1
1
NUMBER OF BITS
SETUP OR
CONFIGURATION BYTE
SETUP OR
CONFIGURATION BYTE
S
SLAVE ADDRESS
W
A
A
A
P or Sr
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
Table 1. Setup Byte Format
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
SEL1
BIT 4
BIT 3
BIT 2
BIP/UNI
BIT 1
REG
SEL2
SEL0
CLK
RST
X
BIT
7
NAME
REG
SEL2
SEL1
SEL0
CLK
DESCRIPTION
Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
6
Three bits select the reference voltage and the state of AIN_/REF
(MAX11606/MAX11607/MAX11610/MAX11611) or REF (MAX11608/MAX11609) (Table 6).
Defaulted to 000 at power-up.
5
4
3
1 = external clock, 0 = internal clock. Defaulted to 0 at power-up.
2
BIP/UNI
RST
1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section).
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t-care bit. This bit can be set to 1 or 0.
1
0
X
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Table 2. Configuration Byte Format
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
REG
SCAN1
SCAN0
CS3
CS2
CS1
CS0
SGL/DIF
BIT
7
NAME
REG
DESCRIPTION
Register bit. 1= setup byte (see Table 1), 0 = configuration byte.
6
SCAN1
SCAN0
CS3
Scan select bits. Two bits select the scanning configuration (Table 5). Defaults to 00 at power-up.
5
4
Channel select bits. Four bits select which analog input channels are to be used for conversion
(Table 3 and Table 4). Defaults to 0000 at power-up. For MAX11606/MAX11607, CS3 and CS2
are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.
3
CS2
2
CS1
1
CS0
1 = single-ended, 0 = differential (Table 3 and Table 4). Defaults to 1 at power-up.
See the Single-Ended/Differential Input section.
0
SGL/DIF
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
1
1
1
1
CS3
0
CS2
0
CS1
0
CS0 AIN0 AIN1 AIN2 AIN3
AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11
GND
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+
0
0
0
+
0
0
1
+
0
0
1
+
0
1
0
+
0
1
0
+
0
1
1
+
0
1
1
+
1
0
0
+
1
0
0
+
1
0
1
+
1
0
1
+
1
1
0
RESERVED
RESERVED
RESERVED
RESERVED
1
1
0
1
1
1
1
1
1
1
2
For the MAX11606/MAX11607, CS3 and CS2 are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.
When SEL1 = 1, a single-ended read of AIN3/REF (MAX11606/MAX11607) or AIN11/REF (MAX11610/MAX11611) is ignored; scan
stops at AIN2 or AIN10. This does not apply to the MAX11608/MAX11609 as each provides separate pins for AIN7 and REF.
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
1
1
2
2
CS3
0
CS2
0
CS1
0
CS0
0
AIN0 AIN1 AIN2 AIN3
AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11
+
-
-
0
0
0
1
+
0
0
1
0
+
-
-
0
0
1
1
+
0
1
0
0
+
-
-
0
1
0
1
+
0
1
1
0
+
-
-
0
1
1
1
+
1
0
0
0
+
-
-
1
0
0
1
+
1
0
1
0
+
-
-
1
0
1
1
+
1
1
0
0
RESERVED
RESERVED
RESERVED
RESERVED
1
1
0
1
1
1
1
0
1
1
1
1
1
2
For the MAX11606/MAX11607, CS3 and CS2 are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.
When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX11606/MAX11607) or AIN10 and AIN11/REF (MAX11610/
MAX11611) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011 returns
the negative difference between AIN10 and GND. This does not apply to the MAX11608/MAX11609 as each provides separate
pins for AIN7 and REF. In differential scanning, the address increments by 2 until the limit set by CS3–CS1 has been reached.
Data Byte (Read Cycle)
Internal Clock
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by seven address bits and
a read bit (R/W = 1). If the address byte is successfully
received, the MAX11606–MAX11611 (slave) issues an
acknowledge. The master then reads from the slave. The
result is transmitted in two bytes; first six bits of the first
byte are high, then MSB through LSB are consecutively
clocked out. After the master has received the byte(s), it
can issue an acknowledge if it wants to continue reading
or a not-acknowledge if it no longer wishes to read. If the
MAX11606–MAX11611 receive a not-acknowledge, they
release SDA, allowing the master to generate a STOP or
a repeated START cition. See the Clock Modes and Scan
Mode sections for detailed information on how data is
obtained and converted.
When configured for internal clock mode (CLK = 0), the
MAX11606–MAX11611 use their internal oscillator as the
conversion clock. In internal clock mode, the MAX11606–
MAX11611 begin tracking the analog input after a valid
address on the eighth rising edge of the clock. On the
falling edge of the ninth clock, the analog signal is
acquired and the conversion begins. While converting the
analog input signal, the MAX11606–MAX11611 holds SCL
low (clock stretching). After the conversion completes,
the results are stored in internal memory. If the scan
mode is set for multiple conversions, they all happen in
succession with each additional result stored in memory.
The MAX11606/MAX11607 contain four 10-bit blocks of
memory, the MAX11608/MAX11609 contain eight 10-bit
blocks of memory, and the MAX11610/MAX11611 contain
twelve 10-bit blocks of memory. Once all conversions
are complete, the MAX11606–MAX11611 release SCL,
allowing it to be pulled high. The master may now clock
the results out of the memory in the same order the scan
conversion has been done at a clock rate of up to
1.7MHz. SCL is stretched for a maximum of 7.6µs per
channel (see Figure 10).
Clock Modes
The clock mode determines the conversion clock and the
data acquisition and conversion time. The clock mode
also affects the scan mode. The state of the set-up byte’s
CLK bit determines the clock mode (Table 1). At power-
up, the MAX11606–MAX11611 are defaulted to internal
clock mode (CLK = 0).
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
1
1
8
8
1
1
NUMBER OF BITS
CLOCK STRETCH
S
SLAVE ADDRESS
R
A
RESULT 2 MSBs
A
RESULT 8 LSBs
A
P or Sr
t
ACQ
t
CONV
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NUMBER
OF BITS
1
7
1
1
8
1
8
1
8
1
8
1
1
CLOCK STRETCH
CLOCK STRETCH
S
SLAVE ADDRESS
R
A
RESULT 1 ( 2MSBs)
A
RESULT 1 (8 LSBs)
A
RESULT N (8MSBs)
A
RESULT N (8LSBs)
A
P or Sr
t
t
t
ACQ1
ACQ2
ACQN
t
t
t
CONVN
CONV1
CONV2
Figure 10. Internal Clock Mode Read Cycles
The device memory contains all of the conversion results
when the MAX11606–MAX11611 release SCL. The
converted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from a
multichannel scan. This does not apply to the MAX11608/
MAX11609 as each provides separate pins for AIN7 and
REF. The memory contents can be read continuously. If
reading continues past the result stored in memory, the
pointer wraps around and point to the first result. Note that
only the current conversion results are read from memory.
The device must be addressed with a read command to
obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during conver-
sion. Using the internal clock also frees the bus master
(typically a microcontroller) from the burden of running the
conversion clock, allowing it to perform other tasks that do
not need to use the bus.
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
1
1
8
1
8
1
1
NUMBER OF BITS
S
R
A
A
A
SLAVE ADDRESS
RESULT (2 MSBs)
RESULT (8 LSBs)
P OR Sr
t
ACQ
t
CONV
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
7
1
1
8
1
8
1
8
1
8
1
1
NUMBER OF BITS
S
R
A
A
A
A
A
P OR Sr
SLAVE ADDRESS
RESULT 1 (2 MSBs)
RESULT 2 (8 LSBs)
RESULT N (2 MSBs)
RESULT N (8 LSBs)
t
t
t
ACQ1
ACQ2
ACQN
t
t
CONV1
CONVN
Figure 11. External Clock Mode Read Cycle
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Table 5. Scanning Configuration
SCAN1 SCAN0
SCANNING CONFIGURATION
Scans up from AIN0 to the input selected by CS3–CS0. When CS3–CS0 exceeds 1011, the scanning stops
at AIN11. When AIN_/REF is set to be a REF input/output, scanning stops at AIN2 or AIN10.
0
0
0
1
*Converts the input selected by CS3–CS0 eight times (see Tables 3 and 4).
MAX11606/MAX11607: Scans upper half of channels.
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0, AIN1, and
AIN2, the only scan that takes place is AIN2 (MAX11606/MAX11607). When AIN/REF is set to be a REF input/
output, scanning stops at AIN2.
MAX11608/MAX11609: Scans upper quartile of channels.
1
1
0
1
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only scan
that takes place is AIN6 (MAX11608/MAX11609).
MAX11610/MAX11611: Scans upper half of channels.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only scan
that takes place is AIN6 (MAX11610/MAX11611). When AIN/REF is set to be a REF input/output, scanning
stops at selected channel or AIN10.
*Converts channel selected by CS3–CS0.
* When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not acknowledge occurs.
memory in the same order as the conversion. Read the
results from memory in the order they were converted.
Each result needs a 2-byte transmission, the first byte
begins with six empty bits during which SDA is left high.
Each byte has to be acknowledged by the master or the
memory transmission is terminated. It is not possible to
read the memory independently of conversion.
External Clock
When configured for external clock mode (CLK = 1), the
MAX11606–MAX11611 use the SCL as the conversion
clock. In external clock mode, the MAX11606–MAX11611
begin tracking the analog input on the ninth rising clock
edge of a valid slave address byte. Two SCL clock cycles
later the analog signal is acquired and the conversion
begins. Unlike internal clock mode, converted data is
available immediately after the first four empty high bits.
The device continuously converts input channels dictated
by the scan mode until given a not acknowledge. There is
no need to re-address the device with a read command to
obtain new conversion results (see Figure 11).
Applications Information
Power-On Reset
The configuration and setup registers (Table 1 and Table 2)
default to a single-ended, unipolar, single-channel
conversion on AIN0 using the internal clock with V
as
DD
The conversion must complete in 1ms or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period exceeds
60µs.
the reference and AIN_/REF configured as an analog
input. The memory contents are unknown after power-up.
Automatic Shutdown
Automatic shutdown occurs between conversions when
the MAX11606–MAX11611 are idle. All analog circuits
participate in automatic shutdown except the internal
reference due to its prohibitively long wake-up time. When
operating in external clock mode, a STOP, not-acknowl-
edge or repeated START, condition must be issued to
place the devices in idle mode and benefit from automatic
shutdown. A STOP condition is not necessary in internal
clock mode to benefit from automatic shutdown because
power-down occurs once all conversion results are written
to memory (Figure 10). When using an external reference
The MAX11606–MAX11611 must operate in external
clock mode for conversion rates from 40ksps to 94.4ksps.
Below 40ksps internal clock mode is recommended due
to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference input
or output (SEL1 = 1, Table 6), AIN_/REF is excluded from
a multichannel scan. The scanned results are written to
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Table 6. Reference Voltage, AIN_/REF, and REF Format
AIN_/REF
(MAX11606/
REF
(MAX11608/
MAX11609)
INTERNAL
REFERENCE
STATE
REFERENCE
VOLTAGE
SEL2
SEL1
SEL0
MAX11607/
MAX11610/
MAX11611)
0
0
1
1
1
1
0
1
0
0
1
1
X
X
0
1
0
1
V
Analog input
Reference input
Analog input
Not connected
Reference input
Not connected
Not connected
Reference output
Reference output
Always off
Always off
Always off
Always on
Always off
Always on
DD
External reference
Internal reference
Internal reference
Internal reference
Internal reference
Analog input
Reference output
Reference output
X = Don’t care.
or V
as a reference, all analog circuitry is inactive in
Internal Reference
DD
shutdown and supply current is less than 0.5µA (typ). The
digital conversion results obtained in internal clock mode
are maintained in memory during shutdown and are avail-
able for access through the serial interface at any time
prior to a STOP or a repeated START condition.
The internal reference is 4.096V for the MAX11606/
MAX11608/MAX11610 and 2.048V for the MAX11607/
MAX11609/MAX11611. SEL1 of the setup byte controls
whether AIN_/REF is used for an analog input or a refer-
ence (Table 6). When AIN_/REF is configured to be an
internal reference output (SEL[2:1] = 11), decouple AIN_/
REF to GND with a 0.1µF capacitor and a 2kΩ series
resistor (see the Typical Operating Circuit). Once powered
up, the reference always remains on until reconfigured.
The internal reference requires 10ms to wake up and is
accessed using SEL0 (Table 6). When in shutdown, the
internal reference output is in a high-impedance state.
The reference should not be used to supply current for
external circuitry. The internal reference does not require
When idle, the MAX11606–MAX11611 continuously wait
for a START condition followed by their slave address
(see Slave Address section). Upon reading a valid
address byte the MAX11606–MAX11611 power-up. The
internal reference requires 10ms to wake up, so when
using the internal reference it should be powered up 10ms
prior to conversion or powered continuously. Wake-up is
invisible when using an external reference or V
reference.
as the
DD
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates and with internal
clock. For example, at a conversion rate of 10ksps, the
average supply current for the MAX11607 is 60µA (typ)
and drops to 6µA (typ) at 1ksps. At 0.1ksps the average
supply current is just 1µA, or a minuscule 3µW of power
consumption, see Average Supply Current vs. Conversion
Rate in the Typical Operating Characteristics).
OUTPUT CODE
MAX11606–
MAX11611
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
FS = V
REF
ZS = GND
Reference Voltage
V
1024
REF
1 LSB =
SEL[2:0] of the setup byte (Table 1) control the reference
and the AIN_/REF configuration (Table 6). When AIN_/
REF is configured to be a reference input or reference
output (SEL1 = 1), differential conversions on AIN_/REF
appear as if AIN_/REF is connected to GND (see note 2
of Table 4). Single-ended conversion in scan mode on
AIN_/REF is ignored by internal limiter, which sets the
highest available channel at AIN2 or AIN10.
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
3
FS
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
Figure 12. Unipolar Transfer Function
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OUTPUT CODE
MAX11606–
MAX11611
V
REF
2
FS
=
011 . . . 111
011 . . . 110
SUPPLIES
ZS = 0
-FS =
-V
GND
REF
2
3V OR 5V
V
= 3V/5V
LOGIC
000 . . . 010
000 . . . 001
000 . . . 000
V
REF
1 LSB =
1024
4.7µF
0.1µF
R* = 5Ω
111 . . . 111
111 . . . 110
111 . . . 101
V
DD
GND
3V/5V DGND
100 . . . 001
100 . . . 000
MAX11606–
MAX11611
DIGITAL
CIRCUITRY
0
- FS
+FS - 1 LSB
*OPTIONAL
INPUT VOLTAGE (LSB)
*V
V
/2
*V = (AIN+) - (AIN-)
IN
COM REF
Figure 13. Bipolar Transfer Function
Figure 14. Power-Supply Grounding Connection
an external bypass capacitor and works best when left
unconnected (SEL1 = 0).
impedance and as short as possible. Route digital signals
far away from sensitive analog and reference inputs.
High-frequency noise in the power supply (V ) could
DD
influence the proper operation of the ADC’s fast comparator.
External Reference
The external reference can range from 1V to V . For
DD
Bypass V
to the star ground with a network of two
DD
maximum conversion accuracy, the reference must be
able to deliver up to 40µA and have an output imped-
ance of 500Ω or less. If the reference has a higher output
impedance or is noisy, bypass it to GND as close as
possible to AIN_/REF with a 0.1µF capacitor.
parallel capacitors, 0.1µF and 4.7µF, located as close as
possible to the MAX11606–MAX11611 power-supply pin.
Minimize capacitor lead length for best supply noise rejection,
and add an attenuation resistor (5Ω) in series with the
power supply, if it is extremely noisy.
Transfer Functions
Output data coding for the MAX11606–MAX11611 is
binary in unipolar mode and two’s complement in bipolar
Definitions
Integral Nonlinearity
mode with 1LSB = (V
/2N) where N is the number
REF
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once offset
and gain errors have been nullified. The MAX11606–
MAX11611’s INL is measured using the endpoint.
of bits (10). Code transitions occur halfway between
successive-integer LSB values. Figure 12 and Figure 13
show the input/output (I/O) transfer functions for unipolar
and bipolar operations, respectively.
Layout, Grounding, and Bypassing
Only use PC boards. Wire-wrap configurations are not
recommended since the layout should ensure proper sep-
aration of analog and digital traces. Do not run analog and
digital lines parallel to each other, and do not layout digital
signal paths underneath the ADC package. Use separate
analog and digital PCB ground sections with only one
star point (Figure 14) connecting the two ground systems
(analog and digital). For lowest noise operation, ensure
the ground return to the star ground’s power supply is low
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no miss-
ing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
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Aperture Delay
Effective Number of Bits
Aperture delay (t ) is the time between the falling edge
of the sampling clock and the instant when an actual
sample is taken.
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the ADC’s
full-scale range, calculate the ENOB as follows:
AD
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the
full-scale analog input (RMS value) to the RMS quantiza-
tion error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SignalRMS
SINAD(dB) = 20×log
NoiseRMS + THDRMS
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
SNR
= 6.02 x N + 1.76dB
dB
MAX[dB]
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the funda-
mental itself. This is expressed as:
In reality, there are other noise sources besides quantiza-
tion noise: thermal noise, reference noise, clock jitter, etc.
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first five harmonics, and the
DC offset.
2
2
2
2
V
+ V
+ V
+ V
5
2
3
4
THD = 20×log
V
1
Signal-to-Noise Plus Distortion
where V is the fundamental amplitude, and V through
1
2
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
V
are the amplitudes of the 2nd through 5th order
5
harmonics.
Spurious-Free Dynamic Range
SINAD (dB) = 20 x log (SignalRMS/NoiseRMS)
Spurious-free dynamic range (SFDR) is the ratio of
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest
distortion component.
Chip Information
PROCESS: BiCMOS
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Pin Configurations
Typical Operating Circuit
3.3V or 5V
TOP VIEW
+
0.1µF
AIN0
AIN1
1
2
3
4
8
7
6
5
V
DD
V
DD
GND
SDA
SCL
R *
S
AIN0
AIN1
MAX11606
MAX11607
SDA
SCL
ANALOG
INPUTS
MAX11606–
MAX11611
AIN2
R *
S
AIN3/REF
2kΩ
RC NETWORK*
AIN3**/REF
GND
5V
C
0.1µF
REF
µMAX
5V
R
P
+
(REF) AIN11/REF
(N.C.) AIN10
(N.C.) AIN9
(N.C.) AIN8
AIN0
1
16
V
DD
R
P
2
3
4
5
6
7
8
15 GND
14 SDA
13 SCL
12 AIN7
11 AIN6
10 AIN5
SDA
SCL
µC
MAX11608–
MAX11611
*OPTIONAL
**AIN11/REF (MAX11610/MAX11611)
AIN1
AIN2
Selector Guide
AIN3
9
AIN4
INTERNAL
REFERENCE VOLTAGE
SUPPLY
QSOP
INPUT
CHANNELS
INL
(LSB)
PART
( ) INDICATES PINS ON THE MAX11608/MAX11609.
(V)
(V)
MAX11606
MAX11607
MAX11608
MAX11609
MAX11610
MAX11611
4
4
4.096
2.048
4.096
2.048
4.096
2.048
4.5 to 5.5
2.7 to 3.6
4.5 to 5.5
2.7 to 3.6
4.5 to 5.5
2.7 to 3.6
±1
±1
±1
±1
±1
±1
TOP VIEW
(BUMPS ON BOTTOM)
MAX11607
8
1
2
3
4
8
+
12
12
AIN3/
REF
AIN1
GND
AIN2
GND
A
B
AIN0
GND
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
GND
SCL
PACKAGE
TYPE
PACKAGE
CODE
DOCUMENT
NO.
LAND
PATTERN NO.
GND
SDA
C
V
DD
8 μMAX
12 WLP
U8CN+1
W121C2+1
E16+1
21-0036
21-0009
21-0055
90-0092
Refer to Application
WLP
Note 1891
16 QSOP
90-0167
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Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
4/09
7/09
3/10
Introduction of the MAX11606/MAX11607
—
1
Introduction of the MAX11608–MAX116011
Changed Absolute Maximum Ratings and timing diagram
2, 12
Added MAX11607 WLP package and updated notes in Electrical Characteristics
table
3
2/11
1–5, 8, 21
4
5
7/13
2/19
Updated the Ordering Information table
1
1
Updated Ordering Information table
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
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