MAX11628EEV [MAXIM]
12-Bit, 300ksps ADCs with FIFO and Internal Reference; 12位，高达300ksps ADC，带有FIFO和内部基准
| 型号： | MAX11628EEV |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Bit, 300ksps ADCs with FIFO and Internal Reference |
| 文件： | 总22页 (文件大小：1276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5323; Rev 2; 3/11
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
General Description
Features
The MAX11626–MAX11629/MAX11632/MAX11633 are
serial 12-bit analog-to-digital converters (ADCs) with an
internal reference. These devices feature on-chip FIFO,
scan mode, internal clock mode, internal averaging,
and AutoShutdown™. The maximum sampling rate is
300ksps using an external clock. The MAX11632/
MAX11633 have 16 input channels; the MAX11628/
MAX11629 have 8 input channels; and the MAX11626/
MAX11627 have 4 input channels. These eight devices
operate from either a +3V supply or a +5V supply, and
contain a 10MHz SPI™-/QSPI™-/MICROWIRE™-com-
patible serial port.
o Analog Multiplexer with Track/Hold
16 Channels (MAX11632/MAX11633)
8 Channels (MAX11628/MAX11629)
4 Channels (MAX11626/MAX11627)
o Single Supply
2.7V to 3.6V (MAX11627/MAX11629/MAX11633)
4.75V to 5.25V
(MAX11626/MAX11628/MAX11632)
o Internal Reference
2.5V (MAX11627/MAX11629/MAX11633)
4.096V (MAX11626/MAX11628/MAX11632)
o External Reference: 1V to V
DD
The MAX11626–MAX11629 are available in 16-pin
QSOP packages. The MAX11632/MAX11633 are avail-
able in 24-pin QSOP packages. All eight devices are
specified over the extended -40°C to +85°C tempera-
ture range.
o 16-Entry First-In/First-Out (FIFO)
o Scan Mode, Internal Averaging, and Internal Clock
o Accuracy: 1 LSB INL, 1 LSB DNL, No Missing
Codes Over Temperature
o 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible
________________________Applications
System Supervision
Interface
o Small Packages
16-Pin QSOP (MAX11626–MAX11629)
24-Pin QSOP (MAX11632/MAX11633)
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
Ordering Information
Data Logging
NUMBER
OF
INPUTS
SUPPLY
VOLTAGE
RANGE (V)
Instrumentation
PIN
PACKAGE
PART
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MAX11626EEE+*
MAX11627EEE+*
MAX11628EEE+
MAX11628EEE/V+
MAX11629EEE+
MAX11632EEG+
MAX11633EEG+
4
4
4.75 to 5.25 16 QSOP
2.7 to 3.6 16 QSOP
MICROWIRE is a trademark of National Semiconductor Corp.
8
4.75 to 5.25 16 QSOP
4.75 to 5.25 16 QSOP
Pin Configurations
8
8
2.7 to 3.6
4.75 to 5.25 24 QSOP
2.7 to 3.6 24 QSOP
16 QSOP
TOP VIEW
16
16
+
AIN0
1
2
3
4
5
6
7
8
16 EOC
15 DOUT
14 DIN
Note: All devices are specified over the -40°C to +85°C operating
AIN1
AIN2
temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact for availability.
/V denotes an automotive qualified part.
AIN3
MAX11626–
MAX11629
13
12
11
SCLK
CS
AIN4 (N.C.)
AIN5 (N.C.)
AIN6 (N.C.)
AIN7/(CNVST)
V
DD
10 GND
REF
9
QSOP
() MAX11626/MAX11627 ONLY
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (V
AIN0–AIN13, AIN_, CNVST/AIN_,
REF to GND...........................................-0.3V to (V
Maximum Current into Any Pin............................................50mA
+ 0.3V)
DD
+ 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); V
= +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), f
=
DD
SAMPLE
DD
300kHz, f
MAX11632), T = T
= 4.8MHz (50% duty cycle), V
= 2.5V (MAX11627//MAX11629/MAX11633); V
= 4.096V (MAX11626/MAX11628/
SCLK
REF
REF
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RES
INL
12
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
1.0
1.0
4.0
4.0
DNL
No missing codes over temperature
(Note 2)
0.5
0.5
Gain Error
Offset Error Temperature
Coefficient
ppm/°C
FSR
2
Gain Temperature Coefficient
0.8
0.1
ppm/°C
Channel-to-Channel Offset
Matching
LSB
DYNAMIC SPECIFICATIONS (30kHz sine-wave input, 2.5V , 300ksps, f
= 4.8MHz)
SCLK
P-P
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/
71
73
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
SINAD
dB
-80
-88
MAX11633
Up to the 5th
harmonic
THD
dBc
dBc
MAX11626/MAX11628/
MAX11632
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
81
89
76
1
Spurious-Free Dynamic Range
SFDR
IMD
–92/MAX163
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
f
= 29.9kHz, f
IN2
= 30.2kHz
dBc
MHz
kHz
IN1
-3dB point
S/(N + D) > 68dB
100
2
_______________________________________________________________________________________
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); V
= +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), f
=
DD
SAMPLE
DD
300kHz, f
MAX11632), T = T
= 4.8MHz (50% duty cycle), V
= 2.5V (MAX11627//MAX11629/MAX11633); V
= 4.096V (MAX11626/MAX11628/
SCLK
REF
REF
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
External reference
0.8
65
Power-Up Time
Acquisition Time
Conversion Time
t
µs
µs
µs
PU
Internal reference (Note 3)
t
0.6
ACQ
Internally clocked
3.5
t
CONV
Externally clocked (Note 4)
Externally clocked conversion
Data I/O
2.7
0.1
4.8
10
External Clock Frequency
f
MHz
SCLK
Aperture Delay
30
ns
ps
Aperture Jitter
< 50
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance
INTERNAL REFERENCE
Unipolar
0
V
V
REF
V
= V
0.01
24
1
µA
pF
IN
DD
During acquisition time (Note 5)
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
4.024
2.48
4.096
2.50
20
4.168
2.52
REF Output Voltage
V
REF Temperature Coefficient
TC
ppm/°C
REF
30
Output Resistance
6.5
kꢀ
REF Output Noise
200
-70
µV
RMS
REF Power-Supply Rejection
EXTERNAL REFERENCE INPUT
REF Input Voltage Range
PSRR
dB
V
REF
1.0
V
DD
+ 50mV
100
V
V
= 2.5V (MAX11627/MAX11629/
REF
MAX11633); V
(MAX11626/MAX11628/MAX11632),
= 4.096V
REF
40
f
= 300ksps
SAMPLE
REF Input Current
I
µA
REF
V
= 2.5V (MAX11627/MAX11629/
REF
MAX11633); V
= 4.096V
REF
0.1
5
(MAX11626/MAX11628/MAX11632),
= 0
f
SAMPLE
_______________________________________________________________________________________
3
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); V
= +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), f
=
DD
SAMPLE
DD
300kHz, f
MAX11632), T = T
= 4.8MHz (50% duty cycle), V
= 2.5V (MAX11627//MAX11629/MAX11633); V
= 4.096V (MAX11626/MAX11628/
SCLK
REF
REF
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
0.8
Input Voltage Low
Input Voltage High
V
V
V
IL
V
x 0.3
DD
2.0
x 0.7
V
IH
V
DD
Input Hysteresis
V
200
0.01
15
mV
µA
pF
HYST
Input Leakage Current
Input Capacitance
I
V
= 0V or V
DD
1.0
IN
IN
C
IN
DIGITAL OUTPUTS (DOUT, EOC)
I
I
I
= 2mA
= 4mA
0.4
0.8
SINK
Output Voltage Low
V
V
OL
SINK
Output Voltage High
V
= 1.5mA
V - 0.5
DD
V
OH
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
I
CS = V
CS = V
0.05
15
1
µA
pF
L
DD
DD
C
OUT
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
4.75
2.7
5.25
3.6
2000
1200
5
Supply Voltage
V
V
DD
f
f
= 300ksps
= 0, REF on
1750
1000
0.2
SAMPLE
SAMPLE
Internal
reference
MAX11627/MAX11629/MAX11633
Supply Current (Note 6)
µA
Shutdown
= 300ksps
I
DD
f
1050
0.2
1200
5
External
SAMPLE
reference
Shutdown
f
f
= 300ksps
= 0, REF on
2300
1050
0.2
2550
1350
5
SAMPLE
SAMPLE
Internal
reference
MAX11626/MAX11628/MAX11632
Supply Current (Note 6)
I
µA
Shutdown
= 300ksps
DD
f
1550
0.2
1700
5
External
reference
SAMPLE
Shutdown
V
V
= 2.7V to 3.6V; full-scale input
= 4.75V to 5.25V; full-scale input
0.2
1
DD
Power-Supply Rejection
PSR
mV
0.2
1.2
DD
Note 1: MAX11627/MAX11629/MAX11633 tested at V
Note 2: Offset nulled.
= +3V. MAX11626/MAX11628/MAX11632 tested at V
= +5V.
DD
DD
–92/MAX163
Note 3: Time for reference to power up and settle to within 1 LSB.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: See Figure 3 (Equivalent Input Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating
Characteristics section.
Note 6: Supply current is specified depending on whether an internal or external reference is used for voltage conversions.
4
_______________________________________________________________________________________
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
TIMING CHARACTERISTICS (Figure 1)
(V
= +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); V
= +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), f
=
DD
SAMPLE
DD
300kHz, f
MAX11628/MAX11632), T = T
= 4.8MHz (50% duty cycle), V
= 2.5V (MAX11627//MAX11629/MAX11633); V
= 4.096V (MAX11626/
SCLK
REF
REF
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
Externally clocked conversion
Data I/O
MIN
208
100
40
TYP
MAX
UNITS
SCLK Clock Period
t
ns
CP
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to DOUT Transition
CS Rise to DOUT Disable
CS Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS Low to SCLK Setup
CS High to SCLK Setup
CS High After SCLK Hold
CS Low After SCLK Hold
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
CH
t
40
CL
t
C
LOAD
C
LOAD
C
LOAD
= 30pF
= 30pF
= 30pF
40
40
40
DOT
t
DOD
t
DOE
t
40
0
DS
DH
t
t
t
40
40
0
CSS0
CSS1
CSH1
CSH0
t
t
0
4
t
CKSEL = 00
40
1.4
CSPW
CNVST Pulse Width Low
CKSEL = 01
Voltage conversion
Reference power-up
7
CS or CNVST Rise to EOC
Low (Note 7)
µs
65
Note 7: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive.
Typical Operating Characteristics
= 30pF, T = +25°C, unless otherwise noted.)
A
(V
= +3V, V
= +2.5V, f
= 4.8MHz, C
DD
REF
SCLK
LOAD
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
1.0
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
1.0
0.8
1.0
0.8
0.6
0.4
0.2
0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.2
-0.4
-0.6
-0.8
-1.0
-0.6
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
MAX11626/MAX11628/MAX11632
f
= 300ksps
f
= 300ksps
f
= 300ksps
SAMPLE
SAMPLE
-0.8
-1.0
SAMPLE
0
1024
2048
3072
4096
0
1024
2048
3072
4096
0
1024
2048
3072
4096
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
_______________________________________________________________________________________
5
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Typical Operating Characteristics (continued)
(V
= +3V, V
= +2.5V, f
= 4.8MHz, C
= 30pF, T = +25°C, unless otherwise noted.)
DD
REF
SCLK
LOAD
A
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
SINAD vs. FREQUENCY
SFDR vs. FREQUENCY
80
75
70
65
60
55
50
1.0
100
90
80
70
60
50
MAX11626/MAX11628/MAX11632
MAX11626/MAX11628/ MAX11632
0.8
0.6
0.4
0.2
MAX11627/MAX11629/MAX11633
0
MAX11627/MAX11629/MAX11633
-0.2
-0.4
-0.6
-0.8
-1.0
MAX11627/MAX11629/MAX11633
f
= 300ksps
SAMPLE
1
10
100
1000
0
1024
2048
3072
4096
1
10
100
1000
FREQUENCY (kHz)
OUTPUT CODE (DECIMAL)
FREQUENCY (kHz)
SUPPLY CURRENT vs. SAMPLING RATE
THD vs. FREQUENCY
3000
2500
2000
1500
1000
500
-50
-60
MAX11626/MAX11628/MAX11632
V
= 5V
DD
MAX11627/MAX11629/MAX11633
-70
INTERNAL REFERENCE
-80
EXTERNAL REFERENCE
-90
MAX11626/MAX11628/MAX11632
0
-100
1
10
100
1000
1
10
100
1000
SAMPLING RATE (ksps)
FREQUENCY (kHz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SAMPLING RATE
2600
2400
2200
2000
1800
1600
1400
1200
1000
1800
1600
1400
1200
1000
800
MAX11627/MAX11629/MAX11633
INTERNAL REFERENCE
V
= 3V
DD
–92/MAX163
INTERNAL REFERENCE
EXTERNAL REFERENCE
600
EXTERNAL REFERENCE
400
MAX11626/MAX11628/MAX11632
200
f
= 300ksps
SAMPLE
0
4.75
4.85
4.95
5.05
5.15
5.25
1
10
100
1000
V
(V)
SAMPLING RATE (ksps)
DD
6
_______________________________________________________________________________________
12-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
–92/MAX163
Typical Operating Characteristics (continued)
(V
= +3V, V
= +2.5V, f
= 4.8MHz, C
= 30pF, T = +25°C, unless otherwise noted.)
DD
REF
SCLK
LOAD A
SHUTDOWN SUPPLY CURRENT
SUPPLY CURRENT vs. SUPPLY VOLTAGE
vs. SUPPLY VOLTAGE
2000
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1800
1600
1400
1200
1000
800
600
400
200
0
INTERNAL REFERENCE
EXTERNAL REFERENCE
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
f
= 300ksps
V
DD
= 5V
SAMPLE
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
(V)
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
V
DD
DD
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
2500
2200
1900
1600
1300
1000
0.5
0.4
0.3
0.2
0.1
0
INTERNAL REFERENCE
EXTERNAL REFERENCE
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
V
f
= 5V
DD
V
= 3V
= 300ksps
DD
SAMPLE
-40
-15
10
35
60
85
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
(V)
TEMPERATURE (°C)
V
DD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
1800
1600
1400
1200
1000
800
2.5
2.0
1.5
1.0
0.5
0
MAX11626/MAX11628/MAX11632
INTERNAL REFERENCE
V
= 5V
DD
MAX11627/MAX11629/MAX11633
V
= 3V
DD
f
= 300ksps
SAMPLE
EXTERNAL REFERENCE
600
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Typical Operating Characteristics (continued)
(V
= +3V, V
= +2.5V, f
= 4.8MHz, C
= 30pF, T = +25°C, unless otherwise noted.)
DD
REF
SCLK
LOAD
A
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.0
4.099
4.098
4.097
4.096
4.095
4.094
2.502
2.501
2.500
2.499
2.498
2.497
MAX11627/MAX11629/MAX11633
V
= 3V
DD
0.8
0.6
0.4
0.2
0
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
V
= 3V
DD
V
DD
= 5V
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
(V)
5.15
5.25
2.7
3.0
3.3
3.6
TEMPERATURE (°C)
V
V
(V)
DD
DD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
4.12
4.11
4.10
4.09
4.08
4.07
2.52
2.51
2.50
2.49
2.48
2.47
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
V
= 5V
V
= 3V
f
= 300ksps
DD
DD
SAMPLE
-40
-15
10
35
60
85
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPARATURE (°C)
TEMPARATURE (°C)
V
DD
(V)
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
OFFSET ERROR vs. TEMPERATURE
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
1.0
0.6
1.5
1.3
1.1
0.9
0.7
0.5
–92/MAX163
0.2
-0.2
-0.6
-1.0
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
MAX11627/MAX11629/MAX11633
f
= 300ksps
f
= 300ksps
SAMPLE
SAMPLE
f
= 300ksps
SAMPLE
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
DD
8
_______________________________________________________________________________________
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
Typical Operating Characteristics (continued)
(V
= +3V, V
= +2.5V, f
= 4.8MHz, C
= 30pF, T = +25°C, unless otherwise noted.)
DD
REF
SCLK
LOAD A
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. SUPPLY VOLTAGE
0.7
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.6
0.5
0.4
0.3
0.2
0.1
0
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
f
= 300ksps
SAMPLE
4.75
4.85
4.95
5.05
5.15
5.25
2.7
3.0
3.3
3.6
V
(V)
V
DD
(V)
DD
SAMPLING ERROR
vs. SOURCE IMPEDANCE
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
1.0
0.5
0.3
0.1
2
0
MAX11627/MAX11629/MAX11633
f
= 300ksps
SAMPLE
0.6
0.2
-2
-4
-0.2
-0.6
-1.0
-0.1
-0.3
-0.5
-6
-8
MAX11626/MAX11628/MAX11632
f
= 300ksps
SAMPLE
-10
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
2
4
6
8
10
TEMPERATURE (°C)
TEMPERATURE (°C)
SOURCE IMPEDANCE (kΩ)
_______________________________________________________________________________________
9
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Pin Description
MAX11626
MAX11627
MAX11628
MAX11629
MAX11632
MAX11633
NAME
FUNCTION
(4 CHANNELS)
(8 CHANNELS)
(16 CHANNELS)
5, 6, 7
—
—
—
—
1–15
—
N.C.
No Connection. Not internally connected.
Analog Inputs
AIN0–AIN14
AIN0–AIN6
AIN0–AIN3
—
1–7
—
Analog Inputs
1–4
—
Analog Inputs
Active-Low Conversion Start Input/Analog Input 15.
See Table 3 for details on programming the setup
register.
—
—
16
CNVST/AIN15
Active-Low Conversion Start Input/Analog Input 7.
See Table 3 for details on programming the setup
register.
—
8
8
—
—
CNVST/AIN7
Active-Low Conversion Start Input. See Table 3 for
details on programming the setup register.
—
CNVST
Reference Input. Bypass to GND with a 0.1µF
capacitor.
9
9
17
18
19
REF
10
11
10
11
GND
Ground
Power Input. Bypass to GND with a 0.1µF
capacitor.
V
DD
Active-Low Chip-Select Input. When CS is low, the
serial interface is enabled. When CS is high, DOUT
is high impedance.
12
12
20
CS
Serial Clock Input. Clocks data in and out of the serial
interface. (Duty cycle must be 40% to 60%.) See
Table 3 for details on programming the clock mode.
13
14
15
16
13
14
15
16
21
22
23
24
SCLK
DIN
Serial Data Input. DIN data is latched into the serial
interface on the rising edge of SCLK.
Serial Data Output. Data is clocked out on the falling
edge of SCLK. High impedance when CS is
DOUT
EOC
connected to V
.
DD
End of Conversion Output. Data is valid after EOC
pulls low.
–92/MAX163
10 ______________________________________________________________________________________
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
CS
t
CSH0
t
t
t
CSH1
t
CH
CP
CSS0
t
CSS1
t
CL
SCLK
DIN
t
DH
t
DS
t
t
DOT
DOD
t
DOE
DOUT
Figure 1. Detailed Serial-Interface Timing Diagram
CS
DIN
SCLK
SERIAL
INTERFACE
DOUT
EOC
OSCILLATOR
CNVST
CONTROL
AIN1
AIN2
12-BIT
SAR
ADC
FIFO AND
ACCUMULATOR
T/H
AIN15
REF
INTERNAL
REFERENCE
MAX11626–MAX11629/MAX11632/MAX11633
Figure 2. Functional Diagram
through a 3-wire SPI-/QSPI-/MICROWIRE-compatible
serial interface.
Detailed Description
The MAX11626–MAX11629/MAX11632/MAX11633 are
low-power, serial-output, multichannel ADCs with FIFO
capability for system monitoring, process-control, and
instrumentation applications. These 12-bit ADCs have
internal track and hold (T/H) circuitry supporting single-
ended inputs. Data is converted from analog voltage
sources in a variety of channel and data-acquisition con-
figurations. Microprocessor (µP) control is made easy
Figure 2 shows a simplified functional diagram of the
MAX11626–MAX11629/MAX11632/MAX11633 internal
architecture. The MAX11632/MAX11633 have 16 sin-
gle-ended analog input channels. The MAX11628/
MAX11629 have 8 single-ended analog input channels.
The MAX11626/MAX11627 have 4 single-ended analog
input channels.
______________________________________________________________________________________ 11
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Converter Operation
The MAX11626–MAX11629/MAX11632/MAX11633
ADCs use a successive-approximation register (SAR)
conversion technique and an on-chip T/H block to con-
vert voltage signals into a 12-bit digital result. This sin-
gle-ended configuration supports unipolar signal
ranges.
bus. In clock mode 01, use CNVST to request conver-
sions one channel at a time, controlling the sampling
speed without tying up the serial bus. Request and
start internally timed conversions through the serial
interface by writing to the conversion register in the
default clock mode 10. Use clock mode 11 with SCLK
up to 4.8MHz for externally timed acquisitions to
achieve sampling rates up to 300ksps. Clock mode 11
disables scanning and averaging. See Figures 4–7 for
timing specifications and how to begin a conversion.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next input
data byte (for clock modes 00 and 10). In clock mode
01, EOC goes low after the ADC completes each
requested operation. EOC goes high when CS or
CNVST goes low. EOC is always high in clock mode 11.
Analog Input Protection
Internal ESD protection diodes clamp all pins to V
DD
Single-Ended Inputs
The single-ended analog input conversion modes can
be configured by writing to the setup register (see
Table 3). Single-ended conversions are internally refer-
enced to GND (see Figure 3).
and GND, allowing the inputs to swing from (GND -
0.3V) to (V + 0.3V) without damage. However, for
DD
accurate conversions near full scale, the inputs must
not exceed V by more than 50mV or be lower than
DD
GND by 50mV. If an off-channel analog input voltage
exceeds the supplies, limit the input current to 2mA.
AIN0–AIN3 are available on the MAX11626–MAX11629/
MAX11632/MAX11633. AIN4–AIN7 are only available on
the MAX11628–MAX11633. AIN8–AIN15 are only avail-
able on the MAX11632/MAX11633. See Tables 2–5 for
more details on configuring the inputs. For the inputs
that can be configured as CNVST or an analog input,
only one can be used at a time.
3-Wire Serial Interface
The MAX11626–MAX11629/MAX11632/MAX11633 fea-
ture a serial interface compatible with SPI/QSPI and
MICROWIRE devices. For SPI/QSPI, ensure the CPU
serial interface runs in master mode so it generates the
serial clock signal. Select the SCLK frequency of 10MHz
or less, and set clock polarity (CPOL) and phase
(CPHA) in the µP control registers to the same value.
The MAX11626–MAX11629/MAX11632/MAX11633 oper-
ate with SCLK idling high or low, and thus operate with
CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to
latch input data at DIN on the rising edge of SCLK.
Output data at DOUT is updated on the falling edge of
SCLK. Results are output in binary format.
Unipolar
The MAX11626–MAX11629/MAX11632/MAX11633
always operate in unipolar mode. The analog inputs are
internally referenced to GND with a full-scale input
range from 0 to V
.
REF
REF
GND
DAC
Serial communication always begins with an 8-bit input
data byte (MSB first) loaded from DIN. A high-to-low
transition on CS initiates the data input operation. The
input data byte and the subsequent data bytes are
clocked from DIN into the serial interface on the rising
edge of SCLK. Tables 1–5 detail the register descrip-
tions. Bits 5 and 4, CKSEL1 and CKSEL0, respectively,
control the clock modes in the setup register (see Table
3). Choose between four different clock modes for vari-
ous ways to start a conversion and determine whether
the acquisitions are internally or externally timed. Select
clock mode 00 to configure CNVST/AIN_ to act as a
conversion start and use it to request the programmed,
internally timed conversions without tying up the serial
AIN0-AIN15
CIN+
COMPARATOR
+
–92/MAX163
HOLD
-
CIN-
GND
HOLD
HOLD
V
DD
/2
Figure 3. Equivalent Input Circuit
12 ______________________________________________________________________________________
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
oscillator is active in clock modes 00, 01, and 10. Read
out the data at clock speeds up to 10MHz. See Figures
4–7 for details on timing specifications and starting a
conversion.
True Differential Analog Input T/H
The equivalent circuit of Figure 3 shows the
MAX11626–MAX11629/MAX11632/MAX11633’s input
architecture. In track mode, a positive input capacitor is
connected to AIN0–AIN15. A negative input capacitor is
connected to GND. For external T/H timing, use clock
mode 01. After the T/H enters hold mode, the difference
between the sampled positive and negative input volt-
ages is converted. The time required for the T/H to
acquire an input signal is determined by how quickly its
input capacitance is charged. If the input signal’s
source impedance is high, the required acquisition time
Applications Information
Register Descriptions
The MAX11626–MAX11629/MAX11632/MAX11633 com-
municate between the internal registers and the exter-
nal circuitry through the SPI-/QSPI-compatible serial
interface. Table 1 details the registers and the bit
names. Tables 2–5 show the various functions within
the conversion register, setup register, averaging regis-
ter, and reset register.
lengthens. The acquisition time, t
, is the maximum
ACQ
time needed for a signal to be acquired, plus the
power-up time. It is calculated by the following equa-
tion:
Conversion Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, and if the external
reference is in use.
t
= 9 x (R + R ) x 24pF + t
S IN PWR
ACQ
where R = 1.5kΩ, R is the source impedance of the
IN
S
input signal, and t
= 1µs, the power-up time of the
PWR
device. The varying power-up times are detailed in the
Use the following formula to calculate the total conver-
sion time for an internally timed conversion in clock
modes 00 and 10 (see the Electrical Characteristics
section as applicable):
explanation of the clock mode conversions. t
is never
ACQ
less than 1.4µs, and any source impedance below 300Ω
does not significantly affect the ADC’s AC performance.
A high-impedance source can be accommodated either
by lengthening t
or by placing a 1µF capacitor
Total Conversion Time = t
where
x n
x n
+ t
ACQ
CNV
AVG
RESULT RP
between the positive and negative analog inputs.
Internal FIFO
t
= t
(max) + t
(max).
CONV
CNV
ACQ
The MAX11626–MAX11629/MAX11632/MAX11633 con-
tain a FIFO buffer that can hold up to 16 ADC results.
This allows the ADC to handle multiple internally clocked
conversions, without tying up the serial bus. If the FIFO is
filled and further conversions are requested without
reading from the FIFO, the oldest ADC results are over-
written by the new ADC results. Each result contains 2
bytes, with the MSB preceded by four leading zeros.
After each falling edge of CS, the oldest available byte of
data is available at DOUT, MSB first. When the FIFO is
empty, DOUT is zero.
n
n
= samples per result (amount of averaging).
AVG
= number of FIFO results requested;
RESULT
determined by the number of channels being
scanned or by NSCAN1, NSCAN0.
t
= internal reference wake-up; set to zero if inter-
RP
nal reference is already powered up or external ref-
erence is being used .
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high, including any time
required to turn on the internal reference. Conversion
time in externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
Internal Clock
The MAX11626–MAX11629/MAX11632/MAX11633 oper-
ate from an internal oscillator, which is accurate within
10% of the 4.4MHz nominal clock rate. The internal
Table 1. Input Data Byte (MSB First)
REGISTER NAME
Conversion
Setup
BIT 7
BIT 6
BIT 5
CHSEL2
CKSEL1
1
BIT 4
CHSEL1
CKSEL0
AVGON
1
BIT 3
CHSEL0
REFSEL1
NAVG1
RESET
BIT 2
SCAN1
REFSEL0
NAVG0
X
BIT 1
SCAN0
X
BIT 0
1
0
0
0
CHSEL3
X
1
0
0
X
NSCAN0
X
Averaging
NSCAN1
X
Reset
0
X = Don’t care.
______________________________________________________________________________________ 13
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Conversion Register
Table 2. Conversion Register*
Select active analog input channels per scan and scan
modes by writing to the conversion register. Table 2
details channel selection and the four scan modes.
Request a scan by writing to the conversion register
when in clock mode 10 or 11, or by applying a low
pulse to the CNVST pin when in clock mode 00 or 01.
BIT
BIT
FUNCTION
NAME
—
7 (MSB) Set to 1 to select conversion register.
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
—
6
5
4
3
2
1
Analog input channel select.
Analog input channel select.
Analog input channel select.
Analog input channel select.
Scan mode select.
A conversion is not performed if it is requested on a
channel that has been configured as CNVST. Do not
request conversions on channels 8–15 on the
MAX11626–MAX11629. Set CHSEL3:CHSEL0 to the
lower channel’s binary values.
Scan mode select.
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel within the requested range. Select
scan mode 10 to scan a single input channel numerous
times, depending on NSCAN1 and NSCAN0 in the
averaging register (Table 4). Select scan mode 11 to
return only one result from a single channel.
0 (LSB) Don’t care.
*See below for bit details.
SELECTED
CHANNEL (N)
CHSEL3 CHSEL2 CHSEL1 CHSEL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1
Setup Register
Write a byte to the setup register to configure the clock,
reference, and power-down modes. Table 3 details the
bits in the setup register. Bits 5 and 4 (CKSEL1 and
CKSEL0) control the clock mode, acquisition and sam-
pling, and the conversion start. Bits 3 and 2 (REFSEL1
and REFSEL0) control internal or external reference use.
AIN2
AIN3
AIN4
AIN5
AIN6
Averaging Register
Write to the averaging register to configure the ADC to
average up to 32 samples for each requested result,
and to independently control the number of results
requested for single-channel scans.
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Table 2 details the four scan modes available in the
conversion register. All four scan modes allow averag-
ing as long as the AVGON bit, bit 4 in the averaging
register, is set to 1. Select scan mode 10 to scan the
same channel multiple times. Clock mode 11 disables
averaging.
Reset Register
Write to the reset register (as shown in Table 5) to clear
the FIFO or to reset all registers to their default states.
Set the RESET bit to 1 to reset the FIFO. Set the reset
bit to zero to return the MAX11626–MAX11629/
MAX11632/MAX11633 to the default power-up state.
SCAN MODE (CHANNEL N IS
SELECTED BY BITS CHSEL3–CHSEL0)
SCAN1 SCAN0
–92/MAX163
0
0
0
1
Scans channels 0 through N.
Scans channels N through the highest
numbered channel.
Scans channel N repeatedly. The averaging
register sets the number of results.
1
1
0
1
No scan. Converts channel N once only.
14 ______________________________________________________________________________________
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
Table 3. Setup Register*
BIT NAME
BIT
FUNCTION
—
7 (MSB) Set to 0 to select setup register.
—
6
Set to 1 to select setup register.
Clock mode and CNVST configuration. Resets to 1 at power-up.
Clock mode and CNVST configuration.
Reference mode configuration.
Reference mode configuration.
Don’t care.
CKSEL1
CKSEL0
REFSEL1
REFSEL0
—
5
4
3
2
1
—
0 (LSB)
Don’t care.
*See below for bit details.
CKSEL1
CKSEL0
CONVERSION CLOCK
Internal
ACQUISITION/SAMPLING
Internally timed
CNVST CONFIGURATION
CNVST
0
0
1
1
0
1
0
1
Internal
Externally timed through CNVST
Internally timed
CNVST
Internal
AIN15/AIN11/AIN7*
AIN15/AIN11/AIN7*
External (4.8MHz max)
Externally timed through SCLK
*For the MAX11626/MAX11627, CNVST has its own dedicated pin.
REFSEL1 REFSEL0
VOLTAGE REFERENCE
Internal
AutoShutdown
Reference off after scan; need
wake-up delay.
0
0
1
1
0
1
0
1
External
Reference off; no wake-up delay.
Reference always on; no wake-up
delay.
Internal
Reserved
Reserved. Do not use.
______________________________________________________________________________________ 15
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Table 4. Averaging Register*
BIT NAME
BIT
FUNCTION
—
7 (MSB) Set to 0 to select averaging register.
—
6
Set to 0 to select averaging register.
Set to 1 to select averaging register.
—
5
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
4
Set to 1 to turn averaging on. Set to 0 to turn averaging off.
Configures the number of conversions for single-channel scans.
Configures the number of conversions for single-channel scans.
Single-channel scan count. (Scan mode 10 only.)
3
2
1
0 (LSB)
Single-channel scan count. (Scan mode 10 only.)
*See below for bit details.
AVGON
NAVG1
NAVG0
FUNCTION
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Performs one conversion for each requested result.
Performs four conversions and returns the average for each requested result.
Performs eight conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
NSCAN1
NSCAN0
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
0
0
1
1
0
1
0
1
Scans channel N and returns four results.
Scans channel N and returns eight results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
Table 5. Reset Register
BIT NAME
BIT
FUNCTION
—
7 (MSB) Set to 0 to select reset register.
—
6
Set to 0 to select reset register.
Set to 0 to select reset register.
Set to 1 to select reset register.
—
5
—
4
–92/MAX163
RESET
3
Set to 0 to reset all registers. Set to 1 to clear the FIFO only.
Reserved. Don’t care.
x
x
x
2
1
Reserved. Don’t care.
0 (LSB)
Reserved. Don’t care.
16 ______________________________________________________________________________________
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
Power-Up Default State
goes low before pulling CS low to communicate with
the serial interface. EOC stays low until CS or CNVST is
pulled low again.
The MAX11626–MAX11629/MAX11632/MAX11633
power up with all blocks in shutdown, including the ref-
erence. All registers power up in state 00000000,
except for the setup register, which powers up in clock
mode 10 (CKSEL1 = 1)
Do not initiate a second CNVST before EOC goes low;
otherwise, the FIFO can become corrupted.
Externally Timed Acquisitions and
Output Data Format
Figures 4–7 illustrate the conversion timing for the
MAX11626–MAX11629/MAX11632/MAX11633. The
12-bit conversion result is output in MSB-first format
with four leading zeros. DIN data is latched into the ser-
ial interface on the rising edge of SCLK. Data on DOUT
transitions on the falling edge of SCLK. Conversions in
clock modes 00 and 01 are initiated by CNVST.
Conversions in clock modes 10 and 11 are initiated by
writing an input data byte to the conversion register.
Data output is binary.
Internally Timed Conversions with CNVST
Performing Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using the
internal oscillator. See Figure 5 for clock mode 01 timing.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If the internal
reference needs to wake up, an additional 65µs is
required for the internal reference to power up.
Set CNVST high to begin a conversion. After the con-
version is complete, the ADC shuts down and pulls
EOC low. EOC stays low until CS or CNVST is pulled
low again. Wait until EOC goes low before pulling CS or
CNVST low.
Internally Timed Acquisitions and
Conversions Using CNVST
Performing Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequences are initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 4 for clock mode 00 timing.
If averaging is turned on, multiple CNVST pulses need
to be performed before a result is written to the FIFO.
Once the proper number of conversions has been per-
formed to generate an averaged FIFO result, as speci-
fied by the averaging register, the scan logic
automatically switches the analog input multiplexer to
the next-requested channel. The result is available on
DOUT once EOC has been pulled low.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX11626–MAX11629/
MAX11632/MAX11633 then wake up, scan all request-
ed channels, store the results in the FIFO, and shut
down. After the scan is complete, EOC is pulled low
and the results are available in the FIFO. Wait until EOC
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
EOC
LSB1
MSB2
MSB1
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION.
Figure 4. Clock Mode 00 Timing
______________________________________________________________________________________ 17
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
CNVST
(CONVERSION2)
(ACQUISITION1)
(ACQUISITION2)
CS
(CONVERSION1)
SCLK
DOUT
EOC
LSB1
MSB1
MSB2
REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION.
Figure 5. Clock Mode 01 Timing
(CONVERSION BYTE)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
DIN
CS
SCLK
DOUT
LSB1
MSB1
MSB2
EOC
THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED.
Figure 6. Clock Mode 10 Timing
Internally Timed Acquisitions and
complete, EOC is pulled low and the results are avail-
able in the FIFO. EOC stays low until CS is pulled low
again.
Conversions Using the Serial Interface
–92/MAX163
Performing Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequences are initiated by writing an
input data byte to the conversion register, and are per-
formed automatically using the internal oscillator. This
is the default clock mode upon power-up. See Figure 6
for clock mode 10 timing.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Initiate a scan by writing a byte to the conversion regis-
ter. The MAX11626–MAX11629/MAX11632/MAX11633
then power up, scan all requested channels, store the
results in the FIFO, and shut down. After the scan is
18 ______________________________________________________________________________________
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
(CONVERSION BYTE)
DIN
(ACQUISITION2)
(ACQUISITION1)
(CONVERSION1)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.
Figure 7. Clock Mode 11 Timing
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eight and ninth cycles, the pulse
width must be less than 100µs. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
If reference mode 00 is requested, wait 65µs with CS
high after writing the conversion byte to extend the
acquisition and allow the internal reference to power up.
FS = V + V
REF
COM
ZS = V
COM
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
V
REF
1 LSB =
4096
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
3
FS
(COM)
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
Figure 8. Unipolar Transfer Function, Full Scale (FS) = V
REF
Layout, Grounding, and Bypassing
For best performance, use PCBs. Do not use wire wrap
boards. Board layout should ensure that digital and ana-
log signal lines are separated from each other. Do not
run analog and digital (especially clock) signals parallel
to one another or run digital lines underneath the
MAX11626–MAX11629/MAX11632/MAX11633 package.
power supply can
supply with a 0.1µF
capacitor to GND, close to the V pin. Minimize capaci-
Transfer Function
Figure 8 shows the unipolar transfer function. Code tran-
sitions occur halfway between successive-integer LSB
High-frequency noise in the V
affect performance. Bypass the V
DD
DD
DD
values. Output coding is binary, with 1 LSB = V
(MAX11627/MAX11629/MAX11633) and 1 LSB = V
4.096V (MAX11626/MAX11628/MAX11632).
/2.5V
REF
REF
tor lead lengths for best supply-noise rejection. If the
power supply is very noisy, connect a 10Ω resistor in
series with the supply to improve power-supply filtering.
/
______________________________________________________________________________________ 19
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Signal-to-Noise Plus Distortion
Definitions
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX11626–MAX11629/MAX11632/MAX11633 is
measured using the end-point method.
SINAD (dB) = 20 x log (Signal
/Noise
)
RMS
RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Aperture Delay
⎛
⎞
2
2
2
2
⎛
⎝
⎞
⎠
THD = 20 x log
V
+ V + V + V
/V
1
2
3
4
5
⎜
⎟
Aperture delay (t ) is the time between the rising
AD
⎝
⎠
edge of the sampling clock and the instant when an
actual sample is taken.
where V1 is the fundamental amplitude, and V2–V5 are
the amplitudes of the first five harmonics.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest distor-
tion component.
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
–92/MAX163
20 ______________________________________________________________________________________
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
–92/MAX163
Pin Configurations (continued)
Chip Information
PROCESS: BiCMOS
TOP VIEW
Package Information
+
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
1
2
3
4
5
6
7
8
9
24 EOC
23 DOUT
22 DIN
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
21
20
19
SCLK
CS
MAX11632
MAX11633
PACKAGE
TYPE
16 QSOP
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
V
DD
E16+5
21-0055
21-0055
91-0168
91-0168
18 GND
24 QSOP
E24+1
17 REF
16 CNVST/AIN15
15 AIN14
14 AIN13
13 AIN12
AIN9 10
AIN10 11
AIN11 12
QSOP
______________________________________________________________________________________ 21
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
1
2
6/10
8/10
3/11
Initial release
—
Initial release of MAX11628/MAX11629 and changed internal reference voltage
Added MAX11628 automotive qualified part to data sheet
1
1
–92/MAX163
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products.
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