MAX1162BEUB-T [MAXIM]
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO10, MO-187CBA, USOP-10;
| 型号： | MAX1162BEUB-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO10, MO-187CBA, USOP-10 信息通信管理 光电二极管 转换器 |
| 文件： | 总18页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2525; Rev 1; 4/10
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX162
General Description
Features
The MAX1162 low-power, 16-bit analog-to-digital con-
verter (ADC) features a successive-approximation ADC,
automatic power-down, fast 1.1µs wakeup, and a high-
speed SPI™/QSPI™/MICROWIRE™-compatible inter-
face. The MAX1162 operates with a single +5V analog
supply and features a separate digital supply, allowing
direct interfacing with +2.7V to +5.25V digital logic.
o 16-Bit Resolution, No Missing Codes
o +5V Single-Supply Operation
o Adjustable Logic Level (+2.7V to +5.25V)
o Input-Voltage Range: 0 to V
REF
o Internal Track/Hold, 4MHz Input Bandwidth
o SPI/QSPI/MICROWIRE-Compatible Serial Interface
o Small 10-Pin µMAX or 10-Pin DFN Package
At the maximum sampling rate of 200ksps, the
MAX1162 consumes typically 2.75mA. Power con-
sumption is typically 13.75mA (AV
= DV
= +5V) at
DD
DD
a 200ksps (max) sampling rate. AutoShutdown™
reduces supply current to 140µA at 10ksps and to less
than 10µA at reduced sampling rates.
o Low Power
2.75mA at 200ksps
140µA at 10ksps
Excellent dynamic performance and low power, com-
bined with ease of use and small package size (10-pin
0.1µA in Power-Down Mode
®
µMAX and 10-pin DFN) make the MAX1162 ideal for
battery-powered and data-acquisition applications or
for other circuits with demanding power consumption
and space requirements.
Ordering Information
TEMP
PIN-
INL
PART
RANGE
PACKAGE
(LSB)
Applications
MAX1162BCUB+
MAX1162BC_B*
MAX1162CCUB+
MAX1162CC_B*
MAX1162BEUB+
MAX1162BE_B*
MAX1162CEUB+
MAX1162CE_B*
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
10 µMAX
10 DFN
10 µMAX
10 DFN
10 µMAX
10 DFN
10 µMAX
10 DFN
2
2
Motor Control
4
Industrial Process Control
Industrial I/O Modules
4
2.5
2.5
4
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Portable- and Battery-Powered Equipment
4
*Future product—contact factory for DFN package availability.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW
Functional Diagram appears at end of data sheet.
REF
1
2
3
4
5
10 AIN
AV
DD
9
8
7
6
AGND
DV
MAX1162
AGND
DD
CS
DGND
DOUT
SPI and QSPI are trademarks of Motorola, Inc.
SCLK
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
µMAX/DFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
ABSOLUTE MAXIMUM RATINGS
AV
DV
to AGND .........................................................-0.3V to +6V
to DGND.........................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
10-Pin µMAX (derate 5.6mW/°C above +70°C)..........444mW
Operating Temperature Ranges
DD
DD
DGND to AGND.....................................................-0.3V to +0.3V
AIN, REF to AGND ...................................-0.3V to (AV + 0.3V)
SCLK, CS to DGND..................................................-0.3V to +6V
MAX1162_CUB .................................................0°C to +70°C
MAX1162_EUB ..............................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
DOUT to DGND .......................................-0.3V to (DV + 0.3V)
DD
Maximum Current Into Any Pin ...........................................50mA
MAX162
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV = DV = +4.75V to +5.25V, f
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
= +4.096V, C = 4.7µF,
REF
DD
DD
SCLK
REF
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
16
-2.5
-2
Bits
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
= -40°C
= 0°C
+2.5
+2
MAX1162B
MAX1162C
MAX1162B
= +85°C
= -40°C
= 0°C
-2
+2
Relative Accuracy (Note 2)
INL
LSB
-4
+4
-4
+4
= +85°C
= -40°C
= 0°C
-4
+4
NMC*
NMC*
NMC*
-2
2
1.75
1.75
+2
= +85°C
= -40°C
= 0°C
Differential Nonlinearity
DNL
LSB
MAX1162C
RMS noise
(Note 3)
-2
+2
= +85°C
-2
+2
Transition Noise
Offset Error
Gain Error
0.65
0.1
LSB
RMS
1
mV
0.002
0.4
0.01
%FSR
ppm/oC
ppm/oC
Offset Drift
Gain Drift
(Note 3)
0.2
*NMC = No missing code.
_______________________________________________________________________________________
2
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX162
ELECTRICAL CHARACTERISTICS (continued)
(AV = DV = +4.75V to +5.25V, f
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
= +4.096V, C = 4.7µF,
REF
DD
DD
SCLK
REF
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096V
P-
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time
SINAD
SNR
86
87
89.5
90
dB
dB
THD
-90
dB
SFDR
92
103
4
dB
-3dB point
MHz
kHz
SINAD > 86dB
10
t
(Note 4)
5
240
4.8
µs
MHz
ns
CONV
Serial Clock Frequency
Aperture Delay
f
0.1
SCLK
t
15
AD
Aperture Jitter
t
<50
ps
AJ
Sample Rate
f
f
/ 24
200
ksps
µs
S
SCLK
Track/Hold Acquisition Time
ANALOG INPUT (AIN)
Input Range
t
1.1
0
ACQ
V
V
V
AIN
REF
Input Capacitance
C
40
pF
AIN
REF
REF
EXTERNAL REFERENCE
Input-Voltage Range
V
3.8
AV
V
DD
V
V
= +4.096V, f
= 4.8MHz
SCLK
100
0.01
0.01
REF
REF
Input Current
I
= +4.096V, SCLK idle
µA
CS = DV , SCLK idle
DD
DIGITAL INPUTS (SCLK, CS)
0.7 x
Input High Voltage
V
DV
DV
= +2.7V to +5.25V
= +2.7V to +5.25V
V
V
IH
DD
DD
DV
DD
0.3 x
DV
Input Low Voltage
V
IL
DD
Input Leakage Current
Input Hysteresis
I
V
= 0 to DV
0.1
0.2
15
1
µA
V
IN
IN
DD
V
HYST
Input Capacitance
C
pF
IN
DIGITAL OUTPUT (DOUT)
DV
0.25V
-
DD
Output High Voltage
Output Low Voltage
V
I
= 0.5mA, DV = +2.7V to +5.25V
DD
V
V
OH
SOURCE
I
I
= 10mA, DV
= +4.75V to +5.25V
= +2.7V to +5.25V
0.7
0.4
SINK
DD
V
OL
= 1.6mA, DV
SINK
DD
Three-State Output Leakage
Current
I
CS = DV
CS = DV
0.1
15
10
µA
pF
L
DD
DD
Three-State Output Capacitance
C
OUT
_______________________________________________________________________________________
3
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(AV = DV = +4.75V to +5.25V, f
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
= +4.096V, C = 4.7µF,
REF
DD
DD
SCLK
REF
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Analog Supply
AV
DV
4.75
2.7
5.25
5.25
3.25
V
V
DD
Digital Supply
DD
MAX162
200ksps
100ksps
10ksps
1ksps
2.75
1.4
Analog Supply Current
Digital Supply Current
I
CS = DGND
mA
mA
AVDD
0.14
0.014
0.6
200ksps
100ksps
10ksps
1ksps
1.0
10
CS = DGND,
DOUT = all
zeros
0.3
I
DVDD
0.03
0.003
I
+
AVDD
Shutdown Supply Current
CS = DV , SCLK = idle
0.1
68
µA
dB
DD
I
DVDD
AV
= DV
= +4.75V to +5.25V, full-scale
DD
DD
Power-Supply Rejection Ratio
PSRR
input (Note 5)
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)
(AV
= DV
= +4.75V to +5.25V, f
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
= +4.096V, T = T
REF A MIN
DD
DD
SCLK
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Acquisition Time
t
1.1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACQ
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
t
C
C
C
= 50pF
= 50pF
= 50pF
50
80
80
DO
DOUT
DOUT
DOUT
t
DV
t
TR
t
50
CSW
CS Fall to SCLK Rise Setup
CS Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
t
100
CSS
CSH
t
0
t
65
65
CH
t
CL
CP
t
208
4
_______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX162
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)
(AV
= +4.75V to +5.25V, DV
= +2.7V to +5.25V, f
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
=
DD
DD
SCLK
REF
+4.096V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
Acquisition Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µs
t
1.1
ACQ
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
t
C
C
C
= 50pF
= 50pF
= 50pF
100
100
80
ns
DO
DOUT
DOUT
DOUT
t
ns
DV
t
ns
TR
t
50
ns
CSW
CS Fall to SCLK Rise Setup
CS Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
t
100
ns
CSS
CSH
t
0
ns
t
65
65
ns
CH
t
ns
CL
t
208
ns
CP
Note 1: AV
= DV
= +5V.
DD
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: Defined as the change in positive full scale caused by a 5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AV
= DV
= +5V, f
= 4.8MHz, C
= 50pF, C
= 4.7µF, V
= +4.096V, T = +25°C, unless otherwise noted.)
DD
DD
SCLK
LOAD
REF
REF A
DNL vs. OUTPUT CODE
INL vs. OUTPUT CODE
MAX1162 FFT
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
0
-20
-40
-60
-80
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
-2.0
-100
-120
-140
-2.0
0
13107 26214 39322 52429 65536
OUTPUT CODE
0
13107 26214 39322 52429 65536
OUTPUT CODE
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
_______________________________________________________________________________________
5
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Typical Operating Characteristics (continued)
(AV
= DV
= +5V, f
= 4.8MHz, C
= 50pF, C
= 4.7µF, V
= +4.096V, T = +25°C, unless otherwise noted.)
DD
DD
SCLK
LOAD
REF
REF A
THD vs. FREQUENCY
SFDR vs. FREQUENCY
SINAD vs. FREQUENCY
0
-10
120
110
100
90
100
90
80
70
60
50
40
30
20
10
0
-20
-30
MAX162
-40
80
-50
70
-60
60
-70
50
-80
40
-90
30
-100
-110
-120
20
10
0
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. CONVERSION RATE
SUPPLY CURRENT
vs. TEMPERATURE
3.5
3.0
2.5
2.0
1.5
1.0
0.5
10
1
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.1
0.01
0.001
0
4.75
4.85
4.95
5.05
5.15
5.25
0.01
0.1
1
10
100
1000
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
CONVERSION RATE (kHz)
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
20
18
16
14
12
10
8
150
125
100
75
50
6
4
25
2
0
0
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
6
_______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX162
Typical Operating Characteristics (continued)
(AV
= DV
= +5V, f
= 4.8MHz, C
= 50pF, C
= 4.7µF, V = +4.096V, T = +25°C, unless otherwise noted.)
REF A
DD
DD
SCLK
LOAD
REF
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
OFFSET ERROR VS. TEMPERATURE
1000
1000
800
600
800
600
400
400
200
200
0
0
-200
-400
-600
-800
-1000
-200
-400
-600
-800
-1000
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
0.020
0.015
0.010
0.005
0
0.020
0.015
0.010
0.005
0
-0.005
-0.010
-0.015
-0.020
-0.005
-0.010
-0.015
-0.020
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Pin Description
PIN
NAME
FUNCTION
External Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7µF
capacitor.
1
REF
2
AV
Analog +5V Supply Voltage. Bypass to AGND (pin 3) with a 0.1µF capacitor.
Analog Ground. Connect pins 3 and 9 together. Place star ground at pin 3.
DD
3, 9
AGND
Active-Low Chip-Select Input. Forcing CS high places the MAX1162 in shutdown with a typical
current of 0.1µA. A high-to-low transition on CS activates normal operating mode and initiates a
conversion.
MAX162
4
CS
Serial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to
4.8MHz.
5
6
SCLK
Serial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when CS
is high.
DOUT
DGND
7
8
Digital Ground
DV
Digital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.
Analog Input
DD
10
AIN
During the acquisition, the analog input (AIN) charges
Detailed Description
capacitor C
. The acquisition interval ends on the
DAC
The MAX1162 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 16-bit out-
put. Figure 4 shows the MAX1162 in its simplest config-
uration. The serial interface requires only three digital
lines (SCLK, CS, and DOUT) and provides an easy
interface to microprocessors (µPs).
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
DAC
C
represents a sample of the input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
16-bit resolution. At the end of the conversion, force CS
The MAX1162 has two power modes: normal and shut-
down. Driving CS high places the MAX1162 in shut-
down, reducing the supply current to 0.1µA (typ), while
pulling CS low places the MAX1162 in normal operating
mode. Falling edges on CS initiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface timing diagram.
high and then low to reset the input side of the C
DAC
to the input
switches back to AIN, and charge C
signal again.
DAC
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(t
ACQ
) is the maximum time the device takes to acquire
Analog Input
Figure 5 illustrates the input sampling architecture of
the ADC. The voltage applied at REF sets the full-scale
input voltage.
the signal. Use the following formula to calculate acqui-
sition time:
t
= 13(R + R ) x 35pF
S IN
ACQ
where R = 800Ω, R = the input signal’s source
IN
S
ACQ
Track-and-Hold (T/H)
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
impedance, and t
is never less than 1.1µs. A
source impedance less than 1kΩ does not significantly
affect the ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (>4MHz) that can
drive the ADC’s input capacitance and settle quickly.
8
_______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX162
V
V
DD
DD
1mA
1mA
DOUT
1mA
DOUT
DOUT
1mA
DOUT
C
LOAD
= 50pF
C
LOAD
= 50pF
C
LOAD
= 50pF
C
LOAD
= 50pF
DGND
a) V TO HIGH-Z
DGND
DGND
DGND
b) HIGH-Z TO V AND V TO V
b) V TO HIGH-Z
a) V TO V
OL
OH
OL
OH
OL
OH
OL
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
Figure 2. Load Circuits for DOUT Disable Time
CS
t
CSW
t
t
CH
CL
t
t
CSS
CSH
SCLK
t
CP
t
DO
t
TR
t
DV
DOUT
TIMING NOT TO SCALE.
Figure 3. Detailed Serial Interface Timing
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use anti-alias filtering.
AIN
REF
CS
SCLK
DOUT
CS
SCLK
DOUT
AIN
REF
AV
V
4.7µF
MAX1162
+5V
+5V
DD
0.1µF
Analog Input Protection
Internal protection diodes, which clamp the analog
DV
DD
AGND
DGND
input to AV
AGND - 0.3V to AV
device.
or AGND, allow the input to swing from
DD
0.1µF
+ 0.3V, without damaging the
DD
GND
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
Figure 4. Typical Operating Circuit
_______________________________________________________________________________________
9
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Digital Interface
Initialization after Power-Up and
REF
Starting a Conversion
TRACK
The digital interface consists of two inputs, SCLK and
CAPACITIVE DAC
AIN
ZERO
CS, and one output, DOUT. A logic high on CS places
the MAX1162 in shutdown (AutoShutdown) and places
DOUT in a high-impedance state. A logic low on CS
places the MAX1162 in the fully powered mode.
C
SWITCH
3pF
C
32pF
HOLD
DAC
R
IN
800Ω
GND
MAX162
TRACK
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
HOLD
AUTO-ZERO
RAIL
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs (Figures 6
and 7). Ensure that the duty cycle on SCLK is between
40% and 60% at 4.8MHz (the maximum clock frequen-
cy). For lower clock frequencies, ensure that the mini-
mum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz can
result in reduced accuracy due to leakage.
Figure 5. Equivalent Input Circuit
SCLK begins shifting out the data (MSB first) after the
falling edge of the 8th SCLK pulse. Twenty-four falling
clock edges are needed to shift out the eight leading
zeros and 16 data bits. Extra clock pulses occurring
after the conversion result has been clocked out, and
prior to the rising edge of CS, produce trailing zeros at
DOUT and have no effect on the converter operation.
Note: Coupling between SCLK and the analog
inputs (AIN and REF) may result in an offset.
Variations in frequency, duty cycle, or other aspects
of the clock signal’s shape result in changing offset.
A CS falling edge initiates an acquisition sequence.
The analog input is stored in the capacitive DAC,
DOUT changes from high impedance to logic low, and
the ADC begins to convert after the sixth clock cycle.
SCLK drives the conversion process and shifts out the
conversion result on DOUT.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX1162 in
shutdown. For maximum throughput, force CS low
again to initiate the next conversion immediately after
the specified minimum time (t
).
CSW
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX1162 in shutdown.
CS
24
1
4
6
8
12
16
D8
20
D4
SCLK
DOUT
t
t
CL
CSS
t
CSH
t
CH
D12 D11 D10 D9
D7
D6
D5
D3
D2
D1
D0
D15 D14 D13
t
t
ACQ
t
DV
DO
t
TR
Figure 6. External Timing Diagram
10 ______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX162
COMPLETE CONVERSION SEQUENCE
CS
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED UP
POWERED DOWN
TIMING NOT TO SCALE.
Figure 7. Shutdown Sequence
Output Coding and
Transfer Function
OUTPUT CODE
The data output from the MAX1162 is binary and Figure
8 depicts the nominal transfer function. Code transitions
occur halfway between successive-integer LSB values
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
(V
= 4.096V and 1LSB = 63µV or 4.096V/65536).
Applications Information
External Reference
REF
The MAX1162 requires an external reference with a
+3.8V and AV voltage range. Connect the external
FS = V
1LSB =
REF
V
65536
DD
REF
reference directly to REF. Bypass REF to AGND (pin 3)
with a 4.7µF capacitor. When not using a low-ESR
bypass capacitor, use a 0.1µF ceramic capacitor in
parallel with the 4.7µF capacitor. Noise on the refer-
ence degrades conversion accuracy.
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
The input impedance at REF is 40kΩ for DC currents.
During a conversion the external reference at REF must
deliver 100µA of DC load current and have an output
impedance of 10Ω or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
0
1
2
3
FS
FS - 3/2LSB
INPUT VOLTAGE (LSB)
Figure 8. Unipolar Transfer Function, Full Scale (FS) = V
Zero Scale (ZS) = GND
,
REF
MAX1162’s equivalent input noise (38µV
choosing a reference.
) when
RMS
At the beginning of the acquisition, the internal sampling
capacitor array connects to AIN (the amplifier output),
causing some output disturbance. Ensure that the sampled
voltage has settled before the end of the acquisition time.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multi-
plexed, switch the input channel immediately after acqui-
sition, rather than near the end of or after a conversion
(Figure 9). This allows the maximum time for the input
buffer amplifier to respond to a large step change in the
input signal. The input amplifier must have a slew rate of
at least 2V/µs to complete the required output-voltage
change before the beginning of the acquisition time.
Digital Noise
Digital noise can couple to AIN and REF. The conver-
sion clock (SCLK) and other digital signals active dur-
ing input acquisition contribute noise to the conversion
result. Noise signals synchronous with the sampling
interval result in an effective input offset. Asynchronous
signals produce random noise on the input, whose
high-frequency components can be aliased into the fre-
______________________________________________________________________________________ 11
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
A0
A1
IN1
IN2
4-TO-1
MUX
MAX1162
IN3
IN4
AIN
CS
MAX162
OUT
CLK
CS
ACQUISITION
CONVERSION
A0
A1
CHANGE MUX INPUT HERE
TIMING NOT TO SCALE.
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
quency band of interest. Minimize noise by presenting
DC Accuracy
a low impedance (at the frequencies contained in the
noise signal) at the inputs. This requires bypassing AIN
to AGND, or buffering the input with an amplifier that
has a small-signal bandwidth of several MHz, or prefer-
ably both. AIN has 4MHz (typ) of bandwidth.
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1162’s offset (1mV (max) for +5V
supply), or whose offset can be trimmed while maintain-
ing stability over the required temperature range.
Serial Interfaces
The MAX1162’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX1162’s
total harmonic distortion (THD = -102dB at 1kHz) at fre-
quencies of interest. If the chosen amplifier has insuffi-
cient common-mode rejection, which results in degraded
THD performance, use the inverting configuration (posi-
tive input grounded) to eliminate errors from this source.
Low temperature-coefficient, gain-setting resistors reduce
linearity errors caused by resistance changes due to self-
heating. To reduce linearity errors due to finite amplifier
gain, use amplifier circuits with sufficient loop gain at the
frequencies of interest.
If a serial interface is available, establish the CPU’s ser-
ial interface as master, so that the CPU generates the
serial clock for the MAX1162. Select a clock frequency
between 100kHz and 4.8MHz:
1) Use a general-purpose I/O line on the CPU to pull
CS low.
2) Activate SCLK for a minimum of 24 clock cycles.
The serial data stream of eight leading zeros fol-
lowed by the MSB of the conversion result begins at
the falling edge of CS. DOUT transitions on SCLK’s
falling edge and the output is available in MSB-first
12 ______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX162
format. Observe the SCLK to DOUT valid timing
characteristic. Clock data into the µP on SCLK’s ris-
ing edge.
SPI and MICROWIRE Interfaces
When using the SPI (Figure 10a) or MICROWIRE
(Figure 10b) interfaces, set CPOL = 0 and CPHA = 0.
Conversion begins with a falling edge on CS (Figure
10c). Three consecutive 8-bit readings are necessary
to obtain the entire 16-bit result from the ADC. DOUT
data transitions on the serial clock’s falling edge. The
first 8-bit data stream contains all leading zeros. The
second 8-bit data stream contains the MSB through D8.
The third 8-bit data stream contains D7 through D0.
3) Pull CS high at or after the 24th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the least significant bit (D0 = LSB).
4) With CS high, wait at least 50ns (t
) before start-
CSW
ing a new conversion by pulling CS low. A conver-
sion can be aborted by pulling CS high before the
conversion ends. Wait at least 50ns before starting a
new conversion.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1162 supports a maximum
Data can be output in three 8-bit sequences or continu-
ously. The bytes contain the results of the conversion
padded with eight leading zeros before the MSB. If the
serial clock has not been idled after the LSB (D0) and
CS has been kept low, DOUT sends trailing zeros.
f
of 4.8MHz. Figure 11a shows the MAX1162 con-
SCLK
nected to a QSPI master and Figure 11b shows the
associated interface timing.
I/O
SK
SI
CS
I/O
SCK
CS
SCLK
DOUT
SCLK
DOUT
MISO
MICROWIRE
V
DD
SPI
MAX1162
MAX1162
SS
Figure 10a. SPI Connections
Figure 10b. MICROWIRE Connections
1ST BYTE READ
4
2ND BYTE READ
12
1
6
8
16
SCLK
CS
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
24
HIGH-Z
D7
D6
D5
D4
D3
D2
D1
D0
TIMING NOT TO SCALE.
LSB
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
______________________________________________________________________________________ 13
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
CS
SCK
CS
SCLK
DOUT
MISO
QSPI
V
DD
MAX1162
SS
MAX162
Figure 11a. QSPI Connections
24
1
4
6
8
12
16
20
SCLK
CS
END OF
ACQUISITION
HIGH-Z
D15 D14 D13 D12 D11 D10 D9
MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT*
LSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
PIC16 with SSP Module and
PIC17 Interface
V
V
DD
DD
The MAX1162 is compatible with a PIC16/PIC17 micro-
controller (µC) using the synchronous serial-port (SSP)
module.
SCLK
DOUT
CS
SCK
SDI
I/O
To establish SPI communication, connect the controller
as shown in Figure 12a. Configure the PIC16/PIC17 as
system master, by initializing its synchronous serial-port
control register (SSPCON) and synchronous serial-port
status register (SSPSTAT) to the bit patterns shown in
Tables 1 and 2.
PIC16/17
MAX1162
GND
In SPI mode, the PIC16/PIC17 µC allows 8 bits of data
to be synchronously transmitted and received simulta-
Figure 12a. SPI Interface Connection for a PIC16/PIC17
Table 1. Detailed SSPCON Register Contents
MAX1162
SETTINGS
CONTROL BIT
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
BIT7
BIT6
X
X
Write Collision Detection Bit
SSPOV
Receive Overflow Detect Bit
Synchronous Serial-Port Enable Bit:
SSPEN
BIT5
1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP
BIT4
BIT3
BIT2
BIT1
BIT0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3
SSPM2
SSPM1
SSPM0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
f
= f
/ 16.
CLK
OSC
14 ______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX162
Table 2. Detailed SSPSTAT Register Contents
MAX1162
SETTINGS
CONTROL BIT
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
SMP
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0
1
X
X
X
X
X
X
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
CKE
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial clock.
D/A
Data Address Bit
Stop Bit
P
S
Start Bit
R/W
Read/Write Bit Information
Update Address
Buffer Full Status Bit
UA
BF
X = Don’t care.
1ST BYTE READ
2ND BYTE READ
12
16
SCLK
CS
0
0
0
0
0
0
0
0
D7
D15
D14
D13
D12
D11
D10
D9
D8
DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
24
HIGH-Z
D7
D6
D5
D4
D3
D2
D1
D0
TIMING NOT TO SCALE.
LSB
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
neously. Three consecutive 8-bit readings (Figure 12b)
are necessary to obtain the entire 16-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains all zeros. The sec-
ond 8-bit data stream contains the MSB through D8.
The third 8-bit data stream contains bits D7 through D0.
tion, once offset and gain errors have been nulled. The
static linearity parameters for the MAX1162 are mea-
sured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-fit straight line fit or a
line drawn between the endpoints of the transfer func-
Aperture Definitions
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between samples. Aperture delay (t ) is the
AD
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
______________________________________________________________________________________ 15
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
ENOB = (SINAD - 1.76) / 6.02
ENOB vs. INPUT FREQUENCY
Figure 13 shows the effective number of bits as a func-
tion of the MAX1162’s input frequency.
16
14
12
10
8
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
MAX162
6
⎡
⎢
⎢
⎣
⎤
⎥
⎥
2
2
2
2
V
+ V + V + V
3 4 5
2
4
THD = 20×log
V
1
2
⎢
⎥
⎦
0
where V is the fundamental amplitude and V through
V are the 2nd- through 5th-order harmonics.
1
2
0.1
1
10
100
5
INPUT FREQUENCY (kHz)
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
Figure 13. Effective Number of Bits vs. Input Frequency
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADCs res-
olution (N bits):
Supplies, Layout, Grounding,
and Bypassing
Use PC boards with separate analog and digital
ground planes. Do not use wire-wrap boards. Connect
the two ground planes together at the MAX1162 (pin 3).
Isolate the digital supply from the analog with a low-
value resistor (10Ω) or ferrite bead when the analog
and digital supplies come from the same source
(Figure 14).
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals,
excluding the DC offset.
AIN
REF
CS
SCLK
DOUT
CS
AIN
REF
AV
SCLK
DOUT
V
4.7µF
MAX1162
+5V
DD
⎡
⎢
⎣
⎤
⎥
Signal
RMS
10Ω
SINAD(dB) = 20 × log
⎢ Noise + Distortion
⎥
⎦
(
)
RMS
0.1µF
DV
DD
AGND
DGND
Effective Number of Bits
Effective number of bits (ENOB) indicate the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
0.1µF
GND
Figure 14. Powering AV
and DV
from a Single Supply
DD
DD
16 ______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX162
Constraints on sequencing the power supplies and
inputs are as follows:
Functional Diagram
• Apply AGND before DGND.
DV
DD
AV
DD
• Apply AIN and REF after AV
are present.
and AGND
DD
• DV
is independent of the supply sequencing.
DD
REF
AIN
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ω creates an error
voltage of about 250µV, 4LSB error with a +4V full-
scale system.
OUTPUT
BUFFER
16-BIT SAR
ADC
TRACK AND
HOLD
DOUT
AGND
SCLK
CONTROL
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and
digital (especially the SCLK and DOUT) lines parallel to
one another. If one must cross another, do so at right
angles.
CS
MAX1162
The ADCs high-speed comparator is sensitive to high-
DGND
frequency noise on the AV
power supply. Bypass an
DD
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.
Package Information
Chip Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 µMAX
U10-2
21-0061
______________________________________________________________________________________ 17
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
7/02
4/10
Initial release
Changed analog supply current and added lead-free information
—
1, 3, 5
MAX162
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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