MAX11644EUA+ [MAXIM]
ADC, Successive Approximation, 12-Bit, 1 Func, 2 Channel, Serial Access, BICMOS, PDSO8, ROHS COMPLIANT, UMAX-8;
| 型号： | MAX11644EUA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, 2 Channel, Serial Access, BICMOS, PDSO8, ROHS COMPLIANT, UMAX-8 |
| 文件： | 总21页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5225; Rev 0; 4/10
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
General Description
The MAX11644/MAX11645 low-power, 12-bit, 1-/2-
channel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, clock, and
an I2C-compatible 2-wire serial interface. These
devices operate from a single supply of 2.7V to 3.6V
(MAX11645) or 4.5V to 5.5V (MAX11644) and require
only 670µA at the maximum sampling rate of 94.4ksps.
Supply current falls below 230µA for sampling rates
under 40ksps. AutoShutdown™ powers down the
devices between conversions, reducing supply current
to less than 1µA at low throughput rates. The
MAX11644/MAX11645 each measure two single-ended
or one differential input. The fully differential analog
inputs are software configurable for unipolar or bipolar,
and single-ended or differential operation.
Features
o High-Speed I C-Compatible Serial Interface
2
400kHz Fast Mode
1.7MHz High-Speed Mode
o Single-Supply
2.7V to 3.6V (MAX11645)
4.5V to 5.5V (MAX11644)
o Internal Reference
2.048V (MAX11645)
4.096V (MAX11644)
o External Reference: 1V to V
o Internal Clock
DD
2-Channel Single-Ended or 1-Channel Fully
Differential
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to V . The MAX11645 fea-
DD
tures a 2.048V internal reference and the MAX11644
features a 4.096V internal reference.
o Internal FIFO with Channel-Scan Mode
o Low Power
670µA at 94.4ksps
230µA at 40ksps
The MAX11644/MAX11645 are available in an 8-pin
60µA at 10ksps
®
µMAX package. The MAX11644/MAX11645 are guar-
6µA at 1ksps
anteed over the extended temperature range (-40°C to
+85°C). For pin-compatible 10-bit parts, refer to the
MAX11646/MAX11647 data sheet.
0.5µA in Power-Down Mode
o Software-Configurable Unipolar/Bipolar
o Small, 8-Pin µMAX Package
Applications
Handheld Portable
Applications
Received-Signal-Strength
Indicators
Ordering Information
2
Medical Instruments
System Supervision
PIN-
I C SLAVE
PART
TEMP RANGE
PACKAGE ADDRESS
Battery-Powered Test
Equipment
Power-Supply Monitoring
MAX11644EUA+ -40°C to +85°C 8 µMAX
MAX11645EUA+ -40°C to +85°C 8 µMAX
+Denotes a lead(Pb)-free/RoHs-compliant package.
0110110
0110110
Solar-Powered Remote
Systems
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
AutoShutdown is a trademark and µMAX is a registered trademark
of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
AIN0, AIN1, REF to GND..............................-0.3V to the lower of
(V + 0.3V) and 6V
DD
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin ......................................... 50mA
Continuous Power Dissipation (T = +70°C)
A
8-Pin µMAX (derate 4.5mW/°C above +70°C)..............362mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 2.7V to 3.6V (MAX11645), V
= 4.5V to 5.5V (MAX11644), V
= 2.048V (MAX11645), V
= 4.096V (MAX11644), f
=
DD
DD
REF
REF
SCL
1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C, see Tables 1–5 for programming notation.)
MAX A
A
MIN
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
LSB
LSB
Relative Accuracy
Differential Nonlinearity
Offset Error
INL
(Note 2)
1
1
4
/MAX1645
DNL
No missing codes over temperature
Offset-Error Temperature
Coefficient
Relative to FSR
0.3
ppm/°C
Gain Error
(Note 3)
4
LSB
Gain-Temperature Coefficient
Relative to FSR
0.3
0.1
ppm/°C
Channel-to-Channel Offset
Matching
LSB
LSB
Channel-to-Channel Gain
Matching
0.1
DYNAMIC PERFORMANCE (f
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Full-Power Bandwidth
= 10kHz, V
= V
, f
= 94.4ksps)
IN(SINE-WAVE)
IN(P-P)
REF SAMPLE
SINAD
70
-78
78
3
dB
dB
THD
Up to the 5th harmonic
SFDR
dB
SINAD > 68dB
-3dB point
MHz
MHz
Full-Linear Bandwidth
5
CONVERSION RATE
Internal clock
7.5
Conversion Time (Note 4)
Throughput Rate
t
µs
CONV
External clock
10.6
800
Internal clock, SCAN[1:0] = 01
External clock
51
f
ksps
SAMPLE
94.4
Track/Hold Acquisition Time
Internal Clock Frequency
ns
2.8
60
30
MHz
External clock, fast mode
Aperture Delay (Note 5)
t
ns
AD
External clock, high-speed mode
2
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX11645), V
= 4.5V to 5.5V (MAX11644), V
= 2.048V (MAX11645), V
= 4.096V (MAX11644), f
=
DD
DD
REF
REF
SCL
1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C, see Tables 1–5 for programming notation.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0/AIN1)
Unipolar
Bipolar
0
0
V
REF
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
V
/2
REF
1
Input Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V _ = 0 or V
AIN
0.01
22
µA
pF
DD
C
IN
INTERNAL REFERENCE (Note 7)
MAX11645
1.968
3.936
2.048
4.096
2.128
4.256
Reference Voltage
V
T
A
= +25°C
V
REF
MAX11644
Reference-Voltage Temperature
Coefficient
TCV
25
ppm/°C
REF
REF Short-Circuit Current
REF Source Impedance
EXTERNAL REFERENCE
REF Input Voltage Range
REF Input Current
2
mA
1.5
kΩ
V
(Note 8)
1
V
V
REF
DD
I
f
= 94.4ksps
40
µA
REF
SAMPLE
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input-High Voltage
Input-Low Voltage
Input Hysteresis
V
0.7 x V
0.1 x V
V
V
IH
DD
DD
V
0.3 x V
DD
IL
V
V
HYST
Input Current
I
V
= 0 to V
DD
10
µA
pF
V
IN
IN
Input Capacitance
Output Low Voltage
POWER REQUIREMENTS
C
15
IN
V
I
= 3mA
0.4
OL
SINK
MAX11645
MAX11644
2.7
4.5
3.6
5.5
Supply Voltage
V
V
DD
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
900
670
530
230
380
60
1150
900
f
= 94.4ksps
SAMPLE
external clock
f
= 40ksps
SAMPLE
internal clock
Supply Current
I
µA
DD
f
= 10ksps
SAMPLE
internal clock
330
6
f
=1ksps
SAMPLE
internal clock
Shutdown (internal REF off)
Full-scale input (Note 9)
0.5
0.5
10
Power-Supply Rejection Ratio
PSRR
2.0
LSB/V
_______________________________________________________________________________________
3
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
TIMING CHARACTERISTICS (Figure 1)
(V
= 2.7V to 3.6V (MAX11645), V
= 4.5V to 5.5V (MAX11644), V
= 2.048V (MAX11645), V
= 4.096V (MAX11644), f
=
DD
DD
REF
REF
SCL
1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C, see Tables 1–5 for programming notation.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
f
400
kHz
µs
SCL
Bus Free Time Between a STOP (P)
and a START (S) Condition
t
1.3
BUF
Hold Time for START Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t
0.6
1.3
0.6
µs
µs
µs
HD,STA
t
LOW
t
HIGH
Setup Time for a Repeated START
(Sr) Condition
t
0.6
µs
SU,STA
Data Hold Time
Data Setup Time
t
(Note 10)
0
900
ns
ns
HD,DAT
t
100
SU,DAT
Rise Time of Both SDA and SCL
Signals, Receiving
t
Measured from 0.3V
Measured from 0.3V
- 0.7V
20 + 0.1C
300
300
ns
R
DD
DD
B
B
/MAX1645
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
- 0.7V (Note 11)
20 + 0.1C
0.6
ns
µs
pF
ns
F
DD
DD
t
SU,STO
C
400
50
B
t
SP
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C = 400pF, Note 12)
B
Serial-Clock Frequency
f
(Note 13)
1.7
MHz
ns
SCLH
Hold Time, Repeated START
Condition
t
160
HD,STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
320
120
ns
ns
LOW
t
HIGH
Setup Time for a Repeated START
Condition
t
,
160
ns
SU STA
Data Hold Time
Data Setup Time
t
,
(Note 10)
0
150
80
ns
ns
HD DAT
t
,
10
SU DAT
Rise Time of SCL Signal
(Current Source Enabled)
t
20
ns
RCL
4
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
= 2.7V to 3.6V (MAX11645), V
= 4.5V to 5.5V (MAX11644), V
= 2.048V (MAX11645), V
= 4.096V (MAX11644), f
=
DD
DD
REF
REF
SCL
1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C, see Tables 1–5 for programming notation.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time of SCL Signal After
Acknowledge Bit
t
Measured from 0.3V
- 0.7V
20
160
ns
RCL1
DD
DD
Fall Time of SCL Signal
t
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
- 0.7V
- 0.7V
20
20
80
ns
ns
ns
ns
pF
ns
FCL
DD
DD
DD
DD
DD
Rise Time of SDA Signal
t
160
160
RDA
Fall Time of SDA Signal
t
- 0.7V (Note 11)
20
FDA
DD
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
,
160
SU STO
C
400
10
B
t
(Notes 10 and 13)
0
SP
Note 1: For DC accuracy, the MAX11644 is tested at V
= 5V and the MAX11645 is tested at V
= 3V with an external
DD
DD
reference for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to V
.
DD
Note 7: When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µV
Note 9: Measured for the MAX11645 as:
.
P-P
2N
⎡
⎢
⎤
⎥
V
(3.6V) − V (2.7V) ×
⎤
FS
⎦
⎡
⎣ FS
V
⎢
⎣
⎥
⎦
REF
(3.6V −2.7V)
and for the MAX11644, where N is the number of bits:
2N
⎡
⎢
⎤
⎥
V
(5.5V) − V (4.5V) ×
⎤
FS
⎦
⎡
⎣ FS
V
⎢
⎣
⎥
⎦
REF
(5.5V −4.5V)
Note 10: A master device must provide a data hold time for SDA (referred to V of SCL) to bridge the undefined region of SCL’s
IL
falling edge (see Figure 1).
Note 11: The minimum value is specified at T = +25°C.
A
Note 12: C = total capacitance of one bus line in pF.
B
Note 13: f
must meet the minimum clock low time plus the rise/fall times.
SCL
_______________________________________________________________________________________
5
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Typical Operating Characteristics
(V
= 3.3V (MAX11645), V
= 5V (MAX11644), f
= 1.7MHz, 50% duty cycle, f = 94.4ksps, single-ended, unipolar,
SAMPLE
DD
DD
SCL
T = +25°C, unless otherwise noted.)
A
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
FFT PLOT
vs. DIGITAL CODE
vs. DIGITAL CODE
1.0
0.8
-20
0.5
f
f
= 94.4ksps
SAMPLE
0.4
0.3
= 10kHz
IN
-40
-60
0.6
0.2
0.1
0.4
0.2
0
-0.1
-0.2
0
-80
-0.2
-0.4
-0.6
-0.8
-1.0
-100
-120
-140
-0.3
-0.4
-0.5
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL OUTPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL OUTPUT CODE
0
10k
20k
30k
40k
50k
FREQUENCY (Hz)
SUPPLY CURRENT
SHUTDOWN SUPPLY CURRENT
/MAX1645
vs. TEMPERATURE
vs. SUPPLY VOLTAGE
800
0.6
0.5
0.4
0.3
0.2
0.1
0
INTERNAL REFERENCE MAX11644
SDA = SCL = V
DD
750
700
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
650
600
550
500
450
400
350
300
INTERNAL REFERENCE MAX11645
EXTERNAL REFERENCE MAX11644
EXTERNAL REFERENCE MAX11645
2.7
3.2
3.7
4.2
4.7
5.2
-40 -25 -10
5
20 35 50 65 80
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT
ANALOG SUPPLY CURRENT vs.
vs. TEMPERATURE
CONVERSION RATE (EXTERNAL CLOCK)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
1000
900
800
700
600
500
INTERNAL REFERENCE ALWAYS ON
MAX11644
MAX11645
400
300
200
100
0
EXTERNAL REFERENCE
0
20
40
60
80
100
-40
-10
5
20 35 50 65 80
-25
CONVERSION RATE (ksps)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
Typical Operating Characteristics (continued)
(V
= 3.3V (MAX11645), V
= 5V (MAX11644), f
= 1.7MHz, 50% duty cycle, f
= 94.4ksps, single-ended, unipolar,
SAMPLE
DD
DD
SCL
T = +25°C, unless otherwise noted.)
A
NORMALIZED REFERENCE VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
1.00010
1.00008
1.00006
1.00004
1.00002
1.00000
0.99998
0.99996
0.99994
0.99992
0.99990
1.0010
1.0008
1.0006
1.0004
1.0002
1.0000
0.9998
0.9996
0.9994
0.9992
0.9990
NORMALIZED TO VALUE AT T = +25°C
A
MAX11644
NORMALIZED TO
REFERENCE VALUE AT
MAX11644
V
= 5V
DD
MAX11645
MAX11645
NORMALIZED TO
REFERENCE VALUE AT
V
= 3.3V
DD
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
(V)
-40 -25 -10
5
20 35 50 65 80
V
TEMPERATURE (°C)
DD
OFFSET ERROR vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
2.0
1.6
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
-2.0
-40 -25 -10
5
20 35 50 65 80
2.7
3.2
3.7
4.2
4.7
5.2 5.5
TEMPERATURE (°C)
V
(V)
DD
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0
1.6
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
-2.0
-40 -25 -10
5
20 35 50 65 80
2.7
3.2
3.7
4.2
4.7
5.2 5.5
TEMPERATURE (°C)
V
(V)
DD
_______________________________________________________________________________________
7
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Pin Configuration
TOP VIEW
+
AIN0
AIN1
N.C.
REF
1
2
3
4
8
7
6
5
V
DD
GND
SDA
SCL
MAX11644
MAX11645
µMAX
Pin Description
PIN
1, 2
3
NAME
FUNCTION
AIN0, AIN1
N.C.
Analog Inputs
No Connection. Not internally connected.
4
REF
Reference Input/Output. Selected in the setup register (see Tables 1 and 6).
/MAX1645
5
SCL
Clock Input
6
SDA
Data Input/Output
7
GND
Ground
8
V
Positive Supply. Bypass to GND with a 0.1µF capacitor.
DD
A) F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
t
t
t
R
F
SDA
t
t
HD,DAT
SU,DAT
t
t
BUF
HD,STA
t
LOW
t
t
SU,STA
SU,STO
SCL
t
HD,STA
t
HIGH
t
t
R
F
S
Sr
A
P
S
B) HS-MODE 2-WIRE SERIAL-INTERFACE TIMING
t
t
RDA
FDA
SDA
t
t
HD,DAT
SU,DAT
t
t
BUF
HD,STA
t
LOW
t
t
SU,STO
SU,STA
SCL
t
t
HD,STA
HIGH
t
t
t
RCL
FCL
RCL1
S
Sr
A
S
F/S MODE
P
HS MODE
Figure 1. 2-Wire Serial-Interface Timing
_______________________________________________________________________________________
8
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
SDA
SCL
INPUT SHIFT REGISTER
V
DD
INTERNAL
OSCILLATOR
CONTROL
LOGIC
SETUP REGISTER
GND
CONFIGURATION REGISTER
AIN0
AIN1
OUTPUT SHIFT
REGISTER
AND RAM
12-BIT
ADC
T/H
ANALOG
INPUT
REF
MUX
REFERENCE
4.096V (MAX11644)
2.048V (MAX11645)
MAX11644
MAX11645
REF
Figure 2. Simplified Functional Diagram
serial interface supporting data rates up to 1.7MHz.
Figure 2 shows the simplified internal structure for the
MAX11644/MAX11645.
V
DD
I
OL
Power Supply
The MAX11644/MAX11645 operate from a single sup-
ply and consume 670µA (typ) at sampling rates up to
94.4ksps. The MAX11645 feature a 2.048V internal ref-
erence and the MAX11644 feature a 4.096V internal ref-
erence. All devices can be configured for use with an
V
SDA
OUT
400pF
external reference from 1V to V
.
I
DD
OH
Analog Input and Track/Hold
The MAX11644/MAX11645 analog-input architecture
contains an analog-input multiplexer (mux), a fully dif-
ferential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
Figure 3. Load Circuit
Detailed Description
The MAX11644/MAX11645 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX11644/MAX11645
measure either two single-ended or one differential
input(s). These devices feature a high-speed, 2-wire
In single-ended mode, the analog input multiplexer
connects C
between the analog input selected by
T/H
CS[0] (see the Configuration/Setup Bytes (Write Cycle)
section) and GND (Table 3). In differential mode, the
analog-input multiplexer connects C
to the + and -
T/H
analog inputs selected by CS[0] (Table 4).
_______________________________________________________________________________________
9
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
During the acquisition interval, the T/H switches are in
the track position and C charges to the analog input
MAX11645 hold SCL low. With external clock mode, the
T/H circuitry enters track mode after a valid address on
the rising edge of the clock during the read (R/W = 1)
bit. Hold mode is then entered on the rising edge of the
second clock pulse during the shifting out of the first
byte of the result. The conversion is performed during
the next 12 clock cycles.
T/H
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on C
as a stable sample of the input signal.
T/H
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of a 12-bit resolution. This action
requires 12 conversion clock cycles and is equivalent
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
to transferring a charge of 11pF x (V
T/H
digital representation of the analog input signal.
- V ) from
IN-
IN+
C
to the binary weighted capacitive DAC, forming a
time (t
) is the minimum time needed for the signal
ACQ
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog input
to GND. This input capacitor forms an RC filter with the
source impedance limiting the analog-input bandwidth.
For larger source impedances, use a buffer amplifier to
maintain analog-input signal integrity and bandwidth.
to be acquired. It is calculated by:
≥ 95 (R + R ) x C
IN
t
ACQ
SOURCE
IN
where R
IN
clock mode and t
is the analog-input source impedance,
SOURCE
= 2.5kΩ, and C = 22pF. t
R
is 1.5/f
for internal
IN
ACQ
SCL
= 2/f
for external clock mode.
ACQ
SCL
Analog Input Bandwidth
6
The MAX11644/MAX11645 feature input-tracking cir-
cuitry with a 5MHz small-signal bandwidth. The 5MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte. See the Slave Address section.
The T/H circuitry enters hold mode on the falling clock
edge of the acknowledge bit of the address byte (the
ninth clock pulse). A conversion or a series of conver-
sions is then internally clocked and the MAX11644/
REF
HOLD
ANALOG INPUT MUX
C
T/H
CAPACITIVE
DAC
AIN0
TRACK
AIN1
V
DD
/2
TRACK
CAPACITIVE
DAC
GND
C
T/H
HOLD
MAX11644
MAX11645
REF
Figure 4. Equivalent Input Circuit
10 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
Analog Input Range and Protection
Internal protection diodes clamp the analog input to V
DD
and GND. These diodes allow the analog inputs to swing
from (GND - 0.3V) to (V + 0.3V) without causing dam-
DD
age to the device. For accurate conversions, the inputs
must not go more than 50mV below GND or above V
.
DD
START and STOP Conditions
The master initiates a transmission with a START (S)
condition, a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a STOP
(P) condition, a low-to-high transition on SDA while SCL
is high (Figure 5). A repeated START (Sr) condition
can be used in place of a STOP condition to leave the
bus active and the interface mode unchanged (see the
HS Mode section).
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX11644/MAX11645 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS[0] and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS[0] (Table 4).
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11644/MAX11645 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to V
. A negative differential analog
REF
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to
V
REF
/2. The digital output code is bina-
ry in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11644/MAX11645
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to V
.
REF
2-Wire Digital Interface
The MAX11644/MAX11645 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock
line (SCL). SDA and SCL facilitate bidirectional commu-
nication between the MAX11644/MAX11645 and the
master at rates up to 1.7MHz. The MAX11644/
MAX11645 are slaves that transfer and receive data.
The master (typically a microcontroller) initiates data
transfer on the bus and generates the SCL signal to
permit that transfer.
S
Sr
P
SDA
SCL
Figure 5. START and STOP Conditions
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional. They
protect the input architecture of the MAX11644/
MAX11645 from high voltage spikes on the bus lines and
minimize crosstalk and undershoot of the bus signals.
S
NOT-ACKNOWLEDGE
SDA
ACKNOWLEDGE
8 9
Bit Transfer
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11644/MAX11645.
1
2
SCL
Figure 6. Acknowledge Bits
______________________________________________________________________________________ 11
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address. When idle, the MAX11644/MAX11645
continuously wait for a START condition followed by
their slave address. When the MAX11644/MAX11645
recognize their slave address, they are ready to accept
or send data. The slave address is factory programmed
to 0110110. The least significant bit (LSB) of the
address byte (R/W) determines whether the master is
writing to or reading from the MAX11644/MAX11645
(R/W = 0 selects a write condition, R/W = 1 selects a
read condition). After receiving the address, the
MAX11644/MAX11645 (slave) issues an acknowledge
by pulling SDA low for one clock cycle.
operate in high-speed mode (HS mode) to achieve con-
version rates up to 94.4ksps. Figure 1 shows the bus
timing for the MAX11644/MAX11645’s 2-wire interface.
HS Mode
At power-up, the MAX11644/MAX11645 bus timing is
set for F/S mode. The bus master selects HS mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After suc-
cessfully receiving the HS-mode master code, the
MAX11644/MAX11645 issue a not-acknowledge, allow-
ing SDA to be pulled high for one clock cycle (Figure
8). After the not-acknowledge, the MAX11644/
MAX11645 are in HS mode. The bus master must then
send a repeated START followed by a slave address to
initiate HS mode communication. If the master gener-
ates a STOP condition, the MAX11644/MAX11645
return to F/S mode.
Bus Timing
At power-up, the MAX11644/MAX11645 bus timing is
set for fast-mode (F/S mode), which allows conversion
rates up to 22.2ksps. The MAX11644/MAX11645 must
/MAX1645
SLAVE ADDRESS
MAX11644/MAX11645
S
0
1
1
0
1
1
0
R/W
A
SDA
SCL
1
2
3
4
5
6
7
8
9
SEE ORDERING INFORMATION FOR SLAVE ADDRESS OPTIONS AND DETAILS.
Figure 7. MAX11644/MAX11645 Slave Address Byte
HS-MODE MASTER CODE
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
F/S MODE
HS MODE
Figure 8. F/S-Mode to HS-Mode Transfer
12 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by seven address bits
(Figure 7) and a write bit (R/W = 0). If the address byte
is successfully received, the MAX11644/MAX11645
(slave) issues an acknowledge. The master then writes
to the slave. The slave recognizes the received byte as
the set-up byte (Table 1) if the most significant bit
(MSB) is 1. If the MSB is 0, the slave recognizes that
byte as the configuration byte (Table 2). The master
can write either one or two bytes to the slave in any
order (setup byte, then configuration byte; configura-
tion byte, then setup byte; setup byte or configuration
byte only; Figure 9). If the slave receives a byte suc-
cessfully, it issues an acknowledge. The master ends
the write cycle by issuing a STOP condition or a repeat-
ed START condition. When operating in HS mode, a
STOP condition returns the bus into F/S mode (see the
HS Mode section).
MASTER TO SLAVE
SLAVE TO MASTER
A) ONE-BYTE WRITE CYCLE
1
7
1
1
8
1
1
NUMBER OF BITS
SETUP OR
CONFIGURATION BYTE
S
SLAVE ADDRESS W A
A
P OR Sr
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B) TWO-BYTE WRITE CYCLE
1
7
1
1
8
1
8
1
1
NUMBER OF BITS
SETUP OR
CONFIGURATION BYTE
SETUP OR
CONFIGURATION BYTE
S
SLAVE ADDRESS W A
A
A
P OR Sr
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
Table 1. Setup Byte Format
BIT 7
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
(MSB)
REG
SEL2
SEL1
SEL0
CLK
BIP/UNI
RST
X
BIT
7
NAME
REG
SEL2
SEL1
SEL0
CLK
DESCRIPTION
Register bit. 1 = setup byte, 0 = configuration byte (Table 2).
6
Three bits select the reference voltage (Table 6).
Default to 000 at power-up.
5
4
3
1 = external clock, 0 = internal clock. Defaults to 0 at power-up.
2
BIP/UNI
RST
1 = bipolar, 0 = unipolar. Defaults to 0 at power-up (see the Unipolar/Bipolar section).
1
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t-care bit. This bit can be set to 1 or 0.
0
X
______________________________________________________________________________________ 13
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Table 2. Configuration Byte Format
BIT 7
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
(MSB)
REG
SCAN1
SCAN0
X
X
X
CS0
SGL/DIF
BIT
7
NAME
REG
SCAN1
SCAN0
X
DESCRIPTION
Register bit. 1 = setup byte (see Table 1), 0 = configuration byte.
6
Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up.
5
4
3
X
Channel select bit. CS0 selects which analog input channels are to be used for conversion
(Tables 3 and 4). Default to 0000 at power-up.
2
X
1
CS0
1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the Single-
Ended/Differential Input section.
0
SGL/DIF
X = Don’t care.
/MAX1645
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
CS0
AIN0
AIN1
GND
0
+
-
-
1
+
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
CS0
AIN0
AIN1
0
+
-
-
1
+
14 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing a
START condition followed by seven address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX11644/MAX11645 (slave) issues an
acknowledge. The master then reads from the slave.
The result is transmitted in 2 bytes; first 4 bits of the first
byte are high, then MSB through LSB are consecutively
clocked out. After the master has received the byte(s), it
can issue an acknowledge if it wants to continue read-
ing or a not-acknowledge if it no longer wishes to read.
If the MAX11644/MAX11645 receive a not-acknowl-
edge, they release SDA, allowing the master to generate
a STOP or a repeated START condition. See the Clock
Modes and Scan Mode sections for detailed information
on how data is obtained and converted.
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While
converting the analog input signal, the MAX11644/
MAX11645 hold SCL low (clock stretching). After the
conversion completes, the results are stored in internal
memory. If the scan mode is set for multiple conver-
sions, they all happen in succession with each addi-
tional result stored in memory. The MAX11644/
MAX11645 contain two 12-bit blocks of memory. Once
all conversions are complete, the MAX11644/
MAX11645 release SCL, allowing it to be pulled high.
The master can now clock the results out of the memo-
ry in the same order the scan conversion has been
done at a clock rate of up to 1.7MHz. SCL is stretched
for a maximum of 8.3µs per channel (see Figure 10).
The device memory contains all of the conversion
results when the MAX11644/MAX11645 release SCL.
The converted results are read back in a first-in-first-out
(FIFO) sequence. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and points to the
first result. Note that only the current conversion results
are read from memory. The device must be addressed
with a read command to obtain new conversion results.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the set-
up byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX11644/MAX11645 are defaulted
to internal clock mode (CLK = 0).
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX11644/MAX11645 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX11644/MAX11645 begin tracking the analog input
after a valid address on the eighth rising edge of the
MASTER TO SLAVE
SLAVE TO MASTER
A) SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
1
1
8
8
1
1
NUMBER OF BITS
S
SLAVE ADDRESS
R
A
RESULT 4 MSBs
A
RESULT 8 LSBs
A
P OR Sr
CLOCK STRETCH
t
ACQ
t
CONV
B) SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
7
1
1
8
1
8
1
8
1
8
1
1
NUMBER OF BITS
CLOCK STRETCH
S
SLAVE ADDRESS
R
A
RESULT 1 ( 4MSBs)
A
RESULT 1 (8 LSBs)
A
RESULT N (4MSBs)
A
RESULT N (8LSBs)
A
P OR Sr
t
t
t
ACQ1
ACQ2
ACQN
t
t
t
CONVN
CONV1
CONV2
Figure 10. Internal Clock Mode Read Cycles
______________________________________________________________________________________ 15
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
External Clock
When configured for external clock mode (CLK = 1),
the MAX11644/MAX11645 use the SCL as the conver-
sion clock. In external clock mode, the MAX11644/
MAX11645 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later, the analog signal is acquired
and the conversion begins. Unlike the internal clock
mode, converted data is available immediately after the
first four empty high bits. The device continuously con-
verts input channels dictated by the scan mode until
given a not-acknowledge. There is no need to read-
dress the device with a read command to obtain new
conversion results (see Figure 11).
Use internal clock mode if the SCL clock period
exceeds 60µs.
The MAX11644/MAX11645 must operate in external
clock mode for conversion rates from 40ksps to
94.4ksps. Below 40ksps, internal clock mode is recom-
mended due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. The scanned results are written to memo-
ry in the same order as the conversion. Read the results
from memory in the order they were converted. Each
result needs a 2-byte transmission; the first byte begins
with 4 empty bits, during which SDA is left high. Each
byte has to be acknowledged by the master or the mem-
ory transmission is terminated. It is not possible to read
the memory independently of conversion.
The conversion must complete in 1ms, or droop on the
track-and-hold capacitor degrades conversion results.
/MAX1645
MASTER TO SLAVE
SLAVE TO MASTER
A) SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
1
1
8
1
8
1
1
NUMBER OF BITS
S
R
A
A
SLAVE ADDRESS
RESULT (4 MSBs)
RESULT (8 LSBs)
A
P OR Sr
t
ACQ
t
CONV
B) SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
7
1
1
8
1
8
1
8
1
8
1
1
NUMBER OF BITS
S
R
A
A
A
A
P OR Sr
A
SLAVE ADDRESS
RESULT 1 (4 MSBs)
RESULT 2 (8 LSBs)
RESULT N (4 MSBs)
RESULT N (8 LSBs)
t
t
t
ACQ1
ACQ2
ACQN
t
t
CONV1
CONVN
Figure 11. External Clock Mode Read Cycle
Table 5. Scanning Configuration
SCAN1
SCAN0
SCANNING CONFIGURATION
0
0
1
1
0
1
0
1
Scans up from AIN0 to the input selected by CS0.
Converts the input selected by CS0 eight times (see Tables 3 and 4).*
Reserved. Do not use.
Converts the input selected by CS0.*
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not-acknowledge occurs.
16 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
Table 6. Reference Voltage and REF Format
REFERENCE
VOLTAGE
INTERNAL REFERENCE
STATE
SEL2
SEL1
SEL0
REF
0
0
1
0
0
1
1
X
X
0
1
0
1
V
Not connected
Reference input
Not connected*
Not connected*
Reference output
Reference output
Always off
Always off
Always off
Always on
Always off
Always on
DD
0
External reference
Internal reference
Internal reference
Internal reference
Internal reference
1
1
1
1
X = Don’t care.
*Preferred configuration for internal reference.
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates and with internal
clock. For example, at a conversion rate of 10ksps, the
average supply current for the MAX11645 is 60µA (typ)
and drops to 6µA (typ) at 1ksps. At 0.1ksps the aver-
age supply current is just 1µA, or a minuscule 3µW of
power consumption. See Average Supply Current vs.
Conversion Rate (External Clock) in the Typical
Operating Characteristics section).
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel con-
version on AIN0 using the internal clock with V
as the
DD
reference. The memory contents are unknown after
power-up.
Automatic Shutdown
Automatic shutdown occurs between conversions when
the MAX11644/MAX11645 are idle. All analog circuits
participate in automatic shutdown except the internal
reference due to its prohibitively long wake-up time.
When operating in external clock mode, a STOP, not-
acknowledge, or repeated START condition must be
issued to place the devices in idle mode and benefit
from automatic shutdown. A STOP condition is not nec-
essary in internal clock mode to benefit from automatic
shutdown because power-down occurs once all con-
version results are written to memory (Figure 10). When
Reference Voltage
SEL[2:0] of the setup byte (Table 1) control the refer-
ence configuration (Table 6).
Internal Reference
The internal reference is 4.096V for the MAX11644 and
2.048V for the MAX11645. When REF is configured to
be an internal reference output (SEL[2:1] = 11), decou-
ple REF to GND with a 0.1µF capacitor and a 2kΩ
series resistor (see the Typical Operating Circuit). Once
powered up, the reference always remains on until
reconfigured. The internal reference requires 10ms to
wake up and is accessed using SEL0 (Table 6). When
in shutdown, the internal reference output is in a high-
impedance state. The reference should not be used to
supply current for external circuitry. The internal refer-
ence does not require an external bypass capacitor
and works best when left unconnected (SEL1 = 0).
using an external reference or V
as a reference, all
DD
analog circuitry is inactive in shutdown and supply cur-
rent is less than 0.5µA. The digital conversion results
obtained in internal clock mode are maintained in mem-
ory during shutdown and are available for access
through the serial interface at any time prior to a STOP
or a repeated START condition.
When idle, the MAX11644/MAX11645 continuously wait
for a START condition followed by their slave address
(see the Slave Address section). Upon reading a valid
address byte, the MAX11644/MAX11645 power up. The
internal reference requires 10ms to wake up, so when
using the internal reference it should be powered up
10ms prior to conversion or powered continuously.
Wake-up is invisible when using an external reference
External Reference
The external reference can range from 1V to V . For
DD
maximum conversion accuracy, the reference must be
able to deliver up to 40µA and have an output imped-
ance of 500kΩ or less. If the reference has a higher
output impedance or is noisy, bypass it to GND as
close as possible to REF with a 0.1µF capacitor.
or V
as the reference.
DD
______________________________________________________________________________________ 17
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Minimize capacitor lead length for best supply noise
Transfer Functions
rejection, and add an attenuation resistor (5Ω) in series
Output data coding for the MAX11644/MAX11645 is
with the power supply if it is extremely noisy.
binary in unipolar mode and two’s complement in bipo-
N
lar mode with 1 LSB = (V
/2 ) where N is the number
REF
Definitions
of bits (12). Code transitions occur halfway between
successive-integer LSB values. Figures 12 and 13
show the input/output (I/O) transfer functions for unipo-
lar and bipolar operations, respectively.
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
MAX11644/MAX11645’s INL is measured using the
endpoint.
Layout, Grounding, and Bypassing
Only use PCBs. Wire-wrap configurations are not rec-
ommended since the layout should ensure proper sep-
aration of analog and digital traces. Do not run analog
and digital lines parallel to each other, and do not lay-
out digital signal paths underneath the ADC package.
Use separate analog and digital PCB ground sections
with only one star point (Figure 14) connecting the two
ground systems (analog and digital). For lowest noise
operation, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
/MAX1645
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
High-frequency noise in the power supply (V ) could
DD
influence the proper operation of the ADC’s fast compara-
Aperture Delay
Aperture delay (t ) is the time between the falling
AD
edge of the sampling clock and the instant when an
actual sample is taken.
tor. Bypass V
to the star ground with a network of two
DD
parallel capacitors, 0.1µF and 4.7µF, located as close as
possible to the MAX11644/MAX11645 power-supply pin.
OUTPUT CODE
OUTPUT CODE
MAX11644
MAX11645
MAX11644
MAX11645
V
FULL-SCALE
TRANSITION
REF
2
FS
=
011 . . . 111
011 . . . 110
11 . . . 111
ZS = 0
-FS =
11 . . . 110
11 . . . 101
-V
REF
2
000 . . . 010
000 . . . 001
000 . . . 000
V
REF
1 LSB =
4096
FS = V
REF
111 . . . 111
111 . . . 110
111 . . . 101
ZS = GND
V
REF
1 LSB =
4096
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
0
1
2
3
FS
0
- FS
+FS - 1 LSB
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 13. Bipolar Transfer Function
Figure 12. Unipolar Transfer Function
18 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
SUPPLIES
RMS equivalent of all other ADC output signals.
⎡
⎢
⎣
⎤
Signal
GND
3V OR 5V
V
= 3V/5V
LOGIC
RMS
SINAD(dB) = 20 × log
⎥
Noise
+ THD
RMS
RMS ⎦
4.7µF
0.1µF
R* = 5Ω
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
V
GND
3V/5V DGND
DD
DIGITAL
CIRCUITRY
ENOB = (SINAD - 1.76)/6.02
MAX11644
MAX11645
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
*OPTIONAL
Figure 14. Power-Supply Grounding Connection
⎛
⎜
⎞
⎟
2
2
2
2
⎛
⎜
⎝
⎞
V
+ V + V + V
3 4 5
2
THD = 20 × log
Signal-to-Noise Ratio
⎟
⎠
V
⎜
⎝
⎟
⎠
1
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 5th-order
5
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
SNR
= 6.02dB x N + 1.76dB
MAX[dB]
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
______________________________________________________________________________________ 19
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Typical Operating Circuit
Selector Guide
INTERNAL
REFERENCE VOLTAGE
SUPPLY
3.3V or 5V
INPUT
CHANNELS
INL
(LSB)
PART
(V)
(V)
0.1µF
V
DD
2 single-
ended/1
differential
R *
S
MAX11644
MAX11645
4.096
4.5 to 5.5
1
1
AIN0
AIN1
ANALOG
INPUTS
SDA
SCL
MAX11644
MAX11645
2 single-
ended/1
R *
S
2.048
2.7 to 3.6
2kΩ
RC NETWORK*
REF
differential
GND
5V
C
0.1µF
REF
5V
R
P
R
P
SDA
SCL
µC
/MAX1645
*OPTIONAL
Package Information
Chip Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 µMAX
U8CN+1
21-0036
20 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/MAX1645
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
4/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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