MAX1168CEEG+ [MAXIM]
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| 型号： | MAX1168CEEG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
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| 文件： | 总30页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2956; Rev 0; 8/03
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
General Description
Features
The MAX1167/MAX1168 low-power, multichannel, 16-
bit analog-to-digital converters (ADCs) feature a suc-
cessive-approximation ADC, integrated +4.096V
reference, a reference buffer, an internal oscillator,
automatic power-down, and a high-speed SPI™/
QSPI™/MICROWIRE™-compatible interface. The
MAX1167/MAX1168 operate with a single +5V analog
supply and feature a separate digital supply, allowing
direct interfacing with +2.7V to +5.5V digital logic.
o 16-Bit Resolution, 1 ꢀLB ꢁDꢀ ꢂ(max
o +5V Lingle-Lupply Opermtion
o Adjustmble ꢀogic ꢀevel ꢂ+2.7V to +5.25Vx
o Input Voltmge Rmnge: 0 to V
REF
o Internml ꢂ+4.096Vx or Eaternml ꢂ+3.8V to AV
x
ꢁꢁ
Reference
o Internml Trmck/Hold, 4MHz Input Bmndwidth
o Internml or Eaternml Clock
The MAX1167/MAX1168 consume only 2.9mA (AV
=
DD
DV = +5V) at 200ksps when using an external reference.
DD
AutoShutdown™ reduces the supply current to 145µA at
10ksps and to less than 10µA at reduced sampling rates.
o LPI/QLPI/MICROWIRE-Co(pmtible Leriml
Interfmce, MAX1168 Perfor(s ꢁLP-Initimted
Conversions
The MAX1167 includes a 4-channel input multiplexer, and
the MAX1168 accepts up to eight analog inputs.
In addition, digital signal processor (DSP)-initiated con-
versions are simplified with the DSP frame-sync input and
output featured in the MAX1168. The MAX1168 includes
a data-bit transfer input to select between 8-bit-wide or
16-bit-wide data-transfer modes. Both devices feature a
scan mode that converts each channel sequentially or
one channel continuously.
o 8-Bit-Wide or 16-Bit-Wide ꢁmtm-Trmnsfer Mode
ꢂMAX1168 Onlyx
o 4-Chmnnel ꢂMAX1167x or 8-Chmnnel ꢂMAX1168x
Input Mua
Lcmn Mode Lequentimlly Converts Multiple
Chmnnels or One Chmnnel Continuously
o ꢀow Power
Excellent dynamic performance and low power, com-
bined with ease of use and an integrated reference, make
the MAX1167/MAX1168 ideal for control and data-acqui-
sition operations or for other applications with demanding
power consumption and space requirements. The
MAX1167 is available in a 16-pin QSOP package and the
MAX1168 is available in a 24-pin QSOP package. Both
devices are guaranteed over the commercial (0°C to
+70°C) and extended (-40°C to +85°C) temperature
ranges. Use the MAX1168 evaluation kit to evaluate the
MAX1168.
2.9(A mt 200ksps
1.45(A mt 100ksps
145µA mt 10ksps
0.6µA in Full Power-ꢁown Mode
o L(mll Pmckmge Lize
16-Pin QLOP ꢂMAX1167x
24-Pin QLOP ꢂMAX1168x
Ordering Information
Applications
PID-
IDꢀ
PART
TEMP RADGE
Motor Control
PACKAGE ꢂꢀLBx
Industrial Process Control
Industrial I/O Modules
MAX1167ACEE
MAX1167BCEE
MAX1167CCEE
MAX1167AEEE*
MAX1167BEEE*
MAX1167CEEE*
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 QSOP
16 QSOP
16 QSOP
16 QSOP
16 QSOP
16 QSOP
1.2
2
3
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
1.2
2
3
*Future product—contact factory for availability.
SPI/QSPI are trademarks of Motorola, Inc.
Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ABLOꢀUTE MAXIMUM RATIDGL
AV
DV
to AGND .........................................................-0.3V to +6V
to DGND.........................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
DD
DD
A
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
Operating Temperature Ranges
DGND to AGND.....................................................-0.3V to +0.3V
AIN_, REF, REFCAP to AGND..................-0.3V to (AV + 0.3V)
DD
SCLK, CS, DSEL, DSPR, DIN to DGND ...................-0.3V to +6V
DOUT, DSPX, EOC to DGND...................-0.3V to (DV + 0.3V)
Maximum Current into Any Pin............................................50mA
MAX116_ _ CE_ ..................................................0°C to +70°C
MAX116_ _ EE_ ...............................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢀECTRICAꢀ CHARACTERILTICL
(AV
= DV
= +4.75V to +5.25V, f
= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external V
DD
DD
A
SCLK REF
= +4.096V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
PARAMETER
ꢁC ACCURACY (Note 1)
Resolution
LYMBOꢀ
CODꢁITIODL
MID
TYP
MAX
UDITL
16
Bits
LSB
MAX116_A
MAX116_B
MAX116_C
1.5
2.0
3.0
2
3
6
Relative Accuracy (Note 2)
INL
MAX116_A
(16 bit, no missing codes over temperature)
1
+1.75
-1.0
MAX116_B
(16 bit, no missing codes over temperature)
Differential Nonlinearity
Transition Noise
DNL
LSB
MAX116_C
(15 bit, no missing codes over temperature)
2
External reference
Internal reference
0.7
0.8
0.1
0.01
1
RMS
noise
LSB
RMS
Offset Error
Gain Error
Offset Drift
Gain Drift
10
mV
(Note 3)
(Note 3)
0.2
%FSR
ppm/°C
ppm/°C
1.2
ꢁYDAMIC LPECIFICATIODL ꢂ1kHz sine wmve, 4.096V x (Note 1)
P-P
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
86
86
88.5
88.5
-100
101
4
dB
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Full-Power Bandwidth
THD
-90
dB
SFDR
92
dB
-3dB point
SINAD > 85dB
(Note 4)
MHz
kHz
dB
Full-Linear Bandwidth
10
Channel-to-Channel Isolation
96
2
_______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
EꢀECTRICAꢀ CHARACTERILTICL ꢂcontinuedx
(AV
= DV
= +4.75V to +5.25V, f
= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external V
DD
DD
A
SCLK REF
= +4.096V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
PARAMETER
LYMBOꢀ
CODꢁITIODL
MID
TYP
MAX
UDITL
CODVERLIOD RATE
Internal clock, no data transfer,
single conversion (Note 5)
5.52
3.75
7.07
Conversion Time
t
µs
CONV
External clock
Acquisition Time
t
(Note 6)
729
0.1
ns
ACQ
External clock, data transfer and conversion
External clock, data transfer only
Internal clock
4.8
9
Serial Clock Frequency
f
MHz
SCLK
Internal Clock Frequency
Aperture Delay
f
3.2
4.0
15
MHz
ns
INTCLK
t
AD
Aperture Jitter
t
<50
ps
AJ
8-bit-wide data-transfer mode
16-bit-wide data-transfer mode
4.17
200.00
150.00
3.125
Internal clock, single conversion, 8-bit-wide
data-transfer mode
89
68
Internal clock, single conversion, 16-bit-
wide data-transfer mode
Sample Rate (Note 7)
f
ksps
S
Internal clock, scan mode, 8-bit-wide data-
transfer mode (four conversions)
103
82
External clock, scan mode, 16-bit-wide
data-transfer mode (four conversions)
Duty Cycle
45
0
55
%
ADAꢀOG IDPUT ꢂAID_x
Input Range
V
_
V
V
AIN
REF
Input Capacitance
C
_
45
pF
AIN
EXTERDAꢀ REFEREDCE
Input Voltage Range
V
I
3.8
AV
V
REF
DD
V
_ = 0
110
0.1
0.1
AIN
Input Current
µA
SCLK idle
CS = DV , SCLK idle
REF
DD
IDTERDAꢀ REFEREDCE
Reference Voltage
V
4.056
4.096
13
4.136
V
REFIN
Reference Short-Circuit Current
I
mA
REFSC
Reference Temperature
Coefficient
25
5
ppm/°C
Reference Wake-Up Time
t
V
= 0
REF
ms
RWAKE
_______________________________________________________________________________________
3
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
EꢀECTRICAꢀ CHARACTERILTICL ꢂcontinuedx
(AV
= DV
= +4.75V to +5.25V, f
= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external V
DD
DD
A
SCLK REF
= +4.096V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
PARAMETER
LYMBOꢀ
CODꢁITIODL
MID
TYP
MAX
UDITL
ꢁIGITAꢀ IDPUTL ꢂLCꢀK, CS, ꢁLEꢀ, ꢁLPR, ꢁIDx ꢂꢁV
= +2.7V to +5.25Vx
ꢁꢁ
0.7 ×
Input High Voltage
Input Low Voltage
V
V
V
IH
DV
DD
0.3 ×
V
IL
DV
DD
Input Leakage Current
Input Hysteresis
I
Digital inputs = 0 to DV
0.1
0.2
15
1
µA
V
IN
DD
V
HYST
Input Capacitance
C
pF
IN
ꢁIGITAꢀ OUTPUT ꢂꢁOUT, ꢁLPX, EOCx ꢂꢁV
= +2.7V to +5.25Vx
ꢁꢁ
DV
0.4
-
DD
Output High Voltage
Output Low Voltage
V
I
= 0.5mA
V
V
OH
SOURCE
I
I
= 10mA, DV
= +4.75V to +5.25V
= +2.7V to +5.25V
0.8
SINK
DD
V
OL
= 1.6mA, DV
0.4
10
SINK
DD
Tri-State Output Leakage Current
Tri-State Output Capacitance
POWER LUPPꢀIEL
I
CS = DV
CS = DV
0.1
15
µA
pF
L
DD
DD
C
OUT
Analog Supply
AV
DV
4.75
2.70
5.25
5.25
2.9
V
V
DD
Digital Supply
DD
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
200ksps
2.0
2.9
200ksps
100ksps
10ksps
1ksps
3.8
1.0
2.0
Analog Supply Current (Note 8)
I
mA
AVDD
0.1
1.1
0.01
1.01
0.87
0.45
0.045
0.005
1.3
100ksps
DOUT =
all zeros
Digital Supply Current
I
mA
mA
DVDD
10ksps
1ksps
Internal reference and
reference buffer on
between conversions
1.01
0.43
CS = DV
SCLK = 0,
DIN = 0,
,
DD
I
+
AVDD
Power-Down Supply Current
I
DVDD
Internal reference on,
reference buffer off
between conversions
DSPR = DV
DD
4
_______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
EꢀECTRICAꢀ CHARACTERILTICL ꢂcontinuedx
(AV
= DV
= +4.75V to +5.25V, f
= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external V
DD
DD
A
SCLK REF
= +4.096V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
PARAMETER
LYMBOꢀ
CODꢁITIODL
CS = DV , SCLK = 0, DIN = 0,
MID
TYP
MAX
UDITL
I
+
AVDD
DD
Shutdown Supply Current
0.6
10
µA
dB
I
DSPR = DV , full power-down
DD
DVDD
AV
= DV
= 4.75V to 5.25V, full-scale
DD
DD
Power-Supply Rejection Ratio
PSRR
63
input (Note 9)
TIMIDG CHARACTERILTICL ꢂFigures 1, 2, 8, mnd 16x
(AV
= ꢁV
= +4.096V, T = T
= +4.75V to +5.25V, f
= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external
ꢁꢁ
ꢁꢁ
SCLK
V
REF
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
LYMBOꢀ
CODꢁITIODL
External clock (Note 6)
MID
TYP
MAX
UDITL
ns
Acquisition Time
t
729
ACQ
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
t
C
C
C
= 30pF
= 30pF
= 30pF
50
80
80
ns
DO
DOUT
DOUT
DOUT
t
ns
DV
t
ns
TR
t
100
100
ns
CSW
SCLK rise
CS to SCLK Setup
CS to SCLK Hold
t
ns
ns
ns
CSS
SCLK fall (DSP)
SCLK rise
t
0
CSH
SCLK fall (DSP)
Conversion
Data transfer
Conversion
Data transfer
93
50
SCLK High Pulse Width
t
Duty cycle 45% to 55%
Duty cycle 45% to 55%
CH
93
SCLK Low Pulse Width
SCLK Period
t
ns
ns
ns
CL
CP
DS
50
t
t
209
SCLK rise
DIN to SCLK Setup
50
0
SCLK fall (DSP)
SCLK rise
DIN to SCLK Hold
t
ns
DH
SCLK fall (DSP)
CS Falling to DSPR Rising
t
100
100
0
ns
ns
ns
DF
DSPR to SCLK Falling Setup
DSPR to SCLK Falling Hold
t
FSS
FSH
t
_______________________________________________________________________________________
5
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
TIMIDG CHARACTERILTICL ꢂFigures 1, 2, 8, mnd 16x
(AV
= +4.75V to +5.25V, ꢁV
= +2.7V to +5.25V, f
= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion
DD
ꢁꢁ
SCLK
(200ksps), external V
= +4.096V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
REF
A
MIN
PARAMETER
Acquisition Time
LYMBOꢀ
CODꢁITIODL
External clock (Note 6)
MID
TYP
MAX
UDITL
ns
t
729
ACQ
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
t
C
C
C
= 30pF
= 30pF
= 30pF
100
100
80
ns
DO
DOUT
DOUT
DOUT
t
ns
DV
t
ns
TR
t
100
100
ns
CSW
SCLK rise
CS to SCLK Setup
CS to SCLK Hold
t
ns
ns
ns
CSS
SCLK fall (DSP)
SCLK rise
t
0
CSH
SCLK fall (DSP)
Conversion
Data transfer
Conversion
Data transfer
93
93
SCLK High Pulse Width
t
Duty cycle 45% to 55%
Duty cycle 45% to 55%
CH
93
SCLK Low Pulse Width
SCLK Period
t
ns
ns
ns
CL
CP
DS
93
t
t
209
SCLK rise
DIN to SCLK Setup
100
0
SCLK fall (DSP)
SCLK rise
DIN to SCLK Hold
t
ns
DH
SCLK fall (DSP)
CS Falling to DSPR Rising
DSPR to SCLK Falling Setup
DSPR to SCLK Falling Hold
t
100
100
0
ns
ns
ns
DF
t
FSS
FSH
t
Dote 1: AV
= DV
= +5.0V.
DD
DD
Dote 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Dote 3: Offset and reference errors nulled.
Dote 4: DC voltage applied to on channel, and a full-scale 1kHz sine wave applied to off channels.
Dote 5: Conversion time is measured from the rising edge of the 8th external SCLK pulse to EOC transition minus t
in 8-bit data-
ACQ
transfer mode.
Dote 6: See Figures 10 and 17.
-1
) where: n
1
Dote 7: f
= 4.8MHz, f
= 4.0MHz. Sample rate is calculated with the formula f = n (n / f
+ n / f
s
1
2
3
SCLK
INTCLK
SCLK
INTCLK
= number of scans, n = number of SCLK cycles, and n = number of internal clock cycles (see Figures 11–14).
2
3
Dote 8: Internal reference and buffer are left on between conversions.
Dote 9: Defined as the change in the positive full scale caused by a 5% variation in the nominal supply voltage.
6
_______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Typical Operating Characteristics
(AV
= DV
= +5V, f
= 4.8MHz, C
= 30pF, external V
= +4.096V, T = +25°C, unless otherwise noted.)
DD
DD
SCLK
DOUT
REF A
INL vs. CODE
DNL vs. CODE
FFT AT f = 1kHz
AIN
20
1.5
1.0
0.5
0
1.5
1.0
0.5
0
0
-20
-40
-60
-80
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
-100
-120
-140
-160
0
16384
32768
CODE
49152
65536
0
16384
32768
CODE
49152
65536
0
20
40
60
80
100
FREQUENCY (kHz)
SINAD vs. FREQUENCY
SFDR vs. FREQUENCY
THD vs. FREQUENCY
100
90
120
100
80
60
40
20
0
0
f
= 200kbps
SAMPLE
-20
-40
80
70
60
50
40
30
20
10
0
-60
-80
-100
-120
f
= 200kbps
f
= 200ksps
SAMPLE
SAMPLE
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
(INTERNAL REFERENCE)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
(EXTERNAL REFERENCE)
SUPPLY CURRENT vs. CONVERSION RATE
(EXTERNAL CLOCK)
3.0
2.5
2.0
1.5
1.0
0.5
0
2.95
2.90
2.85
2.80
2.75
2.70
2.00
1.95
1.90
1.85
1.80
1.75
DV = AV = +5V
DD
OUT
DD
T
= +85°C
= +70°C
DV = +5V
DD
= 200ksps
A
DV = +5V
DD
= 200ksps
D
= ALL ZEROS
f
S
T
A
= +70°C
f
S
EXTERNAL CLOCK
SPI MODE
T
A
T
A
= +85°C
T
A
= +25°C
T
A
= +25°C
I , INT REF
AVDD
T
A
= 0°C
T = 0°C
A
I
, EXT REF
AVDD
I
DVDD
T
A
= -40°C
T
A
= -40°C
-0.5
0
20 40 60 80 100 120 140 160 180 200
CONVERSION RATE (ksps)
4.75
4.85
4.95
5.05
5.15
5.25
4.75
4.85
4.95
5.05
5.15
5.25
AV (V)
DD
AV (V)
DD
_______________________________________________________________________________________
7
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Typical Operating Characteristics (continued)
(AV
= DV
= +5V, f
= 4.8MHz, C
= 30pF, external V
= +4.096V, T = +25°C, unless otherwise noted.)
DD
DD
SCLK
DOUT
REF A
POWER-DOWN SUPPLY CURRENT
POWER-DOWN SUPPLY CURRENT
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
vs. AV SUPPLY VOLTAGE
vs. DV SUPPLY VOLTAGE
DD
DD
(INTERNAL REFERENCE)
(INTERNAL REFERENCE)
MAX1167/68 toc11
MAX1167/68 toc12
2.6
2.2
1.8
1.4
1.0
0.6
0.2
0.58
0.57
0.56
0.55
0.54
0.53
0.52
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1.03
1.02
1.01
1.00
0.99
AV = +5V
DV = +5V
DD
= 0
DD
AV = +5V
DD
V
V
S
IL
IH
= DV
DD
f
= 200ksps
DOUT = 1010...1010
DOUT = 0000...0000
I
AVDD
I
AVDD
I
DVDD
I
DVDD
2.70
3.21
3.72
4.23
4.74
5.25
4.75
4.85
4.95
5.05
5.15
5.25
2.70
3.21
3.72
4.23
4.74
5.25
DV (V)
DD
AV (V)
DD
DV (V)
DD
SHUTDOWN SUPPLY CURRENT
SHUTDOWN SUPPLY CURRENT
vs. DV SUPPLY VOLTAGE
vs. AV SUPPLY VOLTAGE
DD
DD
(EXTERNAL REFERENCE)
(EXTERNAL REFERENCE)
MAX1167/68 toc14
MAX1167/68 toc13
0.7
0.43
0.42
0.41
0.40
0.39
0.38
0.37
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.54
0.50
0.46
0.42
0.38
0.34
0.30
AV = +5V
DD
DV = +5V
DD
0.6
0.5
0.4
0.3
0.2
0.1
I
AVDD
I
DVDD
I
AVDD
I
DVDD
2.70
3.21
3.72
4.23
4.74
5.25
4.75
4.85
4.95
5.05
5.15
5.25
DV (V)
DD
AV (V)
DD
POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE (INTERNAL REFERENCE)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (EXTERNAL REFERENCE)
MAX1167/68 toc15
MAX1167/68 toc16
0.58
1.04
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.45
0.43
0.41
0.39
0.37
0.35
DV = AV = +5V
DV = AV = +5V
DD DD
DD
DD
0.57
0.56
0.55
0.54
0.53
0.52
1.03
1.02
1.01
1.00
0.99
0.98
I
AVDD
I
AVDD
I
I
DVDD
DVDD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
8
_______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Typical Operating Characteristics (continued)
(AV
= DV
= +5V, f
= 4.8MHz, C
= 30pF, external V
= +4.096V, T = +25°C, unless otherwise noted.)
DD
DD
SCLK
DOUT
REF A
OFFSET ERROR vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. SUPPLY VOLTAGE
200
150
200
100
0
0.05
0.04
0.03
0.02
0.01
0
V
REF
= +4.096V
V
REF
= +4.096V
V
REF
= +4.096V
100
50
-100
-200
-300
-400
0
-50
-100
-150
-0.01
-0.02
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
AV (V)
DD
AV (V)
DD
CHANNEL-TO-CHANNEL ISOLATION
vs. FREQUENCY
INTERNAL +4.096V REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
4.104
4.100
4.096
4.092
4.088
0
0
-0.001
-0.002
-0.003
-0.004
-0.005
V
= +4.096V
REF
DV = +5V
DD
T
A
= +85°C
-20
-40
-60
T
A
= +70°C
T
A
= +25°C
-80
T
A
= -40°C
T = 0°C
A
-100
-120
4.75
4.85
4.95
5.05
5.15
5.25
0
20
40
60
80
100
-40
-15
10
35
60
85
AV (V)
DD
FREQUENCY (kHz)
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE
vs. REF LOAD
INTERNAL CLOCK CONVERSION TIME
(8th RISING SCLK TO FALLING EOC)
EXTERNAL REFERENCE INPUT CURRENT
vs. EXTERNAL REFERENCE VOLTAGE
160
140
120
100
80
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
70
60
50
40
30
20
10
0
8-BIT DATA-TRANSFER MODE
60
V
f
= 0
SCLK
AIN
= 4.8MHz
16-BIT DATA-TRANSFER MODE
53
AV = DV = +5V
DD
DD
f
= 4.8MHz
SCLK
46
44
39
38
199ksps, EXTERNAL CLOCK
33
31
28
24
60
22
87.19ksps, INTERNAL CLOCK
f
= 0
17
17
SCLK
40
INTERNAL REFERENCE MODE
12
10
LOAD APPLIED TO REF
6
20
C
= 1µF
REF
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
0
2
4
6
8
10
12
14
1
2
3
4
5
6
7
8
V
REF
I
(mA)
NUMBER OF SCAN-MODE CONVERSIONS
REF
_______________________________________________________________________________________
9
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Pin Description
PID
DAME
DOUT
SCLK
DIN
FUDCTIOD
MAX1167
MAX1168
Serial Data Output. Data changes state on SCLK’s falling edge in SPI/QSPI/MICROWIRE
mode and on SCLK’s rising edge in DSP mode (MAX1168 only). DOUT is high impedance
when CS is high.
1
3
Serial Clock Input. SCLK drives the conversion process in external clock mode and clocks
data out.
2
3
4
4
5
6
Serial Data Input. Use DIN to communicate with the command/configuration/control
register. In SPI/QSPI/MICROWIRE mode, the rising edge of SCLK clocks in data at DIN. In
DSP mode, the falling edge of SCLK clocks in data at DIN.
End-of-Conversion Output. In internal clock mode, a logic low at EOC signals the end of a
conversion with the result available at DOUT. In external clock mode, EOC remains high.
EOC
5
6
7
8
7
8
AIN0
AIN1
AIN2
AIN3
Analog Input 0
Analog Input 1
Analog Input 2
Analog Input 3
9
10
Reference Voltage Input/Output. V
with a 10µF capacitor. Bypass with a 1µF (min) capacitor when using internal reference.
sets the analog voltage range. Bypass to AGND
REF
9
15
16
REF
Reference Bypass Capacitor Connection. Bypass to AGND with a 0.1µF capacitor when
using internal reference. Internal reference and buffer shut down in external reference mode.
10
REFCAP
11
12
13
17
18
19
AGND
AGND
Analog Ground. Connect to pin 18 (MAX1168) or pin 12 (MAX1167).
Primary Analog Ground (Star Ground). Power return for AV
.
DD
AV
Analog Supply Voltage. Bypass to AGND with a 0.1µF capacitor.
DD
Active-Low Chip-Select Input. Forcing CS high places the MAX1167/MAX1168 in shutdown
with a typical supply current of 0.6µA. In SPI/QSPI/MICROWIRE mode, a high-to-low
transition on CS activates normal operating mode. In DSP mode, after the initial CS
transition from high to low, CS can remain low for the entire conversion process (see the
Operating Modes section).
14
20
CS
15
16
21
22
DGND
DV
Digital Ground
Digital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.
DD
DSP Frame-Sync Receive Input. A frame-sync pulse received at DSPR initiates a
conversion. Connect to logic high when using SPI/QSPI/MICROWIRE mode.
—
—
1
2
DSPR
DSEL
Data-Bit Transfer-Select Input. Logic low on DSEL places the device in 8-bit-wide data-
transfer mode. Logic high places the device in 16-bit-wide data-transfer mode. Do not
leave DSEL unconnected.
—
—
11
12
AIN4
AIN5
Analog Input 4
Analog Input 5
10 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Pin Description (continued)
PID
DAME
FUDCTIOD
MAX1167
MAX1168
—
13
AIN6
AIN7
Analog Input 6
Analog Input 7
—
—
—
14
23
24
DSP Frame-Sync Transmit Output. A frame-sync pulse at DSPX notifies the DSP that the
MSB data is available at DOUT. Leave DSPX unconnected when not in DSP mode.
DSPX
N.C.
No Connection. Not internally connected.
DV
DD
DV
DD
1mA
1mA
DOUT
DOUT
DOUT
1mA
DOUT
C
LOAD
= 30pF
C
LOAD
= 30pF
C
LOAD
= 30pF
C = 30pF
LOAD
1mA
DGND
a) V TO HIGH-Z
DGND
b) V TO HIGH-Z
DGND
a) V TO V
DGND
b) HIGH-Z TO V AND V TO V
OL
OH
OL
OH
OL
OL
OH
Figure 1. Load Circuits for DOUT Enable Time and SCLK-to-
DOUT Delay Time
Figure 2. Load Circuits for DOUT Disable Time
In SPI/QSPI/MICROWIRE mode, a falling edge on CS
wakes the analog circuitry and allows SCLK to clock in
data. Acquisition and conversion are initiated by SCLK.
The conversion result is available at DOUT in unipolar
serial format. DOUT is held low until data becomes
available (MSB first) on the 8th falling edge of SCLK
when in 8-bit transfer mode, and on the 16th falling
edge when in 16-bit transfer mode (see the Operating
Modes section). Figure 8 shows the detailed SPI/QSPI/
MICROWIRE serial-interface timing diagram.
Detailed Description
The MAX1167/MAX1168 low-power, multichannel, 16-bit
ADCs feature a successive-approximation ADC, auto-
matic power-down, integrated +4.096V reference, and a
high-speed SPI/QSPI/MICROWIRE-compatible interface.
A DSPR input and DSPX output allow the MAX1168 to
communicate with digital signal processors (DSPs) with
no external glue logic. The MAX1167/MAX1168 operate
with a single +5V analog supply and feature a separate
digital supply, allowing direct interfacing with +2.7V to
+5.5V digital logic.
In external clock mode, the MAX1168 also interfaces
with DSPs. In DSP mode, a frame-sync pulse from the
DSP initiates a conversion that is driven by SCLK. The
MAX1168 formats a frame-sync pulse to notify the DSP
that the conversion results are available at DOUT in
MSB-first, unipolar, serial-data format. Figure 16 shows
the detailed DSP serial-interface timing diagram (see the
Operating Modes section).
Figures 3 and 4 show the functional diagrams of the
MAX1167/MAX1168, and Figures 5 and 6 show the
MAX1167/MAX1168 in a typical operating circuit. The
serial interface simplifies communication with micro-
processors (µPs).
In external reference mode, the MAX1167/MAX1168
have two power modes: normal mode and shutdown
mode. Driving CS high places the MAX1167/MAX1168 in
shutdown mode, reducing the supply current to 0.6µA
(typ). Pull CS low to place the MAX1167/MAX1168 in
normal operating mode. The internal reference mode
offers software-programmable, power-down options as
shown in Table 5.
Analog Input
Figure 7 illustrates the input-sampling architecture of
the ADC. The voltage applied at REF or the internal
+4.096V reference sets the full-scale input voltage.
______________________________________________________________________________________ 11
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
AV
DV
REFCAP
DD
DD
REFERENCE
BUFFER
REF
AGND
MAX1167
AIN0
AIN1
ANALOG-INPUT
MULTIPLEXER
COMPARATOR
DAC
AIN2
AIN3
AZ
RAIL
ANALOG-SWITCH FINE TIMING
BIAS
SCLK
SUCCESSIVE-APPROXIMATION
REGISTER
MULTIPLEXER
OUTPUT
DOUT
EOC
OSCILLATOR
ACCUMULATOR
CONTROL
CS
MEMORY
INPUT REGISTER
DIN
AGND
DGND
Figure 3. MAX1167 Functional Diagram
Track/Hold (T/H)
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive digital-to-analog converter
(DAC) samples the analog input.
(t
) is the maximum time the device takes to acquire
ACQ
During the acquisition, the analog input (AIN_) charges
the signal. Use the following formula to calculate acqui-
sition time:
capacitor C
. At the end of the acquisition interval
DAC
the T/H switches open. The retained charge on C
represents a sample of the input.
DAC
t
= 11(R + R + R
) ✕ 45pF + 0.3µs
ACQ
S
IN
DS(ON)
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to zero within the limits of 16-bit resolution. At the
end of the conversion, force CS high and then low to
reset the T/H switches back to track mode (AIN_),
where R = 340Ω, R = the input signal’s source
IN
S
impedance, R
= 60Ω, and t
is never less
ACQ
DS(ON)
than 729ns. A source impedance of less than 200Ω
does not significantly affect the ADC’s performance.
where C
charges to the input signal again.
DAC
12 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
AV
DV
REFCAP
DD
DD
REFERENCE
BUFFER
REF
MAX1168
AGND
AIN0
AIN1
AIN2
AIN3
AIN4
ANALOG-INPUT
MULTIPLEXER
COMPARATOR
DAC
AIN5
AIN6
AZ
RAIL
AIN7
ANALOG-SWITCH FINE TIMING
BIAS
SCLK
SUCCESSIVE-APPROXIMATION
REGISTER
MULTIPLEXER
OUTPUT
DOUT
OSCILLATOR
ACCUMULATOR
CS
DSEL
DSPR
EOC
DSPX
CONTROL
MEMORY
INPUT REGISTER
DIN
AGND
DGND
Figure 4. MAX1168 Functional Diagram
The MAX1168 features a 16-bit-wide data-transfer
mode that includes a longer acquisition time (11.5
clock cycles). Longer acquisition times are useful in
applications with input source resistances greater than
1kΩ. Noise increases when using large source resis-
tances. To improve the input signal bandwidth under
AC conditions, drive AIN_ with a wideband buffer
(>10MHz) that can drive the ADC’s input capacitance
and settle quickly.
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted, high-frequency signals into
the frequency band of interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AV
or AGND, allow the input to swing from
DD
(AGND - 0.3V) to (AV
+ 0.3V) without damaging the
DD
device. If the analog input exceeds 300mV beyond the
supplies, limit the input current to 10mA.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, making possible the digitization of
high-speed transient events and the measurement of
______________________________________________________________________________________ 13
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
SCLK
DSPX
CS
AIN0
AIN1
AIN2
AIN3
SCLK
DSPX
CS
SCLK
DOUT
CS
AIN0
AIN1
AIN2
AIN3
ANALOG
INPUTS
SCLK
DOUT
EOC
ANALOG
INPUTS
DOUT
EOC
DOUT
EOC
AIN4
AIN5
AIN6
EOC
DIN
DIN
AIN7
DIN
MAX1167
DIN
REF
MAX1168
16
8
DSEL
DSPR
1µF
AGND
AGND
DGND
AV
DD
+5V
+5V
REF
1µF
0.1µF
AGND
AGND
DGND
AV
DD
+5V
+5V
DV
DD
REFCAP
0.1µF
0.1µF
0.1µF
DV
DD
REFCAP
0.1µF
0.1µF
GND
GND
Figure 5. MAX1167 Typical Operating Circuit
Figure 6. MAX1168 T ypical Operating Circuit
In addition to the standard 3-wire serial interface modes,
the MAX1168 includes a DSPR input and a DSPX output
for communicating with DSPs in external clock mode and
a DSEL input to determine 8-bit-wide or 16-bit-wide data-
transfer mode. When not using the MAX1168 in the DSP
REF
MUX
R
DSON
CAPACITIVE
DAC
TRACK
HOLD
AIN_
ZERO
C
MUX
C
DAC
interface mode, connect DSPR to DV
and leave DSPX
DD
R
IN
unconnected.
AGND
HOLD
C
SWITCH
Command/Configuration/Control Register
Table 1 shows the contents of the command/configura-
tion/control register and the state of each bit after initial
power-up. Tables 2–6 define the control and configuration
of the device for each bit. Cycling the power supplies
resets the command/configuration/control register to the
power-on-reset default state.
TRACK
AUTOZERO
RAIL
Figure 7. Equivalent Input Circuit
Initialization After Power-Up
A logic high on CS places the MAX1167/MAX1168 in
the shutdown mode chosen by the power-down bits,
and places DOUT in a high-impedance state. Drive CS
low to power up and enable the MAX1167/MAX1168
before starting a conversion. In internal reference
mode, allow 5ms for the shutdown internal reference
and/or buffer to wake and stabilize before starting a
conversion. In external reference mode (or if the inter-
nal reference is already on), no reference settling time
is needed after power-up.
Digital Interface
The MAX1167/MAX1168 feature an SPI/QSPI/
MICROWIRE-compatible, 3-wire serial interface. The
MAX1167 digital interface consists of digital inputs CS,
SCLK, and DIN and outputs DOUT and EOC. The
MAX1167 operates in the following modes:
• SPI interface with external clock
• SPI interface with internal clock
• SPI interface with internal clock and scan mode
Tmble 1. Co((mnd/Configurmtion/Control Register
BIT7 ꢂMLBx
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0 ꢂꢀLBx
COMMADꢁ
CH LEꢀ2
CH LEꢀ1 CH LEꢀ0
LCAD1
LCAD0
REF/Pꢁ_LEꢀ1
REF/Pꢁ LEꢀ0
IDT/EXT CꢀK
POWER-UP
STATE
0
0
0
0
0
1
1
0
14 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Tmble 2. Chmnnel Lelect
Tmble 3. MAX1167 Lcmn Mode, Internml
Clock Only
BIT7
BIT6
BIT5
CHADDEꢀ
AID_
CH LEꢀ2
CH LEꢀ1
CH LEꢀ0
BIT4
BIT3
ACTIOD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
LCAD1 LCAD0
Single channel, no scan
0
0
Sequentially scan channels 0 through N
(N ≤ 3)
0
1
Sequentially scan channels 2 through N
(2 ≤ N ≤ 3)
1
1
0
1
Scan channel N four times
Tmble 4. MAX1168 Lcmn Mode, Internml
Clock Only ꢂDot for ꢁLP Modex
BIT4
BIT3
ACTIOD
LCAD1 LCAD0
Single channel, no scan
0
0
Sequentially scan channels 0 through N
(N ≤ 7)
0
1
Sequentially scan channels 4 through N
(4 ≤ N ≤ 7)
1
1
0
1
Scan channel N eight times
Tmble 5. Power-ꢁown Modes
BIT2
BIT1
TYPICAꢀ
LUPPꢀY
CURREDT
TYPICAꢀ WAKE-
UP TIME
REFEREDCE MOꢁE
ꢂIDTERDAꢀ REFEREDCEx
REFEREDCE
REF/Pꢁ_
LEꢀ1
REF/Pꢁ
LEꢀ0
ꢂC
= 1µFx
REF
Internal reference and reference buffer on
between conversions
0
0
0
1
Internal
Internal
1mA
NA
Internal reference and reference buffer off
between conversions
0.6µA
5ms
Internal reference on, reference buffer off
between conversions
1
1
0
1
Internal
External
0.43mA
0.6µA
5ms
NA
Internal reference and buffer always off
Tmble 6. Clock Modes
BIT0
CꢀOCK MOꢁE
IDT/EXT
CꢀK
0
1
External clock
Internal clock
______________________________________________________________________________________ 15
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
t
CSW
CS
• • •
• • •
t
t
CP
t
CSS
CSH
t
CL
t
CH
SCLK
t
DS
t
DH
DIN
• • •
• • •
t
t
TR
DO
t
DV
DOUT
Figure 8. Detailed SPI Interface Timing
when in SPI/QSPI/MICROWIRE mode and on the falling
edge of DSPR when in DSP mode. Allow 5ms for the
internal reference to rise and settle when powering up
CS
from a complete shutdown (V
= 0, C
= 1µF).
REF
REF
COMPLETE CONVERSION SEQUENCE
The internal reference stays on and the buffer is shut off
on the rising edge of CS when bit 2 = 1 and bit 1 = 0.
The MAX1167/MAX1168 enter this mode on the rising
edge of CS. The buffer wakes up on the falling edge of
CS when in SPI/QSPI/MICROWIRE mode and on the ris-
ing edge of DSPR when in DSP mode. Allow 5ms for
DOUT
CONVERSION 0
CONVERSION 1
POWERED UP
POWERED UP
POWERED DOWN
V
to settle when powering up from a complete shut-
REF
down (V
= 0, C
= 1µF). V
is always equal
REFCAP
Figure 9. Shutdown Sequence
REF
REF
to +4.096V in this mode.
Set both bit 2 and bit 1 to 1 to turn off the reference and
reference buffer to allow connection of an external ref-
erence. Using an external reference requires no extra
wake-up time.
Power-Down Modes
Table 5 shows the MAX1167/MAX1168 power-down
modes. Three internal reference modes and one exter-
nal reference mode are available. Select power-down
modes by writing to bits 2 and 1 in the command/con-
figuration/control register. The MAX1167/MAX1168
enter the selected power-down mode on the rising
edge of CS.
Operating Modes
External Clock 8-Bit-Wide Data-Transfer Mode
(MAX1167 and MAX1168)
Force DSPR high and DSEL low (MAX1168) for SPI/
QSPI/MICROWIRE interface mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to clock
in data. Ensure the duty cycle on SCLK is between 45%
and 55% when operating at 4.8MHz (the maximum
clock frequency). For lower clock frequencies, ensure
the minimum high and low times are at least 93ns.
External-clock-mode conversions with SCLK rates less
The internal reference stays on when CS is pulled high,
if bits 2 and 1 are set to zero. This mode allows for the
fastest turn-on time.
Setting bit 2 = 0 and bit 1 = 1 turns both the reference
and reference buffer off when CS is brought high. This
mode achieves the lowest supply current. The refer-
ence and buffer wake up on the falling edge of CS
16 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
1
16
24
8
SCLK
DIN
MSB
LSB
0
MSB
LSB
DOUT
DSPR*
DSEL*
ADC
STATE
t
IDLE
t
CONV
ACQ
*MAX1168 ONLY
Figure 10. SPI External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
than 125kHz can reduce accuracy due to leakage of the
sampling capacitor. DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the
rising edge of SCLK. The first SCLK rising edge begins
loading data into the command/configuration/control
register from DIN. The devices select the proper chan-
nel for conversion on the rising edge of the 3rd SCLK
cycle. Acquisition begins immediately thereafter and
ends on the falling edge of the 6th clock cycle. The
MAX1167/MAX1168 sample the input and begin conver-
sion on the falling edge of the 6th clock cycle. Setup
and configuration of the MAX1167/MAX1168 complete
on the rising edge of the 8th clock cycle. The conver-
sion result is available (MSB first) at DOUT on the falling
edge of the 8th SCLK cycle. To read the entire conver-
sion result, 16 SCLK cycles are needed. Extra clock
pulses, occurring after the conversion result has been
clocked out and prior to the rising edge of CS, cause
zeros to be clocked out of DOUT. The MAX1167/
MAX1168 external clock 8-bit-wide data-transfer mode
requires 24 SCLK cycles for completion (Figure 10).
External Clock 16-Bit-Wide Data-Transfer Mode
(MAX1168 Only)
Force DSPR high and DSEL high for SPI/QSPI/
MICROWIRE interface mode. Logic high at DSEL allows
the MAX1168 to transfer data in 16-bit-wide words. The
acquisition time is extended an extra eight SCLK cycles
in the 16-bit-wide data-transfer mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to clock
in data. Ensure the duty cycle on SCLK is between 45%
and 55% when operating at 4.8MHz (the maximum clock
frequency). For lower clock frequencies, ensure that the
minimum high and low times are at least 93ns. External-
clock-mode conversions with SCLK rates less than
125kHz can reduce accuracy due to leakage of the sam-
pling capacitor. DOUT changes from high-Z to logic low
after CS is brought low. Input data latches on the rising
edge of SCLK. The first SCLK rising edge begins loading
data into the command/configuration/control register from
DIN. The devices select the proper channel for conver-
sion and begin acquisition on the rising edge of the 3rd
SCLK cycle. Setup and configuration of the MAX1168
completes on the rising edge of the 8th clock cycle.
Acquisition ends on the falling edge of the 14th SCLK
cycle. The MAX1168 samples the input and begins con-
version on the falling edge of the 14th clock cycle. The
conversion result is available (MSB first) at DOUT on the
falling edge of the 16th SCLK cycle. To read the entire
conversion result, 16 SCLK cycles are needed. Extra
clock pulses, occurring after the conversion result has
been clocked out and prior to the rising edge of CS,
cause zeros to be clocked out of DOUT.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
). Forcing CS high in the middle of a
CSW
conversion immediately aborts the conversion and
places the MAX1167/MAX1168 in shutdown.
_______________________________________________________________________________________ 17
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
1
16
24
32
8
SCLK
DIN
MSB
LSB
0
X
X
X
X
X
X
X
X
MSB
LSB
DOUT
DSPR
DSEL
ADC
STATE
t
t
IDLE
ACQ
CONV
,
X = DON T CARE
Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
CS
1
9
16
24
8
SCLK
2
6
25
INTERNAL
CLK
• • •
MSB
LSB
1
DIN
MSB
LSB
DOUT
EOC
X
ADC
STATE
t
POWER-DOWN
,
t
CONV
ACQ
IDLE
X = DON T CARE
DSPR = DV , DSEL = GND (MAX1168 ONLY)
DD
Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
The MAX1168 external clock 16-bit-wide data-transfer
mode requires 32 SCLK cycles for completion (Figure 11).
register begins reading DIN on the first SCLK rising edge
and ends on the rising edge of the 8th SCLK cycle. The
MAX1167/MAX1168 select the proper channel for con-
version on the rising edge of the 3rd SCLK cycle. The
internal oscillator activates 125ns after the rising edge of
the 8th SCLK cycle. Turn off the external clock while the
internal clock is on. Turning off SCLK ensures the lowest
noise performance during acquisition. Acquisition begins
on the 2nd rising edge of the internal clock and ends on
the falling edge of the 6th internal clock cycle. Each bit
of the conversion result shifts into memory as it becomes
available. The conversion result is available (MSB first) at
DOUT on the falling edge of EOC. The internal oscillator
and analog circuitry are shut down on the high-to-low
EOC transition. Use the EOC high-to-low transition as the
signal to restart the external clock (SCLK). To read the
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
). Forcing CS high in the middle of a
CSW
conversion immediately aborts the conversion and
places the MAX1168 in shutdown.
Internal Clock 8-Bit-Wide Data-Transfer and
Scan Mode (MAX1167 and MAX1168)
Force DSPR high and DSEL low (MAX1168) for the SPI/
QSPI/MICROWIRE interface mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to clock
in data (Figure 12). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the ris-
ing edge of SCLK. The command/configuration/control
18 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
1
8
9
16
17
24
32
• • •
• • •
SCLK
2
13
32
INTERNAL
CLK
• • •
• • •
DIN
DOUT
EOC
DATA
X X X X X X X X
MSB
LSB
X
ADC
STATE
CONFIGURATION
t
ACQ
t
POWER-DOWN
CONV
,
X = DON T CARE
DSPR = DSEL = DV
DD
Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
CS
1
8
9
40
• • •
SCLK
26
30
2
6
24
48
INTERNAL
CLK
• • •
• • •
MSB
LSB
1
DIN
DOUT
EOC
MSB
LSB
• • •
X
ADC
STATE
CONFIGURATION
,
t
t
ACQ
t
t
POWER-DOWN
ACQ
CONV
CONV
X = DON T CARE
DSPR = DV , DSEL = GND (MAX1168 ONLY)
DD
Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing
entire conversion result, 16 SCLK cycles are needed.
Extra clock pulses, occurring after the conversion result
has been clocked out and prior to the rising edge of
CS, cause the conversion result to be shifted out again.
The MAX1167/MAX1168 internal clock 8-bit-wide data-
transfer mode requires 24 external clock cycles and 25
internal clock cycles for completion.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1167/MAX1168 in the internal clock mode. Enable
scanning by setting bits 4 and 3 in the command/con-
figuration/control register (see Tables 3 and 4). In scan
mode, conversion results are stored in memory until the
completion of the last conversion in the sequence.
Upon completion of the last conversion in the
sequence, EOC transitions from high to low to indicate
the end of the conversion and shuts down the internal
oscillator. Use the EOC high-to-low transition as the sig-
nal to restart the external clock (SCLK). DOUT provides
the conversion results in the same order as the channel
conversion process. The MSB of the first conversion is
available at DOUT on the falling edge of EOC (Figure 14).
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
). Forcing CS high in the middle of a
CSW
conversion immediately aborts the conversion and
places the MAX1167/MAX1168 in shutdown.
______________________________________________________________________________________ 19
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
48
17
1
8
9
16
• • •
• • •
• • •
SCLK
32
34
45
64
2
13
INTERNAL
CLK
• • •
• • •
• • •
• • •
DATA
X X X X X X X X
DIN
LSB
MSB
• • •
X
DOUT
EOC
ADC
STATE
t
t
t
t
POWER-DOWN
ACQ
ACQ
,
CONV
CONV
X = DON T CARE
Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1168 Only)
t
CSW
CS
...
...
t
DF
t
FSS
DSPR
t
FSH
t
CSS
t
CSH
t
t
CH
CL
SCLK
DIN
...
...
t
t
DS
CP
t
DH
t
t
TR
DO
t
DV
...
DOUT
Figure 16. Detailed DSP-Interface Timing (MAX1168 Only)
Internal Clock 16-Bit-Wide Data-Transfer and Scan
Mode (MAX1168 Only)
conversion on the rising edge of the 3rd SCLK cycle.
The internal oscillator activates 125ns after the rising
edge of the 16th SCLK cycle. Turn off the external clock
while the internal clock is on. Turning off SCLK ensures
lowest noise performance during acquisition.
Acquisition begins on the 2nd rising edge of the inter-
nal clock and ends on the falling edge of the 18th inter-
nal clock cycle. Each bit of the conversion result shifts
into memory as it becomes available. The conversion
result is available (MSB first) at DOUT on the falling
edge of EOC. The internal oscillator and analog circuitry
Force DSPR high and DSEL low for the SPI/QSPI/
MICROWIRE interface mode. The falling edge of CS
wakes the analog circuitry and allows SCLK to clock in
data (Figure 13). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the
rising edge of SCLK. The command/configuration/con-
trol register begins reading DIN on the first SCLK rising
edge and ends on the rising edge of the 8th SCLK
cycle. The MAX1168 selects the proper channel for
20 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
DSPR
16
24
1
8
SCLK
DIN
MSB
LSB
0
MSB
LSB
DOUT
DSPX
ADC
STATE
IDLE
t
t
ACQ
CONV
Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
CS
DSPR
1
16
24
32
8
SCLK
DIN
MSB
LSB
0
X
X
X
X
X
X
X
X
LSB
MSB
DOUT
DSPX
ADC
STATE
t
t
IDLE
ACQ
CONV
,
X = DON T CARE
Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
are shut down on the EOC high-to-low transition. Use
the EOC high-to-low transition as the signal to restart
the external clock (SCLK). To read the entire conver-
sion result, 16 SCLK cycles are needed. Extra clock
pulses, occurring after the conversion result has been
clocked out and prior to the rising edge of CS, cause
the conversion result to be shifted out again. The
MAX1168 internal-clock 16-bit-wide data-transfer mode
requires 32 external clock cycles and 32 internal clock
cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
). Forcing CS high in the middle of a
CSW
conversion immediately aborts the conversion and
places the MAX1168 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1168 in internal clock mode. Enable scanning by
______________________________________________________________________________________ 21
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
rates less than 125kHz can reduce accuracy due to
leakage of the sampling capacitor. The input data
OUTPUT CODE
1111...111
latches on the falling edge of SCLK. The command/
configuration/control register starts reading data in on
the falling edge of the first SCLK cycle immediately fol-
lowing the falling edge of the frame sync pulse and
ends on the falling edge of the 8th SCLK cycle. The
MAX1168 selects the proper channel for conversion on
the falling edge of the 3rd clock cycle and begins
acquisition. Acquisition continues until the rising edge
of the 7th clock cycle. The MAX1168 samples the input
on the rising edge of the 7th clock cycle. On the rising
edge of the 8th clock cycle, the MAX1168 outputs a
frame sync pulse at DSPX. The frame sync pulse alerts
the DSP that the conversion results are about to be out-
put at DOUT (MSB first) starting on the rising edge of
the 9th clock pulse. To read the entire conversion
result, 16 SCLK cycles are needed. Extra clock pulses,
occurring after the conversion result has been clocked
out and prior to the next rising edge of DSPR, cause
zeros to be clocked out of DOUT. The MAX1168 exter-
nal clock, DSP 8-bit-wide data-transfer mode requires
24 clock cycles to complete.
FULL-SCALE
TRANSITION
1111...110
1111...101
FS = V
REF
V
REF
1 LSB =
65,536
0000...011
0000...010
0000...001
0000...000
0
1
2
3
FS
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
Figure 19. Unipolar Transfer Function, Full Scale (FS) = V
Zero Scale (ZS) = GND
,
REF
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a con-
version immediately aborts the current conversion and
begins a new one. A rising edge on CS in the middle of
a conversion aborts the current conversion and places
the MAX1168 in shutdown.
setting bits 4 and 3 in the command/configuration/con-
trol register (see Tables 3 and 4). In scan mode, conver-
sion results are stored in memory until the completion of
the last conversion in the sequence. Upon completion of
the last conversion in the sequence, EOC transitions
from high to low to indicate the end of the conversion
and shuts down the internal oscillator. Use the EOC
high-to-low transition as the signal to restart the external
clock (SCLK). DOUT provides the conversion results in
the same order as the channel conversion process. The
MSB of the first conversion is available at DOUT on the
falling edge of EOC. Figure 15 shows the timing
diagram for 16-bit-wide data transfer in scan mode.
DSP 16-Bit-Wide Data-Transfer Mode (External
Clock Mode, MAX1168 Only)
Figure 16 shows the DSP-interface timing diagram.
Logic low at DSPR on the falling edge of CS enables
DSP interface mode. After the MAX1168 enters DSP
mode, CS can remain low for the duration of the con-
version process and each subsequent conversion. The
acquisition time is extended an extra eight SCLK cycles
in the 16-bit-wide data-transfer mode. Drive DSEL high
to select the 16-bit-wide data-transfer mode. A sync
pulse from the DSP at DSPR wakes the analog circuitry
and allows SCLK to clock in data (Figure 18). The
frame sync pulse also alerts the MAX1168 that incom-
ing data is about to be sent to DIN. Ensure the duty
cycle on SCLK is between 45% and 55% when operat-
ing at 4.8MHz (the maximum clock frequency). For
lower clock frequencies, ensure the minimum high and
low times are at least 93ns. External-clock-mode con-
versions with SCLK rates less than 125kHz can reduce
accuracy due to leakage of the sampling capacitor.
DSP 8-Bit-Wide Data-Transfer Mode (External Clock
Mode, MAX1168 Only)
Figure 16 shows the DSP-interface timing diagram.
Logic low at DSPR on the falling edge of CS enables
DSP interface mode. After the MAX1168 enters DSP
mode, CS can remain low for the duration of the conver-
sion process and each subsequent conversion. Drive
DSEL low to select the 8-bit data-transfer mode. A sync
pulse from the DSP at DSPR wakes the analog circuitry
and allows SCLK to clock in data (Figure 17). The frame
sync pulse alerts the MAX1168 that incoming data is
about to be sent to DIN. Ensure the duty cycle on SCLK
is between 45% and 55% when operating at 4.8MHz
(the maximum clock frequency). For lower clock fre-
quencies, ensure the minimum high and low times are at
least 93ns. External clock mode conversions with SCLK
22 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
I/O
SCK
CS
I/O
SK
SI
CS
SCLK
DOUT
SCLK
DOUT
MISO
V
MICROWIRE
SPI
DD
MAX1167
MAX1168
MAX1167
MAX1168
SS
Figure 20a. SPI Connections
Figure 20b. MICROWIRE Connections
1ST BYTE READ
4
2ND BYTE READ
12
1
6
8
16
SCLK
CS
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
24
HIGH-Z
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Figure 20c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
The input data latches on the falling edge of SCLK. The
command/configuration/control register starts reading
data in on the falling edge of the first SCLK cycle immedi-
ately following the falling edge of the frame sync pulse
and ends on the falling edge of the 16th SCLK cycle. The
MAX1168 selects the proper channel for conversion on
the falling edge of the 3rd clock cycle and begins acqui-
sition. Acquisition continues until the rising edge of the
15th clock cycle. The MAX1168 samples the input on the
rising edge of the 15th clock cycle. On the rising edge of
the 16th clock cycle, the MAX1168 outputs a frame sync
pulse at DSPX. The frame sync pulse alerts the DSP that
the conversion results are about to be output at DOUT
(MSB first) starting on the rising edge of the 17th clock
pulse. To read the entire conversion result, 16 SCLK
cycles are needed. Extra clock pulses, occurring after the
conversion result has been clocked out and prior to the
next rising edge of DSPR, cause zeros to be clocked out
of DOUT. The MAX1168 external clock, DSP 16-bit-wide
data-transfer mode requires 32 clock cycles to complete.
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a con-
version immediately aborts the current conversion and
begins a new one. A rising edge on CS in the middle of
a conversion aborts the current conversion and places
the MAX1168 in shutdown.
Output Coding and Transfer Function
The data output from the MAX1167/MAX1168 is straight
binary. Figure 19 shows the nominal transfer function.
Code transitions occur halfway between successive
integer LSB values (V
= +4.096V, and 1 LSB =
REF
+62.5µV or 4.096V / 65,536V).
______________________________________________________________________________________ 23
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Tmble 7. ꢁetmiled LLPCOD Register Contents
CODTROꢀ BIT
LETTIDGL
LYDCHRODOUL LERIAꢀ-PORT CODTROꢀ REGILTER ꢂLLPCODx
WCOL
BIT7
BIT6
X
X
Write Collision Detection Bit
SSPOV
Receive Overflow Detection Bit
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial
port pins.
SSPEN
BIT5
1
CKP
SSPM3
BIT4
BIT3
BIT2
BIT1
BIT0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
SSPM2
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and
selects f
= f
OSC
/ 16.
SSPM1
CLK
SSPM0
X = Don’t care.
When using the internal clock mode, the internal oscilla-
tor controls the acquisition and conversion processes,
while the external oscillator shifts data in and out of the
MAX1167/MAX1168. Turn off the external clock (SCLK)
when the internal clock is on to realize lowest noise per-
formance. The internal clock remains off in external
clock mode.
Applications Information
Internal Reference
The internal bandgap reference provides a buffered
+4.096V. Bypass REFCAP with a 0.1µF capacitor to
AGND and REF with a 1µF capacitor to AGND. For best
results, use low-ESR, X5R/X7R ceramic capacitors.
Allow 5ms for the reference and buffer to wake up from
full power-down (see Table 5).
Input Buffer
Most applications require an input-buffer amplifier to
achieve 16-bit accuracy. The input amplifier must have
a slew rate of at least 2V/µs and a unity-gain bandwidth
of at least 10MHz to complete the required output-volt-
age change before the end of the acquisition time.
External Reference
The MAX1167/MAX1168 accept an external reference
with a voltage range between +3.8V and AV . Connect
DD
the external reference directly to REF. Bypass REF to
AGND with a 10µF capacitor. When not using a low-ESR
bypass capacitor, use a 0.1µF ceramic capacitor in paral-
lel with the 10µF capacitor. Noise on the reference
degrades conversion accuracy.
At the beginning of the acquisition, the internal sam-
pling capacitor array connects to AIN_ (the amplifier
input), causing some disturbance on the output of the
buffer. Ensure the sampled voltage has settled before
the end of the acquisition time.
The input impedance at REF is 37kΩ for DC currents.
During a conversion, the external reference at REF
must deliver 118µA of DC load current and have an out-
put impedance of 10Ω or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
CS
SCK
CS
SCLK
DOUT
equivalent input noise (40µV
) of the MAX1167/
RMS
MISO
QSPI
V
DD
MAX1168 when choosing a reference.
MAX1167
MAX1168
Internal/External Oscillator
Select either an external (0.1MHz to 4.8MHz) or the
internal 4MHz (typ) clock to perform conversions
(Table 6). The external clock shifts data in and out of
the MAX1167/MAX1168 in either clock mode.
SS
Figure 21a. QSPI Connections
24 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Tmble 8. ꢁetmiled LLPLTAT Register Contents
CODTROꢀ BIT
LETTIDGL
LYDCHRODOUL LERIAꢀ-PORT LTATUL REGILTER ꢂLLPLTATx
SPI Data-Input Sample Phase. Input data is sampled at the middle of
the data output time.
SMP
BIT7
BIT6
0
1
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the
serial clock.
CKE
D/A
P
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X
X
X
X
X
X
Data Address Bit
Stop Bit
S
Start Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer-Full Status Bit
X = Don’t care.
24
1
4
6
8
12
16
20
SCLK
CS
HIGH-Z
D15 D14 D13 D12 D11 D10 D9
MSB
D8
D7
D6
D5 D4
D3
D2
D1
D0
DOUT*
LSB
SAMPLING INSTANT
*WHEN CS IS HIGH, DOUT = HIGH-Z
Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = 0)
Digital Noise
Digital noise can couple to AIN_ and REF. The conversion
clock (SCLK) and other digital signals active during input
acquisition contribute noise to the conversion result.
Noise signals, synchronous with the sampling interval,
result in an effective input offset. Asynchronous signals
produce random noise on the input, whose high-frequen-
cy components can be aliased into the frequency band
of interest. Minimize noise by presenting a low imped-
ance (at the frequencies contained in the noise signal) at
the inputs. This requires bypassing AIN_ to AGND, or
buffering the input with an amplifier that has a small-sig-
nal bandwidth of several megahertz (doing both is prefer-
able). AIN has a typical bandwidth of 4MHz.
reduce linearity errors due to finite amplifier gain, use
amplifier circuits with sufficient loop gain at the fre-
quencies of interest.
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1167/MAX1168s’ offset ( 10mV
max for +5V supply), or whose offset can be trimmed
while maintaining stability over the required temperature
range.
V
V
DD
DD
SCLK
DOUT
CS
SCK
SDI
I/O
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the total har-
monic distortion of the MAX1167/MAX1168 at the fre-
quencies of interest (THD = -100dB at 1kHz). If the
chosen amplifier has insufficient common-mode rejec-
tion, which results in degraded THD performance, use
the inverting configuration (positive input grounded) to
eliminate errors from this source. Low-temperature-
coefficient, gain-setting resistors reduce linearity errors
caused by resistance changes due to self-heating. To
PIC16/17
MAX1167
MAX1168
GND
Figure 22a. SPI-Interface Connection for a PIC16/PIC17
______________________________________________________________________________________ 25
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
1ST BYTE READ
4
2ND BYTE READ
12
1
6
8
16
SCLK
CS
0
0
0
0
0
0
0
0
D14
D13
D12
D11
D10
D9
D8
D15
DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
24
HIGH-Z
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and
CPHA = 0, the MAX1167/MAX1168 support a maximum
SCLK
EXTERNAL
CLOCK
f
of 4.8MHz. Figure 21a shows the MAX1167/
MAX1168 connected to a QSPI master, and Figure 21b
shows the associated interface timing.
SCLK
TFS
SCLK
DSPR
DSPX
DIN
PIC16 with SSP Module and PIC17
Interface
The MAX1167/MAX1168 are compatible with a
PIC16/PIC17 controller (µC), using the synchronous seri-
al-port (SSP) module.
RFS
DSP
MAX1168
DT
DR
DOUT
CS
FL1
To establish SPI communication, connect the controller
as shown in Figure 22a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 7 and 8.
Figure 23. DSP Interface Connection
Serial Interfaces
SPI and MICROWIRE Interfaces
When using the SPI (Figure 20a) or MICROWIRE (Figure
20b) interfaces, set CPOL = 0 and CPHA = 0. Drive CS
low to power on the MAX1167/MAX1168 before starting a
conversion (Figure 20c). Three consecutive 8-bit-wide
readings are necessary to obtain the entire 16-bit result
from the ADC. DOUT data transitions on the serial clock’s
falling edge. The first 8-bit-wide data stream contains all
leading zeros. The 2nd 8-bit-wide data stream contains
the MSB through D6. The 3rd 8-bit-wide data stream con-
tains D5 through D0 followed by S1 and S0.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data to
be synchronously transmitted and received simultane-
ously. Three consecutive 8-bit-wide readings (Figure
22b) are necessary to obtain the entire 16-bit result from
the ADC. DOUT data transitions on the serial clock’s
falling edge and is clocked into the µC on SCLK’s rising
edge. The first 8-bit-wide data stream contains all zeros.
The 2nd 8-bit-wide data stream contains the MSB
through D6. The 3rd 8-bit-wide data stream contains bits
D5 through D0 followed by S1 and S0.
26 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
EFFECTIVE NUMBER OF BITS (ENOB)
16
AIN_
+5V
CS
SCLK
DOUT
CS
AIN_
REF
14
12
SCLK
DOUT
1µF
AV
DD
MAX1167
MAX1168
10
8
0.1µF
10Ω
6
AGND
AGND
DGND
DV
DD
4
0.1µF
2
f
= 200ksps
SAMPLE
0
0.1
1
10
100
GND
FREQUENCY (kHz)
Figure 25. Powering AV
and DV
from a Single Supply
Figure 24. Effective Bits vs. Frequency
DD
DD
Aperture Definitions
DSP Interface
Aperture jitter (t ) is the sample-to-sample variation in
The DSP mode of the MAX1168 only operates in exter-
nal clock mode. Figure 23 shows a typical DSP interface
connection to the MAX1168. Use the same oscillator as
the DSP to provide the clock signal for the MAX1168.
The DSP provides the falling edge at CS to wake the
MAX1168. The MAX1168 detects the state of DSPR on
the falling edge of CS (Figure 17). Logic low at DSPR
places the MAX1168 in DSP mode. After the MAX1168
enters DSP mode, CS can be left low. A frame sync
pulse from the DSP to DSPR initiates a conversion. The
MAX1168 sends a frame sync pulse from DSPX to the
DSP signaling that the MSB is available at DOUT. Send
another frame sync pulse from the DSP to DSPR to
begin the next conversion. The MAX1168 does not oper-
ate in scan mode when using DSP mode.
AJ
the time between samples. Aperture delay (t ) is the
AD
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N bits):
SNR = (6.02 ✕ N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1167/MAX1168
are measured using the end-point method.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
SINAD (dB) = 20 ✕ log [Signal
/ (Noise +
RMS
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1 LSB. A
DNL error specification of 1 LSB guarantees no miss-
ing codes and a monotonic transfer function.
Distortion)
]
RMS
______________________________________________________________________________________ 27
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
Supplies, Layout, Grounding, and
Bypassing
Use printed circuit (PC) boards with separate analog
and digital ground planes. Do not use wire-wrap
boards. Connect the two ground planes together at the
MAX1167/MAX1168 AGND terminal. Isolate the digital
supply from the analog with a low-value resistor (10Ω)
or ferrite bead when the analog and digital supplies
come from the same source (Figure 25).
ENOB = (SINAD - 1.76) / 6.02
Figure 24 shows the ENOB as a function of the
MAX1167/MAX1168s’ input frequency.
Constraints on sequencing the power supplies and
inputs are as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
• Apply AGND before DGND.
• Apply AIN_ and REF after AV
and AGND are
DD
present.
2
2
2
2
• DV
is independent of the supply sequencing.
V
+V +V +V
3 4 5
DD
(
)
2
THD = 20 × log
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ω creates an error
voltage of about 250µV and a 4 LSB error with a +4.096V
full-scale system.
V
1
where V is the fundamental amplitude and V through
V are the 2nd- through 5th-order harmonics.
1
2
5
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest fre-
quency component.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and dig-
ital lines (especially the SCLK and DOUT) parallel to one
another. If one must cross another, do so at right angles.
The ADC’s high-speed comparator is sensitive to high-
frequency noise on the AV
power supply. Bypass an
DD
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.
28 ______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Ordering Information (continued)
Chip Information
TRANSISTOR COUNT: 20,760
PID-
IDꢀ
PART
TEMP RADGE
PACKAGE ꢂꢀLBx
PROCESS: BiCMOS
MAX1168ACEG
MAX1168BCEG
MAX1168CCEG
MAX1168AEEG*
MAX1168BEEG*
MAX1168CEEG*
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
24 QSOP
24 QSOP
24 QSOP
24 QSOP
24 QSOP
24 QSOP
1.5
2
3
1.5
2
3
*Future product—contact factory for availability.
Pin Configurations
TOP VIEW
DOUT
1
DSPR
DSEL
DOUT
SCLK
DIN
1
2
3
4
5
6
7
8
9
24 N.C.
16 DV
DD
23 DSPX
SCLK
DIN
2
3
4
5
6
7
8
15 DGND
14 CS
22 DV
DD
21 DGND
20 CS
EOC
AIN0
AIN1
AIN2
AIN3
MAX1167
13 AV
DD
MAX1168
12 AGND
11 AGND
10 REFCAP
EOC
19 AV
DD
AIN0
AIN1
AIN2
18 AGND
17 AGND
16 REFCAP
15 REF
9
REF
QLOP
AIN3 10
AIN4 11
AIN5 12
14 AIN7
13 AIN6
QLOP
______________________________________________________________________________________ 29
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.(mai(-ic.co(/pmckmges.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
E
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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