MAX1177BEUP-T [MAXIM]
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Parallel, Word Access, BICMOS, PDSO20, 4.40 MM, MO-153AC, TSSOP-20;
| 型号： | MAX1177BEUP-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Parallel, Word Access, BICMOS, PDSO20, 4.40 MM, MO-153AC, TSSOP-20 信息通信管理 光电二极管 转换器 |
| 文件： | 总13页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2597; Rev 0; 8/03
16-Bit, 135ksps, Single-Supply ADC
with 0 to 10V Input Range
General Description
Features
The MAX1177 is a 16-bit, low-power, successive-
approximation analog-to-digital converter (ADC) featur-
ing automatic power-down, a factory-trimmed internal
clock, and a byte-wide parallel interface. The device
operates from a single +4.75V to +5.25V analog supply
and features a separate digital supply input for direct
interface with +2.7V to +5.25V digital logic.
ꢀ Byte-Wide Parallel Interface
ꢀ Analog Input Voltage Range: 0 to +10V
ꢀ Single +4.75V to +5.25V Analog Supply Voltage
ꢀ Interfaces with +2.7V to +5.25V Digital Logic
ꢀ ±± LSB IꢀL
ꢀ ±1 LSB DꢀL
The MAX1177 accepts an analog input voltage range
from 0 to +10V. It consumes no more than 26.5mW at a
sampling rate of 135ksps when using an external refer-
ence, and 31mW when using the internal +4.096V refer-
ence. AutoShutdown™ reduces supply current to
0.4mA at 10ksps.
ꢀ Low Supply Current (max)
2.9mA (External Reference)
±.8mA (Internal Reference)
5µA AutoShutdown Mode
ꢀ Small Footprint
The MAX1177 is ideal for high-performance, battery-
powered, data-acquisition applications. Excellent AC
performance (THD = -100dB) and DC accuracy ( 3
LSB INL) make this device ideal for industrial process
control, instrumentation, and medical applications.
ꢀ 20-Pin TSSOP Package
Ordering Information
The MAX1177 is available in a 20-pin TSSOP package
and is fully specified over the -40°C to +85°C extended
temperature range and the 0°C to +70°C commercial
temperature range.
PART
TEMP RAꢀGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIꢀ-PACKAGE
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
MAX1177ACUP
MAX1177BCUP
MAX1177CCUP
MAX1177AEUP
MAX1177BEUP
MAX1177CEUP
Applications
Typical Operating Circuit
Temperature Sensing and Monitoring
Industrial Process Control
I/O Modules
+5V ANALOG +5V DIGITAL
0.1µF
0.1µF
Data-Acquisition Systems
Precision Instrumentation
AV
DD
DV
µP DATA
BUS
DD
D0–D7
OR
ANALOG INPUT
AIN
D8–D15
MAX1177
EOC
R/C
CS
REF
REFADJ
HBEN
HIGH
BYTE
0.1µF
10µF
AGND DGND
Pin Configuration and Functional Diagram appear at end of
data sheet.
LOW
BYTE
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
16-Bit, 135ksps, Single-Supply ADC
with to 10V Input Range
Continuous Power Dissipation (T = +70°C)
TSSOP (derate 10.9mW/°C above +70°C) ..................879mW
A
AGND to DGND.....................................................-0.3V to +0.3V
AIN to AGND .....................................................-16.5V to +16.5V
Operating Temperature Ranges
MAX1177_CUP ...................................................0°C to +70°C
MAX1177_EUP ................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
REF, REFADJ to AGND............................-0.3V to (AV
+ 0.3V)
DD
CS, R/C, HBEN to DGND .........................................-0.3V to +6V
D_, EOC to DGND ...................................-0.3V to (DV + 0.3V)
DD
Maximum Continuous Current into Any Pin ........................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= +5V 5ꢀ, external reꢁerence = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV , T = T
to T
,
DD
DD
REF
REFADJ
REFADJ
DD
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
DC ACCURACY
SYMBOL
RES
COꢀDITIOꢀS
MIꢀ
TYP
MAX
UꢀITS
Bits
Resolution
16
-1
MAX1177A
+1
+1.5
+2
No missing codes
over temperature
Diꢁꢁerential Nonlinearity
DNL
LSB
MAX1177B
MAX1177C
-1.0
-1
MAX1177A
MAX1177B
MAX1177C
-3
+3
Integral Nonlinearity
Transition Noise
INL
LSB
-3
+3
-4
+4
RMS noise, external reꢁerence
Internal reꢁerence
0.6
0.75
0
LSB
RMS
Oꢁꢁset Error
Gain Error
Oꢁꢁset Driꢁt
Gain Driꢁt
-10
+10
0.2
mV
0
ꢀFSR
µV/°C
16
1
ppm/°C
AC ACCURACY (ꢁ = 1kHz, V
= ꢁull range, 135ksps)
IN
AIN
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
AꢀALOG IꢀPUT
SINAD
SNR
85
86
90
91
dB
dB
dB
dB
THD
-100
103
-92
SFDR
92
Input Range
V
0
10
V
AIN
Normal operation
Shutdown mode
5.3
5.3
-0.1
6.9
10
9.2
Input Resistance
R
kΩ
AIN
Input Current
I
0 ≤ V
≤ +10V
+2.0
mA
pF
AIN
AIN
Input Capacitance
C
IN
2
_______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADC
with 0 to 10V Input Range
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +5V 5ꢀ, external reꢁerence = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV , T = T
to T
,
DD
DD
REF
REFADJ
REFADJ
DD
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
IꢀTERꢀAL REFEREꢀCE
REF Output Voltage
SYMBOL
COꢀDITIOꢀS
MIꢀ
TYP
MAX
UꢀITS
V
4.056
4.096
35
4.136
V
REF
REF Output Tempco
ppm/°C
mA
REF Short-Circuit Current
EXTERꢀAL REFEREꢀCE
I
10
REF-SC
REF and REFADJ Input-Voltage
Range
3.8
4.2
V
V
AV
-
AV
-
DD
DD
REFADJ Buꢁꢁer-Disable Threshold
REF Input Current
0.4
0.1
Normal mode, ꢁ
= 135ksps
60
0.1
16
100
10
SAMPLE
I
µA
µA
REF
Shutdown mode (Note 1)
REFADJ = AV
REFADJ Input Current
I
REFADJ
DD
DIGITAL IꢀPUTS/OUTPUTS
I
= 0.5mA, DV
= +5.25V
= +2.7V to +5.25V, DV
-
DD
SOURCE
DD
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
V
V
V
V
V
OH
AV
0.4
DD
I
= 1.6mA, DV
= +5.25V
= +2.7V to +5.25V,
DD
SINK
V
0.4
OL
AV
DD
0.7 ×
DV
V
IH
DD
0.3 ×
V
IL
DV
DD
Input Leakage Current
Input Hysteresis
Digital input = DV
or 0V
-1
+1
µA
V
DD
V
0.2
15
HYST
Input Capacitance
C
pF
µA
pF
IN
Tri-State Output Leakage
Tri-State Output Capacitance
POWER SUPPLIES
Analog Supply Voltage
Digital Supply Voltage
I
10
OZ
C
15
OZ
AV
DV
4.75
2.70
5.25
5.25
2.9
V
V
DD
DD
External reꢁerence, 135ksps
Internal reꢁerence, 135ksps
Analog Supply Current
I
mA
µA
AVDD
3.8
Shutdown mode (Note 1), digital input =
DV or 0V
DD
0.5
3.7
5
Shutdown Supply Current
I
I
SHDN
DVDD
Standby mode
mA
mA
Digital Supply Current
Power-Supply Rejection
0.75
AV
= DV
= 4.75V to 5.25V
DD
3.5
LSB
DD
_______________________________________________________________________________________
±
16-Bit, 135ksps, Single-Supply ADC
with to 10V Input Range
TIMIꢀG CHARACTERISTICS (Figures 1 and 2)
(AV
= +4.75V to +5.25V, DV
= +2.7V to AV , external reꢁerence = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV
,
DD
DD
DD
REF
REFADJ
REFADJ
DD
C
LOAD
= 20pF, T = T
to T
.)
A
MIN
MAX
PARAMETER
SYMBOL
COꢀDITIOꢀS
MIꢀ
TYP
MAX
UꢀITS
ksps
µs
Maximum Sampling Rate
Acquisition Time
ꢁ
135
SAMPLE-MAX
t
2
ACQ
Conversion Time
t
4.7
µs
CONV
CS Pulse-Width High
t
(Note 2)
40
40
60
0
ns
CSH
DV
DV
= 4.75V to 5.25V
DD
DD
CS Pulse-Width Low (Note 2)
R/C to CS Fall Setup Time
R/C to CS Fall Hold Time
t
ns
ns
ns
CSL
= 2.7V to 5.25V
t
DS
DH
DV
DV
DV
DV
= 4.75V to 5.25V
= 2.7V to 5.25V
= 4.75V to 5.25V
= 2.7V to 5.25V
40
60
DD
DD
DD
DD
t
40
80
CS to Output Data Valid
EOC Fall to CS Fall
t
ns
ns
ns
DO
t
0
DV
DV
DV
DV
DV
DV
DV
= 4.75V to 5.25V
= 2.7V to 5.25V
= 4.75V to 5.25V
= 2.7V to 5.25V
= 4.75V to 5.25V
= 2.7V to 5.25V
40
80
40
80
40
80
DD
DD
DD
DD
DD
DD
CS Rise to EOC Rise
t
EOC
Bus Relinquish Time
t
ns
ns
BR
HBEN Transition to Output Data
Valid
t
1
DO
ꢀote 1: Maximum speciꢁication is limited by automated test equipment.
ꢀote 2: To ensure best perꢁormance, ꢁinish reading the data and wait t beꢁore starting a new acquisition.
BR
Typical Operating Characteristics
(Typical Operating Circuit, AV
= DV
= +5V, external reꢁerence = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV
,
DD
DD
REF
REFADJ
REFADJ
DD
C
LOAD
= 20pF. Typical values are at T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT (AV + DV
DD
)
DD
DNL vs. CODE
INL vs. CODE
vs. TEMPERATURE
MAX1177 toc02
2.5
3
2
2.25
2.20
2.15
2.10
2.05
2.00
1.95
5.25V
2.0
1.5
1.0
1
0.5
5.0V
0
0
-0.5
-1.0
-1.5
-2.0
-2.5
-1
-2
-3
f
= 135ksps
SAMPLE
SHUTDOWN MODE
4.75V
BETWEEN CONVERSIONS
0
10,000 20,000 30,000 40,000 50,000 60,000
CODE
80
8192
24,576
40,960
57,344
-40
-20
0
20
40
60
CODE
TEMPERATURE (°C)
4
_______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADC
with 0 to 10V Input Range
Typical Operating Characteristics (continued)
(Typical Operating Circuit, AV
= DV
= +5V, external reꢁerence = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV
,
DD
DD
REF
REFADJ
REFADJ
DD
C
LOAD
= 20pF. Typical values are at T = +25°C, unless otherwise noted.)
A
SHUTDOWN CURRENT (AV + DV
DD
)
DD
SUPPLY CURRENT (AV + DV
DD
)
DD
OFFSET ERROR vs. TEMPERATURE
vs. TEMPERATURE
vs. SAMPLE RATE
10
1
10
8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
NO CONVERSIONS
6
4
STANDBY MODE
0.1
2
0
SHUTDOWN MODE
-2
-4
-6
-8
-10
0.01
0.001
0.0001
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
0.01
0.1
1
10
100
1000
TEMPERATURE (°C)
TEMPERATURE (°C)
SAMPLE RATE (ksps)
INTERNAL REFERENCE
vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
FFT AT 1kHz
4.136
4.126
4.116
4.106
4.096
4.086
4.076
4.066
4.056
0.20
0.15
0.10
0.05
0
0
-20
f
= 131ksps
SAMPLE
-40
-60
-80
-100
-120
-140
-160
-180
-0.05
-0.10
-0.15
-0.20
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
0
10
20
30
40
50
60
TEMPERATURE (°C)
TEMPERATURE (°C)
FREQUENCY (kHz)
SINAD vs. FREQUENCY
SFDR vs. FREQUENCY
THD vs. FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
= 131ksps
f
= 131ksps
SAMPLE
f
= 131ksps
SAMPLE
SAMPLE
1
10
FREQUENCY (kHz)
100
1
10
FREQUENCY (kHz)
100
1
10
100
FREQUENCY (kHz)
_______________________________________________________________________________________
5
16-Bit, 135ksps, Single-Supply ADC
with to 10V Input Range
Pin Description
PIꢀ
1
ꢀAME
D4/D12
D5/D13
D6/D14
D7/D15
FUꢀCTIOꢀ
Tri-State Digital-Data Output
2
Tri-State Digital-Data Output
3
Tri-State Digital-Data Output
4
Tri-State Digital-Data Output. D15 is the MSB.
Read/Convert Input. Power up and put the device in acquisition mode by holding R/C low during the
ꢁirst ꢁalling edge oꢁ CS. During the second ꢁalling edge oꢁ CS, the level on R/C determines whether the
reꢁerence and reꢁerence buꢁꢁer power down or remain on aꢁter conversion. Set R/C high during the
second ꢁalling edge oꢁ CS to power down the reꢁerence and buꢁꢁer, or set R/C low to leave the
reꢁerence and buꢁꢁer powered up. Set R/C high during the third ꢁalling edge oꢁ CS to put valid data on
the bus.
5
R/C
6
7
EOC
End oꢁ Conversion. EOC drives low when conversion is complete.
Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
Analog Ground. Primary analog ground (star ground).
Analog Input
AV
DD
8
AGND
AIN
9
10
AGND
Analog Ground. Connect pin 10 to pin 8.
Reꢁerence Buꢁꢁer Output. Bypass REFADJ with a 0.1µF capacitor to AGND ꢁor internal reꢁerence
11
12
REFADJ
REF
mode. Connect REFADJ to AV
to select external reꢁerence mode.
DD
Reꢁerence Input/Output. Bypass REF with a 10µF capacitor to AGND ꢁor internal reꢁerence mode.
External reꢁerence input when in external reꢁerence mode.
High-Byte Enable Input. Used to multiplex the 16-bit conversion result.
1: MSB available on the data bus.
0: LSB available on the data bus.
13
14
HBEN
Convert Start. The ꢁirst ꢁalling edge oꢁ CS powers up the device and enables acquire mode when R/C
is low. The second ꢁalling edge oꢁ CS starts the conversion. The third ꢁalling edge oꢁ CS loads the
result onto the bus when R/C is high.
CS
15
16
17
18
19
20
DGND
Digital Ground
DV
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
Tri-State Digital-Data Output. D0 is the LSB.
Tri-State Digital-Data Output
DD
D0/D8
D1/D9
D2/D10
D3/D11
Tri-State Digital-Data Output
Tri-State Digital-Data Output
6
_______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADC
with 0 to 10V Input Range
Analog Input
Detailed Description
Converter Operation
The MAX1177 uses a successive-approximation (SAR)
conversion technique with an inherent track-and-hold
(T/H) stage to convert an analog input into a 16-bit digital
output. Parallel outputs provide a high-speed interꢁace to
microprocessors (µPs). The Functional Diagram shows a
simpliꢁied internal architecture oꢁ the MAX1177. Figure 3
shows a typical operating circuit ꢁor the MAX1177.
Input Scaler
The MAX1177 has an input scaler, which allows conver-
sion oꢁ input voltages ranging ꢁrom 0 to 10V, while oper-
ating ꢁrom a single +5V analog supply. The input scaler
attenuates and shiꢁts the analog input to match the input
range oꢁ the internal digital-to-analog converter (DAC).
Figure 4 shows the equivalent input circuit oꢁ the
MAX1177. This circuit limits the current going into AIN to
less than 2mA.
Track and Hold (T/H)
In track mode, the internal hold capacitor acquires the
analog signal (Figure 4). In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
During the acquisition, the analog input (AIN) charges
DV
DD
1mA
DO–D15
DO–D15
capacitor C
. The acquisition ends on the second
HOLD
ꢁalling edge oꢁ CS. At this instant, the T/H switches
open. The retained charge on C represents a sam-
C
LOAD
= 20pF
C
= 20pF
LOAD
1mA
HOLD
ple oꢁ the input. In hold mode, the capacitive DAC
adjusts during the remainder oꢁ the conversion time to
restore node T/H OUT to zero within the limits oꢁ 16-bit
resolution. Force CS low to put valid data on the bus
aꢁter conversion is complete.
DGND
DGND
a) HIGH-Z TO V
,
OH
b) HIGH-Z TO V ,
OL
V
V
TO V , AND
TO HIGH-Z
OL
OH
OH
V
OH
V
OL
TO V , AND
OL
TO HIGH-Z
Figure 1. Load Circuits
t
t
CSH
CSL
CS
R/C
t
ACQ
REF POWER-
DOWN CONTROL
t
t
t
DS
t
DV
EOC
DH
EOC
t
t
DO
CONV
HBEN
t
t
t
DO1
BR
DO
HIGH-Z
HIGH-Z
D7/D15–D0/D8
HIGH/LOW
BYTE VALID
HIGH/LOW
BYTE VALID
Figure 2. MAX1177 Timing Diagram
_______________________________________________________________________________________
7
16-Bit, 135ksps, Single-Supply ADC
with to 10V Input Range
Power-Down Modes
Select standby mode or shutdown mode with the R/C
+5V ANALOG +5V DIGITAL
bit during the second ꢁalling edge oꢁ CS (see the
Selecting Standby or Shutdown Mode section). The
MAX1177 automatically enters either standby mode
(reꢁerence and buꢁꢁer on) or shutdown (reꢁerence and
buꢁꢁer oꢁꢁ) aꢁter each conversion, depending on the sta-
tus oꢁ R/C during the second ꢁalling edge oꢁ CS.
0.1µF
0.1µF
AV
DD
DV
DD
Internal Clock
The MAX1177 generates an internal conversion clock to
ꢁree the µP ꢁrom the burden oꢁ running the SAR conver-
µP DATA
BUS
D0–D7
ANALOG INPUT
AIN
OR
D8–D15
sion clock. Total conversion time (t
) aꢁter entering
CONV
hold mode (second ꢁalling edge oꢁ CS) to end-oꢁ-con-
version (EOC) ꢁalling is 4.7µs (max).
MAX1177
EOC
REF
Applications Information
R/C
CS
Starting a Conversion
CS and R/C control acquisition and conversion in the
MAX1177 (Figure 2). The ꢁirst ꢁalling edge oꢁ CS powers
up the device and puts it in acquire mode iꢁ R/C is low.
The convert start is ignored iꢁ R/C is high. The device
needs at least 12ms ꢁor the internal reꢁerence to wake
REFADJ
HBEN
0.1µF
10µF
HIGH
BYTE
AGND DGND
LOW
BYTE
up and settle beꢁore starting the conversion (C
REFADJ
= 0.1µF, C
= 10µF), iꢁ powering up ꢁrom shutdown.
REF
Selecting Standby or Shutdown Mode
The MAX1177 has a selectable standby or low-power
shutdown mode. In standby mode, the ADC’s internal
reꢁerence and reꢁerence buꢁꢁer do not power down
between conversions, eliminating the need to wait ꢁor
the reꢁerence to power up beꢁore perꢁorming the next
conversion. Shutdown mode powers down the reꢁer-
ence and reꢁerence buꢁꢁer aꢁter completing a conver-
sion. The reꢁerence and reꢁerence buꢁꢁer require a
minimum oꢁ 12ms to power up and settle ꢁrom shut-
Figure 3. Typical Operating Circuit for the MAX1177
MAX1177
R1
3.4kΩ
R2
3.92kΩ
C
HOLD
30pF
161Ω
TRACK
S1
AIN
down (C
= 0.1µF, C
= 10µF).
REF
REFADJ
T/H OUT
The state oꢁ R/C at the second ꢁalling edge oꢁ CS
selects which power-down mode the MAX1177 enters
upon conversion completion. Holding R/C low causes
the device to enter standby mode. The reꢁerence and
buꢁꢁer are leꢁt on aꢁter the conversion completes. R/C
high causes the MAX1177 to enter shutdown mode and
power-down the reꢁerence and buꢁꢁer aꢁter conversion
(Figures 5 and 6). Set the voltage at R/C high during
the second ꢁalling edge oꢁ CS to realize the lowest cur-
rent operation.
R3
17.79kΩ
HOLD
TRACK
HOLD
S2
S1, S2 = T/H SWITCH
R2 = 3.92kΩ
R3 = 17.79kΩ
Figure 4. Equivalent Input Circuit
8
_______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADC
with 0 to 10V Input Range
DATA
OUT
DATA
OUT
ACQUISITION
CONVERSION
ACQUISITION
CONVERSION
CS
CS
R/C
R/C
EOC
EOC
REF AND
BUFFER
POWER
REF AND
BUFFER
POWER
Figure 6. Selecting Shutdown Mode
Figure 5. Selecting Standby Mode
Standby Mode
While in standby mode, the supply current is less than
3.7mA (typ). The next ꢁalling edge oꢁ CS with R/C low
causes the MAX1177 to exit standby mode and begin
acquisition. The reꢁerence and reꢁerence buꢁꢁer remain
active to allow quick turn-on time.
+5V
MAX1177
REFADJ
68kΩ
Shutdown Mode
In shutdown mode, the reꢁerence and reꢁerence buꢁꢁer
are shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately aꢁter
the conversion. The next ꢁalling edge oꢁ CS with R/C
low causes the reꢁerence and buꢁꢁer to wake up and
enter acquisition mode. To achieve 16-bit accuracy,
allow 12ms ꢁor the internal reꢁerence to wake up
100kΩ
0.1µF
150kΩ
(C
= 0.1µF, C
= 10µF).
REF
REFADJ
Figure 7. MAX1177 Reference Adjust Circuit
Internal and External Reference
Internal Reference
makes buꢁꢁering the external reꢁerence unnecessary.
The input impedance oꢁ REFADJ is typically 5kΩ. The
internal buꢁꢁer output must be bypassed at REF with a
10µF capacitor.
The internal reꢁerence oꢁ the MAX1177 is internally
buꢁꢁered to provide +4.096V output at REF. Bypass
REF to AGND and REFADJ to AGND with 10µF and
0.1µF, respectively. Sink or source current at REFADJ
to make ꢁine adjustments to the internal reꢁerence. The
input impedance oꢁ REFADJ is nominally 5kΩ. Use the
circuit in Figure 7 to adjust the internal reꢁerence to
1.5ꢀ.
Connect REFADJ to AV
to disable the internal buꢁꢁer.
DD
Directly drive REF using an external 3.8V to 4.2V reꢁer-
ence. During conversion, the external reꢁerence must
be able to drive 100µA oꢁ DC load current and have an
output impedance oꢁ 10Ω or less.
External Reference
An external reꢁerence can be placed at either the input
(REFADJ) or the output (REF) oꢁ the MAX1177’s internal
buꢁꢁer ampliꢁier. Using the buꢁꢁered REFADJ input
For optimal perꢁormance, buꢁꢁer the reꢁerence through
an op amp and bypass REF with a 10µF capacitor.
Consider the MAX1177’s equivalent input noise (0.6
LSB) when choosing a reꢁerence.
_______________________________________________________________________________________
9
16-Bit, 135ksps, Single-Supply ADC
with to 10V Input Range
INPUT RANGE = 0V TO +10V
OUTPUT CODE
FULL-SCALE
TRANSITION
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
MAX1177
AIN
ANALOG
INPUT
MAX427
FULL-SCALE RANGE (FSR) = +10V
FSR x V
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
REF
1 LSB =
65536 x 4.096
0
1
2
3
65,535
65,534 65,536
INPUT VOLTAGE (LSB)
Figure 8. MAX1177 Transfer Function
Figure 9. MAX1177 Fast-Settling Input Buffer
change in input signal. The input ampliꢁier must have a
high enough slew rate to complete the required output
voltage change beꢁore the beginning oꢁ the acquisition
time. Figure 9 shows an example oꢁ this circuit using
the MAX427.
Reading the Conversion Result
EOC is provided to ꢁlag the µP when a conversion is
complete. The ꢁalling edge oꢁ EOC signals that the data is
valid and ready to be output to the bus. D0–D15 are the
parallel outputs oꢁ the MAX1177. These tri-state outputs
allow ꢁor direct connection to a microcontroller I/O bus.
The outputs remain high impedance during acquisition
and conversion. Data is loaded onto the output bus with
Layout, Grounding, and Bypassing
For best perꢁormance, use printed circuit boards. Do
not run analog and digital lines parallel to each other,
and do not lay out digital signal paths underneath the
ADC package. Use separate analog and digital ground
planes with only one point connecting the two ground
systems (analog and digital) as close to the device as
possible.
the third ꢁalling edge oꢁ CS with R/C high (aꢁter t ).
DO
Bringing CS high ꢁorces the output bus back to high
impedance. The MAX1177 then waits ꢁor the next ꢁalling
edge oꢁ CS to start the next conversion cycle (Figure 2).
HBEN toggles the output between the high/low byte. The
low byte is loaded onto the output bus when HBEN is
low, and the high byte is on the bus when HBEN is high.
Route digital signals ꢁar away ꢁrom sensitive analog and
reꢁerence inputs. Iꢁ digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. Iꢁ the analog and digital sections
share the same supply, isolate the digital and analog
supply by connecting them with a low-value (10Ω)
resistor or ꢁerrite bead.
Transfer Function
Figure 8 shows the MAX1177 output transꢁer ꢁunction.
The output is coded in standard binary.
Input Buffer
Most applications require an input buꢁꢁer ampliꢁier to
achieve 16-bit accuracy and prevent loading the
source. When the input signal is multiplexed, switch the
channels immediately aꢁter acquisition, rather than near
the end oꢁ, or aꢁter, a conversion. This allows more time
ꢁor the input buꢁꢁer ampliꢁier to respond to a large step
The ADC is sensitive to high-ꢁrequency noise on the
AV
supply. Bypass AV
to AGND with a 0.1µF
DD
DD
capacitor in parallel with a 1µF to 10µF low-ESR capaci-
tor with the smallest capacitor closest to the device.
Keep capacitor leads short to minimize stray inductance.
10 ______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADC
with 0 to 10V Input Range
Signal-to-Noise Plus Distortion
Definitions
Signal-to-noise plus distortion (SINAD) is the ratio oꢁ the
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation oꢁ the values
on an actual transꢁer ꢁunction ꢁrom a straight line. This
straight line can be either a best-straight-line ꢁit or a line
drawn between the end points oꢁ the transꢁer ꢁunction,
once oꢁꢁset and gain errors have been nulliꢁied. The
static linearity parameters ꢁor the MAX1177 are mea-
sured using the end-point method.
ꢁundamental input ꢁrequency’s RMS amplitude to the
RMS equivalent oꢁ all the other ADC output signals:
Signal
(Noise+Distortion)
RMS
SINAD(dB) = 20 × log
RMS
Effective Number of Bits
Eꢁꢁective number oꢁ bits (ENOB) indicates the global
accuracy oꢁ an ADC at a speciꢁic input ꢁrequency and
sampling rate. An ideal ADC error consists oꢁ quantiza-
tion noise only. With an input range equal to the ꢁull-
scale range oꢁ the ADC, calculate the ENOB as ꢁollows:
Differential Nonlinearity
Diꢁꢁerential nonlinearity (DNL) is the diꢁꢁerence between
an actual step width and the ideal value oꢁ 1 LSB. A
DNL error speciꢁication oꢁ 1 LSB guarantees no missing
codes and a monotonic transꢁer ꢁunction.
SINAD−1.76
Signal-to-Noise Ratio
For a waveꢁorm perꢁectly reconstructed ꢁrom digital
samples, signal-to-noise ratio (SNR) is the ratio oꢁ the
ꢁull-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly ꢁrom the ADC’s res-
olution (N bits):
ENOB=
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio oꢁ the RMS
sum oꢁ the ꢁirst ꢁive harmonics oꢁ the input signal to the
ꢁundamental itselꢁ. This is expressed as:
2
2
2
2
V
+ V + V + V
3 4 5
2
SNR = (6.02 × N + 1.76)dB
THD = 20 × log
V
1
where N = 16 bits.
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reꢁerence noise, clock jitter,
etc. The SNR is computed by taking the ratio oꢁ the
RMS signal to the RMS noise, which includes all spec-
tral components minus the ꢁundamental, the ꢁirst ꢁive
harmonics, and the DC oꢁꢁset.
where V is the ꢁundamental amplitude and V through
5
1
2
V are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-ꢁree dynamic range (SFDR) is the ratio oꢁ the
RMS amplitude oꢁ the ꢁundamental (maximum signal
component) to the RMS value oꢁ the next-largest ꢁre-
quency component.
______________________________________________________________________________________ 11
16-Bit, 135ksps, Single-Supply ADC
with to 10V Input Range
Functional Diagram
REFADJ
HBEN
AV AGND DV DGND
DD
DD
5kΩ
REFERENCE
8 BITS
8 BITS
OUTPUT
REGISTERS
D0–D7
OR
D8–D15
REF
INPUT
SCALER
CAPACITIVE
DAC
AIN
AGND
MAX1177
SUCCESSIVE-
CLOCK
APPROXIMATION
REGISTER AND
CONTROL LOGIC
EOC
CS
R/C
Pin Configuration
Chip Information
TRANSISTOR COUNT: 15,383
TOP VIEW
PROCESS: BiCMOS
D4/D12
D5/D13
D6/D14
D7/D15
R/C
1
2
20 D3/D11
19
18
D2/D10
D1/D9
3
4
17 D0/D8
16
5
DV
DD
MAX1177
EOC
6
15 DGND
7
14
13
12
11
AV
CS
DD
8
AGND
AIN
HBEN
REF
9
10
AGND
REFADJ
TSSOP
12 ______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADC
with 0 to 10V Input Range
Package Information
(The package drawing(s) in this data sheet may not reꢁlect the most current speciꢁications. For the latest package outline inꢁormation,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 1±
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark oꢁ Maxim Integrated Products.
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