MAX1186 [MAXIM]
Dual 10-Bit.40Msps.3V.Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs ; 双10 - Bit.40Msps.3V.Low功耗ADC，内置电压基准及复用并行输出\n
| 型号： | MAX1186 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual 10-Bit.40Msps.3V.Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
|
| 文件： | 总21页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2263; Rev 0; 12/01
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
General Description
Features
The MAX1186 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully-differential wideband track-
and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1186 is optimized for low-power, high
dynamic performance applications in imaging, instru-
mentation, and digital communication applications. This
ADC operates from a single 2.7V to 3.6V supply, con-
suming only 105mW while delivering a typical signal-to-
noise ratio (SNR) of 59.4dB at an input frequency of
20MHz and a sampling rate of 40Msps. Digital outputs
A and B are updated alternating on the rising (CHA)
and the falling (CHB) edge of the clock. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1186 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.
o Single 3V Operation
o Excellent Dynamic Performance:
59.4dB SNR at f = 20MHz
IN
72dBc SFDR at f = 20MHz
IN
o Low Power:
35mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
o 0.02dB Gain and 0.25° Phase Matching
o Wide 1V
Differential Analog Input Voltage
P-P
Range
o 400MHz, -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o Single 10-Bit Bus for Multiplexed, Digital Outputs
o User-Selectable Output Format–Two’s
Complement or Offset Binary
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADCs. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
o 48-Pin TQFP Package with Exposed Paddle For
Improved Thermal Dissipation
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
The MAX1186 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output for-
mat can be set to two’s complement or straight offset
binary through a single control pin. The device provides
for a separate output power supply of 1.7V to 3.6V for
flexible interfacing. The MAX1186 is available in a
7mm x 7mm, 48-pin TQFP-EP package, and is speci-
fied for the extended industrial (-40°C to +85°C) tem-
perature range.
MAX1186ECM
-40°C to +85°C
48 TQFP-EP
Functional Diagram appears at end of data sheet.
Pin Configuration
Pin-compatible, nonmultiplexed, high-speed versions of
the MAX1186 are also available. Please refer to the
MAX1180 data sheet for 105Msps, the MAX1181 data
sheet for 80Msps, the MAX1182 data sheet for 65Msps,
the MAX1183 data sheet for 40Msps, and the MAX1184
data sheet for 20Msps. For a pin-compatible lower
speed version (20Msps) of the MAX1186, please refer
to the MAX1185 data sheet.
COM
1
2
36 D1A/B
35 D0A/B
34 OGND
V
DD
GND
INA+
INA-
3
4
33 OV
32 OV
DD
DD
5
V
6
31 OGND
30 A/B
DD
MAX1186
GND
INB-
INB+
GND
7
8
29 N.C.
Applications
N.C.
N.C.
N.C.
N.C.
9
28
27
26
25
High-Resolution Imaging
I/Q Channel Digitization
Multichannel IF Sampling
Instrumentation
10
11
12
V
DD
CLK
Video Application
Ultrasound
48 TQFP-EP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
V
, OV
to GND ...............................................-0.3V to +3.6V
Continuous Power Dissipation (T = +70°C)
A
DD
DD
OGND to GND.......................................................-0.3V to +0.3V
48-Pin TQFP (derate 12.5mW/°C above +70°C).......1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
REFIN, REFOUT, REFP, REFN, COM,
DD
CLK to GND............................................-0.3V to (V + 0.3V)
DD
OE, PD, SLEEP, T/B, D9A/B–D0A/B,
A/B to OGND .......................................-0.3V to (OV + 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3V, OV
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V
= 2V
(differential w.r.t. COM), C = 10pF at digital outputs (Note 5), f
= 40MHz,
IN
L
CLK
P-P
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
f
f
= 7.5MHz
0.5
1.7
1.0
1.7
2
IN
IN
DNL
= 7.5MHz, no missing codes guaranteed
0.25
LSB
<
1
% FS
% FS
Gain Error
0
ANALOG INPUT
Differential Input Voltage
Range
V
Differential or single-ended inputs
Switched capacitor load
1
V
V
DIFF
Common-Mode Input Voltage
Range
V
/2
DD
0.5
V
CM
Input Resistance
R
100
5
kΩ
IN
IN
Input Capacitance
C
pF
CONVERSION RATE
Maximum Clock Frequency
f
40
MHz
CLK
CHA
CHB
5
Clock
Cycles
Data Latency
5.5
DYNAMIC CHARACTERISTICS (f
Signal-to-Noise Ratio
= 40MHz, 4096-point FFT)
CLK
f
f
f
f
f
f
= 7.5MHz, T = +25°C
57.3
56.8
57
59.5
59.4
59.4
59.2
74
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
A
SNR
dB
dB
= 20MHz, T = +25°C
A
= 7.5MHz, T = +25°C
A
Signal-to-Noise and Distortion
Spurious-Free Dynamic Range
SINAD
SFDR
= 20MHz, T = +25°C
56.5
64
A
= 7.5MHz, T = +25°C
A
dBc
= 20MHz, T = +25°C
64
72
A
2
_______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V
= 2V
(differential w.r.t. COM), C = 10pF at digital outputs (Note 5), f
= 40MHz,
IN
L
CLK
P-P
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
= 7.5MHz
MIN
TYP
-74
MAX
UNITS
f
f
f
f
f
f
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
Third-Harmonic Distortion
Intermodulation Distortion
HD3
dBc
= 20MHz
-72
= 11.6066MHz at -6.5dB FS
= 13.3839MHz at -6.5dB FS (Note 2)
IMD
THD
-76
dBc
dBc
= 7.5MHz, T = +25°C
-72
-71
500
400
1
-64
-63
A
Total Harmonic Distortion
(first four harmonics)
= 20MHz
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Input at -20dB FS, differential inputs
Input at -0.5dB FS, differential inputs
MHz
MHz
ns
FPBW
t
AD
Aperture Jitter
t
2
ps
rms
AJ
✕
Overdrive Recovery Time
Differential Gain
For 1.5 full-scale input
2
ns
1
%
Differential Phase
Output Noise
0.25
0.2
degrees
INA+ = INA- = INB+ = INB- = COM
LSB
RMS
INTERNAL REFERENCE
2.048
3%
Reference Output Voltage
REFOUT
TC
V
Reference Temperature
Coefficient
60
ppm/°C
REF
Load Regulation
1.25
mV/mA
BUFFERED EXTERNAL REFERENCE (V
= 2.048V)
REFIN
REFIN Input Voltage
V
2.048
2.012
V
V
REFIN
Positive Reference Output
Voltage
V
REFP
Negative Reference Output
Voltage
V
0.988
V
REFN
Differential Reference Output
Voltage Range
∆V
∆V
= V
- V
REFN
0.98
1.024
>50
1.07
V
REF
REF
REFP
REFIN Resistance
R
MΩ
REFIN
_______________________________________________________________________________________
3
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V
= 2V
(differential w.r.t. COM), C = 10pF at digital outputs (Note 5), f
= 40MHz,
IN
L
CLK
P-P
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum REFP, COM Source
Current
I
5
mA
SOURCE
Maximum REFP, COM Sink
Current
I
-250
µA
SINK
Maximum REFN Source Current
Maximum REFN Sink Current
I
250
-5
µA
SOURCE
I
mA
SINK
UNBUFFERED EXTERNAL REFERENCE (V
= GND, reference voltage applied to REFP, REFN, and COM)
REFIN
R
R
,
Measured between REFP and COM, and
REFN and COM
REFP
REFP, REFN Input Resistance
4
kΩ
V
REFN
Differential Reference Input
Voltage
1.024
10%
∆V
∆V
= V
- V
REFP REFN
REF
REF
V
/2
10%
DD
COM Input Voltage
REFP Input Voltage
REFN Input Voltage
V
V
V
COM
REFP
REFN
V
+
COM
V
∆V
/2
REF
V
-
COM
V
V
∆V
/2
REF
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
✕
✕
CLK
0.8
V
DD
Input High Threshold
V
V
IH
PD, OE, SLEEP, T/B
CLK
0.8 OV
DD
✕
0.2
V
DD
Input Low Threshold
Input Hysteresis
Input Leakage
V
V
V
IL
✕
PD, OE, SLEEP, T/B
0.2 OV
DD
V
0.1
5
HYST
I
V
V
= OV or V (CLK)
5
5
IH
IH
IL
DD
DD
µA
pF
I
= 0
IL
Input Capacitance
C
IN
DIGITAL OUTPUTS (D0A/B–D9A/B, A/B)
Output Voltage Low
V
I
I
= -200µA
0.2
10
V
V
OL
SINK
Output Voltage High
V
= 200µA
OV - 0.2
DD
OH
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
I
OE = OV
µA
pF
LEAK
DD
DD
C
OE = OV
5
OUT
4
_______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V
= 2V
(differential w.r.t. COM), C = 10pF at digital outputs (Note 5), f
= 40MHz,
IN
L
CLK
P-P
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
V
2.7
1.7
3.0
2.5
35
2.8
1
3.6
3.6
50
V
V
DD
OV
DD
Operating, f
Sleep mode
= 20MHz at -0.5dB FS
INA or B
mA
µA
Analog Supply Current
Output Supply Current
Power Dissipation
I
VDD
Shutdown, clock idle, PD = OE = OV
15
DD
Operating, C = 15pF, f
L
-0.5dB FS
= 20MHz at
INA or B
4
mA
I
OVDD
Sleep mode
100
2
µA
Shutdown, clock idle, PD = OE = OV
10
DD
Operating, f
Sleep mode
= 20MHz at -0.5dB FS
105
8.4
3
150
INA or B
mW
PDISS
PSRR
Shutdown, clock idle, PD = OE = OV
45
µW
mV/V
%/V
DD
Offset
Gain
0.2
0.1
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
t
t
Figure 3 (Note 3)
Figure 3 (Note 3)
5
5
6
8
8
ns
ns
ns
DOA
DOB
DA/B
CLK Fall to CHB Output Data
Valid
Clock Rise/Fall to A/B Rise/Fall
Time
t
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
t
Figure 4
10
ns
ns
ns
ns
ENABLE
t
Figure 4
1.5
DISABLE
12.5 3.8
12.5 3.8
t
Figure 3, clock period: 25ns
Figure 3, clock period: 25ns
Wake-up from sleep mode (Note 4)
Wake-up from shutdown (Note 4)
CH
t
CL
0.41
1.5
Wake-Up Time
t
µs
WAKE
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
f
f
f
= 20MHz at -0.5dB FS
= 20MHz at -0.5dB FS
= 20MHz at -0.5dB FS
-70
dB
dB
INA or B
INA or B
INA or B
Gain Matching
0.02
0.25
0.2
Phase Matching
degrees
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 3: Digital outputs settle to V and V . Parameter guaranteed by design.
IH
IL
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Equivalent dynamic performance is obtainable over full OV range with reduced C .
DD
L
_______________________________________________________________________________________
5
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics
(V
= 3V, OV
= 2.5V, V
= 2.048V, differential input at -0.5dB FS, f
= 40.00057MHz, C ≈ 10pF, T = +25°C,
CLK L A
DD
DD
REFIN
unless otherwise noted.)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
f
= 40.0005678MHz
= 19.8879776MHz
= 24.9661747MHz
CHA
f
f
f
= 40.0005678MHz
= 6.1475482MHz
= 7.5342866MHz
CHA
f
f
f
= 40.0005678MHz
= 6.1475482MHz
= 7.5342866MHz
CLK
INA
INB
CLK
INA
INB
CHB
CLK
INA
INB
AINA = -0.516dB FS
AINA = -0.552dB FS
AINB = -0.534dB FS
HD3
HD3
HD3
HD2
HD2
HD2
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
8192-POINT DATA RECORD)
0
0
61
60
59
58
57
56
55
f
f
f
= 40.0005678MHz
= 11.606610MHz
= 13.383979MHz
f
f
f
= 40.0005678MHz
= 19.8879776MHz
= 24.9661747MHz
CHB
CLK
IN1
IN2
CLK
INA
INB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CHB
f
IN2
AIN = -6.5dB FS
AINB = -0.498dB FS
TWO-TONE ENVELOPE =
-0.471dB FS
CHA
f
IN1
HD3
IMD3
IMD3
IMD2
IMD2
HD2
0
2
4
6
8
10 12 14 16 18 20
1
10
100
0
2
4
6
8
10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE PLUS DISTORTION vs.
ANALOG INPUT FREQUECNY
TOTAL HARMONIC DISTORTION vs.
ANALOG INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE vs.
ANALOG INPUT FREQUENCY
-60
-64
-68
-72
62
60
58
56
54
80
76
72
68
64
60
CHB
CHA
CHB
CHA
CHA
CHB
-76
-80
1
10
100
1
10
100
1
10
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
6
_______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)
(V
= 3V, OV
= 2.5V, V
= 2.048V, differential input at -0.5dB FS, f
= 40.00057MHz, C ≈ 10pF, T = +25°C,
CLK L A
DD
DD
REFIN
unless otherwise noted.)
FULL-POWER INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, SINGLE-ENDED
SMALL-SIGNAL INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, SINGLE-ENDED
SIGNAL-TO-NOISE RATIO vs.
INPUT POWER (f = 19.8879776MHz)
IN
6
6
65
60
55
50
45
40
35
V
= 100mV
P-P
IN
4
2
4
2
0
0
-2
-4
-6
-8
-2
-4
-6
-8
1
10
100
1000
1
10
100
1000
-20
-16
-12
-8
-4
0
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
INPUT POWER (dB FS)
TOTAL HARMONIC DISTORTION vs.
SIGNAL-TO-NOISE PLUS DISTORTION vs.
SPURIOUS-FREE DYNAMIC RANGE vs.
INPUT POWER (f = 19.8879776MHz)
INPUT POWER (f = 19.8879776MHz)
INPUT POWER (f = 19.8879776MHz)
IN
IN
IN
65
60
55
50
45
40
35
-55
-60
-65
-70
-75
-80
80
75
70
65
60
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
INPUT POWER (dB FS)
INPUT POWER (dB FS)
INPUT POWER (dB FS)
INTEGRAL NONLINEARITY
(BEST ENDPOINT FIT)
GAIN ERROR vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
EXTERNAL REFERENCE (V
= 2.048V)
REFIN
0.3
0.2
0.1
0
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
CHB
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.1
-0.2
CHA
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)
(V
= 3V, OV
= 2.5V, V
= 2.048V, differential input at -0.5dB FS, f
= 40.00057MHz, C ≈ 10pF, T = +25°C,
CLK L A
DD
DD
REFIN
unless otherwise noted.)
ANALOG SUPPLY CURRENT vs.
ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT vs.
TEMPERATURE
OFFSET ERROR vs. TEMPERATURE
EXTERNAL REFERENCE (V
= 2.048V)
REFIN
45
43
41
39
37
35
0.2
42
41
40
0.1
0
39
38
37
36
-0.1
-0.2
-0.3
-0.4
CHB
CHA
2.70 2.85 3.00 3.15 3.30 3.45 3.60
(V)
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
DD
TEMPERATURE (°C)
SFDR, SNR, THD, SINAD vs.
CLOCK DUTY CTCLE
ANALOG POWER-DOWN CURRENT
vs. ANALOG POWER SUPPLY
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
80
0.40
0.32
0.24
0.16
0.08
0
2.0100
2.0080
2.0060
2.0040
2.0020
2.0000
f
= 7.5342866MHz
INA/B
SFDR
OE = PD = OV
DD
74
68
62
56
50
THD
SNR
SINAD
20
30
40
50
60
70
80
2.70 2.85 3.00 3.15 3.30 3.45 3.60
(V)
2.70 2.85 3.00 3.15 3.30 3.45 3.60
(V)
CLOCK DUTY CYCLE (%)
V
V
DD
DD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OUTPUT NOISE HISTOGRAM (DC INPUT)
70,000
2.014
2.010
2.006
64,515
63,000
56,000
49,000
42,000
35,000
28,000
21,000
14,000
7,000
2.002
1.998
1.994
869
N-1
152
N+1
0
0
0
-40
-15
10
35
60
85
N-2
N
N+2
TEMPERATURE (°C)
DIGITAL OUTPUT CODE
8
_______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Pin Description
PIN
NAME
FUNCTION
1
COM
Common-Mode Voltage Input/Output. Bypass to GND with a ≥0.1µF capacitor.
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with
0.1µF.
2, 6, 11, 14, 15
V
DD
3, 7, 10, 13, 16
GND
INA+
INA-
INB-
INB+
CLK
Analog Ground
4
5
Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
Converter Clock Input
8
9
12
T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.
17
18
19
20
T/B
SLEEP
PD
Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.
Power-Down Input.
High: Power-down mode.
Low: Normal operation.
Output Enable Input.
High: Digital outputs disabled.
Low: Digital outputs enabled.
OE
21–29
30
N.C.
A/B
No Connection
A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0) to
be present on the output. A/B follows the external clock signal with typically 6ns delay.
31, 34
32, 33
OGND
Output Driver Ground
Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in
parallel with 0.1µF.
OV
DD
Three-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects
channel A or channel B data.
35
D0A/B
Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A or
channel B data.
36
37
38
39
40
D1A/B
D2A/B
D3A/B
D4A/B
D5A/B
Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A or
channel B data.
_______________________________________________________________________________________
9
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A or
channel B data.
41
D6A/B
Three-State Digital Output, Bit 7. Depending on status of A/B, output data reflects channel A or
channel B data.
42
43
44
D7A/B
D8A/B
D9A/B
Three-State Digital Output, Bit 8. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 9 (MSB). Depending on status of A/B, output data reflects
channel A or channel B data.
Internal Reference Voltage Output. Maybe connected to REFIN through a resistor or a resistor-
divider.
45
46
47
REFOUT
REFIN
REFP
✕
Reference Input. V
= 2 (V
- V
REFN
). Bypass to GND with a >1nF capacitor.
REFIN
REFP
Positive Reference Input/Output. Conversion range is (V
>0.1µF capacitor.
- V
REFN
). Bypass to GND with a
REFP
Negative Reference Input/Output. Conversion range is (V
a >0.1µF capacitor.
- V
REFN
). Bypass to GND with
REFP
48
REFN
10 ______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
time of 6ns and remains high when CHA data is updat-
ed and low when CHB data is updated.
Detailed Description
The MAX1186 uses a nine-stage, fully-differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consumption.
Samples taken at the inputs move progressively through
the pipeline stages every one-half clock cycle. Including
the delay through the output latch, the total clock-cycle
latency is five clock cycles.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track- and hold-
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully-differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the out-
put of the amplifier and switch S4c is closed. The result-
ing differential voltages are held on capacitors C2a and
C2b. The amplifiers are used to charge capacitors C1a
and C1b to the same values originally held on C2a and
C2b. These values are then presented to the first stage
quantizers and isolate the pipelines from the fast-chang-
ing inputs. The wide input bandwidth T/H amplifiers allow
the MAX1186 to track and sample/hold analog inputs of
high frequencies (> Nyquist). Both ADC inputs (INA+,
INB+, INA-, and INB-) can be driven either differentially or
single-ended. Match the impedance of INA+ and INA-,
as well as INB+ and INB-, and set the common-mode
1.5-bit (2-comparator) flash ADCs convert the held input
voltages into a digital code. The digital-to-analog con-
verters (DACs) convert the digitized results back into
analog voltages, which are then subtracted from the
original held input signals. The resulting error signals
are then multiplied by two and the residues are passed
along to the next pipeline stages, where the process is
repeated until the signals have been processed by all
nine stages. Digital error correction compensates for
ADC comparator offsets in each of these pipeline
stages and ensures no missing codes.
Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (5 clock
cycles later) and CHB data is updated on the falling
edge (5.5 clock cycles later) of the clock signal. The A/B
indicator follows the clock signal with a typical delay
voltage to midsupply (V /2) for optimum performance.
DD
V
V
V
OUT
V
OUT
IN
IN
x2
x2
Σ
Σ
T/H
T/H
FLASH
ADC
FLASH
ADC
DAC
DAC
1.5 BITS
1.5 BITS
2-BIT FLASH
ADC
2-BIT FLASH
ADC
STAGE 1
STAGE 2
STAGE 8
STAGE 9
STAGE 1
STAGE 2
STAGE 8
STAGE 9
DIGITAL CORRECTION LOGIC
10
DIGITAL CORRECTION LOGIC
10
T/H
T/H
V
INB
V
INA
OUTPUT
MULTIPLEXER
10
D0A/B–D9A/B
Figure 1. Pipelined Architecture—Stage Blocks
______________________________________________________________________________________ 11
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
INTERNAL
COM
S5a
BIAS
S2a
C1a
S3a
S4a
S4b
INA+
INA-
OUT
OUT
C2a
C2b
S4c
S1
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
HOLD
HOLD
INTERNAL
BIAS
TRACK
TRACK
COM
S5a
S2a
C1a
S3a
S4a
S4b
INB+
INB-
OUT
OUT
C2a
C2b
S4c
S1
MAX1186
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
Figure 2. MAX1186 T/H Amplifiers
12 ______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
The MAX1186 clock input operates with a voltage thresh-
Analog Inputs and Reference
Configurations
old set to V /2. Clock inputs with a duty cycle other
DD
than 50%, must meet the specifications for high and low
periods as stated in the Electrical Characteristics.
The full-scale range of the MAX1186 is determined by the
internally generated voltage difference between REFP
(V /2 + V
/4) and REFN (V /2 - V /4). The
REFIN
DD
REFIN
DD
System Timing Requirements
Figure 3 shows the relationship between clock and ana-
log input, A/B indicator, and the resulting CHA/CHB
data output. CHA and CHB data are sampled on the
rising edge of the clock signal. Following the rising
edge of the 5th clock cycles, the digitized value of the
original CHA sample is presented at the output. This
followed one-half clock cycle later by the digitized
value of the original CHB sample.
full-scale range for both on-chip ADCs is adjustable
through the REFIN pin, which is provided for this purpose.
REFOUT, REFP, COM (V /2), and REFN are internally
DD
buffered low-impedance outputs.
The MAX1186 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
A channel selection signal (A/B indicator) allows the user
to determine which output data represents which input
channel. With A/B = 1, digitized data from CHA is present
at the output and with A/B = 0 digitized data from CHB is
present.
In internal reference mode, connect the internal reference
output REFOUT to REFIN through a resistor (e.g., 10kΩ)
or resistor-divider, if an application requires a reduced
full-scale range. For stability and noise filtering purposes,
bypass REFIN with a >10nF capacitor to GND. In internal
reference mode, REFOUT, COM, REFP, and REFN
become low-impedance outputs.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (OE), Channel
Selection (A/B)
In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu-
rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or con-
nected to REFIN through a >10kΩ resistor.
In unbuffered external reference mode, connect REFIN to
GND. This deactivates the on-chip reference buffers for
REFP, COM, and REFN. With their buffers shut down,
these nodes become high impedance and may be driven
through separate, external reference sources.
All digital outputs, D0A/B–D9A/B (CHA or CHB data) and
A/B are TTL/CMOS logic-compatible. The output coding
can be chosen to be either offset binary or two’s comple-
ment (Table 1) controlled by a single pin (T/B). Pull T/B
low to select offset binary and high to activate two’s com-
plement output coding. The capacitive load on the digital
outputs D0A/B–D9A/B should be kept as low as possible
(<15pF), to avoid large digital currents that could feed
back into the analog portion of the MAX1186, thereby
degrading its dynamic performance. Using buffers on the
digital outputs of the ADCs can further isolate the digital
outputs from heavy capacitive loads. To further improve
the dynamic performance of the MAX1186, small-series
resistors (e.g., 100Ω) may be added to the digital output
paths, close to the MAX1186.
Clock Input (CLK)
The MAX1186’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low jit-
ter and fast rise and fall times (< 2ns). In particular, sam-
pling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR performance
of the on-chip ADCs as follows:
Figure 4 displays the timing relationship between output
enable and data output valid as well as power-
down/wake-up and data output valid.
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1186 offers two power-save modes—sleep
and full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to
2.8mA.
SNR = 20 x log (1 / [2π x f x t ])
dB
10
IN AJ
where f represents the analog input frequency and t
IN
AJ
is the time of the aperture jitter.
Clock jitter is especially critical for undersampling appli-
cations. The clock input should always be considered as
an analog input and routed away from any analog input
or other digital signal lines.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power-down. Pulling OE high, forces
the digital outputs into a high-impedance state.
______________________________________________________________________________________ 13
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB
t
CLK
t
CL
t
CH
CLK
t
t
DOA
DOB
A/B
CHB
D0B
CHA
D1A
CHB
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
t
DA/B
D0A/B–D9A/B
D1B
Figure 3. Timing Diagram for Multiplexed Outputs
the amplifiers. The user may select the R
and C
ISO
IN
values to optimize the filter performance, to suit a par-
ticular application. For the application in Figure 5, a
R
of 50Ω is placed before the capacitive load to pre-
ISO
OE
vent ringing and oscillation. The 22pF C capacitor
IN
acts as a small bypassing capacitor.
t
t
DISABLE
ENABLE
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1186 for
optimum performance. Connecting the center tap of the
OUTPUT
D0A/B–D9A/B
HIGH-Z
HIGH-Z
VALID DATA
transformer to COM provides a V /2 DC level shift to
DD
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
Figure 4. Output Timing Diagram
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
In general, the MAX1186 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
reference provides a V /2 output voltage for level
DD
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers that follows
14 ______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Table 1. MAX1186 Output Codes For Differential Inputs
STRAIGHT OFFSET
DIFFERENTIAL INPUT
VOLTAGE*
DIFFERENTIAL
INPUT
TWO’S COMPLEMENT
BINARY
T/B = 0
T/B = 1
V
x 511/512
+FULL SCALE - 1LSB
+1LSB
11 1111 1111
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
11 1111 1111
10 0000 0001
10 0000 0000
REF
V
x 1/512
0
REF
Bipolar Zero
- V
x 1/512
-1LSB
REF
-V
x 511/512
- FULL SCALE + 1LSB
- FULL SCALE
REF
REF
-V
= V
x 512/512
- V
REFN
*V
REF
REFP
Single-Ended AC-Coupled Input Signal
Grounding, Bypassing, and
Board Layout
Figure 7 shows an AC-coupled, single-ended applica-
tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to maintain
the integrity of the input signal.
The MAX1186 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
Typical QAM Demodulation Application
The most frequently used modulation technique for digital
communications applications is probably the Quadrature
Amplitude Modulation (QAM). Typically found in spread-
spectrum based systems, a QAM signal represents a
carrier frequency modulated in both amplitude and
phase. At the transmitter, modulating the baseband sig-
nal with quadrature outputs, a local oscillator followed by
subsequent up-conversion can generate the QAM signal.
The result is an in-phase (I) and a quadrature (Q) carrier
component, where the Q component is 90 degree phase-
shifted with respect to the in-phase component. At the
receiver, the QAM signal is divided down into it’s I and Q
components, essentially representing the modulation
process reversed. Figure 8 displays the demodulation
process performed in the analog domain, using the dual
matched 3V, 10-bit ADC MAX1186, and the MAX2451
quadrature demodulator to recover and digitize the
I and Q baseband signals. Before being digitized by the
MAX1186, the mixed-down signal components may be fil-
tered by matched analog filters, such as Nyquist or
pulse-shaping filters. These remove any unwanted
images from the mixing process, thereby enhancing the
overall signal-to-noise (SNR) performance and minimizing
intersymbol interference.
inductance. Bypass V , REFP, REFN, and COM with
DD
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV ) to OGND. Multilayer
DD
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi-
mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
(1Ω to 5Ω), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground plane (e.g.,
downstream output buffer or DSP ground plane). Route
high-speed digital signal traces away from the sensitive
analog traces of either channel. Make sure to isolate
the analog input lines to each respective converter to
minimize channel-to-channel crosstalk. Keep all signal
lines short and free of 90 degree turns.
______________________________________________________________________________________ 15
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
+5V
0.1µF
LOWPASS FILTER
INA+
MAX4108
R
IS0
50Ω
0.1µF
300Ω
C
IN
22pF
0.1µF
-5V
600Ω
600Ω
300Ω
COM
0.1µF
+5V
+5V
0.1µF
0.1µF
600Ω
INPUT
0.1µF
0.1µF
LOWPASS FILTER
MAX4108
-5V
300Ω
300Ω
INA-
MAX4108
R
IS0
C
IN
22pF
50Ω
-5V
+5V
300Ω
300Ω
600Ω
MAX1186
0.1µF
0.1µF
LOWPASS FILTER
INB+
MAX4108
-5V
R
IS0
0.1µF
300Ω
C
IN
22pF
50Ω
600Ω
600Ω
300Ω
0.1µF
+5V
+5V
0.1µF
0.1µF
600Ω
INPUT
0.1µF
0.1µF
LOWPASS FILTER
MAX4108
-5V
300Ω
300Ω
INB-
MAX4108
-5V
R
IS0
50Ω
C
IN
22pF
300Ω
300Ω
600Ω
Figure 5. Typical Application for Single-Ended to Differential Conversion
16 ______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
25Ω
INA+
22pF
0.1µF
6
5
4
1
2
T1
V
IN
N.C.
COM
2.2µF
0.1µF
3
MINICIRCUITS
TT1–6
25Ω
INA-
INB+
22pF
22pF
MAX1186
25Ω
0.1µF
6
5
4
1
2
3
T1
V
IN
N.C.
2.2µF
0.1µF
MINICIRCUITS
TT1–6
25Ω
INB-
22pF
Figure 6. Transformer-Coupled Input Drive
Static Parameter Definitions
Dynamic Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the MAX1186 are measured using
the best straight-line fit method.
Aperture Jitter
Figure 9 depicts the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 9).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
______________________________________________________________________________________ 17
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
REFP
1kΩ
1kΩ
R
ISO
50Ω
V
IN
0.1µF
INA+
COM
INA-
MAX4108
C
IN
22pF
100Ω
100Ω
REFN
0.1µF
R
50Ω
ISO
C
IN
22pF
REFP
MAX1186
R
1kΩ
ISO
50Ω
V
IN
0.1µF
INB+
MAX4108
C
IN
22pF
100Ω
100Ω
1kΩ
REFN
0.1µF
R
ISO
50Ω
INB-
C
IN
22pF
Figure 7: Using an Op Amp for Single-Ended, AC-Coupled Input Drive
tion error only and results directly from the ADC’s reso-
Effective Number of Bits (ENOB)
lution (N-Bits):
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC error consists of quantization noise only. ENOB is
computed from:
SNR
= 6.02 x N + 1.76
dB dB
dB[max]
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
SINAD −1.76
dB
dB
ENOB=
6.02
dB
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
18 ______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX2451
INA+
INA-
A/B
0°
DSP
POST
PROCESSING
90°
MAX1186
INB+
INB-
CHA AND CHB DATA
ALTERNATINGLY
AVAILABLE ON 10-BIT,
MULTIPLEXED
DOWNCONVERTER
÷
8
OUTPUT BUS
Figure 8. Typical QAM Application, Using the MAX1186
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
CLK
2
2
2
2
V
+ V + V + V
3 4 5
2
ANALOG
INPUT
THD = 20 ×log
10
V
1
t
AD
where V is the fundamental amplitude, and V through
5
harmonics.
t
1
2
AJ
V
are the amplitudes of the 2nd- through 5th-order
SAMPLED
DATA (T/H)
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
HOLD
TRACK
TRACK
T/H
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are at -6.5dB full scale and their envelope is at -0.5dB
full scale.
Figure 9. T/H Aperture Timing
Chip Information
TRANSISTOR COUNT: 10,811
PROCESS: CMOS
______________________________________________________________________________________ 19
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Functional Diagram
V
OGND
OV
DD
GND
DD
INA+
PIPELINE
ADC
A/B
DEC
MUX
T/H
INA-
CLK
10
CONTROL
INB+
INB-
10
PIPELINE
ADC
OUTPUT
DRIVERS
DEC
T/H
D0A/B–D9A/B
OE
T/B
REFERENCE
PD
SLEEP
MAX1186
REFOUT
REFN COM REFP
REFIN
20 ______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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