MAX1191 [MAXIM]
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC; 超低功耗， 7.5Msps ，双8位ADC
| 型号： | MAX1191 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC |
| 文件： | 总27页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2836; Rev 1; 9/03
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
General Description
Features
The MAX1191 is an ultra-low-power, dual, 8-bit,
7.5Msps analog-to-digital converter (ADC). The device
features two fully differential wideband track-and-hold
(T/H) inputs. These inputs have a 440MHz bandwidth
and accept fully differential or single-ended signals.
The MAX1191 delivers a typical signal-to-noise and dis-
tortion (SINAD) of 48.6dB at an input frequency of
1.875MHz and a sampling rate of 7.5Msps while con-
suming only 12mW. This ADC operates from a 2.7V to
3.6V analog power supply. A separate 1.8V to 3.6V
supply powers the digital output driver. In addition to
ultra-low operating power, the MAX1191 features three
power-down modes to conserve power during idle peri-
ods. Excellent dynamic performance, ultra-low power,
and small size make the MAX1191 ideal for applica-
tions in imaging, instrumentation, and digital communi-
cations.
ꢀ Ultra-Low Power
12mW (Normal Operation: 7.5Msps)
0.3µW (Shutdown Mode)
ꢀ Excellent Dynamic Performance
48.7dB SNR at f = 1.875MHz
IN
69dBc SFDR at f = 1.875MHz
IN
ꢀ 2.7V to 3.6V Single Analog Supply
ꢀ 1.8V to 3.6V TTL/CMOS-Compatible Digital
Outputs
ꢀ Fully Differential or Single-Ended Analog Inputs
ꢀ Internal/External Reference Option
ꢀ Multiplexed CMOS-Compatible Tri-State Outputs
ꢀ 28-Pin Thin QFN Package
ꢀ Evaluation Kit Available (Order MAX1193EVKIT)
An internal 1.024V precision bandgap reference sets
the full-scale range of the ADC to 0.512V. A flexible
reference structure allows the MAX1191 to use its inter-
nal reference or accept an externally applied reference
for applications requiring increased accuracy.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
28 Thin QFN-EP*
(5mm x 5mm)
The MAX1191 features parallel, multiplexed, CMOS-
compatible tri-state outputs. The digital output format is
offset binary. A separate digital power input accepts a
voltage from 1.8V to 3.6V for flexible interfacing to dif-
ferent logic levels. The MAX1191 is available in a 5mm
× 5mm, 28-pin thin QFN package, and is specified for
the extended industrial (-40°C to +85°C) temperature
range.
MAX1191ETI-T
-40°C to +85°C
*EP = Exposed paddle.
Pin Configuration
TOP VIEW
For higher sampling frequency applications, refer to the
MAX1195–MAX1198 dual 8-bit ADCs. Pin-compatible
versions of the MAX1191 are also available. Refer to the
MAX1192 data sheet for 22Msps, and the MAX1193
data sheet for 45Msps.
INA-
INA+
GND
CLK
D0
D1
D2
1
2
3
4
5
6
7
21
20
19
Applications
Ultrasound and Medical Imaging
IQ Baseband Sampling
18 D3
Battery-Powered Portable Instruments
Low-Power Video
MAX1191
17
16
GND
INB+
INB-
A/B
D4
WLAN, Mobile DSL, WLL Receiver
EXPOSED PADDLE
15 D5
5mm x 5mm THIN QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
ABSOLUTE MAXIMUM RATINGS
V
, OV
to GND ...............................................-0.3V to +3.6V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
DD
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND .................-0.3V to (V
CLK, REFIN, REFP, REFN, COM to GND...-0.3V to (V
PD0, PD1 to OGND .................................-0.3V to (OV
Digital Outputs to OGND.........................-0.3V to (OV
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
DD
DD
DD
DD
Continuous Power Dissipation (T = +70°C)
A
28-Pin Thin QFN (derated 20.8mW/°C above +70°C)...1667mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, f
= 7.5MHz, C
= C = C
REFN COM
DD
DD
REFIN
DD
L
CLK
REFP
= 0.33µF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
8
Bits
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
INL
0.15
0.13
1.00
1.00
4
DNL
No missing codes over temperature
≥+25°C
Offset Error
%FS
<+25°C
6
Gain Error
Excludes REFP - REFN error
2
%FS
dB
DC Gain Matching
Gain Temperature Coefficient
0.01
30
0.2
ppm/°C
Offset (V
5%)
5%)
0.2
DD
Power-Supply Rejection
LSB
Gain (V
0.05
DD
ANALOG INPUT
Differential Input Voltage Range
V
Differential or single-ended inputs
Switched capacitor load
0.512
/ 2
V
V
DIFF
Common-Mode Input Voltage
Range
V
V
COM
DD
Input Resistance
R
C
720
5
kΩ
IN
Input Capacitance
pF
IN
CONVERSION RATE
Maximum Clock Frequency
f
7.5
MHz
CLK
Channel A
Channel B
5.0
5.5
Clock
cycles
Data Latency
DYNAMIC CHARACTERISTICS (differential inputs, 4096 point FFT)
f
IN
f
IN
f
IN
f
IN
= 1.875MHz
= 3.75MHz
= 1.875MHz
= 3.75
47
47
48.7
48.6
48.6
48.5
Signal-to-Noise Ratio
(Note 2)
SNR
dB
dB
Signal-to-Noise and Distortion
(Note 2)
SINAD
2
_______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, f
= 7.5MHz, C
= C = C
REFN COM
DD
DD
REFIN
DD
L
CLK
REFP
= 0.33µF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
A
PARAMETER
SYMBOL
CONDITIONS
= 1.875MHz
MIN
TYP
69
MAX
UNITS
f
f
f
f
59
IN
IN
IN
IN
Spurious-Free Dynamic Range
(Note 2)
SFDR
dBc
= 3.75MHz
= 1.875MHz
= 3.75MHz
68.7
72.0
-70.0
Third-Harmonic Distortion
(Note 2)
HD3
IMD
IM3
dBc
dBc
dBc
dBc
f
= 1MHz at -7dB FS, f
at -7dB FS
= 1.01MHz
= 1.01MHz
IN1
IN2
IN2
Intermodulation Distortion
Third-Order Intermodulation
-66
-70
f
= 1MHz at -7dB FS, f
IN1
at -7dB FS
f
f
= 1.875MHz
= 3.75MHz
-68.0
-67.0
440
440
1.5
2
-57.0
IN
Total Harmonic Distortion
(Note 2)
THD
IN
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
SSBW Input at -20dB FS
FPBW Input at -0.5dB FS
MHz
MHz
ns
t
AD
Aperture Jitter
t
1dB SNR degradation at Nyquist
ps
RMS
AJ
Overdrive Recovery Time
1.5 × full-scale input
2
ns
INTERNAL REFERENCE (REFIN = V ; V
, V
, and V
are generated internally)
COM
DD REFP REFN
REFP Output Voltage
REFN Output Voltage
V
V
- V
0.256
V
V
REFP
REFN
COM
- V
-0.256
COM
V
/ 2
V
/ 2
DD
DD
COM Output Voltage
V
V
/ 2
DD
V
V
COM
- 0.15
+ 0.15
Differential Reference Output
V
V
- V
REFN
0.512
30
REF
REFP
Differential Reference Output
Temperature Coefficient
V
ppm/°C
REFTC
Maximum REFP/REFN/COM
Source Current
I
2
2
mA
mA
SOURCE
Maximum REFP/REFN/COM Sink
Current
I
SINK
BUFFERED EXTERNAL REFERENCE (V
= 1.024V, V
, V
, and V
COM
are generated internally)
1.024
REFIN
REFP REFN
REFIN Input Voltage
V
V
REFIN
V
/ 2
V
/ 2
DD
DD
COM Output Voltage
V
V
/ 2
DD
V
V
COM
- 0.15
+ 0.15
Differential Reference Output
V
V
- V
REFN
0.512
2
REF
SOURCE
REFP
Maximum REFP/REFN/COM
Source Current
I
mA
_______________________________________________________________________________________
3
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, f
= 7.5MHz, C
= C = C
REFN COM
DD
DD
REFIN
DD
L
CLK
REFP
= 0.33µF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum REFP/REFN/COM Sink
Current
I
2
mA
SINK
REFIN Input Resistance
REFIN Input Current
>500
-0.7
kΩ
µA
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, V
, V
, and V
are applied
COM
REFP REFN
REFP Input Voltage
REFN Input Voltage
COM Input Voltage
V
V
- V
0.256
V
V
V
REFP
REFN
COM
- V
-0.256
COM
V
R
V
/ 2
DD
COM
Differential Reference Input
Voltage
V
V
- V
REFN
0.512
V
REF
REFP
REFP Input Resistance
Measured between REFP and COM
Measured between REFN and COM
4
4
kΩ
kΩ
REFP
REFN
REFN Input Resistance
R
DIGITAL INPUTS (CLK, PD0, PD1)
0.7 x
CLK
V
DD
Input High Threshold
Input Low Threshold
V
V
V
IH
0.7 x
OV
PD0, PD1
CLK
DD
0.3 x
V
DD
V
IL
0.3 x
PD0, PD1
OV
DD
Input Hysteresis
V
0.1
5
V
HYST
CLK at GND or V
5
5
DD
Digital Input Leakage Current
DI
µA
pF
IN
PD0 and PD1 at OGND or OV
DD
Digital Input Capacitance
DC
IN
DIGITAL OUTPUTS (D7–D0, A/B)
0.2 x
Output Voltage Low
Output Voltage High
V
I
= 200µA
SINK
V
V
OL
OV
DD
0.8 x
OV
V
I = 200µA
SOURCE
OH
DD
Tri-State Leakage Current
Tri-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
I
5
µA
pF
LEAK
C
5
OUT
V
2.7
1.8
3.0
3.6
V
V
DD
Digital Output Supply Voltage
OV
V
DD
DD
4
_______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, f
= 7.5MHz, C
= C = C
REFN COM
DD
DD
REFIN
DD
L
CLK
REFP
= 0.33µF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
A
PARAMETER
SYMBOL
CONDITIONS
Normal operating mode, f = 1.875MHz
MIN
TYP
MAX
UNITS
IN
4.0
5.0
at -0.5dB FS, CLK input from GND to V
DD
Idle mode (tri-state), f = 1.875MHz at -
IN
4.0
2.2
0.1
1.0
0.1
0.1
0.1
mA
0.5dB FS, CLK input from GND to V
DD
Analog Supply Current
I
DD
Standby mode, CLK input from GND to
V
DD
Shutdown mode, CLK = GND or V
PD0 = PD1 = OGND
,
DD
5.0
5.0
5.0
µA
Normal operating mode,
mA
f
IN
= 1.875MHz at -0.5dB FS, C ≈ 10pF
L
Idle mode (tri-state), DC input, CLK =
GND or V PD0 = OV , PD1 = OGND
DD,
DD
Digital Output Supply Current
(Note 3)
I
ODD
Standby mode, DC input, CLK = GND or
PD0 = OGND, PD1 = OV
µA
V
DD,
DD
Shutdown mode, CLK = GND or V
PD0 = PD1 = OGND
,
DD
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
50% of CLK to 50% of data, Figure 5
(Note 4)
t
t
1
1
1
6
6
6
8.5
8.5
8.5
ns
ns
ns
DOA
DOB
DA/B
CLK Fall to CHB Output Data
Valid
50% of CLK to 50% of data, Figure 5
(Note 4)
CLK Rise/Fall to A/B Rise/Fall
Time
50% of CLK to 50% of A/B, Figure 5
(Note 4)
t
PD1 Rise to Output Enable
PD1 Fall to Output Disable
CLK Duty Cycle
t
PD0 = OV
PD0 = OV
5
5
ns
ns
%
%
EN
DD
t
DIS
DD
50
10
CLK Duty-Cycle Variation
Wake-Up Time from Shutdown
Mode
t
(Note 5)
(Note 5)
20
µs
WAKE, SD
Wake-Up Time from Standby
Mode
t
5.5
2
µs
ns
WAKE, ST
Digital Output Rise/Fall Time
20% to 80%
INTERCHANNEL CHARACTERISTICS
f
f
= 1.875MHz at -0.5dB FS,
= 0.3MHz at -0.5dB FS (Note 6)
IN,X
Crosstalk Rejection
-75
dB
IN,Y
Amplitude Matching
Phase Matching
f
f
= 1.875MHz at -0.5dB FS (Note 7)
= 1.875MHz at -0.5dB FS (Note 7)
0.03
0.03
dB
IN
Degrees
IN
_______________________________________________________________________________________
5
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, f
= 7.5MHz, C
= C = C
REFN COM
DD
DD
REFIN
DD
L
CLK
REFP
= 0.33µF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
A
Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dB FS referenced to the
amplitude of the digital output. SNR and THD are calculated using HD2 through HD6.
Note 3: The power consumption of the output driver is proportional to the load capacitance (C ).
L
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: SINAD settles to within 0.5dB of its typical value.
Note 6: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the
second channel. FFTs are performed on each channel. The parameter is specified as power ratio of the first and second
channel FFT test tone bins.
Note 7: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
Typical Operating Characteristics
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, differential input at -0.5dB FS, f
=
DD
DD
REFIN
DD
L
CLK
7.500567MHz at 50% duty cycle, T = +25°C, unless otherwise noted.)
A
FFT PLOT CHANNEL A (DIFFERENTIAL INPUTS,
FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS,
FFT PLOT CHANNEL A (DIFFERENTIAL INPUTS,
8192-POINT DATA RECORD)
8192-POINT DATA RECORD)
8192-POINT DATA RECORD)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
f
f
f
= 7.500567MHz
= 1.000747MHz
= 3.020553MHz
f
f
f
= 7.500567MHz
= 1.000747MHz
= 3.020553MHz
f
f
f
= 7.500567MHz
= 3.020553MHz
= 1.000747MHz
CLK
INA
INB
CLK
INA
INB
CLK
INA
INB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
A
= A = -0.5dB FS
A
INA
= A = -0.5dB FS
INB
A
= A = -0.5dB FS
INA INB
INA
INB
HD3
f
INB
HD2
HD2
HD3
HD2
f
INA
HD3
f
INB
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS,
TWO-TONE IMD PLOT (DIFFERENTIAL INPUTS,
8192-POINT DATA RECORD)
8192-POINT DATA RECORD)
0
0
f
f
f
= 7.500567MHz
= 3.020553MHz
= 1.000747MHz
f
f
f
= 7.500567MHz
= 1.8MHz
= 2.3MHz
CLK
INA
INB
CLK
IN1
IN2
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
A
= A = -0.5dB FS
A = -7dB FS
INA
INB
IN
f
f
IN2
IN1
HD2
HD3
f
INA
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
6
_______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, differential input at -0.5dB FS, f
=
DD
DD
REFIN
DD
L
CLK
7.500567MHz at 50% duty cycle, T = +25°C, unless otherwise noted.)
A
FFT PLOT CHANNEL A (SINGLE-ENDED INPUTS,
FFT PLOT CHANNEL B (SINGLE-ENDED INPUTS,
8192-POINT DATA RECORD)
8192-POINT DATA RECORD)
0
0
f
f
f
= 7.500567MHz
= 1.000747MHz
= 3.020553MHz
= A = -0.5dB FS
f
f
f
= 7.500567MHz
= 1.000747MHz
= 3.020553MHz
= A = -0.5dB FS
CLK
INA
INB
CLK
INA
INB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
A
INA
A
INA
INB
INB
HD2
HD3
HD2
HD3
f
INA
f
INB
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHANNEL A (SINGLE-ENDED INPUTS,
FFT PLOT CHANNEL B (SINGLE-ENDED INPUTS,
8192-POINT DATA RECORD)
8192-POINT DATA RECORD)
0
0
f
f
f
= 7.500567MHz
= 3.020553MHz
= 1.000747MHz
= A = -0.5dB FS
f
f
f
= 7.500567MHz
= 3.020553MHz
= 1.000747MHz
= A = -0.5dB FS
CLK
INA
INB
CLK
INA
INB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
A
INA
A
INA
INB
INB
INB
HD3
HD2
f
f
HD2
INA
HD3
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT (SINGLE-ENDED INPUTS,
8192-POINT DATA RECORD)
0
f
f
f
= 7.500567MHz
= 1.8MHz
= 2.3MHz
= -7dB FS
CLK
IN1
IN2
-10
-20
-30
-40
-50
-60
-70
-80
-90
A
IN
f
f
IN2
IN1
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
7
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, differential input at -0.5dB FS, f
=
DD
DD
REFIN
DD
L
CLK
7.500567MHz at 50% duty cycle, T = +25°C, unless otherwise noted.)
A
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
50
49
48
47
46
45
44
43
42
50
49
48
47
46
45
44
CHANNEL A
CHANNEL B
CHANNEL A
43
CHANNEL B
42
0
10
100
0
10
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
-45
-50
-55
-60
-65
-70
-75
-80
-85
85
80
75
70
65
60
55
50
45
CHANNEL A
CHANNEL B
CHANNEL A
CHANNEL B
0
10
100
0
10
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
8
_______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, differential input at -0.5dB FS, f
=
DD
DD
REFIN
DD
L
CLK
7.500567MHz at 50% duty cycle, T = +25°C, unless otherwise noted.)
A
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT POWER
60
60
50
40
30
20
10
0
f
IN
= 2.017059MHz
f
IN
= 2.017059MHz
50
40
30
20
10
0
-10
-30
-25
-20
-15
-5
0
-30
-20
-10
0
ANALOG INPUT POWER (dB FS)
ANALOG INPUT POWER (dB FS)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
-30
-40
-50
80
70
60
50
40
30
f
IN
= 2.017059MHz
f
= 2.017059MHz
IN
-60
-70
-10
ANALOG INPUT POWER (dB FS)
-30
-25
-20
-15
-5
0
-10
ANALOG INPUT POWER (dB FS)
-30
-25
-20
-15
-5
0
_______________________________________________________________________________________
9
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, differential input at -0.5dB FS, f
=
DD
DD
REFIN
DD
L
CLK
7.500567MHz at 50% duty cycle, T = +25°C, unless otherwise noted.)
A
SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
SIGNAL-TO-NOISE AND DISTORTION
vs. SAMPLING RATE
50
50
49
48
47
46
45
f
IN
= 2.017059MHz
f
IN
= 2.017059MHz
49
48
47
46
45
0
5
10
15
20
0
5
10
15
20
f
(MHz)
f
(MHz)
CLK
CLK
TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
-50
-55
-60
-65
-70
-75
-80
80
75
70
65
60
55
50
f
= 2.017059MHz
f
IN
= 2.017059MHz
IN
0
5
10
15
20
0
5
10
15
20
f
(MHz)
f
(MHz)
CLK
CLK
10 ______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, differential input at -0.5dB FS, f
=
DD
DD
REFIN
DD
L
CLK
7.500567MHz at 50% duty cycle, T = +25°C, unless otherwise noted.)
A
SIGNAL-TO-NOISE AND DISTORTION
vs. CLOCK DUTY CYCLE
SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
50
49
48
47
46
45
50
f = 2.017059MHz
IN
f
= 2.017059MHz
IN
49
48
47
46
45
40
45
50
55
60
40
45
50
55
60
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
-60
-62
-64
-66
-68
-70
-72
-74
-76
-78
-80
80
78
76
74
72
70
68
66
64
62
60
f
IN
= 2.017059MHz
f = 2.017059MHz
IN
40
45
50
55
60
40
45
50
55
60
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
______________________________________________________________________________________ 11
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, differential input at -0.5dB FS, f
=
DD
DD
REFIN
DD
L
CLK
7.500567MHz at 50% duty cycle, T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
0
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
0.30
0.25
0.20
0.15
0.10
0.05
0
0.30
0.25
0.20
0.15
0.10
0.05
0
V
= 1.024V
REFIN
V
= 1.024V
REFIN
CHANNEL A
CHANNEL A
CHANNEL B
-0.05
-0.10
-0.05
-0.10
CHANNEL B
10
-40
-15
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
REFERENCE VOLTAGE
vs. TEMPERATURE
INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY
0.5130
0.5125
0.5120
0.5115
0.5110
0.5105
0.5100
0.5130
6
4
V
DD
= V
V
= V
REFIN
DD REFIN
SMALL-SIGNAL
BANDWIDTH
-20dB FS
0.5125
0.5120
0.5115
0.5110
0.5105
0.5100
2
0
-2
-4
-6
-8
-10
FULL-POWER
BANDWIDTH
-0.5dB FS
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
(V)
-40
-15
10
35
60
85
1
10
100
1000
V
DD
TEMPERATURE (°C)
ANALOG INPUT FREQUENCY (MHz)
12 ______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(V
= 3.0V, OV
= 1.8V, V
= V
(internal reference), C ≈ 10pF at digital outputs, differential input at -0.5dB FS, f
=
DD
DD
REFIN
DD
L
CLK
7.500567MHz at 50% duty cycle, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SAMPLING RATE
SUPPLY CURRENT
vs. INPUT FREQUENCY
MAX1191 toc34
7
6
5
4
3
2
1
0
0.9
0.8
0.7
0.6
0.5
0.4
4.3
4.2
4.1
4.0
3.9
3.8
f
IN
= 2.017059MHz
DIGITAL SUPPLY CURRENT
ANALOG SUPPLY CURRENT
A
B
C
0
5
10
(MHz)
15
20
0
1
2
3
4
f
CLK
f
IN
(MHz)
A: ANALOG SUPPLY CURRENT (I ) - INTERNAL AND BUFFERED EXTERNAL
DD
REFERENCE MODES
B: ANALOG SUPPLY CURRENT (I ) - UNBUFFERED EXTERNAL REFERENCE MODE
DD
C: DIGITAL SUPPLY CURRENT (I ) - ALL REFERENCE MODES
ODD
Pin Description
PIN
NAME
INA-
FUNCTION
1
Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
Analog Ground. Connect all GND pins together.
2
INA+
GND
CLK
3, 5, 10
4
6
7
Converter Clock Input
INB+
INB-
Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
Converter Power Input. Connect to a 2.7V to 3.6V power supply. Bypass V
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
to GND with a
DD
8, 9, 28
11
V
DD
OGND
OV
Output Driver Ground
Output Driver Power Input. Connect to a 1.8V to V
power supply. Bypass OV
to GND with a
DD
DD
12
DD
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
13
14
15
16
D7
Tri-State Digital Output. D7 is the most significant bit (MSB).
Tri-State Digital Output
D6
D5
D4
Tri-State Digital Output
Tri-State Digital Output
Channel Data Indicator. This digital output indicates channel A data (A/B = 1) or channel B data
(A/B = 0) is present on the output.
17
A/B
18
19
20
21
22
D3
D2
Tri-State Digital Output
Tri-State Digital Output
D1
Tri-State Digital Output
D0
Tri-State Digital Output. D0 is the least significant bit (LSB).
Power-Down Digital Input 1. See Table 3.
PD1
______________________________________________________________________________________ 13
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Pin Description (continued)
PIN
23
NAME
PD0
FUNCTION
Power-Down Digital Input 0. See Table 3.
Reference Input. Internally pulled up to V
24
REFIN
COM
.
DD
25
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
Negative Reference I/O. Conversion range is (V
capacitor.
- V
REFN
). Bypass REFN to GND with a 0.33µF
REFP
26
REFN
Positive Reference I/O. Conversion range is (V
capacitor.
- V
). Bypass REFP to GND with a 0.33µF
REFP
REFN
27
REFP
EP
—
Exposed Paddle. Internally connected to pin 3. Externally connect EP to GND.
Detailed Description
The MAX1191 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for channel A and
5.5 clock cycles for channel B.
+
T/H
x2
∑
-
FLASH
ADC
DAC
1.5 BITS
STAGE 1
At each stage, flash ADCs convert the held input volt-
ages into a digital code. The following digital-to-analog
converter (DAC) converts the digitized result back into
an analog voltage, which is then subtracted from the
original held input signal. The resulting error signal is
then multiplied by two, and the product is passed along
to the next pipeline stage where the process is repeated
until the signal has been processed by all stages. Digital
error correction compensates for ADC comparator off-
sets in each pipeline stage and ensures no missing
codes. Figure 2 shows the MAX1191 functional diagram.
INA+
INA-
STAGE 2
STAGE 7
T/H
DIGITAL ERROR CORRECTION
D0–D7
Figure 1. Pipeline Architecture—Stage Blocks
V
GND
DD
INA+
PIPELINE
ADC
A
/
T/H
/
DEC
MAX1191
PD0
PD1
POWER
CONTROL
INA-
OV
DD
REFIN
REFP
COM
REFN
REFERENCE
SYSTEM AND
BIAS
D0–D7
A/B
/
OUTPUT
DRIVERS
MULTIPLEXER
CIRCUITS
OGND
INB+
PIPELINE
ADC
/
T/H
/
DEC
CLK
TIMING
INB-
B
Figure 2. MAX1191 Functional Diagram
14 ______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
INTERNAL
COM
S5a
BIAS
S2a
C1a
S3a
S4a
S4b
INA+
INA-
OUT
OUT
C2a
C2b
S4c
S1
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
HOLD
HOLD
INTERNAL
BIAS
TRACK
TRACK
COM
S5a
S2a
C1a
S3a
S4a
S4b
INB+
INB-
OUT
OUT
C2a
C2b
S4c
S1
MAX1191
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
Figure 3. Internal T/H Circuits
fier input, and open simultaneously with S1, sampling
the input waveform. Switches S4a, S4b, S5a, and S5b
are then opened before switches S3a and S3b connect
capacitors C1a and C1b to the output of the amplifier
and switch S4c is closed. The resulting differential volt-
ages are held on capacitors C2a and C2b. The ampli-
fiers charge capacitors C1a and C1b to the same
Input Track-and-Hold (T/H) Circuits
Figure 3 displays a simplified functional diagram of the
input T/H circuits. In track mode, switches S1, S2a,
S2b, S4a, S4b, S5a, and S5b are closed. The fully dif-
ferential circuits sample the input signals onto the two
capacitors (C2a and C2b) through switches S4a and
S4b. S2a and S2b set the common mode for the ampli-
______________________________________________________________________________________ 15
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Table 1. Reference Modes
V
REFIN
REFERENCE MODE
Internal reference mode. V
each with a 0.33µF capacitor.
is internally generated to be 0.512V. Bypass REFP, REFN, and COM
REF
>0.8 x V
DD
Buffered external reference mode. An external 1.024V 10% reference voltage is applied to
1.024V 10%
<0.3V
REFIN. V is internally generated to be V /2. Bypass REFP, REFN, and COM each with a
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
REF
REFIN
Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference
sources. V
is the difference between the externally applied V
and V . Bypass REFP,
REFN
REF
REFP
REFP
COM
REFN, and COM each with a 0.33µF capacitor.
values originally held on C2a and C2b. These values
are then presented to the first stage quantizers and iso-
late the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the MAX1191
to track and sample/hold analog inputs of high frequen-
cies (>Nyquist). Both ADC inputs (INA+, INB+, INA-,
and INB-) can be driven either differentially or single
ended. Match the impedance of INA+ and INA-, as well
as INB+ and INB-, and set the common-mode voltage
62.5µA
MAX1191
1.75V
1.5V
4kΩ
0µA
to midsupply (V /2) for optimum performance.
DD
Analog Inputs and Reference
Configurations
4kΩ
The MAX1191 full-scale analog input range is
V
REF
with a common-mode input range of V /2 0.2V. V
62.5µA
DD
and V
REF
. The
REFN
REFN
is the difference between V
REFP
MAX1191 provides three modes of reference operation.
The voltage at REFIN (V
ation mode (Table 1).
) sets the reference oper-
REFIN
1.25V
In internal reference mode, connect REFIN to V
or
DD
leave REFIN unconnected. V
is internally generated
REF
to be 0.512V 3%. COM, REFP, and REFN are low-
impedance outputs with V = V /2, V = V /2
Figure 4. Unbuffered External Reference Mode Impedance
COM
= V /2 - V
DD
REFP
/2. Bypass REFP,
DD
+ V
/2, and V
REF
REFN
DD
REF
V
to (V /2 +0.256V) 10%, and drive V
to
REFN
REFP
DD
REFN, and COM each with a 0.33µF capacitor.
(V /2 - 0.256V) 10%. Bypass REFP, REFN, and COM
DD
In buffered external reference mode, apply a 1.024V
10% at REFIN. In this mode, COM, REFP, and REFN
each with a 0.33µF capacitor.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
are low-impedance outputs with V
= V /2, V
DD
=
COM
= V /2 - V
DD
REFP
/4.
REFIN
V
/2 + V
/4, and V
DD
REFIN
REFN
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
Clock Input (CLK)
CLK accepts a CMOS-compatible signal level. Since
the interstage conversion of the device depends on the
repeatability of the rising and falling edges of the exter-
nal clock, use a clock with low jitter and fast rise and
fall times (<2ns). In particular, sampling occurs on the
rising edge of the clock signal, requiring this edge to
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for COM, REFP, and REFN. With their buffers shut
down, these nodes become high-impedance inputs
(Figure 4) and can be driven through separate, external
reference sources. Drive V
to V /2 10%, drive
DD
COM
16 ______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB
t
CLK
t
CL
t
CH
CLK
t
t
DOA
DOB
A/B
CHB
D0B
CHA
D1A
CHB
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
t
DA/B
D0–D7
D1B
Figure 5. System Timing Diagram
provide lowest possible jitter. Any significant aperture
jitter would limit the SNR performance of the on-chip
ADCs as follows:
2 x V
REF
V
REF
= V
- V
1LSB =
REFP REFN
256
V
REF
V
REF
1111 1111
1111 1110
1111 1101
1
SNR = 20 × log
2 × π × f × t
IN
AJ
where f represents the analog input frequency and
AJ
IN
1000 0001
1000 0000
0111 1111
t
is the time of the aperture jitter.
(COM)
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines. The MAX1191
clock input operates with a V /2 voltage threshold
DD
and accepts a 50% 10% duty cycle (see Typical
Operating Characteristics).
0000 0011
0000 0010
0000 0001
0000 0000
-128 -127 -126 -125
-1
0
+1
+125 +126 +127 +128
System Timing Requirements
Figure 5 shows the relationship between the clock, ana-
log inputs, A/B indicator, and the resulting output data.
Channel A (CHA) and channel B (CHB) are simultane-
ously sampled on the rising edge of the clock signal
(CLK) and the resulting data is multiplexed at the out-
put. CHA data is updated on the rising edge and CHB
data is updated on the falling edge of the CLK. The A/B
indicator follows CLK with a typical delay time of 6ns
and remains high when CHA data is updated and low
when CHB data is updated. Including the delay
through the output latch, the total clock-cycle latency is
5 clock cycles for CHA and 5.5 clock cycles for CHB.
(COM)
INPUT VOLTAGE (LSB)
Figure 6. Transfer Function
Digital Output Data (D0–D7),
Channel Data Indicator (A/ )
B
D0–D7 and A/B are TTL/CMOS-logic compatible. The
digital output coding is offset binary (Table 2, Figure 6).
The capacitive load on the digital outputs D0–D7
should be kept as low as possible (<15pF) to avoid
large digital currents feeding back into the analog por-
tion of the MAX1191 and degrading its dynamic perfor-
mance. Buffers on the digital outputs isolate them from
______________________________________________________________________________________ 17
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Table 2. Output Codes vs. Input Voltage
DIFFERENTIAL INPUT VOLTAGE
(IN+ - IN-)
DIFFERENTIAL INPUT
(LSB)
OFFSET BINARY
(D7–D0)
OUTPUT DECIMAL CODE
127
+127
(+ full scale – 1 LSB)
1111 1111
1111 1110
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
255
254
129
128
127
1
V
×
×
×
×
REF
128
126
128
1
128
0
+126
(+ full scale – 2 LSB)
V
REF
V
+1
0 (bipolar zero)
-1
REF
V
REF
128
1
-V
×
REF
128
127
128
-127
-V
×
REF
(- full scale + 1 LSB)
128
128
-128 (- full scale)
0
-V
×
REF
Table 3. Power Logic
INTERNAL
REFERENCE
PD0
PD1
POWER MODE
ADC
CLOCK DISTRIBUTION
OUTPUTS
0
0
1
1
0
1
0
1
Shutdown
Standby
Off
Off
On
On
Off
On
On
On
Off
On
On
On
Tri-state
Tri-state
Tri-state
On
Idle
Normal operating
heavy capacitive loads. To improve the dynamic perfor-
mance of the MAX1191, add 100Ω resistors in series
with the digital outputs close to the MAX1191. Refer to
the MAX1193 Evaluation Kit schematic for an example
of the digital outputs driving a digital buffer through
100Ω series resistors.
wake-up time from shutdown mode is dominated by the
time required to charge the capacitors at REFP, REFN,
and COM. In internal reference mode and buffered
external reference mode, the wake-up time is typically
20µs. When operating in the unbuffered external refer-
ence mode, the wake-up time is dependent on the
external reference drivers. When the outputs transition
from tri-state to on, the last converted word is placed
on the digital outputs.
Power Modes (PD0, PD1)
The MAX1191 has four power modes that are con-
trolled with PD0 and PD1. Four power modes allow the
MAX1191 to efficiently use power by transitioning to a
low-power state when conversions are not required
(Table 3).
In standby mode, the reference and clock distribution
circuits are powered up, but the pipeline ADCs are
unpowered and the outputs are in tri-state. The wake-
up time from standby mode is dominated by the 5.5µs
required to activate the pipeline ADCs. When the out-
puts transition from tri-state to on, the last converted
word is placed on the digital outputs.
Shutdown mode offers the most dramatic power sav-
ings by shutting down all the analog sections of the
MAX1191 and placing the outputs in tri-state. The
18 ______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
R4
600Ω
R5
600Ω
MAX1191
R
ISO
22Ω
R1
600Ω
INA-
C
IN
5pF
V
= 0.5V TO 1.5V
COM
V
= 85mV
SIG
P-P
R2
300Ω
R3
600Ω
R6
600Ω
R7
600Ω
COM
A = 6V/V
V
V
COM
= V /2
DD
R8
600Ω
R9
600Ω
R
ISO
22Ω
INA+
C
IN
5pF
R10
600Ω
R11
600Ω
RESISTOR NETWORKS
OPERATIONAL AMPLIFIERS
RESISTOR NETWORKS ENSURE PROPER THERMAL AND TOLERANCE
MATCHING. FOR R1, R2, AND R3 USE A NETWORK SUCH AS VISHAY'S
3R MODEL NUMBER 300192. FOR R4–R11, USE A NETWORK SUCH AS
VISHAY'S 4R MODEL NUMBER 300197.
CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/
DUAL/QUAD +3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT.
CONNECT THE POSITIVE SUPPLY RAIL (V ) TO 3V. CONNECT THE
CC
NEGATIVE SUPPLY RAIL (V ) TO GROUND. DECOUPLE V WITH A
EE
CC
0.1µF CAPACITOR TO GROUND.
Figure 7. DC-Coupled Differential Input Driver
In idle mode, the pipeline ADCs, reference, and clock
distribution circuits are powered, but the outputs are
forced to tri-state. The wake-up time from idle mode is
dominated by the 5ns required for the output drivers to
start from tri-state. When the outputs transition from tri-
state to on, the last converted word is placed on the
digital outputs.
Applications Information
The circuit of Figure 7 operates from a single 3V supply
and accommodates a wide 0.5V to 1.5V input common-
mode voltage range for the analog interface between
an RF quadrature demodulator (differential, DC-cou-
pled signal source) and a high-speed ADC.
Furthermore, the circuit provides required SINAD and
SFDR to demodulate a wideband (BW = 3.84MHz),
In the normal operating mode, all sections of the
MAX1191 are powered.
QAM-16 communication link. R
isolates the op amp
ISO
output from the ADC capacitive input to prevent ringing
and oscillation. C filters high-frequency noise.
IN
______________________________________________________________________________________ 19
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
REFP
25Ω
INA+
22pF
1kΩ
R
ISO
50Ω
V
IN
0.1µF
0.1µF
1
2
6
5
4
T1
INA+
COM
INA-
V
IN
MAX4108
C
IN
22pF
100Ω
100Ω
1kΩ
N.C.
COM
2.2µF
0.1µF
3
REFN
0.1µF
MINICIRCUITS
TT1-6-KK81
R
ISO
50Ω
25Ω
25Ω
INA-
INB+
C
22pF
IN
22pF
22pF
MAX1191
REFP
MAX1191
R
1kΩ
ISO
50Ω
V
IN
0.1µF
0.1µF
1
2
3
6
5
4
T1
INB+
V
IN
MAX4108
C
IN
22pF
100Ω
100Ω
1kΩ
N.C.
2.2µF
0.1µF
REFN
0.1µF
MINICIRCUITS
TT1-6-KK81
R
ISO
50Ω
25Ω
INB-
INB-
C
IN
22pF
22pF
Figure 8. Transformer-Coupled Input Drive
Figure 9. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive
anced, and each of the ADC inputs only requires half
the signal swing compared to single-ended mode.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1191 for
optimum performance. Connecting the center tap of the
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended applica-
tion. Amplifiers such as the MAX4108 provide high
speed, high bandwidth, low noise, and low distortion to
maintain the input signal integrity.
transformer to COM provides a V /2 DC level shift to
DD
the input. Although a 1:1 transformer is shown, a step-
up transformer can be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, can also improve the overall
distortion.
Buffered External Reference Drives
Multiple ADCs
The buffered external reference mode allows for more
control over the MAX1191 reference voltage and allows
multiple converters to use a common reference. To
drive one MAX1191 in buffered external reference
mode, the external circuit must sink 0.7µA, allowing one
reference circuit to easily drive the REFIN of multiple
converters to 1.024V 10%.
In general, the MAX1191 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for high input frequencies. In
differential input mode, even-order harmonics are lower
as both inputs (INA+, INA- and/or INB+, INB-) are bal-
20 ______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
3V
V
DD
24
27
26
25
REFIN
REFP
REFN
COM
1.248V
0.1µF
0.1µF
0.33µF
0.33µF
0.33µF
1
2
N = 1
MAX6061
10Hz
LOWPASS
FILTER
1%
MAX1191
20kΩ
3
1%
90.9kΩ
1µF
GND
3V
0.1µF
15Ω
5
3
NOTE: ONE FRONT-END REFERENCE
1.023V
CIRCUIT PROVIDES 15mA OF OUTPUT
1
DRIVE AND SUPPORTS OVER 1000 MAX1191s.
4
V
DD
MAX4250
24
27
2.2µF
0.1µF
REFIN
REFP
2
0.1µF
N = 1000
0.33µF
MAX1191
26
25
REFN
COM
0.33µF
0.33µF
GND
Figure 10. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
Figure 10 shows the MAX6061 precision bandgap ref-
erence used as a common reference for multiple con-
verters. The 1.248V output of the MAX6061 is divided
down to 1.023V as it passes through a one-pole, 10Hz,
lowpass filter to the MAX4250. The MAX4250 buffers
the 1.023V reference before its output is applied to the
MAX1191. The MAX4250 provides a low offset voltage
(for high gain accuracy) and a low noise level.
Unbuffered External Reference Drives
Multiple ADCs
The unbuffered external reference mode allows for pre-
cise control over the MAX1191 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal refer-
ence, allowing REFP, REFN, and COM to be driven
directly by a set of external reference sources.
______________________________________________________________________________________ 21
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
3V
2.500V
1
0.1µF
2
V
DD
27
26
25
REFP
REFN
COM
MAX6066
1%
30.1kΩ
3
0.33µF
0.33µF
0.33µF
N = 1
1.748V
MAX1191
24
3
REFIN
47Ω
1/4
1
MAX4254
2
330µF
6V
10µF
6V
1µF
1.47kΩ
47Ω
NOTE: ONE FRONT-END
REFERENCE CIRCUIT
SUPPORTS UP TO 160 MAX1191s.
GND
1%
10.0kΩ
1.498V
5
1/4
7
MAX4254
6
330µF
10µF
2.2µF
0.1µF
6V
6V
3V
1.47kΩ
47Ω
1%
UNCOMMITTED
V
DD
10.0kΩ
1MΩ
27
26
25
REFP
REFN
COM
1.248V
10
0.1µF
0.33µF
0.33µF
0.33µF
N = 160
12
13
1/4
4
8
1/4
14
MAX4254
24
MAX1191
9
330µF
6V
MAX4254
REFIN
1MΩ
10µF
6V
11
1.47kΩ
1%
49.9kΩ
GND
Figure 11. External Unbuffered Reference Driving 160 ADCs with MAX4254 and MAX6066
Figure 11 shows the MAX6066 precision bandgap ref-
erence used as a common reference for multiple con-
verters. The 2.500V output of the MAX6066 is followed
by a 10Hz lowpass filter and precision voltage-divider.
The MAX4254 buffers the taps of this divider to provide
the 1.75V, 1.5V, and 1.25V sources to drive REFP,
REFN, and COM. The MAX4254 provides a low offset
voltage and low noise level. The individual voltage fol-
lowers are connected to 10Hz lowpass filters, which fil-
ter both the reference-voltage and amplifier noise to a
level of 3nV/√Hz. The 1.75V and 1.25V reference volt-
ages set the differential full-scale range of the associat-
ed ADCs at 0.5V.
The common power supply for all active components
removes any concern regarding power-supply
sequencing when powering up or down.
With the outputs of the MAX4252 matching better than
0.1%, the buffers and subsequent lowpass filters sup-
port as many as 160 MAX1191s.
22 ______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
A/B
MAX2451
INA+
INA-
0°
DSP
90°
POST-
MAX1191
PROCESSING
INB+
INB-
DOWNCONVERTER
÷
8
Figure 12. Typical QAM Receiver Application
ably on the same side as the ADC, using surface-
mount devices for minimum inductance. Bypass V to
Typical QAM Demodulation Application
Quadrature amplitude modulation (QAM) is frequently
used in digital communications. Typically found in
spread-spectrum-based systems, a QAM signal repre-
sents a carrier frequency modulated in both amplitude
and phase. At the transmitter, modulating the baseband
signal with quadrature outputs, a local oscillator fol-
lowed by subsequent upconversion can generate the
QAM signal. The result is an in-phase (I) and a quadra-
ture (Q) carrier component, where the Q component is
90° phase shifted with respect to the in-phase compo-
nent. At the receiver, the QAM signal is demodulated
into analog I and Q components. Figure 12 displays the
demodulation process performed in the analog domain
using the MAX1191 dual-matched, 3V, 8-bit ADC and
the MAX2451 quadrature demodulator to recover and
digitize the I and Q baseband signals. Before being dig-
itized by the MAX1191, the mixed-down signal compo-
nents can be filtered by matched analog filters, such as
Nyquist or pulse-shaping filters. The filters remove
unwanted images from the mixing process, thereby
enhancing the overall signal-to-noise (SNR) perfor-
mance and minimizing intersymbol interference.
DD
GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF bipolar capacitor. Bypass OV to OGND with a
DD
0.1µF ceramic capacitor in parallel with a 2.2µF bipolar
capacitor. Bypass REFP, REFN, and COM each to
GND with a 0.33µF ceramic capacitor.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity. Use
a split ground plane arranged to match the physical
location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC’s package.
Connect the MAX1191 exposed backside paddle to
GND. Join the two ground planes at a single point such
that the noisy digital ground currents do not interfere
with the analog ground plane. The ideal location of this
connection can be determined experimentally at a
point along the gap between the two ground planes,
which produces optimum results. Make this connection
with a low-value, surface-mount resistor (1Ω to 5Ω), a
ferrite bead, or a direct short. Alternatively, all ground
pins could share the same ground plane, if the ground
plane is sufficiently isolated from any noisy, digital sys-
tems ground plane (e.g., downstream output buffer or
DSP ground plane).
Grounding, Bypassing,
and Board Layout
The MAX1191 requires high-speed board layout design
techniques. Refer to the MAX1193 Evaluation Kit data
sheet for a board layout reference. Locate all bypass
capacitors as close to the device as possible, prefer-
Route high-speed digital signal traces away from the
sensitive analog traces of either channel. Make sure to
isolate the analog input lines to each respective con-
verter to minimize channel-to-channel crosstalk. Keep
all signal lines short and free of 90° turns.
______________________________________________________________________________________ 23
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Dynamic Parameter Definitions
CLK
Aperture Jitter
Figure 13 depicts the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
ANALOG
INPUT
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 13).
t
AD
t
AJ
SAMPLED
DATA (T/H)
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
HOLD
TRACK
TRACK
T/H
Figure 13. T/H Aperture Timing
Static Parameter Definitions
SNR
= 6.02 × N + 1.76
dB[max]
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the MAX1191 are measured using
the end-point method.
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
the fundamental and the DC offset.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
for a full-scale sinusoidal input waveform is computed
from:
Offset Error
Ideally, the midscale MAX1191 transition occurs at 0.5
LSB above midscale. The offset error is the amount of
deviation between the measured transition point and
the ideal transition point.
SINAD - 1.76
Gain Error
Ideally, the full-scale MAX1191 transition occurs at 1.5
LSB below full-scale. The gain error is the amount of
deviation between the measured transition point and
the ideal transition point with the offset error removed.
ENOB =
6.02
24 ______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
Third-Order Intermodulation (IM3)
IM3 is the power of the worst third-order intermodula-
tion product relative to the input power of either input
tone when two tones, f1 and f2, are present at the
inputs. The third-order intermodulation products are (2
x f1 f2), (2 x f2 f1). The individual input tone levels
are at -7dB FS.
2
2
2
2
2
V
+ V
+ V
+ V
+ V
6
2
3
4
5
THD = 20 × log
V
1
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supplies are moved
5%.
where V is the fundamental amplitude, and V –V are
1
2
6
the amplitudes of the 2nd- through 6th-order harmonics.
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
Small-Signal Bandwidth
A small -20dB FS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by -3dB.
Note that the track/hold (T/H) performance is usually
the limiting factor for the small-signal input bandwidth.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2
f1). The individual input tone levels are at -7dB FS.
Full-Power Bandwidth
A large -0.5dB FS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
Chip Information
TRANSISTOR COUNT: 7925
PROCESS: CMOS
______________________________________________________________________________________ 25
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
D2
0.15
C A
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
PIN # 1
I.D.
0.15
C
B
PIN # 1 I.D.
0.35x45
E/2
E2/2
C
(NE-1) X
e
L
E2
E
k
L
DETAIL A
e
(ND-1) X
e
C
C
L
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0140
C
2
26 ______________________________________________________________________________________
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0140
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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