MAX1196ECM+T [MAXIM]
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, EXPOSED PAD, MO-136, TQFP-48;
| 型号： | MAX1196ECM+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, EXPOSED PAD, MO-136, TQFP-48 |
| 文件： | 总23页 (文件大小：632K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2600; Rev 0; 9/02
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
General Description
Features
The MAX1196 is a 3V, dual 8-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1196
is optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumenta-
tion, and digital communications. This ADC operates
from a single 2.7V to 3.6V supply, consuming only
87mW while delivering a typical signal-to-noise and dis-
tortion (SINAD) of 48.4dB at an input frequency of
20MHz and a sampling rate of 40Msps. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters can also be operated with single-
ended inputs. In addition to low operating power, the
MAX1196 features a 3mA sleep mode as well as a
0.1µA power-down mode to conserve power during idle
periods.
ꢀ Single 2.7V to 3.6V Operation
ꢀ Excellent Dynamic Performance
48.4dB/44.7dB SINAD at f = 20MHz/200MHz
68.9dB/53dBc SFDR at f = 20MHz/200MHz
IN
IN
ꢀ -72dB Interchannel Crosstalk at f = 20MHz
IN
ꢀ Low Power
87mW (Normal Operation)
9mW (Sleep Mode)
0.3µW (Shutdown Mode)
ꢀ 0.05dB Gain and 0.05° Phase Matching
ꢀ Wide 1V
Differential Analog Input Voltage
P-P
Range
ꢀ 400MHz -3dB Input Bandwidth
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired for applications requiring
increased accuracy or a different input voltage range.
ꢀ On-Chip 2.048V Precision Bandgap Reference
ꢀ User-Selectable Output Format—Two’s
Complement or Offset Binary
ꢀ Pin-Compatible 8-Bit and 10-Bit Upgrades
Available
The MAX1196 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output format
can be set to two’s complement or straight offset binary
through a single control pin. The device provides for a
separate output power supply of 1.7V to 3.6V for flexible
interfacing. The MAX1196 is available in a 7mm × 7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1196ECM
*EP = Exposed pad.
-40°C to +85°C
48 TQFP-EP*
Pin Configuration
Pin-compatible, nonmultiplexed higher speed versions of
the MAX1196 are also available. Refer to the MAX1198
data sheet for 100Msps, the MAX1197 data sheet for
60Msps, and the MAX1195 data sheet for 40Msps.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1186 data sheet. With the N.C. pins of the
MAX1196 internally pulled down to ground, this ADC
becomes a drop-in replacement for the MAX1186.
COM
1
2
36 N.C.
35 N.C.
34 OGND
V
DD
GND
INA+
INA-
3
4
33 OV
32 OV
DD
DD
5
Applications
V
6
31 OGND
30 A/B
DD
MAX1196
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical Imaging
Battery-Powered Instrumentation
WLAN, WWAN, WLL, MMDS Modems
Set-Top Boxes
GND
INB-
INB+
GND
7
8
29 N.C.
N.C.
N.C.
N.C.
N.C.
9
28
27
26
25
10
11
12
V
DD
CLK
VSAT Terminals
TQFP-EP
Functional Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
V
, OV
to GND .............................................. -0.3V to +3.6V
Continuous Power Dissipation (T = +70°C)
DD
DD
A
OGND to GND...................................................... -0.3V to +0.3V
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
REFIN, REFOUT, REFP, REFN, COM,
DD
CLK to GND............................................-0.3V to (V
OE, PD, SLEEP, T/B,
+ 0.3V)
DD
D7A/B–D0A/B, A/B to OGND...............-0.3V to (OV
+ 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= OV
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
DD
DD
resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs (Note 5), f
= 40MHz, T = T
to T
,
IN
P-P
CLK
A
MIN
MAX
L
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DC ACCURACY
Resolution
8
Bits
Integral Nonlinearity
INL
f
f
= 7.51MHz (Note 1)
0.3
1
1
LSB
IN
IN
= 7.51MHz, no missing codes
Differential Nonlinearity
DNL
0.15
LSB
guaranteed (Note 1)
Offset Error
4
4
%FS
%FS
Gain Error
Gain Temperature Coefficient
ANALOG INPUT
100
1.0
ppm/°C
Differential Input Voltage Range
V
Differential or single-ended inputs
Switched capacitor load
V
V
DIFF
Common-Mode Input Voltage
Range
V
/ 2
DD
0.2
V
CM
Input Resistance
R
140
5
kΩ
IN
Input Capacitance
C
pF
IN
CONVERSION RATE
Maximum Clock Frequency
f
40
MHz
CLK
CHA
CHB
5
Clock
Cycles
Data Latency
5.5
DYNAMIC CHARACTERISTICS (f
= 40MHz)
SNR
CLK
f
f
f
f
f
f
f
f
= 2MHz at -1dB FS
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 101MHz at -1dB FS
= 2MHz at -1dB FS
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 101MHz at -1dB FS
48.7
48.7
48.5
48
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
Signal-to-Noise Ratio
dB
dB
47.5
47
48.6
48.7
48.4
48
Signal-to-Noise and Distortion
SINAD
2
_______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= OV
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
DD
DD
resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs (Note 5), f
= 40MHz, T = T
to T
,
IN
P-P
CLK
A
MIN
MAX
L
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T = +25°C.)
A
UNITS
PARAMETER
SYMBOL
CONDITIONS
= 2MHz at -1dB FS
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 101MHz at -1dB FS
= 2MHz at -1dB FS
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 101MHz at -1dB FS
MIN
TYP
69
MAX
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
INA or B
70
INA or B
Spurious-Free Dynamic Range
Third-Harmonic Distortion
SFDR
dBc
60
68.9
65
INA or B
INA or B
-72
-73.7
-75
-67
INA or B
INA or B
HD3
dBc
INA or B
INA or B
= 1.997MHz at -7dB FS,
= 2.046MHz at -7dB FS
= 1.997MHz at -7dB FS,
= 2.046MHz at -7dB FS
IN1(A or B)
IN2(A or B)
IN1(A or B)
IN2(A or B)
Intermodulation Distortion
(First Five Odd-Order IMDs) (Note 2)
dBc
dBc
IMD
IM3
-68
Third-Order Intermodulation
Distortion (Note 2)
-73.2
= 2MHz at -1dB FS
= 7.5MHz at -1dB FS
= 20MHz at -1dB FS
= 101MHz at -1dB FS
-70
-69
-69
-63
500
400
INA or B
INA or B
INA or B
INA or B
Total Harmonic Distortion
(First Four Harmonics)
THD
dBc
-57
Small-Signal Bandwidth
Full-Power Bandwidth
Input at -20dB FS, differential inputs
Input at -1dB FS, differential inputs
MHz
MHz
FPBW
f
f
= 106MHz at -1dB FS,
= 118MHz at -1dB FS
IN1(A or B)
IN2(A or B)
Gain Flatness (12MHz Spacing)
(Note 3)
0.05
dB
ns
Aperture Delay
t
1
2
2
AD
Aperture Jitter
t
1dB SNR degradation at Nyquist
ps
RMS
AJ
Overdrive Recovery Time
For 1.5 × full-scale input
ns
INTERNAL REFERENCE (REFIN = REFOUT through 10kΩ resistor; REFP, REFN, and COM levels are generated internally.)
2.048
3%
Reference Output Voltage
V
(Note 4)
(Note 5)
(Note 5)
(Note 5)
V
REFOUT
Positive Reference Output
Voltage
V
2.012
V
REFP
REFN
Negative Reference Output
Voltage
V
0.988
V
V
/ 2
DD
Common-Mode Level
V
V
V
COM
0.1
Differential Reference Output
Voltage Range
1.024
3%
∆V
∆V
= V
- V
REFP REFN
REF
REF
Reference Temperature
Coefficient
TC
100
ppm/°C
REF
_______________________________________________________________________________________
3
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= OV
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
DD
DD
resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs (Note 5), f
= 40MHz, T = T
to T
,
IN
P-P
CLK
A
MIN
MAX
L
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BUFFERED EXTERNAL REFERENCE (V
= 2.048V)
(Note 5)
REFIN
Positive Reference Output
V
2.012
0.988
V
V
V
REFP
Voltage
Negative Reference Output
Voltage
V
(Note 5)
(Note 5)
REFN
V
/ 2
DD
Common-Mode Level
V
COM
0.1
Differential Reference Output
Voltage Range
1.024
2%
∆V
∆V
= V
- V
REFN
V
REF
REF
REFP
REFIN Resistance
R
>50
MΩ
mA
REFIN
Maximum REFP, COM Source
Current
I
I
5
SOURCE
Maximum REFP, COM Sink Current
Maximum REFN Source Current
Maximum REFN Sink Current
I
-250
250
-5
µA
µA
SINK
SOURCE
I
mA
SINK
UNBUFFERED EXTERNAL REFERENCE (V
= AGND, reference voltage applied to REFP, REFN, and COM)
REFIN
R
R
,
REFP
REFP, REFN Input Resistance
Measured between REFP and REFN
4
kΩ
pF
V
REFN
REFP, REFN, COM Input
Capacitance
C
15
IN
Differential Reference Input
Voltage Range
1.024
10%
∆V
∆V
= V
- V
REFP REFN
REF
REF
V
/ 2
5%
DD
COM Input Voltage Range
REFP Input Voltage
V
V
V
COM
REFP
REFN
V
COM
+
V
∆V
/ 2
REF
V
-
COM
REFN Input Voltage
V
V
∆V
/ 2
REF
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
0.8 ×
V
DD
CLK
Input High Threshold
Input Low Threshold
V
V
V
IH
0.8 ×
OV
PD, OE, SLEEP, T/B
CLK
DD
0.2 ×
V
DD
V
IL
0.2 ×
OV
PD, OE, SLEEP, T/B
DD
4
_______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= OV
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
DD
DD
resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs (Note 5), f
= 40MHz, T = T
to T
,
IN
P-P
CLK
A
MIN
MAX
L
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Hysteresis
V
0.15
V
HYST
I
V
V
= V
= 0
= OV
DD
20
20
IH
IH
IL
DD
Input Leakage
µA
pF
I
IL
Input Capacitance
C
5
IN
DIGITAL OUTPUTS (D0A/B–D7A/B, A/B)
Output Voltage Low
V
I
I
= -200µA
0.2
10
V
V
OL
SINK
OV
0.2
-
DD
Output Voltage High
V
= 200µA
SOURCE
OH
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
I
OE = OV
OE = OV
µA
pF
LEAK
DD
C
5
OUT
DD
V
2.7
1.7
3
3
3.6
3.6
V
V
DD
OV
DD
Operating, f
applied to both channels
= 20MHz at -1dB FS
INA&B
29
36
mA
Analog Supply Current
Output Supply Current
Analog Power Dissipation
I
VDD
Sleep mode
3
Shutdown, clock idle, PD = OE = OV
0.1
20
µA
DD
DD
DD
Operating, f
= 20MHz at -1dB FS
INA&B
8
mA
applied to both channels (Note 6)
I
OVDD
Sleep mode
3
3
µA
Shutdown, clock idle, PD = OE = OV
10
Operating, f
= 20MHz at -1dB FS
INA&B
87
108
applied to both channels
mW
PDISS
PSRR
Sleep mode
9
0.3
3
Shutdown, clock idle, PD = OE = OV
60
µW
Offset, V
5%
DD
Power-Supply Rejection
mV/V
Gain, V
5%
3
DD
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
t
t
C = 20pF (Notes 1, 7)
6
6
6
8.25
8.25
ns
ns
ns
DOA
DOB
DA/B
L
CLK Fall to CHB Output Data
Valid
C = 20pF (Notes 1, 7)
L
Clock Rise/Fall to A/B Rise/Fall
Time
t
OE Fall to Output Enable Time
OE Rise to Output Disable Time
t
5
5
ns
ns
ENABLE
t
DISABLE
12.5
1.5
CLK Pulse Width High
t
Clock period: 25ns (Note 7)
ns
CH
_______________________________________________________________________________________
5
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= OV
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
DD
DD
resistor, V = 2V
(differential with respect to COM), C = 10pF at digital outputs (Note 5), f
= 40MHz, T = T
to T
,
IN
P-P
CLK
A
MIN
MAX
L
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12.5
1.5
CLK Pulse Width Low
Wake-Up Time
t
Clock period: 25ns (Note 7)
ns
CL
Wake-up from sleep mode
1
t
µs
WAKE
Wake-up from shutdown mode (Note 8)
20
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
f
f
f
= 20MHz at -1dB FS (Note 9)
= 20MHz at -1dB FS (Note 10)
= 20MHz at -1dB FS (Note 11)
-72
dB
dB
INA or B
INA or B
INA or B
Gain Matching
0.05
0.05
Phase Matching
Degrees
Note 1: Guaranteed by design. Not subject to production testing.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two
applied input signals with the same magnitude (peak-to-peak) at f and f
.
IN2
IN1
Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 6: Typical digital output current at f
= 20MHz. For digital output currents vs. analog input frequency, see the Typical
INA&B
Operating Characteristics.
Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock level to
50% of the data output level.
Note 8: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.
Note 9: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level. Crosstalk is
measured by calculating the power ratio of the fundamental of each channel’s FFT.
Note 10:Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT.
Note 11:Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
6
_______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics
(V
DD
= OV
= 3V, V
= 2.048V, differential input at -1dB FS, f
= 40MHz, C ≈ 10pF, T = +25°C, unless otherwise noted.)
DD
REFIN
CLK L A
FFT PLOT CHA
FFT PLOT CHB
FFT PLOT CHA
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
f
f
f
= 40.0005678MHz
= 1.958036MHz
= 7.534287MHz
f
f
f
= 40.0005678MHz
= 1.958036MHz
= 7.534287MHz
f
f
f
= 40.0005678MHz
= 7.534287MHz
= 1.958036MHz
CLK
INA
INB
CLK
INA
INB
CLK
INA
INB
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
INA
f
INA
AINA = AINB = -1dB FS
COHERENT SAMPLING
AINA = AINB = -1dB FS
COHERENT SAMPLING
AINA = AINB = -1dB FS
COHERENT SAMPLING
f
INB
f
INB
HD3
HD2
HD3
HD2
f
INA
HD2
HD3
f
INB
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
FFT PLOT CHA
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
f
f
= 40.0005678MHz
= 19.88798MHz
= 40.49374MHz
f
f
f
= 40.0005678MHz
= 7.534287MHz
= 1.958036MHz
CLK
INA
INB
f
f
f
= 40.0005678MHz
= 19.88798MHz
= 40.49374MHz
CLK
INA
INB
CLK
INA
INB
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
INB
f
INB
AINA = AINB = -1dB FS
COHERENT SAMPLING
AINA = AINB = -1dB FS
COHERENT SAMPLING
AINA = AINB = -1dB FS
COHERENT SAMPLING
f
INA
HD2
HD3
HD2
f
HD2
INB
f
f
INA
INA
HD3
HD3
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
FFT PLOT CHA
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
f
f
= 40.0005678MHz
= 40.49374MHz
= 19.88798MHz
f
f
f
= 40.0005678MHz
= 40.49374MHz
= 19.88798MHz
f
f
f
= 40.001536MHz
= 1.997147MHz
= 2.045977MHz
CLK
INA
INB
CLK
INA
INB
CLK
INA
INB
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
AINA = AINB = -1dB FS
COHERENT SAMPLING
AINA = AINB = -1dB FS
COHERENT SAMPLING
AIN = -7dB FS
INA
COHERENT SAMPLING
f
INB
f
f
IN1
IN2
f
INA
HD2
HD3
HD2
f
INB
HD3
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ANALOG INPUT FREQUENCY (MHz)
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
7
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)
(V
DD
= OV
= 3V, V
= 2.048V, differential input at -1dB FS, f
= 40MHz, C ≈ 10pF, T = +25°C, unless otherwise noted.)
DD
REFIN
CLK L A
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT FREQUENCY
TWO-TONE IMD PLOT
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
50
0
50
49
48
47
46
45
44
f
f
f
= 40.001536MHz
= 9.95643MHz
= 10.024799MHz
AIN = -7dB FS
COHERENT SAMPLING
CHB
CLK
IN1
IN2
CHB
-10
-20
-30
-40
-50
-60
-70
-80
-90
49
48
47
46
45
44
43
f
IN1
f
IN2
CHA
CHA
0
40
80
120
160
200
7
8
9
10
11
12
13
0
40
80
120
160
200
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
FULL-POWER INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL
-38
90
80
70
60
50
40
2
1
0
-48
-58
-68
-78
-88
CHB
CHA
-1
-2
-3
-4
CHA
CHB
0
40
80
120
160
200
0
40
80
120
160
200
1
10
100
1000
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE RATIO
SMALL-SIGNAL INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL
SIGNAL-TO-NOISE + DISTORTION
vs. INPUT POWER (f = 19.88798MHz)
vs. INPUT POWER (f = 19.88798MHz)
IN
IN
2
55
55
50
45
40
35
30
25
V
= 100mV
P-P
IN
1
0
50
45
40
35
30
25
-1
-2
-3
-4
1
10
100
1000
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
ANALOG INPUT FREQUENCY (MHz)
INPUT POWER (dB FS)
INPUT POWER (dB FS)
8
_______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)
(V
DD
= OV
= 3V, V
= 2.048V, differential input at -1dB FS, f
= 40MHz, C ≈ 10pF, T = +25°C, unless otherwise noted.)
DD
REFIN
CLK
L
A
SNR/SINAD, THD/SFDR
vs. CLOCK DUTY CYCLE
TOTAL HARMONIC DISTORTION
vs. INPUT POWER (f = 19.88798MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT POWER (f = 19.88798MHz)
IN
IN
80
70
60
50
40
30
-45
72
67
62
57
52
47
42
f
= 7.534287MHz
SFDR
INA/B
-50
-55
-60
-65
-70
-75
THD
SNR
SINAD
40
44
48
52
56
60
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
CLOCK DUTY CYCLE (%)
INPUT POWER (dB FS)
INPUT POWER (dB FS)
INTEGRAL NONLINEARITY
(131,072-POINT DATA RECORD)
DIFFERENTIAL NONLINEARITY
(131,072-POINT DATA RECORD)
0.5
0.4
0.5
0.4
f
= 7.534287MHz
IN
f
= 7.534287MHz
IN
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
0
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE,
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE V
= 2.048V
EXTERNAL REFERENCE V
= 2.048V
REFIN
REFIN
0.2
0
0.5
0.4
0.3
0.2
0.1
0
CHA
CHB
-0.2
-0.4
-0.6
-0.8
CHB
CHA
-0.1
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
9
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)
(V
DD
= OV
= 3V, V
= 2.048V, differential input at -1dB FS, f
= 40MHz, C ≈ 10pF, T = +25°C, unless otherwise noted.)
DD
REFIN
CLK
L
A
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. ANALOG INPUT FREQUENCY
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
33
2.0324
2.0320
2.0316
2.0312
2.0308
2.0304
2.0300
8
7
6
5
4
3
32
31
30
29
28
27
26
25
-40
-15
10
35
60
85
2.70 2.85 3.00 3.15 3.30 3.45 3.60
0
4
8
12
16
20
TEMPERATURE (°C)
V
(V)
ANALOG INPUT FREQUENCY (MHz)
DD
SNR/SINAD, THD/SFDR
vs. SAMPLING SPEED
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
100
2.040
2.036
2.032
2.028
2.024
2.020
SNR
SFDR
f
= 20MHz
IN
80
60
40
SINAD
20
0
-20
-40
-60
-80
-100
THD
0
10
20
30
40
50
60
-40
-15
10
35
60
85
SAMPLING SPEED (Msps)
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
1
COM
Common-Mode Voltage Input/Output. Bypass to GND with a ≥0.1µF capacitor.
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF.
Analog Ground
2, 6, 11, 14, 15
V
DD
3, 7, 10, 13, 16
GND
INA+
INA-
INB-
INB+
CLK
4
5
Channel ‘A’ Positive Analog Input. For single-ended operation, connect signal source to INA+.
Channel ‘A’ Negative Analog Input. For single-ended operation, connect INA- to COM.
Channel ‘B’ Negative Analog Input. For single-ended operation, connect INB- to COM.
Channel ‘B’ Positive Analog Input. For single-ended operation, connect signal source to INB+.
Converter Clock Input
8
9
12
10 ______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
T/B selects the ADC digital output format.
High: Two’s complement.
17
T/B
Low: Straight offset binary.
Sleep Mode Input.
18
19
20
SLEEP High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.
High-Active Power-Down Input.
High: Power-down mode
Low: Normal operation
PD
Low-Active Output Enable Input.
High: Digital outputs disabled
Low: Digital outputs enabled
OE
21–29, 35, 36
30
N.C.
A/B
No Connection. Do not connect.
A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0) to be
present on the output. A/B follows the external clock signal with typically 6ns delay.
31, 34
OGND Output-Driver Ground
Output-Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with
32, 33
OV
DD
0.1µF.
Three-State Digital Output, Bit 0. Depending on status of A/B, output data reflects channel A or
channel B data.
37
38
39
40
41
42
43
44
D0A/B
D1A/B
D2A/B
D3A/B
D4A/B
D5A/B
D6A/B
D7A/B
Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A or
channel B data.
Three-State Digital Output, Bit 7 (MSB). Depending on status of A/B, output data reflects channel A or
channel B data.
45
46
47
REFOUT Internal Reference Voltage Output. Can be connected to REFIN through a resistor or a resistor-divider.
REFIN Reference Input. V = 2 × (V - V ). Bypass to GND with a ≥0.1µF capacitor.
REFIN
REFP
REFN
REFP
Positive Reference I/O. Conversion range is (V
- V
REFN
). Bypass to GND with a ≥0.1µF capacitor.
REFP
Negative Reference I/O. Conversion range is (V
capacitor.
- V
REFN
). Bypass to GND with a ≥0.1µF
REFP
48
REFN
______________________________________________________________________________________ 11
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
2-BIT FLASH
ADC
2-BIT FLASH
ADC
STAGE 1
STAGE 2
STAGE 6
STAGE 7
STAGE 1
STAGE 2
STAGE 6
STAGE 7
DIGITAL ALIGNMENT LOGIC
8
DIGITAL ALIGNMENT LOGIC
8
T/H
T/H
V
V
INB
INA
OUTPUT MULTIPLEXER
8
D0A/B–D7A/B
Figure 1. Pipelined Architecture—Stage Blocks
S4b, S5a, and S5b are closed. The fully differential cir-
cuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the amplifier input, and
open simultaneously with S1, sampling the input wave-
form. Switches S4a, S4b, S5a, and S5b are then
opened before switches S3a and S3b connect capaci-
tors C1a and C1b to the output of the amplifier and
switch S4c is closed. The resulting differential voltages
are held on capacitors C2a and C2b. The amplifiers are
used to charge capacitors C1a and C1b to the same
values originally held on C2a and C2b. These values
are then presented to the first stage quantizers and iso-
late the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the MAX1196
to track and sample/hold analog inputs of high frequen-
cies (>Nyquist). Both ADC inputs (INA+, INB+, INA-,
and INB-) can be driven either differentially or single
ended. Match the impedance of INA+ and INA-, as well
as INB+ and INB-, and set the common-mode voltage
Detailed Description
The MAX1196 uses a 7-stage, fully differential, pipelined
architecture (Figure 1) that allows for high-speed con-
version while minimizing power consumption. Samples
taken at the inputs move progressively through the
pipeline stages every half clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is 5 clock cycles for CHA and 5.5 clock cycles
for CHB.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all 7 stages.
Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (5
clock cycles later) and CHB data is updated on the
falling edge (5.5 clock cycles later) of the clock signal.
The A/B indicator follows the clock signal with a typical
delay time of 6ns and remains high when CHA data is
updated and low when CHB data is updated.
to midsupply (V /2) for optimum performance.
DD
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1196 is determined by
the internally generated voltage difference between
REFP (V /2 + V
/4) and REFN (V /2 - V
/4).
DD
REFIN
DD
REFIN
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track and
hold mode. In track mode, switches S1, S2a, S2b, S4a,
The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose.
12 ______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
INTERNAL
COM
S5a
BIAS
S2a
C1a
S3a
S4a
S4b
INA+
INA-
OUT
OUT
C2a
C2b
S4c
S1
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
HOLD
HOLD
INTERNAL
BIAS
TRACK
TRACK
COM
S5a
S2a
C1a
S3a
S4a
S4b
INB+
INB-
OUT
OUT
C2a
C2b
S4c
S1
MAX1196
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
Figure 2. MAX1196 T/H Amplifiers
The MAX1196 provides three modes of reference
operation:
10kΩ) or resistor-divider, if an application requires a
reduced full-scale range. For stability and noise-filtering
purposes, bypass REFIN with a ≥0.1µF capacitor to
GND. In internal reference mode, REFOUT, COM,
REFP, and REFN become low-impedance outputs.
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In buffered external reference mode, adjust the refer-
ence voltage levels externally by applying a stable and
accurate voltage at REFIN. In this mode, COM, REFP,
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
______________________________________________________________________________________ 13
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
and REFN are outputs. REFOUT can be left open or
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
connected to REFIN through a >10kΩ resistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut down,
these nodes become high-impedance inputs and can be
driven through separate, external reference sources.
The MAX1196 clock input operates with a voltage
threshold set to V /2. Clock inputs with a duty cycle
DD
other than 50%, must meet the specifications for high
and low periods as stated in the Electrical
Characteristics.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
System Timing Requirements
Figure 3 shows the relationship between clock and
analog input, A/B indicator, and the resulting valid
CHA/CHB data output. CHA and CHB data are sam-
pled on the rising edge of the clock signal. Following
the rising edge of the 5th clock cycles, the digitized
value of the original CHA sample is presented at the
output, followed one-half clock cycle later by the digi-
tized value of the original CHB sample.
Clock Input (CLK)
The MAX1196’s CLK input accepts CMOS-compatible
clock signal. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
A channel selection signal (A/B indicator) allows the
user to determine which output data represents which
input channel. With A/B = 1, digitized data from CHA is
present at the output and with A/B = 0 digitized data
from CHB is present.
1
SNR = 20 × log
2 × π × f × t
IN
AJ
where f represents the analog input frequency and
IN
t
AJ
is the time of the aperture jitter.
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB
t
CLK
t
t
CL
CH
CLK
t
t
DOA
DOB
A/B
CHB
D0B
CHA
D1A
CHB
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
t
DA/B
D0A/B–D7A/B
D1B
Figure 3. System Timing Diagram
14 ______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (OE),
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1196 offers two power-save modes—sleep
and full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to 3mA.
Channel Selection (A/B)
All digital outputs, D0A/B–D7A/B (CHA or CHB data) and
A/B are TTL/CMOS-logic compatible. The output coding
can be chosen to be either offset binary or two’s comple-
ment (Table 1) controlled by a single pin (T/B). Pull T/B
low to select offset binary and high to activate two’s com-
plement output coding. The capacitive load on the digital
outputs D0A/B–D7A/B should be kept as low as possible
(<15pF), to avoid large digital currents that could feed
back into the analog portion of the MAX1196, thereby
degrading its dynamic performance. Using buffers on
the digital outputs of the ADCs can further isolate the
digital outputs from heavy capacitive loads. To further
improve the dynamic performance of the MAX1196,
small-series resistors (e.g., 100Ω) can be added to the
digital output paths, close to the MAX1196.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended-to-differential converters. The internal
reference provides a V /2 output voltage for level-shift-
DD
ing purposes. The input is buffered and then split to a
voltage follower and inverter. One lowpass filter per
amplifier suppresses some of the wideband noise asso-
ciated with high-speed operational amplifiers. The user
Figure 4 displays the timing relationship between out-
put enable and data output valid as well as power-
down/wake-up and data output valid.
can select the R
and C values to optimize the filter
IN
ISO
performance, to suit a particular application. For the
application in Figure 5, an R of 50Ω is placed before
ISO
the capacitive load to prevent ringing and oscillation.
The 22pF C capacitor acts as a small filter capacitor.
IN
OE
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent solu-
tion to convert a single-ended source signal to a fully dif-
ferential signal, required by the MAX1196 for optimum
performance. Connecting the center tap of the trans-
t
t
DISABLE
ENABLE
OUTPUT
D0A/B–D7A/B
HIGH-Z
HIGH-Z
VALID DATA
former to COM provides a V /2 DC level shift to the
DD
input. Although a 1:1 transformer is shown, a step-up
transformer can be selected to reduce the drive require-
ments. A reduced signal swing from the input driver, such
as an op amp, can also improve the overall distortion.
Figure 4. Output Timing Diagram
Table 1. MAX1196 Output Codes for Differential Inputs
STRAIGHT OFFSET
DIFFERENTIAL INPUT
VOLTAGE*
TWO’S COMPLEMENT
DIFFERENTIAL INPUT
BINARY
T/B = 0
T/B = 1
V
× 255/256
+Full Scale - 1LSB
+1LSB
1111 1111
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
0111 1111
0000 0001
0000 0000
1111 1111
1000 0001
1000 0000
REF
V
× 1/256
0
REF
Bipolar Zero
-1LSB
-V
× 1/256
REF
-V
× 255/256
× 256/256
-Full Scale + 1LSB
-Full Scale
REF
REF
-V
= V
*V
- V
REFN
REF
REFP
______________________________________________________________________________________ 15
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
+5V
0.1µF
LOWPASS FILTER
INA-
MAX4108
R
IS0
50Ω
0.1µF
300Ω
C
IN
22pF
0.1µF
-5V
600Ω
600Ω
+5V
300Ω
0.1µF
COM
INA+
+5V
0.1µF
0.1µF
600Ω
INPUT
0.1µF
0.1µF
LOWPASS FILTER
MAX4108
300Ω
300Ω
MAX4108
R
IS0
C
IN
22pF
50Ω
-5V
-5V
+5V
300Ω
300Ω
600Ω
MAX1196
0.1µF
0.1µF
LOWPASS FILTER
INB-
MAX4108
R
IS0
50Ω
0.1µF
300Ω
C
IN
22pF
-5V
600Ω
+5V
600Ω
600Ω
300Ω
0.1µF
0.1µF
0.1µF
+5V
INPUT
LOWPASS FILTER
0.1µF
MAX4108
300Ω
300Ω
INB+
MAX4108
R
IS0
50Ω
C
IN
22pF
-5V
0.1µF
-5V
300Ω
300Ω
600Ω
Figure 5. Typical Application for Single-Ended-to-Differential Conversion
16 ______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
In general, the MAX1196 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
Buffered External Reference Drives
Multiple ADCs
Multiple-converter systems based on the MAX1196 are
well suited for use with a common reference voltage.
The REFIN pin of those converters can be connected
directly to an external reference source.
A precision bandgap reference like the MAX6062 gen-
erates an external DC level of 2.048V (Figure 8), and
exhibits a noise voltage density of 150nV/√Hz. Its out-
put passes through a one-pole lowpass filter (with 10Hz
cutoff frequency) to the MAX4250, which buffers the
reference before its output is applied to a second 10Hz
lowpass filter. The MAX4250 provides a low offset volt-
age (for high gain accuracy) and a low noise level. The
passive 10Hz filter following the buffer attenuates noise
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended applica-
tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to main-
tain the integrity of the input signal.
REFP
25Ω
INA+
22pF
1kΩ
1kΩ
R
ISO
50Ω
V
IN
0.1µF
0.1µF
INA+
COM
INA-
6
5
4
1
2
T1
V
IN
MAX4108
C
IN
22pF
100Ω
100Ω
N.C.
COM
2.2µF
0.1µF
3
REFN
0.1µF
MINICIRCUITS
TT1-6-KK81
R
ISO
50Ω
25Ω
25Ω
INA-
INB+
C
22pF
IN
22pF
22pF
MAX1196
REFP
MAX1196
R
1kΩ
ISO
50Ω
V
IN
0.1µF
0.1µF
6
5
4
INB+
1
2
3
T1
V
IN
MAX4108
C
IN
22pF
100Ω
100Ω
1kΩ
N.C.
2.2µF
0.1µF
REFN
0.1µF
MINICIRCUITS
TT1-6-KK81
R
ISO
50Ω
25Ω
INB-
INB-
C
IN
22pF
22pF
Figure 6. Transformer-Coupled Input Drive
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive
______________________________________________________________________________________ 17
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
3.3V
3.3V
0.1µF
N.C.
29
31
32
1
REFOUT
REFIN
REFP
2.048V
0.1µF
1
MAX6062
3
0.1µF
16.2kΩ
REFN
N = 1
5
2
3
4
2
162Ω
COM
1
MAX1196
MAX4250
2
1µF
100µF
10Hz LOWPASS
FILTER
0.1µF 0.1µF 0.1µF
10Hz LOWPASS
FILTER
2.2µF
10V
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN CAN BE USED WITH UP TO 1000 ADCs.
0.1µF
29
31
32
1
N.C.
REFOUT
REFIN
REFP
N = 1000
0.1µF
REFN
MAX1196
2
COM
0.1µF 0.1µF 0.1µF
Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
produced in the voltage-reference and buffer stages.
This filtered noise density, which decreases for higher
frequencies, meets the noise levels specified for preci-
sion-ADC operation.
ual voltage followers are connected to 10Hz lowpass fil-
ters, which filter both the reference-voltage and amplifier
noise to a level of 3nV/√Hz. The 2.0V and 1.0V reference
voltages set the differential full-scale range of the asso-
ciated ADCs at 2V . The 2.0V and 1.0V buffers drive
P-P
Unbuffered External Reference Drives
Multiple ADCs
the ADCs’ internal ladder resistances between them.
Note that the common power supply for all active com-
ponents removes any concern regarding power-supply
sequencing when powering up or down.
Connecting each REFIN to analog ground disables the
internal reference of each device, allowing the internal
reference ladders to be driven directly by a set of exter-
nal reference sources. Followed by a 10Hz lowpass fil-
ter and precision voltage-divider, the MAX6066
generates a DC level of 2.500V. The buffered outputs of
this divider are set to 2.0V, 1.5V, and 1.0V, with an
accuracy that depends on the tolerance of the divider
resistors.
With the outputs of the MAX4252 matching better than
0.1%, the buffers and subsequent lowpass filters can
be replicated to support as many as 32 ADCs. For
applications requiring more than 32 matched ADCs, a
voltage-reference and divider string common to all con-
verters is highly recommended.
Those three voltages are buffered by the MAX4252,
which provides low noise and low DC offset. The individ-
18 ______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
3.3V
0.1µF
N.C.
29
31
32
1
REFOUT
REFIN
REFP
1
MAX6066
3
2.0V
3.3V
4
4
4
21.5kΩ
REFN
N = 1
2.0V AT 8mA
2
3
2
1/4 MAX4252
1
47kΩ
MAX1196
2
COM
10µF
6V
330µF
6V
11
21.5kΩ
1.47kΩ
0.1µF 0.1µF 0.1µF
1.5V
3.3V
1.5V AT 0mA
5
6
1/4 MAX4252
7
47kΩ
1µF
10µF
330µF
11
6V
6V
21.5kΩ
2.2µF
10V
1.47kΩ
0.1µF
3.3V
0.1µF
1.0V
3.3V
1.0V AT -8mA
47kΩ
10
9
1/4 MAX4252
8
21.5kΩ
21.5kΩ
330µF
6V
29
31
32
1
N.C.
10µF
11
REFOUT
REFIN
REFP
MAX4254 POWER-SUPPLY
BYPASSING. PLACE CAPACITOR
AS CLOSE AS POSSIBLE TO
THE OP AMP.
6V
1.47kΩ
N = 32
REFN
MAX1196
2
COM
0.1µF 0.1µF 0.1µF
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN CAN BE USED WITH UP TO 32 ADCs.
Figure 9. External Unbuffered Reference Drive With MAX4252 and MAX6066
component, where the Q component is 90 degrees
phase-shifted with respect to the in-phase component.
At the receiver, the QAM signal is divided down into its
I and Q components, essentially representing the mod-
ulation process reversed. Figure 10 displays the
demodulation process performed in the analog domain,
using the dual matched 3V, 8-bit ADC MAX1196, and
the MAX2451 quadrature demodulator to recover and
digitize the I and Q baseband signals. Before being
digitized by the MAX1196, the mixed-down signal com-
ponents can be filtered by matched analog filters, such
Typical QAM Demodulation Application
A frequently used modulation technique in digital com-
munications applications is quadrature amplitude mod-
ulation (QAM). Typically found in spread- spectrum-
based systems, a QAM signal represents a carrier fre-
quency modulated in both amplitude and phase. At the
transmitter, modulating the baseband signal with quad-
rature outputs, a local oscillator followed by subse-
quent up-conversion can generate the QAM signal. The
result is an in-phase (I) and a quadrature (Q) carrier
______________________________________________________________________________________ 19
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
A/B
MAX2451
INA+
INA-
0°
DSP
90°
POST-
MAX1196
PROCESSING
INB+
INB-
CHA AND CHB DATA
ALTERNATINGLY
AVAILABLE ON
DOWNCONVERTER
÷
8
8-BIT MULTIPLEXED
OUTPUT BUS.
Figure 10. Typical QAM Application Using the MAX1196
as Nyquist or pulse-shaping filters, which remove
unwanted images from the mixing process, thereby
enhancing the overall signal-to-noise (SNR) perfor-
mance and minimizing intersymbol interference.
high-speed digital signal traces away from the sensitive
analog traces of either channel. Make sure to isolate
the analog input lines to each respective converter to
minimize channel-to-channel crosstalk. Keep all signal
lines short and free of 90 degree turns.
Grounding, Bypassing,
and Board Layout
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the MAX1196 are measured using
the best-straight-line fit method.
The MAX1196 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass V , REFP, REFN, and COM with
DD
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV ) to OGND. Multilayer
DD
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output-driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi-
mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
(1Ω to 5Ω), a ferrite bead, or a direct short.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground plane (e.g.,
downstream output buffer or DSP ground plane). Route
20 ______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
CLK
harmonics of the input signal to the fundamental itself.
This is expressed as:
ANALOG
INPUT
2 +
2
2
2
V
V
+ V
+ V
5
2
3
4
THD = 20 × log
t
AD
V
1
t
AJ
SAMPLED
DATA (T/H)
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 5th-order
5
harmonics.
HOLD
TRACK
TRACK
T/H
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
Figure 11. T/H Aperture Timing
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst third-order (or higher)
intermodulation products. The individual input tone lev-
els are at -7dB full scale.
Pin-Compatible Upgrades
(Sampling Speed and Resolution)
SNR
= 6.02 × N + 1.76
dB dB
dB[max]
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
SAMPLING SPEED
8-BIT PART
10-BIT PART
(Msps)
N/A
MAX1185
MAX1183
MAX1182
MAX1180
MAX1190
MAX1186
20
MAX1195
MAX1197
MAX1198
N/A
40
60
100
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
120
MAX1196
40, multiplexed
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
Chip Information
TRANSISTOR COUNT: 11,601
PROCESS: CMOS
SINAD - 1.76
6.02
ENOB =
______________________________________________________________________________________ 21
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Functional Diagram
V
OGND
OV
DD
GND
DD
INA+
8
ADC
A/B
DEC
MUX
T/H
INA-
CLK
8
8
CONTROL
INB+
INB-
8
D7B–D0B
OR
OUTPUT
DRIVERS
ADC
DEC
T/H
D7A–D0A
OE
T/B
PD
SLEEP
REFERENCE
MAX1196
REFOUT
REFN COM REFP
REFIN
22 ______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX1196ECM-D
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, EXPOSED PAD, MO-136, TQFP-48
MAXIM
MAX1196ECM-T
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, EXPOSED PAD, MO-136, TQFP-48
MAXIM
MAX1197ECM
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-48
MAXIM
MAX1197ECM+D
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, EXPOSED PAD, TQFP-48
MAXIM
MAX1197ECM+TD
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, EXPOSED PAD, TQFP-48
MAXIM
MAX1197ECM-T
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-48
MAXIM
MAX1197ECM-TD
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-48
MAXIM
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
MAXIM
MAX1198ECM
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
MAXIM
MAX1198ECM+D
ADC, Flash Method, 8-Bit, 1 Func, 2 Channel, Parallel, 8 Bits Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MO-136AE, TQFP-48
MAXIM
©2020 ICPDF网 联系我们和版权申明