MAX1202BEPP+ [MAXIM]
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface;
| 型号： | MAX1202BEPP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface |
| 文件： | 总24页 (文件大小：2496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
General Description
Features
The MAX1202/MAX1203 are 12-bit data-acquisition sys-
tems specifically designed for use in applications with
mixed +5V (analog) and +3V (digital) supply voltages.
They operate with a single +5V analog supply or dual ±5V
analog supplies, and combine an 8-channel multiplexer,
high-bandwidth track/hold, and serial interface with high
conversion speed and low power consumption.
● 8-Channel Single-Ended or 4-Channel Differential
Inputs
● Operates from Single +5V or Dual ±5V Supplies
● User-Adjustable Output Logic Levels
(2.7V to 5.25V)
●
Low Power: 1.5mA (Operating Mode)
2μA (Power-Down Mode)
● Internal Track/Hold, 133kHz Sampling Rate
● Internal 4.096V Reference (MAX1202)
● SPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
● Software-Configurable Unipolar/Bipolar Inputs
● 20-Pin PDIP/SSOP
A 4-wire serial interface connects directly to SPI/
MICROWIRE® devices without external logic, and a serial
strobe output allows direct connection to TMS320-family
digital signal processors. The MAX1202/MAX1203 use
either the internal clock or an external serial-interface clock
to perform successive approximation analog-to-digital con-
versions. The serial interface operates at up to 2MHz.
Ordering Information
The MAX1202 features an internal 4.096V reference,
while the MAX1203 requires an external reference. Both
parts have a reference-buffer amplifier that simplifies gain
PIN-
PACKAGE
INL
(LSB)
PART
TEMP RANGE
MAX1202ACPP+
MAX1202BCPP+
MAX1202ACAP+
MAX1202BCAP+
0ºC to +70ºC
0ºC to +70ºC
0ºC to +70ºC
0ºC to +70ºC
20 PDIP
±1/2
±1
trim. They also have a V pin that is the power supply for
the digital outputs. Output logic levels (3V, 3.3V, or 5V) are
determined by the value of the voltage applied to this pin.
L
20 PDIP
20 SSOP
20 SSOP
±1/2
±1
These devices provide a hard-wired SHDN pin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the devices. A
quick turn-on time enables the MAX1202/MAX1203 to
be shut down between conversions, allowing the user
to optimize supply currents. By customizing power-down
between conversions, supply current can drop below
10μA at reduced sampling rates.
Ordering Information continued at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW
+
The MAX1202/MAX1203 are available in 20-pin SSOP
and PDIP packages, and are specified for the commercial
and extended temperature ranges.
20
V
DD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
19 SCLK
18 CS
3
MAX1202
MAX1203
Applications
● 5V/3V Mixed-Supply Systems
● Data Acquisition
● High-Accuracy Process Control
● Battery-Powered Instruments
● Medical Instruments
4
17 DIN
5
SSTRB
16
15 DOUT
14
6
V
7
L
8
13 GND
V
9
12 REFADJ
11 REF
SS
Typical Operating Circuit appears at end of data sheet.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
SHDN
10
PDIP/SSOP
19-1173; Rev 3; 3/12
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Absolute Maximum Ratings
V
to GND ............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
V ............................................................. -0.3V to (V
+ 0.3V)
PDIP (derate 11.11mW/°C above +70°C)....................889mW
SSOP (derate 8.00mW/°C above +70°C)....................640mW
Operating Temperature Ranges
L
DD
V
V
to GND.............................................................+0.3V to -6V
SS
to V ............................................................-0.3V to +12V
DD
SS
CH0–CH7 to GND.........................(V - 0.3V) to (V
CH0–CH7 Total Input Current ..........................................±20mA
+ 0.3V)
MAX1202_C_P/MAX1203_C_P..........................0°C to +70°C
MAX1202_E_P/MAX1203_E_P...................... -40°C to +85°C
Storage Temperature Range............................ -60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
SS
DD
REF to GND............................................. -0.3V to (V
REFADJ to GND....................................... -0.3V to (V
Digital Inputs to GND ............................... -0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
DD
DD
DD
Digital Outputs to GND................................-0.3V to (V + 0.3V)
L
Digital Output Sink Current ................................................25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
= +5V ±5%, V = 2.7V to 3.6V; V
= 0V or -5V ±5%; f
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
SCLK
DD
L
SS
cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin; T = T
REF
A MIN
to T
, unless otherwise noted.)
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution
RES
INL
12
Bits
MAX1202A/MAX1203A
±0.5
±1.0
±1.0
±3.0
±3
Relative Accuracy (Note 2)
LSB
MAX1202B/MAX1203B
Differential Nonlinearity
Offset Error
DNL
no missing codes over temperature
LSB
LSB
MAX1202 (all grades)
Gain Error (Note 3)
MAX1203A
MAX1203B
±1.5
±3
LSB
External reference,
4.096V
Gain Temperature Coefficient
External reference, 4.096V
±0.8
±0.1
ppm/°C
LSB
Channel-to-Channel Offset Matching
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096V , 133ksps, 2.0MHz external clock, bipolar-input mode)
P-P
Signal-to-Noise Plus Distortion Ratio
SINAD
70
dB
dB
Total Harmonic Distortion (up to the
5th Harmonic)
THD
-80
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
SFDR
80
dB
dB
V
= 4.096V , 65kHz (Note 4)
-85
4.5
IN
P-P
-3dB rolloff
MHz
kHz
Full-Power Bandwidth
800
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Electrical Characteristics (continued)
(V
= +5V ±5%, V = 2.7V to 3.6V; V
= 0V or -5V ±5%; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
DD
L
SS
SCLK
cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin; T = T
A MIN
REF
to T
, unless otherwise noted.)
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
CONVERSION RATE
Internal clock
5.5
6
10
Conversion Time (Note 5)
t
µs
CONV
External clock, 2MHz, 12 clocks/conversion
Track/Hold Acquisition Time
Aperture Delay
t
1.5
µs
ns
ACQ
10
< 50
1.7
Aperture Jitter
ps
Internal Clock Frequency
MHz
External compensation mode, 4.7µF
Internal compensation mode (Note 6)
Used for data transfer only
0.1
0.1
0
2.0
0.4
2.0
External Clock Frequency Range
MHz
ANALOG INPUT
Unipolar, V = 0V
SS
V
Input Voltage Range, Single-Ended
and Differential (Note 7)
REF
V
Bipolar, V = -5V
SS
±V
/2
REF
Multiplexer Leakage Current
Input Capacitance
On/off-leakage current, V
(Note 6)
= ±5V
±0.01 ±1
16
µA
pF
CH_
INTERNAL REFERENCE (MAX1202 only, reference-buffer enabled)
REF Output Voltage
T = +25°C
A
4.076 4.096 4.116
30
V
REF Short-Circuit Current
mA
MAX1202AC
±30
±30
±30
2.5
±50
V
REF
Temperature Coefficien
MAX1202AE
±60 ppm/°C
MAX1202B
Load Regulation (Note 8)
Capacitive Bypass at REF
0 to 0.5mA output load
mV
µF
Internal compensation mode
External compensation mode
0
4.7
Capacitive Bypass at REFADJ
REFADJAdjustment Range
0.01
µF
%
1.5
EXTERNAL REFERENCE AT REF (Reference buffer disabled, V
= 4.096V)
REF
V
50mV
+
DD
Input Voltage Range
2.50
12
V
Input Current
200
20
350
µA
kΩ
µA
Input Resistance
REF Input Current in Shutdown
V
= 0V
1.5
10
SHDN
V
50mV
-
DD
REFADJ Buffer Disable Threshold
V
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Electrical Characteristics (continued)
(V
= +5V ±5%, V = 2.7V to 3.6V; V
= 0V or -5V ±5%; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
DD
L
SS
SCLK
cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin; T = T
A MIN
REF
to T
, unless otherwise noted.)
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
EXTERNAL REFERENCE AT REFADJ
Internal compensation mode
External compensation mode
MAX1202
0
Capacitive Bypass at REF
µF
V/V
µA
4.7
1.68
1.64
Reference-Buffer Gain
REFADJ Input Current
MAX1203
MAX1202
±50
±5
MAX1203
POWER REQUIREMENTS
Positive Supply Voltage
V
5 ±5%
V
V
DD
0 or 5
±5%
Negative Supply Voltage
V
SS
Operating mode
1.5
30
2
2.5
70
mA
Positive Supply Current
I
Fast power-down (Note 9)
Full power-down (Note 9)
DD
µA
µA
10
Operating mode and fast power-down
Full power-down
50
Negative Supply Current
I
SS
10
Logic Supply Voltage
V
2.70
5.25
10
V
L
Logic Supply Current (Notes 6, 10)
I
V = V = 5V
DD
µA
L
L
V
= 5V ±5%; external reference, 4.096V;
DD
Positive Supply Rejection (Note 11)
PSR
±0.06
0.5
mV
full-scale input
V
= -5V ±5%; external reference, 4.096V;
SS
Negative Supply Rejection (Note 11)
Logic Supply Rejection (Note 12)
PSR
PSR
±0.01
±0.06
0.5
0.5
mV
mV
full-scale input
External reference, 4.096V; full-scale input
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Electrical Characteristics (continued)
(V
= +5V ±5%, V = 2.7V to 3.6V; V
= 0V or -5V ±5%; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
DD
L
SS
SCLK
cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin; T = T
A MIN
REF
to T
, unless otherwise noted.)
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
DIGITAL INPUTS—DIN, SCLK, CS, SHDN
DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
V
2.0
V
V
IH
V
0.8
IL
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
SHDN Input High Voltage
V
0.15
V
HYST
I
V
= 0V or V
DD
±1
µA
pF
V
IN
IN
C
(Note 6)
15
IN
V
V
V
- 0.5
SH
DD
SHDN Input Mid Voltage
1.5
V
- 1.5
V
SM
DD
SHDN Voltage, Unconnected
SHDN Input Low Voltage
V
SHDN = open
2.75
V
FLT
V
0.5
4.0
V
SL
SHDN Input Current, High
SHDN Input Current, Low
I
SHDN = V
µA
µA
SH
DD
I
V
= 0V
-4.0
SL
SHDN
SHDN Maximum Allowed Leakage,
Mid-Input
SHDN = open
-100
+100
0.4
nA
DIGITAL OUTPUTS—DOUT, SSTR (V = 2.7V to 3.6V)
L
I
I
I
= 3mA
= 6mA
SINK
SINK
Output Voltage Low
V
OL
V
0.3
Output Voltage High
V
= 1mA
SOURCE
V - 0.5
L
V
OH
Three-State Leakage Current
Three-State Output Capacitance
I
CS = V
±10
15
µA
pF
LEAK
L
C
CS = V (Note 6)
L
OUT
DIGITAL OUTPUTS—DOUT, SSTR (V = 4.75V to 5.25V)
L
I
I
I
= 5mA
= 8mA
0.4
SINK
SINK
Output Voltage Low
V
V
OL
0.3
Output Voltage High
V
= 1mA
SOURCE
4
V
OH
Three-State Leakage Current
Three-State Output Capacitance
I
V
= 5V
±10
15
µA
pF
LEAK
CS
CS
C
V
= 5V (Note 6)
OUT
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
TIMING CHARACTERISTICS
(V
= +5V ±5%, V = 2.7V to 3.6V, V = 0V or -5V ±5%, T = T
to T , unless otherwise noted.)
MAX
DD
L
SS
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1.5
TYP
MAX
UNITS
µs
Acquisition Time
t
ACQ
DIN to SCLK Setup
t
100
ns
DS
DH
DO
DIN to SCLK Hold
t
0
ns
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
t
C
C
C
= 100pF
= 100pF
= 100pF
20
240
240
240
ns
LOAD
LOAD
LOAD
t
ns
DV
t
ns
TR
t
t
100
0
ns
CSS
ns
CSH
t
200
200
ns
CH
t
C
= 100pF
ns
CL
LOAD
t
240
240
ns
SSTRB
CS Fall to SSTRB Output Enable
(Note 6)
t
External-clock mode only, C
= 100pF
ns
ns
ns
SDV
LOAD
CS Rise to SSTRB Output Disable
(Note 6)
t
240
STR
SCK
SSTRB Rise to SCLK Rise
(Note 6)
t
0
Note 1: Tested at V
= 5.0V; V = 0V; unipolar-input mode.
SS
DD
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is cali-
brated.
Note 3: MAX1202—internal reference, offset nulled; MAX1203—external reference (V
Note 4: On-channel grounded; sine wave applied to all off-channels.
= 4.096V), offset nulled.
REF
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not production tested.
Note 7: Common-mode range for analog inputs is from V to V
.
SS
DD
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with V at 3.3V, and with all digital inputs tied to either V or GND;
L
L
REFADJ = GND. Shutdown supply current is also dependent on V (Figure 12c).
IH
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on f , and on the static and capacitive load at DOUT and SSTRB.
SCLK
Note 11: Measured at V
+ 5% and V
- 5% only.
SUPPLY
SUPPLY
Note 12: Measured at V = 2.7V and V = 3.6V.
L
L
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Typical Operating Characteristics
(V
= 5V ±5%; V = 2.7V to 3.6V; V = 0V; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
DD
L
SS
SCLK
MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin; T = +25°C, unless other-
A
REF
wise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
3.0
2.5
2.0
1.5
1.0
6
2.0
REFADJ = GND
FULL POWER-DOWN
5
1.8
1.6
4
3
MAX1202
MAX1202
1.4
1.2
1.0
MAX1203
2
1
0.5
0
MAX1203
0
4.5
4.7
4.9
5.1
5.3
5.5
-60
-20
20
60
100
140
-60
-20
20
60
100
140
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (ºC)
INTEGRAL NONLINEARITY
vs. TEMPERATURE
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
5
4
0.8
0.7
0.6
2.0
1.5
1.0
3
2
DIFFERENTIAL
0.5
0.4
0.3
0.2
0.1
0
0.5
0
1
0
SINGLE-ENDED
-1
-2
-3
-0.5
-1.0
-1.5
-2.0
-4
-5
-60
-20
20
60
100
140
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (ºC)
TEMPERATURE (ºC)
TEMPERATURE (ºC)
CHANNEL-TO-CHANNEL OFFSET-ERROR
MATCHING vs. TEMPERATURE
CHANNEL-TO-CHANNEL GAIN-ERROR
MATCHING vs. TEMPERATURE
5
4
3
2
3
2
1
0
1
0
-1
-2
-3
-1
-2
-3
-4
-5
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (ºC)
TEMPERATURE (ºC)
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Typical Operating Characteristics (continued)
(V
= 5V ±5%; V = 2.7V to 3.6V; V = 0V; f
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
DD
L
SS
SCLK
MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin; T = +25°C, unless other-
A
REF
wise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL
FFT PLOT
1.0
20
V
SS
= -5V
0.8
0.6
0.4
0.2
0
0
-20
-40
-60
-0.2
-0.4
-0.6
-0.8
-1.0
-80
-100
-120
0
750 1500 2250 3000 3750 4500
DIGITAL CODE
0
33.25
66.50
FREQUENCY (kHz)
Pin Description
PIN
1–8
9
NAME
CH0–CH7
FUNCTION
Sampling Analog Inputs
Negative Supply Voltage. Tie V to -5V ±5% or to GND.
V
SS
SS
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10µA (max)
supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to V puts
the reference-buffer amplifier in internal compensation mode. Leaving SHDN unconnected puts the
DD
10
SHDN
reference-buffer amplifier in external compensation mode.
Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the
reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external
11
REF
reference mode, disable the internal buffer by pulling REFADJ to V
.
DD
12
13
REFADJ
GND
Input to the Reference-Buffer Amplifier. Tie REFADJ to V
to disable the reference-buffer amplifier.
DD
Ground; IN- Input for Single-Ended Conversions
Supply Voltage for Digital Output Pins. Voltage applied to V determines the positive output swing of
L
14
15
V
L
the Digital Outputs (DOUT, SSTRB). 2.7V ≤ V ≤ 5.25V.
L
DOUT
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin
the analog-to-digital conversion, and goes high when the conversion is finished. In external clock
mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is
high (external clock mode).
16
SSTRB
17
18
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
CS
Serial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK
also sets the conversion speed (Duty cycle must be 40% to 60% in external clock mode).
19
20
SCLK
V
Positive Supply Voltage, +5V ±5%
DD
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
+3.3V
3kΩ
18
DOUT
DOUT
CS
SCLK
19
3kΩ
C
C
LOAD
INPUT
SHIFT
LOAD
INT
17
10
DIN
CLOCK
REGISTER
CONTROL
LOGIC
GND
a. High-Z to V and V to V
OH
GND
SHDN
1
2
3
4
5
6
7
8
b. High-Z to V and V to V
OH
OL
OL
OH
OL
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
15
16
OUTPUT
SHIFT
DOUT
REGISTER
SSTRB
Figure 1. Load Circuits for Enable Time
ANALOG
INPUT
MUX
T/H
CLOCK
IN
12-BIT
SAR
ADC
+3.3V
MAX1202
MAX1203
OUT
20
14
9
13
REF
ª 1.68
V
V
DD
GND
3kΩ
A
+2.44V
REFERENCE
(MAX1202)
L
20kΩ
DOUT
DOUT
V
SS
12
11
REFADJ
REF
3kΩ
C
LOAD
C
LOAD
+4.096V
GND
GND
a. V to High-Z
OH
b. V to High-Z
OL
Figure 2. Load Circuits for Disable Time
Figure 3. Block Diagram
to GND during a conversion. To do this, connect a 0.1μF
capacitor from IN- (of the selected analog input) to GND.
Detailed Description
The MAX1202/MAX1203 analog-to-digital converters
(ADCs) use a successive-approximation conversion tech-
nique and input track/hold (T/H) circuitry to convert an
analog signal to a 12-bit digital output. A flexible serial
interface provides easy interface to 3V microprocessors
(μPs). Figure 3 is the MAX1202/MAX1203 block diagram.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
. The
HOLD
acquisition interval spans three SCLK cycles and ends on
the falling SCLK edge after the input control word’s last bit
is entered. The T/H switch opens at the end of the acquisi-
tion interval, retaining charge on C
the signal at IN+.
as a sample of
HOLD
Pseudo-Differential Input
Figure 4 shows the ADC’s analog comparator’s sampling
architecture. In single-ended mode, IN+ is internally
switched to CH0–CH7 and IN- is switched to GND. In
differential mode, IN+ and IN- are selected from pairs of
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels using Tables 3 and 4.
The conversion interval begins with the input multiplexer
switching C from the positive input (IN+) to the nega-
HOLD
tive input (IN-). In single-ended mode, IN- is simply GND.
This unbalances node ZERO at the comparator’s input.
The capacitive DAC adjusts during the remainder of the
conversion cycle to restore node ZERO to 0V within the
limits of 12-bit resolution. This action is equivalent to trans-
In differential mode, IN- and IN+ are internally switched to
either of the analog inputs. This configuration is pseudo-
differential such that only the signal at IN+ is sampled.
The return side (IN-) must remain stable (typically within
±0.5 LSB, within ±0.1 LSB for best results) with respect
ferring a charge of 16pF x [(V ) - (V )] from C
to
IN+ IN- HOLD
the binary-weighted capacitive DAC, which in turn forms a
digital representation of the analog input signal.
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
performance. Higher source impedances can be used if
an input capacitor is connected to the analog inputs, as
shown in Figure 5. Note that the input capacitor forms
an RC filter with the input source impedance, limiting the
ADC’s signal bandwidth.
Track/Hold
The T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN- is connected
to GND if the converter is set up for single-ended inputs,
and the converter samples the “+” input. IN- connects to
the “-” input if the converter is set up for differential inputs,
and the difference of |N+ - IN-| is sampled. The positive
input connects back to IN+, at the end of the conversion,
12-BIT CAPACITIVE DAC
REF
COMPARATOR
INPUT
MUX
C
HOLD
and C
charges to the input signal.
HOLD
ZERO
–
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, acquisition
time increases and more time must be allowed between
16pF
9kΩ
R
IN
C
SWITCH
HOLD
TRACK
conversions. The acquisition time, t
, is the maximum
ACQ
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
time the device takes to acquire the signal, and is also the
minimum time needed for the signal to be acquired. It is
calculated by the following:
T/H
SWITCH
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = GND.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
t
= 9 x (R + R ) x 16pF
S IN
ACQ
where R = 9kΩ, R = the source impedance of the input
IN
S
signal, and t
is never less than 1.5μs. Source imped-
ACQ
ances below 1kΩ do not significantly affect the ADC’s AC
Figure 4. Equivalent Input Circuit
+3V
V
V
DD
+5V
OSCILLOSCOPE
L
0.1µF
0.1µF
4.7µF
GND
SCLK
V
SS
MAX1202
MAX1203
SSTRB
DOUT*
0 TO
4.096V
ANALOG
INPUT
CH7
CS
0.01µF
SCLK
CH4
2MHz
OSCILLATOR
CH3
CH1
CH2
+3V
DIN
SSTRB
DOUT
REFADJ
REF
SHDN
N.C.***
C1
4.7µF
C2
0.01µF
+2.5V
**
+2.5V
REFERENCE
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX).
**REQUIRED FOR MAX1203 ONLY.
***NO CONNECTION
Figure 5. Quick-Look Circuit
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Table 1a. Unipolar Full Scale and Zero
Scale
Table 1b. Bipolar Full Scale, Zero Scale,
and Negative Full Scale
ZERO
SCALE
NEGATIVE
FULL SCALE SCALE
ZERO
REFERENCE
Internal
External
FULL SCALE
REFERENCE
Internal
External
FULL SCALE
0V
+4.096V
V x A*
REFADJ
+4.096V/2
-1/2 V
0V
0V
0V
+4.096V/2
at REFADJ
at REF
0V
at
+1/2 V
REFADJ
REFADJ
REFADJ
x A*
x A*
0V
V
REF
at REF
+1/2 V
+1/2 V
REF
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
REF
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
which triggers single-ended unipolar conversions on CH7
in external clock mode without powering down between
conversions. In external clock mode, the SSTRB output
pulses high for one clock period before the most signifi-
cant bit of the 12-bit conversion result shifts out of DOUT.
Varying the analog input to CH7 alters the sequence of
bits from DOUT. A total of 15 clock cycles per conversion
is required. All SSTRB and DOUT output transitions occur
on SCLK’s falling edge.
Input Bandwidth
The ADC’s input tracking circuitry has a 4.5MHz small-
signal bandwidth. Therefore it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Analog Input Range and Input Protection
Internal protection diodes, which clamp the analog inputs
How to Start a Conversion
Clocking a control byte into DIN starts conversion on the
MAX1202/MAX1203. With CS low, each rising edge on
SCLK clocks a bit from DIN into the MAX1202/MAX1203’s
internal shift register. After CS falls, the first logic “1” bit
defines the control byte’s MSB. Until this first “start” bit
arrives, any number of logic “0” bits can be clocked into
DIN with no effect. Table 2 shows the control-byte format.
to V
and V , allow the analog input pins to swing from
DD
SS
(V
- 0.3V) to (V
+ 0.3V) without damage. However,
SS
DD
for accurate conversions near full scale, the inputs must
not exceed V by more than 50mV, or be lower than
DD
by 50mV.
V
SS
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off-channels more than 2mA.
The MAX1202/MAX1203 are fully compatible with SPI/
MICROWIRE devices. For SPI, select the correct clock
polarity and sampling edge in the SPI control registers:
set CPOL = 0 and CPHA = 0. MICROWIRE and SPI both
transmit and receive a byte at the same time. Using the
Typical Operating Circuit, the simplest software interface
requires only three 8-bit transfers to perform a conversion
(one 8-bit transfer to configure the ADC, and two more
8-bit transfers to clock out the 12-bit conversion result).
The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).
Quick Look
Use the circuit of Figure 5 to quickly evaluate the MAX1202/
MAX1203’s analog performance. The MAX1202/MAX1203
require a control byte to be written to DIN before each con-
version. Tying DIN to +3V feeds in control byte $FF hex,
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Table 2. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT1
BIT 0 (LSB)
START
SEL 2
SEL 1
SEL 0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
DESCRIPTION
7 (MSB)
START
The first logic 1 bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels is used for the conversion
(Tables 3 and 4).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog
input signal from 0 to V can be converted; in bipolar mode, the signal can range from -V /2
3
2
UNI/BIP
SGL/DIF
REF
REF
to +V
/2.
REF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-ended
mode, input signal voltages are referred to GND. In differential mode, the voltage difference
between two channels is measured. (Tables 3 and 4).
Selects clock and power-down modes.
PD1
PD0
Mode
1
PD1
PD0
0
0
1
1
0
1
0
1
Full power-down (I
Fast power-down (I
Internal clock mode
External clock mode
= 2µA, internal reference)
= 30µA, internal reference)
DD
0 (LSB)
DD
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
-
+
-
+
-
-
+
-
-
-
+
-
+
+
+
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Simple Software Interface
Digital Output
Make sure the CPU’s serial interface runs in master mode
so the CPU generates the serial clock. Choose a clock
frequency from 100kHz to 2MHz.
In unipolar-input mode, the output is straight binary
(Figure 15); for bipolar inputs, the output is two’s comple-
ment (Figure 16). Data is clocked out at SCLK’s falling
edge in MSB-first format. The digital output logic level is
1) Set up the control byte for external clock mode and
call it TB1. TB1’s format should be: 1XXXXX11 binary,
where the Xs denote the particular channel and con-
version mode selected.
adjusted with the V pin. This allows DOUT and SSTRB
L
to interface with 3V logic without the risk of overdrive. The
MAX1202/MAX1203’s digital inputs are designed to be
compatible with 5V CMOS logic as well as 3V logic.
2) Use a general-purpose I/O line on the CPU to pull CS
on the MAX1202/MAX1203 low.
Internal and External Clock Modes
The MAX1202/MAX1203 can use either an external serial
clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the MAX1202/
MAX1203. The T/H acquires the input signal as the last
three bits of the control byte are clocked into DIN. Bits
PD1 and PD0 of the control byte program the clock mode.
Figures 7–10 show the timing characteristics common to
both modes.
3) Transmit TB1 and simultaneously receive a byte and
call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and simultane-
ously receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and simultane-
ously receive byte RB3.
6) Pull CS on the MAX1202/MAX1203 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded with
one leading zero and three trailing zeros. The total con-
version time is a function of the serial-clock frequency and
the amount of idle time between 8-bit transfers. To avoid
excessive T/H droop, make sure that the total conversion
time does not exceed 120μs.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the A/D conversion
steps. SSTRB pulses high for one clock period after the
last bit of the control byte. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and DOUT
go into a high-impedance state when CS goes high; after
CS
t
ACQ
SCLK
1
4
8
12
16
20
24
UNI/ SGL/
BIP DIF
DIN
SSTRB
DOUT
SEL2 SEL1 SEL0
PD1 PD0
START
RB2
B8
RB3
B0
LSB
RB1
FILLED WITH
ZEROS
B11
MSB
B10 B9
B7
B6
B5
B4
B3
B2
B1
ACQUISITION
1.5µs
CONVERSION
IDLE
ADC STATE
IDLE
(SCLK = 2MHz)
Figure 6. 24-Bit External Clock Mode Conversion Timing (MICROWIRE and SPI Compatible)
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
• • •
CS
t
t
t
CSH
CSS
CH
t
t
CL
CSH
SCLK
• • •
t
DS
t
DH
DIN
• • •
t
t
t
TR
DV
DO
DOUT
• • •
Figure 7. Detailed Serial-Interface Timing
CS
• • •
• • •
t
t
STR
SDV
SSTRB
• • •
• • •
t
t
SSTRB
SSTRB
SCLK
• • •
• • •
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
the next CS falling edge, SSTRB outputs a logic low.
ning the SAR conversion clock, and allows the conversion
results to be read back at the processor’s convenience,
at any clock rate from zero to 2MHz. SSTRB goes low
at the start of the conversion, then goes high when the
conversion is complete. SSTRB is low for a maximum
of 10μs, during which time SCLK should remain low for
best noise performance. An internal register stores data
while the conversion is in progress. SCLK clocks the
data out at this register at any time after the conversion
is complete. After SSTRB goes high, the next falling clock
edge produces the MSB of the conversion at DOUT, fol-
Figure 8 shows SSTRB timing in external clock mode.
The conversion must complete in some minimum time or
droop on the sample-and-hold capacitors might degrade
conversion results. Use internal clock mode if the clock
period exceeds 10μs or if serial-clock interruptions could
cause the conversion interval to exceed 120μs.
Internal Clock
In internal clock mode, the MAX1202/MAX1203 generate
their own conversion clock. This frees the μP from run-
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
CS
SCLK
DIN
1
4
8
18
24
2
3
5
6
7
9
10
11
12
19
20
21
22
23
UNI/ SGL/
BIP DIF
SEL2 SEL1 SEL0
PD1 PD0
START
SSTRB
t
CONV
FILLED WITH
ZEROS
B11
MSB
B0
LSB
DOUT
B10 B9
B2
B1
ACQUISITION
1.5s
(SCLK = 2MHz)
CONVERSION
10s MAX
ADC STATE
IDLE
IDLE
Figure 9. Internal Clock Mode Timing
CS • • •
t
t
CONV
CSS
t
t
SCK
CSH
SSTRB • • •
SCLK • • •
t
SSTRB
PD0 CLOCK IN
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
lowed by the remaining bits in MSB-first format (Figure
9). CS does not need to be held low once a conversion is
started. Pulling CS high prevents data from being clocked
into the MAX1202/MAX1203 and three-states DOUT, but
it does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode is
selected, SSTRB does not go into a high-impedance state
when CS goes high.
DIN is interpreted as a start bit and defines the first bit
of the control byte. A conversion starts on SCLK’s falling
edge after the eighth bit of the control byte (the PD0 bit)
is clocked into DIN. The start bit is defined as one of the
following:
The first high bit clocked into DIN with CS low anytime
the converter is idle (e.g., after V
is applied).
DD
or
Figure 10 shows SSTRB timing in internal clock mode.
Data can be shifted in and out of the MAX1202/MAX1203
The first high bit clocked into DIN after bit 5 (B5) of a
conversion in progress appears at DOUT.
at clock rates up to 2.0MHz, if t
is kept above 1.5μs.
ACQ
If a falling edge on CS forces a start bit before B5
becomes available, the current conversion is terminated
and a new one started. Thus, the fastest the MAX1202/
MAX1203 can run is 15 clocks/conversion.
Data Framing
CS’s falling edge does not start a conversion on the
MAX1202/MAX1203. The first logic high clocked into
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5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Figure 11a shows the serial-interface timing necessary to
perform a conversion every 15 SCLK cycles in external
clock mode. If CS is low and SCLK is continuous, guar-
antee a start bit by first clocking in 16 zeros.
Full power-down mode turns off all chip functions that draw
quiescent current, reducing I
and I typically to 2μA.
DD
SS
For the MAX1202, fast power-down mode turns off all
circuitry except the bandgap reference. With fast power-
down mode, the supply current is 30μA. Power-up time
can be shortened to 5μs in internal compensation mode.
Since the MAX1203 does not have an internal reference,
power-up times coming out of full or fast power-down are
identical.
Most microcontrollers (μCs) require that data transfers
occur in multiples of eight clock cycles; 16 clocks per
conversion is typically the fastest that a μC can drive
the MAX1202/MAX1203. Figure 11b shows the serial-
interface timing necessary to perform a conversion every
16 SCLK cycles in external clock mode.
I
shutdown current can increase if any digital input
DD
(DIN, SCLK, CS) is held high in either power-down mode.
The actual shutdown current depends on the state of the
Applications Information
digital inputs, the voltage applied to the digital inputs (V ),
the supply voltage (V ), and the operating temperature.
DD
Power-On Reset
IH
When power is first applied and if SHDN is not pulled low,
internal power-on reset circuitry activates the MAX1202/
MAX1203 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies are stabilized, the
internal reset time is 100μs. No conversions should be per-
formed during this phase. SSTRB is high on power-up, and
if CS is low, the first logical 1 on DIN is interpreted as a start
bit. Until a conversion takes place, DOUT shifts out zeros.
Figure 12c shows the maximum I
increase for each
DD
digital input held high in power-down mode for different
operating conditions. This current is cumulative, so if all
three digital inputs are held high, the additional shutdown
current is three times the value shown in Figure 12c.
In both software power-down modes, the serial interface
remains operational, but the ADC does not convert.
Table 5 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7μF compen-
sation capacitor (200ms with a 33μF capacitor) when the
capacitor is initially fully discharged. From fast power-
down, start-up time can be eliminated by using low-
leakage capacitors that do not discharge more than 1/2
LSB while shut down. In power-down, the capacitor has
to supply the current into the reference (typically 1.5μA)
and the transient currents at power-up.
Reference-Buffer Compensation
In addition to its shutdown function, SHDN also selects
internal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. Compensated or not, the minimum clock rate is
100kHz due to droop on the sample-and-hold.
Leave SHDN unconnected to select external compensa-
tion. The Typical Operating Circuit uses a 4.7μF capacitor
at REF. A value of 4.7μF or greater ensures stability and
allows converter operation at the 2MHz full clock speed.
External compensation increases power-up time (see the
section Choosing Power-Down Mode, and Table 5).
Figures 12a and 12b show the various power-down
sequences in both external and internal clock modes.
Internal compensation requires no external capacitor
at REF, and is selected by pulling SHDN high. Internal
compensation allows for the shortest power-up times, but
the external clock must be limited to 400kHz during the
conversion.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software power-
down is asserted, the ADC continues to operate in the
last specified clock mode until the conversion is complete.
The ADC then powers down into a low quiescent-current
state. In internal clock mode, the interface remains active
and conversion results can be clocked out even though
the MAX1202/MAX1203 have already entered software
power-down.
Power-Down
Choosing Power-Down Mode
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down or fast power-down mode via bits 1 and 0
of the DIN control byte with SHDN high or unconnected
(Tables 2 and 6). Pull SHDN low at any time to shut down
the converter completely. SHDN overrides bits 1 and 0 of
the control byte.
The first logical 1 on DIN is interpreted as a start bit and
powers up the MAX1202/MAX1203. Following the start
bit, the control byte also determines clock and power-
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5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
CS
1
8
1
8
1
SCLK
S
CONTROL BYTE 2
DIN
DOUT
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
SSTRB
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
• • •
• • •
• • •
• • •
CS
SCLK
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DIN
DOUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
down modes. For example, if the DIN word contains PD1
= 1, the chip remains powered up. If PD1 = 0, power-down
resumes after one conversion.
this example) are required for the reference buffer to set-
tle. When exiting FULLPD, waiting this 2ms in FASTPD
mode (instead of just exiting FULLPD mode and returning
to normal operating mode) reduces power consumption
by a factor of 10 or more (Figure 13).
Hardware Power-Down
The SHDN pin places the converter into full power-down
mode. Unlike the software power-down modes, conversion
is not completed; it stops coincidentally with SHDN being
brought low. There is no power-up delay if an external ref-
erence, which is not shut down, is used. SHDN also selects
internal or external reference compensation (Table 7).
Lowest Power at Higher Throughputs
Figure 14b shows power consumption with external ref-
erence compensation in fast power-down, with one and
eight channels converted. The external 4.7μF compen-
sation requires a 50μs wait after power-up. This circuit
combines fast multichannel conversion with the lowest
power consumption possible. Full power-down mode
can increase power savings in applications where the
MAX1202/MAX1203 are inactive for long periods of time,
but where intermittent bursts of high-speed conversion
are required.
Power-Down Sequencing
The MAX1202/MAX1203’s automatic power-down modes
can save considerable power when operating at less than
maximum sample rates. The following sections discuss
the various power-down sequences.
Lowest Power at up to
500 Conversions per Channel per Second
Figure 14a depicts MAX1202 power consumption for one
or eight channel conversions using full power-down mode
and internal reference compensation. A 0.01μF bypass
capacitor at REFADJ forms an RC filter with the internal
20kΩ reference resistor, with a 0.2ms time constant. To
achieve full 12-bit accuracy, 10 time constants (or 2ms in
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
CLOCK
MODE
INTERNAL
EXTERNAL
EXTERNAL
SHDN
SETS FAST
POWER-DOWN
MODE
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1
1
S X X X X X 0
1
S X X X X X 1 1
DOUT
DATA VALID
(12 DATA BITS)
DATA VALID
(12 DATA BITS)
DATA
INVALID
POWERED
UP
FULL
POWER-
DOWN
POWERED UP
POWERED UP
MODE
FAST
POWER-DOWN
Figure 12a. Timing Diagram for Power-Down Modes, External Clock
Table 5. Typical Power-Up Delay Times
REF
CAPACITOR
(µF)
POWER-UP
DELAY
(µs)
MAXIMUM
SAMPLING RATE
(ksps)
REFERENCE
BUFFER
REFERENCE-BUFFER
COMPENSATION MODE
POWER-DOWN
MODE
Enabled
Enabled
Enabled
Disabled
Disabled
Internal
Internal
External
—
—
—
Fast
Full
5
26
26
300
4.7
—
Fast/Full
Fast
See Figure 14c
133
133
133
2
2
—
—
Full
Table 6. Software Shutdown
Table 7. Hard-Wired Shutdown
and Clock Mode
and Compensation Mode
PD1
PD0
DEVICE MODE
Full power-down mode
SHDN
DEVICE
MODE
REFERENCE-BUFFER
COMPENSATION
STATE
0
0
1
1
0
1
0
1
Fast power-down mode
Internal clock mode
External clock mode
V
Enabled
Internal compensation
External compensation
DD
Unconnected Enabled
Full
power-down
GND
N/A
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
CLOCK
MODE
INTERNAL CLOCK MODE
SETS FULL
POWER-DOWN
SETS INTERNAL
CLOCK MODE
DIN
S X X X X X 1
0
S X X X X X 0
0
S
DOUT
DATA VALID
DATA VALID
SSTRB
MODE
CONVERSION
CONVERSION
FULL
POWER-DOWN
POWERED UP
POWERED
UP
Figure 12b. Timing Diagram for Power-Down Modes, Internal Clock
External and Internal References
40
The MAX1202 can be used with an internal or external
reference, whereas an external reference is required for
the MAX1203. An external reference can be connected
directly at the REF terminal, or at the REFADJ pin.
35
(V - V ) = 2.55V
DD
IH
30
25
20
15
10
5
An internal buffer is designed to provide 4.096V at REF
for both the MAX1202 and the MAX1203. The MAX1202’s
internally trimmed 2.44V reference is buffered with a gain
of 1.68. The MAX1203’s REFADJ pin is buffered with
a gain of 1.64, to scale an external 2.5V reference at
REFADJ to 4.096V at REF.
(V - V ) = 2.25V
DD
IH
(V - V ) = 1.95V
DD
IH
0
MAX1202 Internal Reference
-60
-20
20
60
100
140
The MAX1202’s full-scale range using the internal refer-
ence is 4.096V with unipolar inputs and ±2.048V with
bipolar inputs. The internal reference voltage is adjustable
to ±1.5% with the circuit of Figure 17.
TEMPERATURE (°C)
Figure 12c. Additional I
Shutdown Supply Current vs. V for
IH
Each Digital Input at a Logic 1
DD
COMPLETE CONVERSION SEQUENCE
2ms WAIT
0 1
(ZEROS)
CH1
CH7
(ZEROS)
DIN
1
0 0
1
1
1 1
1
0 0
FULLPD
1
0 1
FASTPD
FULLPD
2.5V
FASTPD
NOPD
REFADJ
REF
0V
4V
0V
t = RC = 20kW x C
REFADJ
t
ª 15µs
BUFFEN
Figure 13. MAX1202 FULLPD/FASTPD Power-Up Sequence
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
MAX1202/MAX1203
FAST POWER-DOWN
FULL POWER-DOWN
1000
10,000
2ms FASTPD WAIT
8 CHANNELS
1 CHANNEL
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
8 CHANNELS
100
10
1000
1 CHANNEL
100
10
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
1
0
50 100 150 200 250 300 350 400 450 500
CONVERSIONS PER CHANNEL PER SECOND
0
2k
4k
6k
8k 10k 12k 14k 16k 18k
CONVERSIONS PER CHANNEL PER SECOND
Figure 14a. MAX1202 Supply Current vs. Sample Rate/
Second, FULLPD, 400kHz Clock
Figure 14b. MAX1202/MAX1203 Supply Current vs. Sample
Rate/Second, FASTPD, 2MHz Clock
External Reference
With both the MAX1202 and MAX1203, an external refer-
ence can be placed at either the input (REFADJ) or the
output (REF) of the internal reference-buffer amplifier.
The REFADJ input impedance is typically 20kΩ for the
MAX1202, and higher than 100kΩ for the MAX1203,
where the internal reference is omitted. At REF, the DC
input resistance is a minimum of 12kΩ. During conversion,
an external reference at REF must deliver up to 350μA DC
load current and have an output impedance of 10Ω or less.
If the reference has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7μF capacitor.
3.0
2.5
2.0
1.5
1.0
0.5
0
Using the buffered REFADJ input makes buffering of the
external reference unnecessary. When connecting an
external reference directly at REF, disable the internal
0.0001 0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
buffer by tying REFADJ to V . In power-down, the input
DD
bias current to REFADJ can be as much as 25μA with
REFADJ tied to V
GND to minimize the input bias current in power-down.
(MAX1202 only). Pull REFADJ to
DD
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
Transfer Function and Gain Adjust
Figure 15 depicts the nominal, unipolar input/output (I/O)
transfer function, and Figure 16 shows the bipolar I/O
transfer function. Code transitions occur halfway between
successive-integer LSB values. Output coding is binary
with 1 LSB = 1.00mV (4.096V/4096) for unipolar opera-
tion, and 1 LSB = 1.00mV [(4.096V/2 - -4.096V/2)/4096]
for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines under-
neath the ADC package.
Figure 17 shows how to adjust the ADC gain in applica-
tions that use the internal reference. The circuit provides
±1.5% (±65 LSBs) of gain adjustment range.
Figure 18 shows the recommended system ground
connections. Establish a single-point analog ground
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
OUTPUT CODE
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
011 . . . 111
FS = +2.048V
011 . . . 110
+4.096V
1LSB =
11 . . . 101
4096
000 . . . 010
000 . . . 001
000 . . . 000
FS = +4.096V
4.096V
4096
1LSB = +
111 . . . 111
111 . . . 110
111 . . . 101
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
0
1
2
3
FS
0V
-FS
+FS - 1LSB
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
INPUT VOLTAGE (LSBs)
Figure 15. Unipolar Transfer Function, 4.096V = Full Scale
Figure 16. Bipolar Transfer Function, ±4.096V/2 = Full Scale
(“star” ground point) at GND. Connect all other analog
grounds to this ground. No other digital system ground
should be connected to this single-point analog ground.
The ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
+5V
MAX1202
510kΩ
100kΩ
REFADJ
12
High-frequency noise in the power supplies can affect the
ADC’s high-speed comparator. Bypass these supplies
to the single-point analog ground with 0.1μF and 4.7μF
bypass capacitors close to the MAX1202/MAX1203.
Minimize capacitor lead lengths for best supply-noise
rejection. If the +5V power supply is very noisy, a 10Ω
resistor can be connected as a lowpass filter, as shown
in Figure 18.
0.01µF
24kΩ
Figure 17. MAX1202 Reference-Adjust Circuit
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
3) Write an 8-bit word (1XXXXX11) to the MAX1202/
MAX1203 to initiate a conversion and place the device
into external clock mode. Refer to Table 2 to select the
proper XXXXX bit values for your specific application.
TMS320CL3x to MAX1202/
MAX1203 Interface
Figure 19 shows an application circuit to interface the
MAX1202/MAX1203 to the TMS320 in external clock
mode. Figure 20 shows the timing diagram for this inter-
face circuit.
4) The MAX1202/MAX1203’s SSTRB output is moni-
tored via the TMS320’s FSR input. A falling edge on
the SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX1202/MAX1203.
Use the following steps to initiate a conversion in the
MAX1202/MAX1203 and to read the results:
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
The TMS320’s CLKX and CLKR are tied together with
the MAX1202/MAX1203’s SCLK input.
5) The TMS320 reads in one data bit on each of the next
16 rising edges of SCLK. These data bits represent the
12-bit conversion result followed by four trailing bits,
which should be ignored.
6) Pull CS high to disable the MAX1202/MAX1203 until
2) The MAX1202/MAX1203’s CS is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX1202/MAX1203’s DIN.
the next conversion is initiated.
SUPPLIES
+5V
-5V
+3V
GND
XF
CS
CLKX
SCLK
TMS320LC3x
R* = 10Ω
MAX1202
MAX1203
CLKR
DX
DIN
V
DD
GND
V
SS
V
+3V DGND
L
DOUT
DR
MAX1202
MAX1203
DIGITAL
CIRCUITRY
SSTRB
FSR
*OPTIONAL
Figure 18. Power-Supply Grounding Connection
Figure 19. MAX1202/MAX1203-to-TMS320 Serial Interface
CS
SCLK
DIN
START SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
DOUT
HIGH
IMPEDANCE
MSB
B10
B1
LSB
Figure 20. TMS320 Serial-Interface Timing Diagram
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Ordering Information (continued)
Chip Information
PROCESS: BiCMOS
PIN-
INL
(LSB)
PART
TEMP RANGE
PACKAGE
MAX1202AEPP+
MAX1202BEPP+
MAX1202AEAP+
MAX1202BEAP+
MAX1203ACPP+
MAX1203BCPP+
MAX1203ACAP+
MAX1203BCAP+
MAX1203AEPP+
MAX1203BEPP+
MAX1203AEAP+
MAX1203BEAP+
-40ºC to +85ºC 20 PDIP
-40ºC to +85ºC 20 PDIP
-40ºC to +85ºC 20 SSOP
-40ºC to +85ºC 20 SSOP
±1/2
±1
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
±1/2
±1
0ºC to +70ºC
0ºC to +70ºC
0ºC to +70ºC
0ºC to +70ºC
20 PDIP
20 PDIP
20 SSOP
20 SSOP
±1/2
±1
PACKAGE
TYPE
PACKAGE
CODE
DOCUMENT
NO.
LAND
PATTERN NO.
±1/2
±1
20 SSOP
20 PDIP
A20+2
P20+3
21-0056
21-0043
90-0094
-40ºC to +85ºC 20 PDIP
-40ºC to +85ºC 20 PDIP
-40ºC to +85ºC 20 SSOP
-40ºC to +85ºC 20 SSOP
±1/2
±1
—
±1/2
±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit
+5V
+3V
V
DD
CH0
V
DD
V
L
0 to
4.096V
ANALOG
INPUTS
C3
0.1µF
C4
4.7µF
C5
0.1µF
MAX1202
GND
CPU
CH7
V
SS
I/O
CS
SCLK
SCK (SK)
MOSI (SO)
MISO (SI)
REF
DIN
C1
4.7µF
DOUT
SSTRB
REFADJ
C2
0.01µF
V
SS
SHDN
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MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Package Information
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
2
1/97
3/97
5/98
Initial release
—
Added MAX1203 to the data sheet
Corrected gain error limit
1–24
2, 20
1–10, 13, 16, 18,
3
3/12
Removed military grade packages and updated style throughout data sheet
22, 23
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2012 Maxim Integrated Products, Inc.
│ 24
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