MAX1204_12 [MAXIM]
5V, 8-Channel, Serial, 10-Bit ADC with 3V Digital Interface; 5V，8通道，串行， 10位ADC， 3V数字接口
| 型号： | MAX1204_12 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 5V, 8-Channel, Serial, 10-Bit ADC with 3V Digital Interface |
| 文件： | 总23页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
_______________General Description
____________________________Features
o 8-Channel Single-Ended or 4-Channel Differential
The MAX1204 is a 10-bit data-acquisition system
specifically designed for use in applications with mixed
+5V (analog) and +3V (digital) supply voltages. It oper-
ates with a single +5V analog supply or dual 5V ana-
log supplies, and combines an 8-channel multiplexer,
internal track/hold, and serial interface with high con-
version speed and low power consumption.
Inputs
o Operates from +5V Single or 5V Dual Supplies
o User-Adjustable Output Logic Levels (2.7V to
5.25V)
o Low Power: 1.5mA (Operating Mode)
2µA (Power-Down Mode)
A 4-wire serial interface connects directly to
o Internal Track/Hold, 133kHz Sampling Rate
o Internal 4.096V Reference
®
SPI/MICROWIRE devices without external logic, and a
serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1204
uses either the internal clock or an external serial-inter-
face clock to perform successive-approximation ana-
log-to-digital conversions. The serial interface operates
at up to 2MHz.
o SPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial Interface
o Software-Configurable Unipolar/Bipolar Inputs
o 20-Pin PDIP/SSOP
o Pin-Compatible 12-Bit Upgrade: MAX1202
The MAX1204 features an internal 4.096V reference and
a reference-buffer amplifier that simplifies gain trim. It
also has a V pin that supplies power to the digital out-
L
puts. Output logic levels (3V, 3.3V, or 5V) are determined
by the value of the voltage applied to this pin.
______________Ordering Information
TOP
MARK
PIN-
PACKAGE
A hard-wired SHDN pin and two software-selectable
power-down modes are provided. Accessing the serial
interface automatically powers up the device. A quick
turn-on time allows the MAX1204 to be shut down
between conversions, enabling the user to optimize
supply currents. By customizing power-down between
conversions, supply current can drop below 10µA at
reduced sampling rates.
PART
TEMP RANGE
MAX1204ACPP+
MAX1204BCPP+
MAX1204ACAP+
MAX1204BCAP+
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
20 PDIP
20 PDIP
20 SSOP
20 SSOP
1/2
1
1/2
1
Ordering Information continued at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
The MAX1204 is available in 20-pin SSOP and PDIP
packages, and is specified for the commercial and
extended temperature ranges.
__________________Pin Configuration
________________________Applications
5V/3V Mixed-Supply Systems
TOP VIEW
+
Data Acquisition
20
V
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
DD
Process Control
19 SCLK
Battery-Powered Instruments
Medical Instruments
CS
18
3
MAX1204
4
17
DIN
5
16 SSTRB
15 DOUT
6
14
13
12
11
V
L
7
8
GND
V
9
REFADJ
REF
SS
SHDN
10
Typical Operating Circuit appears on last page.
MICROWIRE is a registered trademark of National Semiconductor Corp.
PDIP/SSOP
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-1179; Rev 1; 1/12
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Digital Output Sink Current .................................................25mA
V ................................................................-0.3V to (V
+ 0.3V)
Continuous Power Dissipation (T = +70°C)
L
DD
A
V
V
to GND...............................................................+0.3V to -6V
PDIP (derate 11.11mW/°C above +70°C).....................889mW
SSOP (derate 8.00mW/°C above +70°C) .....................640mW
Operating Temperature Ranges
SS
DD
to V ..............................................................-0.3V to +12V
SS
CH0–CH7 to GND............................(V - 0.3V) to (V
+ 0.3V)
SS
DD
MAX1204_C_P.....................................................0°C to +70°C
MAX1204_E_P ..................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
Digital Outputs to GND .................................-0.3V to (V + 0.3V)
L
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V 5ꢀ, V = 2.7V to 3.6V; V = 0V or -5V 5ꢀ; f
= 2.0MHz, external clock (50ꢀ duty cycle); 15 clocks/conversion
SCLK
DD
L
SS
cycle (133ksps); 4.7µF capacitor at REF; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
Bits
LSB
LSB
LSB
MAX1204A
0.5
1.0
1.0
1.0
2.0
1.0
2.0
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
MAX1204B
DNL
No missing codes over temperature
MAX1204A
MAX1204B
MAX1204A
Gain Error (Note 3)
LSB
ppm/°C
LSB
MAX1204B
Gain Temperature Coefficient
External reference, 4.096V
0.8
0.1
Channel-to-Channel
Offset Matching
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096V , 133ksps, 2.0MHz external clock, bipolar input mode)
P-P
Signal-to-Noise + Distortion Ratio
SINAD
66
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
SFDR
70
-75
4.5
800
dB
dB
V
= 4.096
, 65kHz (Note 4)
V
P-P
IN
-3dB rolloff
MHz
kHz
Full-Power Bandwidth
Maxim Integrated
2
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)
= 2.0MHz, external clock (50ꢀ duty cycle); 15 clocks/conversion
SCLK
(V
= +5V 5ꢀ, V = 2.7V to 3.6V; V = 0V or -5V 5ꢀ; f
DD
L
SS
cycle (133ksps); 4.7µF capacitor at REF; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Internal clock
5.5
6
10
Conversion Time (Note 5)
t
µs
CONV
External clock, 2MHz, 12 clocks/conversion
Track/Hold Acquisition Time
Aperture Delay
t
1.5
µs
ns
ACQ
10
<50
1.7
Aperture Jitter
ps
Internal Clock Frequency
MHz
External compensation mode, 4.7µF
Internal compensation mode (Note 6)
Used for data transfer only
0.1
0.1
0
2.0
0.4
2.0
External Clock-Frequency Range
MHz
ANALOG INPUT
Input Voltage Range, Single-
Ended and Differential (Note 7)
Unipolar, V = 0V
V
REF
SS
V
Bipolar, V = -5V
SS
V
/ 2
REF
Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V
(Note 6)
=
5V
0.01
16
1
µA
pF
CH_
INTERNAL REFERENCE
REF Output Voltage
T
A
= +25°C
4.076
4.096
4.116
30
V
REF Short-Circuit Current
mA
MAX1204AC
MAX1204AE
MAX1204B
30
30
50
V
REF
Temperature Coefficient
60
ppm/°C
30
Load Regulation (Note 8)
Capacitive Bypass at REF
0mA to 0.5mA output load
Internal compensation mode
External compensation mode
2.5
mV
µF
0
4.7
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
0.01
µF
ꢀ
1.5
EXTERNAL REFERENCE AT REF (Buffer disabled, V
= 4.096V)
REF
2.50
12
V
+
DD
Input Voltage Range
V
50mV
Input Current
200
20
350
µA
kΩ
µA
Input Resistance
REF Input Current in Shutdown
1.5
10
V
SHDN
= 0V
V
-
DD
REFADJ Buffer Disable Threshold
V
50mV
Maxim Integrated
3
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)
= 2.0MHz, external clock (50ꢀ duty cycle); 15 clocks/conversion
SCLK
V
= +5V 5ꢀ, V = 2.7V to 3.6V; V = 0V or -5V 5ꢀ; f
DD
L
SS
cycle (133ksps); 4.7µF capacitor at REF; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE AT REFADJ
Internal compensation mode
External compensation mode
0
Capacitive Bypass at REF
µF
4.7
Reference-Buffer Gain
REFADJ Input Current
POWER REQUIREMENTS
1.68
V/V
µA
V
50
Positive Supply Voltage
V
DD
5 5ꢀ
Negative Supply Voltage
V
SS
0 or -5 5ꢀ
V
Operating mode
1.5
30
2
2.5
70
mA
Positive Supply Current
Negative Supply Current
I
Fast power-down (Note 9)
Full power-down (Note 9)
Operating mode and fast power-down
Full power-down
DD
µA
µA
10
50
I
SS
10
Logic Supply Voltage
V
2.70
5.25
10
V
L
Logic Supply Current (Notes 6, 10)
I
VL
V = V = 5V
L DD
µA
Positive Supply Rejection
(Note 11)
V
= 5V 5ꢀ; external reference, 4.096V;
DD
PSR
PSR
PSR
0.06
0.01
0.06
0.5
0.5
0.5
mV
mV
mV
full-scale input
Negative Supply Rejection
(Note 11)
V
SS
full-scale input
= -5V 5ꢀ; external reference, 4.096V;
Logic Supply Rejection
(Note 12)
External reference, 4.096V; full-scale input
Maxim Integrated
4
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS
(V
= +5V 5ꢀ, V = 2.7V to 5.25V; V = 0V or -5V 5ꢀ; f
= 2.0MHz, external clock (50ꢀ duty cycle); 15 clocks/conversion
SCLK
DD
L
SS
cycle (133ksps); 4.7µF capacitor at REF; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS: DIN, SCLK, CS, SHDN
V
2.0
V
V
DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
SHDN Input High Voltage
IH
V
IL
0.8
V
0.15
V
HYST
I
V
= 0V or V
DD
1
µA
pF
V
IN
IN
C
IN
(Note 6)
15
V
V
V
- 0.5
SH
DD
1.5
V
DD
- 1.5
V
SHDN Input Mid-Voltage
SM
V
FLT
2.75
V
SHDN Voltage, Open
SHDN = open
V
0.5
4.0
V
SHDN Input Low Voltage
SL
I
µA
µA
SHDN Input Current, High
SHDN Input Current, Low
SHDN = V
SH
DD
I
SL
V
SHDN
= 0V
-4.0
SHDN Maximum Allowed
Leakage, Mid-Input
-100
100
0.4
nA
SHDN = open
DIGITAL OUTPUTS: DOUT, SSTRB (V = 2.7V to 3.6V)
L
I
I
I
= 3mA
SINK
Output Voltage Low
V
OL
V
= 6mA
0.3
0.3
SINK
Output Voltage High
V
OH
= 1mA
SOURCE
V - 0.5
L
V
Three-State Leakage Current
Three-State Output Capacitance
I
10
15
µA
pF
CS = V
L
L
C
OUT
CS = V (Note 6)
L
DIGITAL OUTPUTS: DOUT, SSTRB (V = 4.75V to 5.25V)
L
I
I
I
= 5mA
0.4
SINK
Output Voltage Low
V
V
OL
= 8mA
SINK
Output Voltage High
V
OH
= 1mA
SOURCE
4
V
Three-State Leakage Current
Three-State Output Capacitance
I
V
CS
V
CS
= 5V
10
15
µA
pF
L
C
= 5V (Note 6)
OUT
Maxim Integrated
5
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
TIMING CHARACTERISTICS
(V
= +5V 5ꢀ, V = 2.7V to 3.6V, V = 0V or -5V 5ꢀ, T = T
to T
, unless otherwise noted.)
MAX
DD
L
SS
A
MIN
PARAMETER
Acquisition Time
SYMBOL
t
ACQ
CONDITIONS
MIN
1.5
TYP
MAX
UNITS
µs
DIN to SCLK Setup
t
100
ns
DS
DH
DO
DIN to SCLK Hold
t
0
ns
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
t
C
C
C
= 100pF
= 100pF
= 100pF
20
240
240
240
ns
LOAD
LOAD
LOAD
t
ns
DV
t
ns
TR
t
100
0
ns
CSS
CSH
t
ns
t
200
200
ns
CH
t
ns
CL
t
C
LOAD
= 100pF
240
240
ns
SSTRB
CS Fall to SSTRB Output Enable
(Note 6)
t
External clock mode only, C
External clock mode only, C
Internal clock mode only
= 100pF
= 100pF
ns
ns
ns
SDV
LOAD
CS Rise to SSTRB Output
Disable (Note 6)
t
240
STR
LOAD
SSTRB Rise to SCLK Rise
(Note 6)
t
0
SCK
Note 1: Tested at V
= 5.0V; V = 0V; unipolar input mode.
SS
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is
DD
calibrated.
Note 3: Internal reference, offset nulled.
Note 4: On-channel grounded; sine-wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50ꢀ duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from V to V
.
DD
SS
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with V at 3.3V, and with all digital inputs tied to either V or GND (Figure 12c);
L
L
REFADJ = GND.
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on f , and on the static and capacitive load at DOUT and SSTRB.
SCLK
Note 11: Measured at V
+5ꢀ and V
-5ꢀ only.
SUPPLY
L
SUPPLY
Note 12: Measured at V = 2.7V and V = 3.6V.
L
Maxim Integrated
6
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
__________________________________________Typical Operating Characteristics
(V
= 5V 5ꢀ; V = 2.7V to 3.6V; f
= 2.0MHz, external clock (50ꢀ duty cycle); 15 clocks/conversion cycle (133ksps);
DD
L
SCLK
4.7µF capacitor at REF; T = +25°C; unless otherwise noted.)
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
2.0
2.0
6
5
REFADJ = GND
1.8
1.6
1.8
1.6
4
3
1.4
1.2
1.0
1.4
1.2
1.0
2
1
0
4.5
4.7
4.9
5.1
5.3
5.5
-60
-20
20
60
100
140
-60
-20
20
60
100
140
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
9
V
SS
Negative Supply Voltage. Tie V to -5V 5ꢀ or GND.
SS
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1204 down to 10µA (max) supply
current; otherwise, the MAX1204 is fully operational. Pulling SHDN to V
amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in
external compensation mode.
puts the reference-buffer
DD
10
11
SHDN
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode,
REF
disable the internal buffer by pulling REFADJ to V
DD.
12
13
REFADJ
GND
Input to the Reference-Buffer Amplifier. Tie REFADJ to V to disable the reference-buffer amplifier.
DD
Ground; IN- Input for Single-Ended Conversions
Supply Voltage for Digital Output Pins. Voltage applied to V determines the positive output swing of
L
the Digital Outputs (DOUT, SSTRB).
14
15
V
L
DOUT
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1204 begins the analog-
to-digital conversion and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
16
SSTRB
17
18
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
CS
Serial-Clock Input. SCLK clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed. (Duty cycle must be 40ꢀ to 60ꢀ in external clock mode.)
19
20
SCLK
V
DD
Positive Supply Voltage, +5V 5ꢀ
Maxim Integrated
7
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
+3.3V
3kΩ
DOUT
DOUT
18
19
CS
SCLK
C
3kΩ
INPUT
SHIFT
C
LOAD
LOAD
INT
17
10
DIN
CLOCK
REGISTER
CONTROL
LOGIC
SHDN
GND
a. High-Z to V and V to V
OH
GND
1
2
3
4
5
6
7
8
CH0
15
16
b. High-Z to V and V to V
OH
OL
OL
OH
OL
OUTPUT
SHIFT
REGISTER
DOUT
CH1
CH2
CH3
CH4
CH5
SSTRB
Figure 1. Load Circuits for Enable Time
ANALOG
INPUT
MUX
T/H
CLOCK
+3.3V
IN
SAR
ADC
CH6
CH7
OUT
3kΩ
20
14
9
13
REF
V
V
DD
L
GND
DOUT
DOUT
A ≈ 1.68
+2.44V
REFERENCE
20k
V
3kΩ
SS
C
C
LOAD
12
11
LOAD
REFADJ
REF
MAX1204
+4.096V
GND
GND
a. V to High-Z
OH
b. V to High-Z
OL
Figure 2. Load Circuits for Disable Time
Figure 3. Block Diagram
GND during a conversion. To do this, connect a 0.1µF
capacitor from IN- (of the selected analog input) to
GND.
_______________Detailed Description
The MAX1204 uses a successive-approximation con-
version technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to 3V
microprocessors (µPs). Figure 3 is the MAX1204 block
diagram.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
. The
HOLD
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
Pseudo-Differential Input
Figure 4 shows the analog-to-digital converter’s
(ADC’s) analog comparator’s sampling architecture. In
single-ended mode, IN+ is internally switched to
CH0–CH7 and IN- is switched to GND. In differential
mode, IN+ and IN- are selected from pairs of CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels using Tables 3 and 4.
the acquisition interval, retaining charge on C
sample of the signal at IN+.
as a
HOLD
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
HOLD
negative input (IN-). In single-ended mode, IN- is sim-
ply GND. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable with-
in 0.5 LSB ( 0.1 LSB for best results) with respect to
[(V +) - (V -)] from C to the binary-weighted
HOLD
IN
IN
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Maxim Integrated
8
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
impedances can be used if an input capacitor is con-
nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
Track/Hold
The T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN- is connect-
ed to GND if the converter is set up for single-ended
inputs, and the converter samples the “+” input. IN- con-
nects to the “-” input if the converter is set up for differen-
CAPACITIVE DAC
REF
⏐
⏐
tial inputs, and the difference of |N+ - IN- is sampled.
The positive input connects back to IN+ at the end of
COMPARATOR
INPUT
MUX
C
HOLD
ZERO
HOLD
–
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
the conversion, and C
charges to the input signal.
HOLD
16pF
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
acquisition time increases and more time must be
allowed between conversions. The acquisition time,
9k
R
IN
C
SWITCH
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN– CHANNEL.
T/H
SWITCH
t
ACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following:
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = GND.
DIFFERENTIAL MODE:
IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
tACQ = 7 x (RS + RIN) x 16pF
where RIN = 9kΩ, RS = the source impedance of the
input signal, and tACQ is never less than 1.5µs. Note that
source impedances below 4kΩ do not significantly
affect the ADC’s AC performance. Higher source
Figure 4. Equivalent Input Circuit
+3V
V
V
+5V
L
DD
OSCILLOSCOPE
0.1µF
0.1µF
GND
SCLK
V
SS
MAX1204
SSTRB
DOUT
0V TO
4.096V
ANALOG
INPUT
CH7
CS
SCLK
DIN
0.01µF
CH4
2MHz
OSCILLATOR
CH3
CH1
CH2
+3V
SSTRB
DOUT
REFADJ
REF
SHDN
N.C.
C2
0.01µF
C1
4.7µF
FULL-SCALE ANALOG INPUT
Figure 5. Quick-Look Circuit
Maxim Integrated
9
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Table 1a. Unipolar Full Scale
Table 1b. Bipolar Full Scale, Zero Scale,
and Zero Scale
and Negative Full Scale
ZERO
REFERENCE
NEGATIVE
ZERO
FULL SCALE
REFERENCE
FULL SCALE
SCALE
FULL SCALE SCALE
Internal
External
0V
0V
0V
+4.096V
Internal
-4.096V/2
0V
0V
0V
+4.096V / 2
at REFADJ
at REF
V
x 1.68
REFADJ
at
-1/2 V
x
+1/2 V
REFADJ
REFADJ
1.68
REFADJ
x 1.68
V
REF
External
at REF
-1/2 V
REF
+1/2 V
REF
which triggers single-ended unipolar conversions on
CH7 in external clock mode without powering down
between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result shifts out
of DOUT. Varying the analog input to CH7 alters the
sequence of bits from DOUT. A total of 15 clock cycles
per conversion is required. All SSTRB and DOUT output
transitions occur on SCLK’s falling edge.
Input Bandwidth
The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth. Therefore, it is possible to digi-
tize high-speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Range and Input Protection
How to Start a Conversion
Clocking a control byte into DIN starts conversion on
the MAX1204. With CS low, each rising edge on SCLK
clocks a bit from DIN into the MAX1204’s internal shift
register. After CS falls, the first logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with
no effect. Table 2 shows the control-byte format.
Internal protection diodes, which clamp the analog
inputs to V
and V , allow the analog input pins to
SS
DD
swing from (V - 0.3V) to (V
+ 0.3V) without dam-
DD
SS
age. However, for accurate conversions near full scale,
the inputs must not exceed V by more than 50mV, or
DD
be lower than V by 50mV.
SS
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off-channels over 2mA, as excessive current
degrades on-channel conversion accuracy.
The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).
The MAX1204 is fully compatible with MICROWIRE and
SPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. MICROWIRE and SPI both
transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest soft-
ware interface requires only three 8-bit transfers to per-
form a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the con-
version result).
Quick Look
Use the circuit of Figure 5 to quickly evaluate the
MAX1204’s analog performance. The MAX1204 requires
that a control byte be written to DIN before each conver-
sion. Tying DIN to +3V feeds in control byte $FF hex,
Maxim Integrated
10
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
MAX1204
Table 2. Control-Byte Format
Bit 7
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSB)
(LSB)
START
SEL 2
SEL 1
SEL 0
PD1
PD0
UNI/BIP
SGL/DIF
Bit
Name
Description
7 (MSB)
START
The first logic 1 bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels is used for the conversion
(Tables 3 and 4).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to V can be converted; in bipolar mode, the signal can range
3
2
UNI/BIP
SGL/DIF
REF
from -V
/ 2 to +V
/ 2.
REF
REF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to GND. In differential mode, the voltage dif-
ference between two channels is measured. (Tables 3 and 4.)
Selects clock and power-down modes.
PD1
0
PD0
0
Mode
Full power-down (I
Fast power-down (I
Internal clock mode
External clock mode
= 2µA, internal reference)
= 30µA, internal reference)
1
PD1
PD0
DD
DD
0 (LSB)
0
1
1
0
1
1
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
+
–
–
–
+
–
+
–
+
+
Maxim Integrated
11
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
PD0 of the control byte program the clock mode.
Figures 7–10 show the timing characteristics common
to both modes.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the A/D conversion
steps. SSTRB pulses high for one clock period after the
last bit of the control byte. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.
1) Set up the control byte for external clock mode and
call it TB1. TB1’s format should be: 1XXXXX11 binary,
where the Xs denote the particular channel and
conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS on the MAX1204 low.
3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB2.
The conversion must complete in some minimum time or
droop on the sample-and-hold can degrade conversion
results. Use internal clock mode if the clock period
exceeds 10µs or if serial-clock interruptions could cause
the conversion interval to exceed 120µs.
5) Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB3.
6) Pull CS on the MAX1204 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with one leading zero, two trailing sub-bits (S1 and S0),
and three trailing zeros. Total conversion time is a func-
tion of the serial clock frequency and the amount of idle
time between 8-bit transfers. To avoid excessive T/H
droop, make sure that the total conversion time does
not exceed 120µs.
Internal Clock
In internal clock mode, the MAX1204 generates its own
conversion clock. This frees the µP from running the
SAR conversion clock, and allows the conversion
results to be read back at the processor’s convenience,
at any clock rate from zero to 2MHz. SSTRB goes low
at the start of the conversion, then goes high when the
conversion is complete. SSTRB is low for a maximum of
10µs, during which time SCLK should remain low for
best noise performance. An internal register stores data
while the conversion is in progress. SCLK clocks the
data out at this register at any time after the conversion
is complete. After SSTRB goes high, the next falling
clock edge produces the MSB of the conversion at
DOUT, followed by the remaining bits in MSB-first for-
mat (Figure 9). CS does not need to be held low once a
conversion is started. Pulling CS high prevents data
from being clocked into the MAX1204 and three-states
DOUT, but it does not adversely affect an internal
clock-mode conversion already in progress. When
internal clock mode is selected, SSTRB does not go
high impedance when CS goes high.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 15); for bipolar inputs, the output is two’s-
complement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format. The digital output logic
level is adjusted with the V pin. This allows DOUT and
L
SSTRB to interface with 3V logic without the risk of
overdrive. The MAX1204’s digital inputs are designed
to be compatible with 3V CMOS logic as well as 5V
logic.
Internal and External Clock Modes
The MAX1204 can use either an external serial clock
or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the MAX1204.
The T/H acquires the input signal as the last three bits
of the control byte are clocked into DIN. Bits PD1 and
Figure 10 shows the SSTRB timing in internal clock
mode. Data can be shifted in and out of the MAX1204 at
clock rates up to 2.0MHz if the acquisition time, tACQ, is
kept above 1.5µs.
Maxim Integrated
12
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
CS
t
ACQ
SCLK
1
4
8
12
16
20
24
UNI/ SGL/
DIN
SSTRB
DOUT
SEL2 SEL1 SEL0
PD1 PD0
BIP
DIF
START
RB2
B6
RB3
S1
RB1
FILLED WITH
ZEROS
B9
MSB
B0
LSB
B8
B7
B5
B4
B3
B2
B1
S0
ACQUISITION
1.5µs
(SCLK = 2MHz)
CONVERSION
IDLE
IDLE
ADC STATE
Figure 6. 24-Bit External-Clock-Mode Conversion Timing (Microwire/SPI Compatible)
• • •
• • •
CS
t
t
t
CSH
CSS
CH
t
t
CL
CSH
SCLK
t
DS
t
DH
DIN
• • •
• • •
t
DV
t
t
TR
DO
DOUT
Figure 7. Detailed Serial-Interface Timing
CS
• • •
• • •
t
t
STR
SDV
SSTRB
• • •
• • •
• • •
t
t
SSTRB
SSTRB
• • •
SCLK
PD0 CLOCKED IN
Figure 8. External Clock-Mode SSTRB Detailed Timing
Maxim Integrated
13
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
CS
SCLK
DIN
1
4
8
18
24
2
3
5
6
7
9
10
11
12
19
20
21
22
23
UNI/ SGL/
DIP DIF
SEL2 SEL1 SEL0
PD1 PD0
START
SSTRB
t
CONV
FILLED WITH
ZEROS
B9
MSB
B0
LSB
DOUT
B8
B7
S1
S0
ACQUISITION
1.5µs
(SCLK = 2MHz)
CONVERSION
10µs MAX
IDLE
IDLE
ADC STATE
Figure 9. Internal Clock Mode Timing
CS • • •
t
t
CONV
CSS
t
t
SCK
CSH
SSTRB • • •
SCLK • • •
t
SSTRB
PD0 CLOCK IN
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
Data Framing
If a falling edge on CS forces a start bit before B3
becomes available, the current conversion is termi-
nated and a new one started. Thus, the fastest the
MAX1204 can run is 15 clocks/conversion. Figure 11a
shows the serial-interface timing necessary to perform
a conversion every 15 SCLK cycles in external clock
mode. If CS is low and SCLK is continuous, guarantee
a start bit by first clocking in 16 zeros.
CS’s falling edge does not start a conversion on the
MAX1204. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on SCLK’s falling edge after the
eighth bit of the control byte (the PD0 bit) is clocked into
DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any-
time the converter is idle; (e.g., after VDD is applied).
Most microcontrollers (µCs) require that conversions
occur in multiples of eight SCLK clocks; 16 clocks per
conversion is typically the fastest that a µC can drive
the MAX1204. Figure 11b shows the serial-interface
timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
or
The first high bit clocked into DIN after bit 3 (B3) of a
conversion in progress appears at DOUT.
Maxim Integrated
14
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
CS
1
8
1
8
1
15
15
SCLK
DIN
S
CONTROL BYTE 2
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DOUT
SSTRB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
• • •
CS
• • •
• • •
• • •
SCLK
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DIN
DOUT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6 B5
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Float SHDN to select external compensation. The Typical
Operating Circuit uses a 4.7µF capacitor at REF. A value
of 4.7µF or greater ensures stability and allows converter
operation at the 2MHz full clock speed. External com-
pensation increases power-up time (see the section
Choosing Power-Down Mode, and Table 5).
__________ Applications Information
Power-On Reset
When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1204 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies are stabilized,
the internal reset time is 100µs. No conversions should
be performed during this phase. SSTRB is high on
power-up, and if CS is low, the first logical 1 on DIN is
interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros.
Internal compensation requires no external capacitor at
REF, and is selected by pulling SHDN high. Internal com-
pensation allows for the shortest power-up times, but is
only available using an external clock up to 400kHz.
Power-Down
Choosing Power-Down Mode
You can save power by placing the converter in a
low-current shutdown state between conversions.
Select full power-down or fast power-down mode via
bits 1 and 0 of the DIN control byte with SHDN high or
open (Tables 2 and 6). Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
Reference-Buffer Compensation
In addition to its shutdown function, SHDN also selects
internal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. Compensated or not, the minimum clock rate is
100kHz due to droop on the sample-and-hold.
Maxim Integrated
15
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Full power-down mode turns off all chip functions
that draw quiescent current, reducing IDD and ISS typi-
cally to 2µA.
From fast power-down, start-up time can be eliminated
by using low-leakage capacitors that do not discharge
more than 1/2 LSB while shut down. In power-down, the
capacitor has to supply the current into the reference
(typically 1.5µA) and the transient currents at power-up.
Fast power-down mode turns off all circuitry except the
bandgap reference. With fast power-down mode, the
supply current is 30µA. Power-up time can be shortened
to 5µs in internal compensation mode.
Figures 12a and 12b show the various power-down
sequences in both external and internal clock modes.
The I
shutdown current can increase if any digital input
DD
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify clock mode. When software power-
down is asserted, the ADC continues to operate in the
last specified clock mode until the conversion is com-
plete. The ADC then powers down into a low
quiescent-current state. In internal clock mode, the
interface remains active and conversion results can be
clocked out even though the MAX1204 has already
entered a software power-down.
(DIN, SCLK, CS) is held high in either power-down mode.
The actual shutdown current depends on the state of the
digital inputs, the voltage applied to the digital inputs
(V ), the supply voltage (V ), and the operating temper-
IH
DD
ature. Figure 12c shows the maximum I
increase for
DD
each digital input held high in power-down mode for differ-
ent operating conditions. This current is cumulative, so if
all three digital inputs are held high, the additional shut-
down current is three times the value shown in Figure 12c.
In both software power-down modes, the serial interface
remains operational, but the ADC does not convert.
Table 5 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate.
The first logical 1 on DIN is interpreted as a start bit
and powers up the MAX1204. Following the start bit,
the control byte also determines clock and power-down
modes. For example, if the control byte contains PD1 =
1, the chip remains powered up. If PD1 = 0,
power-down resumes after one conversion.
In external compensation mode, power-up time is 20ms
with a 4.7µF compensation capacitor (200ms with a 33µF
capacitor) when the capacitor is initially fully discharged.
Table 5. Typical Power-Up Delay Times
REFERENCE
MAXIMUM
POWER-UP
REFERENCE
BUFFER
REFERENCE-BUFFER
COMPENSATION MODE
POWER-DOWN
MODE
CAPACITOR
SAMPLING RATE
(ksps)
DELAY (µs)
(µF)
Enabled
Enabled
Enabled
Disabled
Disabled
Internal
Internal
External
—
—
Fast
Full
5
26
—
300
26
4.7
—
Fast/Full
Fast
See Figure 14c
133
133
133
2
2
—
—
Full
Table 7. Hard-Wired Shutdown and
Compensation Mode
Table 6. Software Shutdown and
Clock Mode
DEVICE
MODE
REFERENCE-BUFFER
SHDN
STATE
PD1
PD0
DEVICE MODE
COMPENSATION
1
1
0
0
1
0
1
0
External clock mode
Internal clock mode
Fast power-down mode
Full power-down mode
V
Enabled
Internal compensation
External compensation
DD
Open
Enabled
Full
Power-Down
GND
N/A
Maxim Integrated
16
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
CLOCK
MODE
INTERNAL
EXTERNAL
EXTERNAL
SHDN
SETS FAST
POWER-DOWN
MODE
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
DIN
S
X
X X X X 1
1
S X
X
X X X 0
1
S
X X X X X 1
1
DOUT
DATA VALID
(10 + 2 DATA BITS)
DATA VALID
(10 + 2 DATA BITS)
DATA
INVALID
FULL
POWER-
DOWN
POWERED UP
MODE
POWERED UP
POWERED
UP
FAST
POWER-DOWN
Figure 12a. Timing Diagram for Power-Down Modes (External Clock)
CLOCK
MODE
INTERNAL CLOCK MODE
SETS FULL
POWER-DOWN
SETS INTERNAL
CLOCK MODE
DIN
S
X
X X X X 1
0
S X
X
X X X 0
0
S
DOUT
DATA VALID
DATA VALID
SSTRB
MODE
CONVERSION
CONVERSION
FULL
POWER-DOWN
POWERED UP
POWERED
UP
Figure 12b. Timing Diagram for Power-Down Modes (Internal Clock)
Hardware Power-Down
The SHDN pin places the converter into full
power-down mode. Unlike the software power-down
modes, conversion is not completed; it stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference, which is not
shut down, is used. SHDN also selects internal or
external reference compensation (Table 7).
Lowest Power at up to
500 Conversions per Channel per Second
Figure 14a depicts MAX1204’s power consumption for one
or eight channel conversions using full power-down mode
and internal reference compensation. A 0.01µF bypass
capacitor at REFADJ forms an RC filter with the internal
20kΩ reference resistor, with a 0.2ms time constant. To
achieve full 10-bit accuracy, 10 time constants (or 2ms in
this example) are required for the reference buffer to settle.
When exiting FULLPD, waiting this 2ms in FASTPD mode
(instead of just exiting FULLPD mode and returning to nor-
mal operating mode) reduces power consumption by a
factor of 10 or more (Figure 13).
Power-Down Sequencing
The MAX1204’s automatic power-down modes can
save considerable power when operating at less than
maximum sample rates. The following sections discuss
the various power-down sequences.
Maxim Integrated
17
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Lowest Power at Higher Throughputs
Figure 14b shows power consumption with external-
reference compensation in fast power-down, with one and
eight channels converted. The external 4.7µF compensa-
tion requires a 50µs wait after power-up. This circuit com-
bines fast multichannel conversion with the lowest power
consumption possible. Full power-down mode can
increase power savings in applications where the
MAX1204 is inactive for long periods of time, but where
intermittent bursts of high-speed conversions are required.
An internal buffer is designed to provide 4.096V at REF
for the MAX1204. Its internally trimmed 2.44V reference
is buffered with a 1.68 nominal gain.
Internal Reference
The MAX1204’s full-scale range with internal reference is
4.096V with unipolar inputs and 2.048V with bipolar
inputs. The internal reference voltage is adjustable to
1.5ꢀ with the circuit of Figure 17.
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1204’s internal
buffer amplifier. The REFADJ input impedance is typical-
ly 20kΩ. At REF, the input impedance is a minimum of
12kΩ for DC currents. During conversion, an external
reference at REF must deliver up to 350µA DC load cur-
rent and have an output impedance of 10Ω or less. If the
reference has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7µF capacitor.
External and Internal References
The MAX1204 can be used with an internal or external
reference. An external reference can be connected
directly at the REF terminal or at the REFADJ pin.
40
35
(V - V ) = 2.55V
DD
IH
30
25
20
15
10
5
Using the buffered REFADJ input makes buffering of
the external reference unnecessary. To use the direct
REF input, disable the internal buffer by tying REFADJ
to VDD. In power-down, the input bias current to
REFADJ can be as much as 25µA with REFADJ tied to
(V - V ) = 2.25V
V
. Pull REFADJ to GND to minimize the input bias
DD
IH
DD
current in power-down.
(V - V ) = 1.95V
DD
IH
Transfer Function and Gain Adjust
0
Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive integer LSB values. Output coding
is binary with 1 LSB = 4mV (4.096V/1024) for
unipolar operation and 1 LSB = 4mV [(4.096V/2 -
-4.096V/2)/1024] for bipolar operation.
-60
-20
20
60
100
140
TEMPERATURE (°C)
Figure 12c. Additional IDD Shutdown Supply Current vs. VIH
for Each Digital Input at a Logic 1
COMPLETE CONVERSION SEQUENCE
2ms WAIT
0 1
(ZEROS)
CH1
CH7
(ZEROS)
DIN
1
0 0
1
1
1 1
1
0 0
1
0 1
FULLPD
2.5V
FASTPD
NOPD
FULLPD
FASTPD
REFADJ
REF
0V
4V
0V
τ = RC = 20kΩ x C
REFADJ
t
≈ 15µs
BUFFEN
Figure 13. MAX1204 FULLPD/FASTPD Power-Up Sequence
18
Maxim Integrated
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
FULL POWER-DOWN
3.0
2.5
2.0
1.5
1.0
1000
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
8 CHANNELS
1 CHANNEL
100
10
0.5
0
1
0.0001 0.001
0.01
0.1
1
10
0
50 100 150 200 250 300 350 400 450 500
CONVERSIONS PER CHANNEL PER SECOND
TIME IN SHUTDOWN (sec)
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
Figure 14a. MAX1204 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock
Layout, Grounding, Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
FAST POWER-DOWN
10,000
8 CHANNELS
1000
Figure 18 shows the recommended system-ground con-
nections. Establish a single-point analog ground (star
ground point) at GND. Connect all other analog grounds
to this ground. No other digital system ground should be
connected to this single-point analog ground. The
ground return to the power supply should be low imped-
ance and as short as possible for noise-free operation.
1 CHANNEL
100
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
10
High-frequency noise in the VDD power supply may affect
the high-speed comparator in the ADC. Bypass these
supplies to the single-point analog ground with 0.1µF and
4.7µF bypass capacitors close to the MAX1204. Minimize
capacitor lead lengths for best supply-noise rejection. If
the +5V power supply is very noisy, a 10Ω resistor can
be connected as a lowpass filter, as shown in Figure 18.
0
2k
4k
6k
8k 10k 12k 14k 16k 18k
CONVERSIONS PER CHANNEL PER SECOND
Figure 14b. MAX1204 Supply Current vs. Sample Rate/Second,
FASTPD, 2MHz Clock
Figure 17, the Reference-Adjust Circuit, shows how to
adjust ADC gain in applications that use the internal
reference. The circuit provides 1.5ꢀ ( 16 LSBs) of
gain-adjustment range.
Maxim Integrated
19
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
OUTPUT CODE
+5V
MAX1204
REFADJ
FULL-SCALE
TRANSITION
11 . . . 111
510kΩ
100kΩ
11 . . . 110
12
11 . . . 101
0.01µF
24kΩ
FS = +4.096V
FS
1024
1 LSB =
Figure 17. Reference-Adjust Circuit
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
3
FS
SUPPLIES
FS - 3/2 LSB
INPUT VOLTAGE (LSBs)
+5V
-5V
+3V
GND
Figure 15. Unipolar Transfer Function, 4.096V = Full Scale
R* = 10Ω
V
GND
V
SS
V
L
+3V
DGND
DD
OUTPUT CODE
011 . . . 111
DIGITAL
CIRCUITRY
MAX1204
011 . . . 110
+4.096V
FS =
2
*OPTIONAL
+4.096V
1 LSB =
000 . . . 010
000 . . . 001
000 . . . 000
1024
Figure 18. Power-Supply Grounding Connection
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
0V
-FS
+FS - 1 LSB
INPUT VOLTAGE (LSBs)
Figure 16. Bipolar Transfer Function, 4.096V/2 = Full Scale
20
Maxim Integrated
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
TMS320CL3x to MAX1204 Interface
Figure 19 shows an application circuit to interface the
MAX1204 to the TMS320 in external clock mode. Figure
20 is the timing diagram for this interface circuit.
XF
CLKX
CLKR
DX
CS
Use the following steps to initiate a conversion in the
MAX1204 and to read the results.
SCLK
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
The TMS320’s CLKX and CLKR are tied together with
the MAX1204’s SCLK input.
TMS320LC3x
MAX1204
DIN
2) The MAX1204’s CS is driven low by the TMS320’s
XF_ I/O port to enable data to be clocked into the
MAX1204’s DIN.
DR
DOUT
FSR
SSTRB
3) Write an 8-bit word (1XXXXX11) to the MAX1204 to
initiate a conversion and place the device into exter-
nal clock mode. Refer to Table 2 to select the proper
XXXXX bit values for your specific application.
4) The MAX1204’s SSTRB output is monitored via the
TMS320’s FSR input. A falling edge on the SSTRB
output indicates that the conversion is in progress
and data is ready to be received from the MAX1204.
Figure 19. MAX1204 to TMS320 Serial Interface
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits repre-
sent the 10-bit conversion result followed by two
sub-bits and four trailing bits, which should be
ignored.
6) Pull CS high to disable the MAX1204 until the next
conversion is initiated.
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
HIGH
IMPEDANCE
DOUT
MSB
LSB
Figure 20. TMS320 Serial-Interface Timing Diagram
Maxim Integrated
21
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
_Ordering Information (continued)
__________Typical Operating Circuit
TOP
MARK
PIN-
PACKAGE
PART
TEMP RANGE
+5V
+3V
V
V
CH0
CH7
DD
DD
MAX1204AEPP+
MAX1204BEPP+
MAX1204AEAP+
MAX1204BEAP+
-40°C to +85°C 20 PDIP
-40°C to +85°C 20 PDIP
-40°C to +85°C 20 SSOP
-40°C to +85°C 20 SSOP
1/2
1
C3
0.1µF
0V to
4.096V
ANALOG
INPUTS
V
L
MAX1204
C4
0.1µF
1/2
1
GND
CPU
V
SS
+Denotes a lead(Pb)-free/RoHS-compliant package.
I/O
CS
SCLK
SCK (SK)
MOSI (SO)
MISO (SI)
REF
DIN
C1
DOUT
4.7µF
___________________Chip Information
SSTRB
SHDN
REFADJ
C2
0.01µF
V
SS
SUBSTRATE CONNECTED TO V
SS
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
LAND
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
PATTERN NO.
—
90-0094
20 PDIP
P20+3
21-0043
21-0056
20 SSOP
A20+2
Maxim Integrated
22
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
1/97
1/12
Initial release
Remove military grade packages.
—
22
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 23
© 2012 Maxim Integrated
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
相关型号：
MAX1205CMH+
ADC, Proprietary Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PQFP44, ROHS COMPLIANT, MO-108AA-2, MQFP-44
MAXIM
MAX1205CMH+T
ADC, Proprietary Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PQFP44, MO-108AA-2, MQFP-44
MAXIM
MAX1205CMH-T
ADC, Proprietary Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PQFP44, M0-108AA-2, MQFP-44
MAXIM
MAX1205EMH-T
ADC, Proprietary Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PQFP44, M0-108AA-2, MQFP-44
MAXIM
©2020 ICPDF网 联系我们和版权申明