MAX1208ETL+T [MAXIM]
ADC, Flash Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, 6 X 6 MM, 0.8 MM HEIGHT, MO-220-WJJD, TQFN-40;
| 型号： | MAX1208ETL+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Flash Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, 6 X 6 MM, 0.8 MM HEIGHT, MO-220-WJJD, TQFN-40 转换器 |
| 文件： | 总27页 (文件大小：1036K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1002; Rev 0; 8/04
12-Bit, 80Msps, 3.3V ADC
General Description
Features
The MAX1208 is a 3.3V, 12-bit, 80Msps analog-to-digital
converter (ADC) featuring a fully differential wideband
track-and-hold (T/H) input amplifier, driving a low-noise
internal quantizer. The analog input stage accepts single-
ended or differential signals. The MAX1208 is optimized
for low power, small size, and high dynamic performance
in baseband applications.
♦ Excellent Dynamic Performance
68.2dB/68.0dB SNR at f = 3MHz/70MHz
89.3dBc/85.1dBc SFDR at f = 3MHz/70MHz
IN
IN
♦ 3.3V Low-Power Operation
373mW (Single-Ended Clock Mode)
399mW (Differential Clock Mode)
3µW (Power-Down Mode)
Powered from a single 3.0V to 3.6V supply, the
MAX1208 consumes only 373mW while delivering a
typical signal-to-noise (SNR) performance of 68.2dB at
an input frequency of 32.5MHz. In addition to low oper-
ating power, the MAX1208 features a 3µW power-down
mode to conserve power during idle periods.
♦ Differential or Single-Ended Clock
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Full-Scale Analog Input Range: 0.35V
to 1.15V
♦ Common-Mode Reference
A flexible reference structure allows the MAX1208 to use
the internal 2.048V bandgap reference or accept an
externally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from 0.35V to 1.15V. The MAX1208 provides a com-
mon-mode reference to simplify design and reduce exter-
nal component count in differential analog input circuits.
The MAX1208 supports both a single-ended and differ-
ential input clock drive. Wide variations in the clock
duty cycle are compensated with the ADC’s internal
duty-cycle equalizer (DCE).
ADC conversion results are available through a 12-bit,
parallel, CMOS-compatible output bus. The digital out-
put format is pin selectable to be either two’s comple-
ment or Gray code. A data-valid indicator eliminates
external components that are normally required for reli-
able digital interfacing. A separate digital power input
accepts a wide 1.7V to 3.6V supply, allowing the
MAX1208 to interface with various logic levels.
♦ CMOS-Compatible Outputs in Two’s Complement
or Gray Code
♦ Data-Valid Indicator Simplifies Digital Design
♦ Data Out-of-Range Indicator
♦ Miniature, 40-Pin Thin QFN Package with Exposed
Paddle
♦ Evaluation Kit Available (Order MAX1211EVKIT)
Ordering Information
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
40 Thin QFN
(6mm x 6mm x
0.8mm)
MAX1208ETL -40°C to +85°C
T4066-3
The MAX1208 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to
+85°C) temperature range.
See the Pin-Compatible Versions table for a complete
family of 14-bit and 12-bit high-speed ADCs.
Pin-Compatible Versions
SAMPLING
RATE (Msps)
RESOLUTION
(BITS)
TARGET
APPLICATION
PART
MAX12553
MAX1209
MAX1211
MAX1208
MAX1207
MAX1206
65
80
65
80
65
40
14
12
12
12
12
12
IF/Baseband
IF
Applications
Communication Receivers
IF
Cellular, Point-to-Point Microwave, HFC, WLAN
Baseband
Baseband
Baseband
Ultrasound and Medical Imaging
Portable Instrumentation
Low-Power Data Acquisition
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12-Bit, 80Msps, 3.3V ADC
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND...........................................................-0.3V to +3.6V
D11 Through D0 I.C., DAV, DOR to GND...-0.3V to (OV + 0.3V)
DD
OV
to GND........-0.3V to the lower of (V
+ 0.3V) and +3.6V
+ 0.3V) and +3.6V
Continuous Power Dissipation (T = +70°C)
40-Pin Thin QFN 6mm x 6mm x 0.8mm
(derated 26.3mW/°C above +70°C)........................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
DD
DD
DD
A
INP, INN to GND ...-0.3V to the lower of (V
REFIN, REFOUT, REFP, REFN,
COM to GND......-0.3V to the lower of (V
CLKP, CLKN, CLKTYP, G/T, DCE,
PD to GND ........-0.3V to the lower of (V
+ 0.3V) and +3.6V
+ 0.3V) and +3.6V
DD
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
A
PARAMETER
DC ACCURACY (Note 2)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
Integral Nonlinearity
INL
f
f
= 20MHz
0.65
0.35
IN
= 20MHz, no missing codes over
IN
Differential Nonlinearity
DNL
-0.83
LSB
temperature
Offset Error
V
V
= 2.048V
= 2.048V
0.25
1.0
0.92
5.6
%FS
%FS
REFIN
REFIN
Gain Error
ANALOG INPUT (INP, INN)
Differential Input Voltage Range
Common-Mode Input Voltage
V
Differential or single-ended inputs
1.024
V
V
DIFF
V
/ 2
DD
2
C
Fixed capacitance to ground
Switched capacitance
PAR
Input Capacitance
(Figure 3)
pF
C
1.9
SAMPLE
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
f
80
MHz
MHz
CLK
5
Clock
cycles
Data Latency
Figure 6
8.5
DYNAMIC CHARACTERISTICS (differential inputs, Note 2)
Small-Signal Noise Floor
SSNF
Input at less than -35dBFS
-68.8
68.2
68.2
68.0
68.1
68.1
67.8
dBFS
dB
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 3MHz at -0.5dBFS
= 32.5MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 3MHz at -0.5dBFS
= 32.5MHz at -0.5dBFS
= 70MHz at -0.5dBFS
Signal-to-Noise Ratio
SNR
65.4
65.2
Signal-to-Noise and Distortion
SINAD
dB
2
_______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
A
PARAMETER
SYMBOL
CONDITIONS
fIN = 3MHz at -0.5dBFS
MIN
TYP
MAX
UNITS
89.3
88.2
85.1
-87.1
-85.0
-81.2
-93
Spurious-Free Dynamic Range
Total Harmonic Distortion
Second Harmonic
SFDR
THD
HD2
HD3
dBc
fIN = 32.5MHz at -0.5dBFS
fIN = 70MHz at -0.5dBFS
fIN = 3MHz at -0.5dBFS
fIN = 32.5MHz at -0.5dBFS
fIN = 70MHz at -0.5dBFS
fIN = 3MHz at -0.5dBFS
fIN = 32.5MHz at -0.5dBFS
fIN = 70MHz at -0.5dBFS
fIN = 3MHz at -0.5dBFS
fIN = 32.5MHz at -0.5dBFS
fIN = 70MHz at -0.5dBFS
78.7
-77.2
dBc
dBc
dBc
-89
-86.5
-96.8
-95.1
-85.1
Third Harmonic
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS
Intermodulation Distortion
Third-Order Intermodulation
IMD
IM3
-81.1
-84.4
85.4
dBc
dBc
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS
Two-Tone Spurious-Free
Dynamic Range
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS
SFDRTT
Aperture Delay
Aperture Jitter
Output Noise
tAD
tAJ
Figure 4
0.9
ns
Figure 4
<0.2
0.52
psRMS
LSBRM
nOUT
INP = INN = COM
Clock
cycles
Overdrive Recovery Time
10% beyond full scale
1
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally)
REFOUT Output Voltage
COM Output Voltage
VREFOUT
VCOM
1.978
2.048
1.65
1.024
35
2.079
V
V
VDD / 2
Differential Reference Output
VREF
VREF = VREFP - VREFN
V
REFOUT Load Regulation
mV/mA
ppm/°C
REFOUT Temperature Coefficient
TCREF
+50
0.24
2.1
Short to VDD—sinking
Short to GND—sourcing
REFOUT Short-Circuit Current
mA
BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated
internally)
REFIN Input Voltage
REFP Output Voltage
VREFIN
VREFP
2.048
2.162
V
V
(VDD/2) + (VREFIN / 4)
_______________________________________________________________________________________
3
12-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
A
PARAMETER
REFN Output Voltage
COM Output Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
(V / 2) - (V / 4)
REFIN
1.138
1.65
V
V
REFN
DD
V
V
/ 2
DD
1.60
1.70
COM
Differential Reference Output
Voltage
V
V
= V
- V
0.969
1.024
1.069
V
REF
REF
REFP
REFN
Differential Reference
Temperature Coefficient
25
ppm/°C
REFIN Input Resistance
>50
MΩ
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; V
, V
, and V
are applied externally)
REFP REFN
COM
COM Input Voltage
REFP Input Voltage
REFN Input Voltage
V
V
V
V
/ 2
DD
1.65
0.512
-0.512
V
V
V
COM
- V
REFP
REFN
COM
- V
COM
Differential Reference Input
Voltage
V
V
= V
- V
REFN
1.024
V
REF
REF
REFP
REFP Sink Current
I
V
V
= 2.162V
= 1.138V
1.1
1.1
0.3
13
6
mA
mA
mA
pF
REFP
REFP
REFN
REFN Source Current
COM Sink Current
I
REFN
I
COM
REFP, REFN Capacitance
COM Capacitance
pF
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold
0.8 x
V
CLKTYP = GND, CLKN = GND
V
V
IH
V
DD
Single-Ended Input Low
Threshold
0.2 x
V
CLKTYP = GND, CLKN = GND
CLKTYP = high
IL
V
DD
Differential Input Voltage Swing
1.4
/ 2
V
P-P
V
Differential Input Common-Mode
Voltage
CLKTYP = high
V
DD
Input Resistance
R
C
Figure 5
5
2
kΩ
CLK
Input Capacitance
pF
CLK
DIGITAL INPUTS (CLKTYP, G/T, PD)
0.8 x
OV
Input High Threshold
V
V
IH
DD
4
_______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
A
PARAMETER
Input Low Threshold
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.2 x
OV
UNITS
V
V
IL
DD
V
V
= OV
= 0
5
5
IH
IL
DD
Input Leakage Current
Input Capacitance
µA
pF
C
5
DIN
DIGITAL OUTPUTS (D11–D0, DAV, DOR)
D11–D0, DOR, I
= 200µA
0.2
0.2
SINK
Output Voltage Low
V
V
V
OL
DAV, I
= 600µA
SINK
OV
0.2
-
DD
D11–D0, DOR, I
= 200µA
SOURCE
Output Voltage High
V
OH
OV
0.2
-
DD
DAV, I
= 600µA
SOURCE
Tri-State Leakage Current
I
(Note 3)
(Note 3)
5
µA
pF
LEAK
D11–D0, DOR Tri-State Output
Capacitance
C
3
6
OUT
DAV
DAV Tri-State Output
Capacitance
C
(Note 3)
pF
POWER REQUIREMENTS
Analog Supply Voltage
V
3.0
1.7
3.3
2.0
3.6
DD
0.3V
V
V
DD
V
+
Digital Output Supply Voltage
Analog Supply Current
OV
DD
Normal operating mode,
= 32.5MHz at -0.5dBFS,
CLKTYP = GND, single-ended clock
f
IN
113
I
Normal operating mode,
mA
VDD
121
0.001
373
132.2
f
= 32.5MHz at -0.5dBFS,
IN
CLKTYP = OV
differential clock
DD,
Power-down mode clock idle, PD = OV
DD
Normal operating mode,
f
IN
= 32.5MHz at -0.5dBFS,
CLKTYP = GND, single-ended clock
Analog Power Dissipation
P
Normal operating mode,
mW
DISS
f
IN
= 32.5MHz at -0.5dBFS,
399
436.3
CLKTYP = OV , differential clock
DD
Power-down mode clock idle, PD = OV
0.003
DD
_______________________________________________________________________________________
5
12-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
A
PARAMETER
SYMBOL
CONDITIONS
Normal operating mode,
MIN
TYP
MAX
UNITS
9.9
mA
f
C
= 32.5MHz at -0.5dBFS, OV
≈ 5pF
= 2.0V,
IN
DD
Digital Output Supply Current
I
OVDD
L
Power-down mode clock idle, PD = OV
0.9
µA
DD
TIMING CHARACTERISTICS (Figure 6)
Clock Pulse Width High
Clock Pulse Width Low
Data-Valid Delay
t
6.25
6.25
6.4
ns
ns
ns
CH
t
CL
t
C = 5pF (Note 5)
L
DAV
Data Setup Time Before Rising
Edge of DAV
t
C = 5pF (Note 4, Note 5)
7.7
4.2
ns
SETUP
L
Data Hold Time After Rising Edge
of DAV
t
C = 5pF (Note 4, Note 5)
L
ns
HOLD
Wake-Up Time from Power-Down
t
V
= 2.048V
10
ms
WAKE
REFIN
Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: See definitions in the Parameter Definitions section.
Note 3: During power-down, D11–D0, DOR, and DAV are high impedance.
Note 4: Guaranteed by design and characterization.
Note 5: Digital outputs settle to V or V .
IH
IL
6
_______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
A
CLK
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
f
= 80.00353MHz
= 2.99817879MHz
f
f
A
= 80.00353MHz
CLK
f
f
A
= 80.00353MHz
= 69.99331395MHz
= -0.510dBFS
CLK
IN
CLK
IN
IN
= 32.49166395MHz
= -0.495dBFS
IN
IN
AIN = -0.527dBFS
SNR = 68.100dB
SINAD = 68.061dB
THD = -88.539dBc
SFDR = 90.612dBc
SNR = 68.236dB
SNR = 68.011dB
SINAD = 68.173dB
THD = -86.624dBc
SFDR = 89.446dBc
SINAD = 67.819dB
THD = -81.470dBc
SFDR = 85.617dBc
HD2
HD3
HD4
HD2
HD2
HD3
HD3
0
4
8
12 16 20 24 28 32 36 40
FREQUENCY (MHz)
0
4
8
12 16 20 24 28 32 36 40
FREQUENCY (MHz)
0
4
8
12 16 20 24 28 32 36 40
FREQUENCY (MHz)
SINGLE-TONE FFT PLOT
(16,384-POINT DATA RECORD)
SINGLE-TONE FFT PLOT
(16,384-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
f
= 80MHz
= 43.90137MHz
= -7.010dBFS
= 45.90332MHz
= -7.041dBFS
f
f
= 80MHz
= 68.50098MHz
= -7.043dBFS
= 71.499MHz
= -7.041dBFS
IN2
CLK
IN1
IN1
CLK
IN1
IN1
f
IN1
f
IN1
A
f
A
f
f
IN2
IN2
IN2
A
A
f
IN2
IN2
SFDR = 87.239dBc
IMD = -85.288dBc
IM3 = -87.415dBc
IMD = -80.988dBc
IM3 = -84.424dBc
TT
f
+ f
IN1 IN2
2 x f + f
IN1 IN2
2 x f + f
IN1 IN2
f
+ 2 x f
IN2
IN1
0
4
8
12 16 20 24 28 32 36 40
FREQUENCY (MHz)
0
4
8
12 16 20 24 28 32 36 40
FREQUENCY (MHz)
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
_______________________________________________________________________________________
7
12-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics (continued)
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
CLK
A
SFDR, -THD
SNR, SINAD
POWER DISSIPATION
vs. SAMPLING RATE
vs. SAMPLING RATE
vs. SAMPLING RATE
100
500
450
400
350
300
250
200
70
f
≈ 32.5MHz
DIFFERENTIAL CLOCK
≈ 32.5MHz
IN
f
≈ 32.5MHz
IN
f
95
90
85
80
75
70
65
60
IN
L
69
68
67
66
65
64
63
62
C ≈ 5pF
SFDR
-THD
ANALOG + DIGITAL POWER
ANALOG POWER
SNR
SINAD
0
20
40
60
(MHz)
80
100
100
125
0
20
40
60
(MHz)
80
100
0
20
40
60
(MHz)
80
100
f
CLK
f
CLK
f
CLK
SNR, SINAD
vs. SAMPLING RATE
SFDR, -THD
vs. SAMPLING RATE
POWER DISSIPATION
vs. SAMPLING RATE
70
69
68
67
66
65
64
63
62
100
95
90
85
80
75
70
65
60
450
400
350
300
250
200
f
≈ 70MHz
DIFFERENTIAL CLOCK
≈ 70MHz
IN
f
≈ 70MHz
IN
f
IN
C ≈ 5pF
L
SNR
SINAD
SFDR
-THD
ANALOG + DIGITAL POWER
ANALOG POWER
0
20
40
60
(MHz)
80
100
0
20
40
60
(MHz)
80
0
20
40
60
80
100
120
f
CLK
f
f
(MHz)
CLK
CLK
SNR, SINAD
vs. ANALOG INPUT FREQUENCY
SFDR, -THD
vs. ANALOG INPUT FREQUENCY
POWER DISSIPATION
vs. ANALOG INPUT FREQUENCY
70
69
68
67
66
65
64
63
62
61
60
95
90
85
80
75
70
500
450
400
350
300
f
≈ 80MHz
f
≈ 80MHz
CLK
DIFFERENTIAL CLOCK
CLK
f
≈ 80MHz
CLK
L
C = 5pF
SNR
SINAD
SFDR
-THD
ANALOG + DIGITAL POWER
ANALOG POWER
0
25
50
75
100
125
0
25
50
75
100
0
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
8
_______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics (continued)
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
A
CLK
SNR, SINAD
vs. ANALOG INPUT AMPLITUDE
SFDR, -THD
vs. ANALOG INPUT AMPLITUDE
POWER DISSIPATION
vs. ANALOG INPUT AMPLITUDE
75
90
85
80
75
70
65
60
55
50
45
40
500
450
400
350
300
f
f
= 80.003702MHz
= 32.125257MHz
f
f
= 80.003702MHz
CLK
DIFFERENTIAL CLOCK
CLK
IN
70
65
60
55
50
45
40
35
30
25
= 32.125257MHz
f
f
= 80.003702MHz
= 32.125257MHz
IN
CLK
IN
C ≈ 5pF
L
SNR
SINAD
SFDR
-THD
ANALOG + DIGITAL POWER
ANALOG POWER
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
SNR, SINAD
vs. ANALOG POWER-INPUT VOLTAGE
SFDR, -THD
vs. ANALOG POWER-INPUT VOLTAGE
POWER DISSIPATION
vs. ANALOG POWER-INPUT VOLTAGE
70
69
68
67
66
65
64
63
62
61
60
100
95
90
85
80
75
70
65
60
550
500
450
400
350
300
250
200
f
f
= 80.03584MHz
= 32.11399MHz
f
f
= 80.03584MHz
CLK
CLK
IN
DIFFERENTIAL CLOCK
= 32.11399MHz
IN
f
f
= 80.03584MHz
= 32.11399MHz
CLK
IN
C ≈ 5pF
L
SNR
SINAD
SFDR
-THD
ANALOG + DIGITAL POWER
ANALOG POWER
2.6
2.8
3.0
3.2
(V)
3.4
3.6
2.6
2.8
3.0
3.2
(V)
3.4
3.6
2.6
2.8
3.0
3.2
(V)
3.4
3.6
V
V
V
DD
DD
DD
SFDR, -THD
vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE
SNR, SINAD
vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE
POWER DISSIPATION
vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE
100
95
90
85
80
75
70
65
60
70
69
68
67
66
65
64
63
62
61
60
550
f
f
= 80.03584MHz
= 32.11399MHz
f
f
= 80.03584MHz
= 32.11399MHz
DIFFERENTIAL CLOCK
CLK
IN
CLK
IN
f
= 80.03584MHz
CLK
500
450
400
350
300
250
225
200
f
IN
= 32.11399MHz
C ≈ 5pF
L
SFDR
-THD
SNR
SINAD
ANALOG + DIGITAL POWER
ANALOG POWER
1.4
1.8
2.2
2.6
3.0
3.4
3.8
1.4
1.8
2.2
2.6
3.0
3.4
3.8
1.4
1.8
2.2
2.6
3.0
3.4
3.8
OV (V)
DD
OV (V)
DD
OV (V)
DD
_______________________________________________________________________________________
9
12-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics (continued)
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
A
CLK
SNR, SINAD
vs. TEMPERATURE
SFDR, -THD
vs. TEMPERATURE
ANALOG POWER DISSIPATION
vs. TEMPERATURE
70
95
93
91
89
87
85
83
81
79
77
75
550
500
450
400
350
300
250
200
f
f
= 80.003072MHz
= 32.481716MHz
f
f
= 80.003072MHz
CLK
DIFFERENTIAL CLOCK
CLK
IN
69
68
67
66
65
64
63
62
61
60
= 32.481716MHz
f
= 80.003072MHz
IN
CLK
f
IN
= 32.481716MHz
SNR
SINAD
SFDR
-THD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
0.5
0.4
3
2
V
= 2.048V
V
= 2.048V
REFIN
REFIN
0.3
0.2
1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-2
-3
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
10 ______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics (continued)
(V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
A
CLK
REFERENCE OUTPUT VOLTAGE
LOAD REGULATION
REFERENCE OUTPUT VOLTAGE
SHORT-CIRCUIT PERFORMANCE
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
2.05
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.039
2.037
2.035
2.033
2.031
2.029
+85°C
+85°C
+25°C
-40°C
-40°C
+25°C
1.95
-2.0
-1.5
I
-1.0
-0.5
0
0.5
-3.0
-2.0
-1.0
0
1.0
-40
-15
10
35
60
85
SINK CURRENT (mA)
I
SINK CURRENT (mA)
TEMPERATURE (°C)
REFOUT
REFOUT
REFP, COM, REFN
SHORT-CIRCUIT PERFORMANCE
REFP, COM, REFN
LOAD REGULATION
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
V
REFP
2.5
2.0
1.5
1.0
0.5
0
V
COM
V
REFP
V
COM
V
REFN
V
REFN
INTERNAL REFERENCE
MODE AND BUFFERED
EXTERNAL REFERENCE MODE
INTERNAL REFERENCE MODE AND
BUFFERED EXTERNAL REFERENCE MODE
-8
-4
0
4
8
-2
-1
0
1
2
SINK CURRENT (mA)
SINK CURRENT (mA)
______________________________________________________________________________________ 11
12-Bit, 80Msps, 3.3V ADC
Pin Description
PIN
NAME
FUNCTION
Positive Reference I/O. The full-scale analog input range is (V
- V
). Bypass REFP to GND with
REFP
REFN
a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN.
Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side of the
printed circuit (PC) board.
1
REFP
Negative Reference I/O. The full-scale analog input range is (V
- V
). Bypass REFN to GND
REFP
REFN
with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and
REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side
of the PC board.
2
3
REFN
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to
GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the
opposite side of the PC board and connected to the MAX1208 through a via.
COM
GND
4, 7, 16,
35
Ground. Connect all ground pins and EP together.
5
6
INP
INN
Positive Analog Input
Negative Analog Input
Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
8
DCE
Connect DCE high (OV
or V ) to enable the internal duty-cycle equalizer.
DD
DD
Negative Clock Input. In differential clock input mode (CLKTYP = OV
or V ), connect the differential
DD
DD
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
9
CLKN
Positive Clock Input. In differential clock input mode (CLKTYP = OV
or V ), connect the differential
DD
DD
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
10
CLKP
Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect
11
CLKTYP
CLKTYP to OV
or V
to define the differential clock input.
DD
DD
Analog Power Input. Connect V
capacitor combination of ≥2.2µF and 0.1µF. Connect all V
to a 3.0V to 3.6V power supply. Bypass V to GND with a parallel
DD
DD
12–15, 36
17, 34
V
DD
pins to the same potential.
DD
Output-Driver Power Input. Connect OV
parallel capacitor combination of ≥2.2µF and 0.1µF.
to a 1.7V to V
power supply. Bypass OV
to GND with a
DD
DD
DD
OV
DD
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog
input is within its full-scale range (Figure 6).
18
DOR
19
20
21
22
23
24
25
26
27
D11
D10
D9
D8
D7
D6
D5
D4
D3
CMOS Digital Output, Bit 11 (MSB)
CMOS Digital Output, Bit 10
CMOS Digital Output, Bit 9
CMOS Digital Output, Bit 8
CMOS Digital Output, Bit 7
CMOS Digital Output, Bit 6
CMOS Digital Output, Bit 5
CMOS Digital Output, Bit 4
CMOS Digital Output, Bit 3
12 ______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
Pin Description (continued)
PIN
28
NAME
D2
FUNCTION
CMOS Digital Output, Bit 2
CMOS Digital Output, Bit 1
CMOS Digital Output, Bit 0 ( LSB)
29
D1
30
D0
Internally Connected. Leave I.C. unconnected.
31, 32
I.C.
Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for
any input clock duty-cycle variations. DAV is typically used to latch the MAX1208 output data into an
external back-end digital circuit.
33
37
38
DAV
PD
Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN
or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a
≥0.1µF capacitor.
REFOUT
Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
39
40
—
REFIN
G/T
GND with a ≥0.1µF capacitor. In these modes, V
- V
= V
/ 2. For unbuffered external
REFIN
REFP
REFN
reference-mode operation, connect REFIN to GND.
Output Format Select Input. Connect G/T to GND for the two’s complement digital output format.
Connect G/T to OV or V for the Gray code digital output format.
DD
DD
Exposed Paddle. The MAX1208 relies on the exposed paddle connection for a low-inductance ground
connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the
top-side PC board ground plane to the bottom-side PC board ground plane.
EP
+
MAX1208
T/H
Σ
−
FLASH
DAC
ADC
INP
INN
STAGE 10
END OF PIPE
STAGE 1
STAGE 2
STAGE 9
T/H
DIGITAL ERROR CORRECTION
D11–D0
OUTPUT
DRIVERS
D11–D0
Figure 1. Pipeline Architecture—Stage Blocks
______________________________________________________________________________________ 13
12-Bit, 80Msps, 3.3V ADC
CLOCK
GENERATOR
AND
DUTY-CYCLE
EQUALIZER
CLKP
CLKN
V
DD
BOND WIRE
INDUCTANCE
1.5nH
MAX1208
V
DD
MAX1208
GND
DCE
CLKTYP
INP
OV
*C
SAMPLE
C
PAR
DD
1.9pF
2pF
D11–D0
DAV
12-BIT
PIPELINE
ADC
INP
INN
OUTPUT
DRIVERS
T/H
DEC
DOR
V
DD
BOND WIRE
INDUCTANCE
1.5nH
G/T
PD
REFOUT
REFIN
REFP
INN
*C
1.9pF
C
2pF
SAMPLE
PAR
REFERENCE
SYSTEM
POWER CONTROL
AND
BIAS CIRCUITS
COM
REFN
SAMPLING
CLOCK
Figure 2. Simplified Functional Diagram
Detailed Description
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS: R
1
The MAX1208 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
From input to output, the total clock-cycle latency is 8.5
clock cycles.
=
SAMPLE
f
x C
SAMPLE
CLK
Figure 3. Simplified Input Track-and-Hold Circuit
capacitors must be charged to one-half LSB accuracy
within one-half of a clock cycle.
The analog input of the MAX1208 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to mid-
Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX1208 functional diagram.
supply (V
/ 2). The MAX1208 provides the optimum
DD
common-mode voltage of V
/ 2 through the COM
DD
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 10, 11, and 12.
Input Track-and-Hold (T/H) Circuit
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies up to 70MHz and supports a
Reference Output (REFOUT)
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX1208. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX1208 or when PD transitions from
high to low. REFOUT has approximately 17kΩ to GND
when the MAX1208 is in power-down.
common-mode input voltage of V
/ 2 0.5V.
DD
The MAX1208 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure 3), allowing
the analog input signal to be stored as charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and open (hold) when
the sampling clock is low (Figure 4). The analog input
signal source must be capable of providing the dynam-
ic current necessary to charge and discharge the sam-
pling capacitors. To avoid signal degradation, these
The internal bandgap reference and its buffer generate
V
to be 2.048V. The reference temperature coeffi-
REFOUT
cient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.
14 ______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
CLKP
CLKN
t
AD
ANALOG
INPUT
t
AJ
SAMPLED
DATA
T/H
TRACK
HOLD
TRACK
HOLD
TRACK
HOLD
TRACK
HOLD
Figure 4. T/H Aperture Timing
REFOUT sources up to 1.0mA and sinks up to 0.1mA
for external circuits with a load regulation of 35mV/mA.
divider, use resistances ≥10kΩ to avoid loading
REFOUT.
Short-circuit protection limits I
to a 2.1mA
REFOUT
Buffered external reference mode is virtually identical to
internal reference mode except that the reference
source is derived from an external reference and not the
MAX1208 REFOUT. In buffered external reference
mode, apply a stable 0.7V to 2.3V source at REFIN. In
this mode, COM, REFP, and REFN are low-impedance
source current when shorted to GND and a 0.24mA
sink current when shorted to V
.
DD
Analog Inputs and Reference
Configurations
The MAX1208 full-scale analog input range is
adjustable from 0.35V to 1.15V with a common-
outputs with V
= V / 2, V
= V / 2 + V
/
COM
= V / 2 - V
DD
REFP
/ 4.
DD
REFIN
4, and V
REFN
DD
REFIN
mode input range of V
/ 2 0.5V. The MAX1208 pro-
DD
To operate the MAX1208 in unbuffered external refer-
ence mode, connect REFIN to GND. Connecting REFIN
to GND deactivates the on-chip reference buffers for
COM, REFP, and REFN. With the respective buffers
deactivated, COM, REFP, and REFN become high-
impedance inputs and must be driven through sepa-
vides three modes of reference operation. The voltage
at REFIN (V
(Table 1).
) sets the reference operation mode
REFIN
To operate the MAX1208 with the internal reference,
connect REFOUT to REFIN either with a direct short or
through a resistive divider. In this mode, COM, REFP,
rate, external reference sources. Drive V
to V
/ 2
COM
DD
and REFN are low-impedance outputs with V
=
COM
5%, and drive REFP and REFN such that V
=
COM
V
/ 2, V
= V
/ 2 + V
V
= V
/ 2
DD
REFP
DD
REFIN / 4, REFN
DD
(V
+ V
/ 2. The full-scale analog input range is
).
REFP
REFN
- V
- V
/ 4. The REFIN input impedance is very large
REFIN
(V
REFP
REFN
(>50MΩ). When driving REFIN through a resistive
Table 1. Reference Modes
V
REFIN
REFERENCE MODE
Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider.
The full-scale analog input range is
V
/ 2:
REFIN
35% V
100% V
to
REFOUT
V
V
V
= V / 2
DD
COM
REFP
REFN
REFOUT
= V / 2 + V
/ 4
/ 4
DD
REFIN
REFIN
= V / 2 - V
DD
Buffered External Reference Mode. Apply an external 0.7V to 2.3V reference voltage to REFIN.
The full-scale analog input range is / 2:
V
REFIN
0.7V to 2.3V
<0.4V
V
V
V
= V / 2
DD
COM
REFP
REFN
= V / 2 + V
/ 4
/ 4
DD
REFIN
= V / 2 - V
DD
REFIN
Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources.
The full-scale analog input range is (V - V ).
REFP
REFN
______________________________________________________________________________________ 15
12-Bit, 80Msps, 3.3V ADC
All three modes of reference operation require the
same bypass capacitor combinations. Bypass COM
with a 2.2µF capacitor to GND. Bypass REFP and
REFN each with a 0.1µF capacitor to GND. Bypass
REFP to REFN with a 1µF capacitor in parallel with a
10µF capacitor. Place the 1µF capacitor as close to
the device as possible on the same side of the PC
board. Bypass REFIN and REFOUT to GND with a
0.1µF capacitor.
V
DD
S
1H
MAX1208
10kΩ
CLKP
For detailed circuit suggestions, see Figures 13 and 14.
10kΩ
Clock Input and Clock Control Lines
(CLKP, CLKN, CLKTYP)
DUTY-CYCLE
EQUALIZER
S
2H
The MAX1208 accepts both differential and single-
ended clock inputs. For single-ended clock-input oper-
ation, connect CLKTYP to GND, CLKN to GND, and
drive CLKP with the external single-ended clock signal.
For differential clock-input operation, connect CLKTYP
S
1L
10kΩ
CLKN
to OV
or V , and drive CLKP and CLKN with the
DD
DD
10kΩ
SWITCHES S AND S ARE OPEN
DURING POWER-DOWN, MAKING
CLKP AND CLKN HIGH IMPEDANCE.
external differential clock signal. To reduce clock jitter,
the external single-ended clock must have sharp falling
edges. Consider the clock input as an analog input and
route it away from any other analog inputs and digital
signal lines.
1_
2_
S
2L
SWITCHES S ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
2_
GND
CLKP and CLKN are high impedance when the
MAX1208 is powered down (Figure 5).
Figure 5. Simplified Clock Input Circuit
Low clock jitter is required for the specified SNR perfor-
mance of the MAX1208. Analog input sampling occurs
on the falling edge of the clock signal, requiring this
edge to have the lowest possible jitter. Jitter limits the
maximum SNR performance of any ADC according to
the following relationship:
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the MAX1208
requires approximately 100 clock cycles to acquire and
lock to new clock frequencies.
Disabling the clock duty-cycle equalizer reduces the
analog supply current by 1.5mA.
1
SNR = 20 × log
2 × π f × t
IN
J
System Timing Requirements
Figure 6 shows the relationship between the clock, ana-
log inputs, DAV indicator, DOR indicator, and the result-
ing output data. The analog input is sampled on the
falling edge of the clock signal and the resulting data
appears at the digital outputs 8.5 clock cycles later.
where f represents the analog input frequency and t
IN
J
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 68.2dB of SNR with an input fre-
quency of 32.5MHz, the system must have less than
1.9ps of clock jitter.
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
cuitry can be latched with the rising edge of the con-
version clock (CLKP-CLKN).
Clock Duty-Cycle Equalizer (DCE)
Enable the MAX1208 clock duty-cycle equalizer by
connecting DCE to OV
or V . Disable the MAX1208
DD
DD
clock duty-cycle equalizer by connecting DCE to GND.
16 ______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
N+4
DIFFERENTIAL ANALOG INPUT (INP–INN)
N+5
N+3
N+6
(V
(V
- V
- V
)
)
REFP
REFN
N-3
N-2
N+2
N+7
N+9
N-1
N
N+1
N+8
REFN
REFP
t
AD
CLKN
CLKP
t
CL
t
CH
t
DAV
DAV
D11–D0
DOR
t
t
HOLD
SETUP
N-3
N-2
N-1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
t
t
8.5 CLOCK-CYCLE DATA LATENCY
SETUP
HOLD
Figure 6. System Timing Diagram
Data-Valid Output (DAV)
side this valid differential range cause DOR to assert
high as shown in Table 2 and Figure 6.
DAV is a single-ended version of the input clock (CLKP).
Output data changes on the falling edge of DAV, and
DAV rises once output data is valid (Figure 6).
DOR is synchronized with DAV and transitions along
with the output data D11–D0. There is an 8.5 clock-
cycle latency in the DOR function as with the output
data (Figure 6).
The state of the duty-cycle equalizer input (DCE)
changes the waveform at DAV. With the duty-cycle
equalizer disabled (DCE = low), the DAV signal is the
inverse of the signal at CLKP delayed by 6.8ns. With the
duty-cycle equalizer enabled (DCE = high), the DAV
signal has a fixed pulse width that is independent of
CLKP. In either case, with DCE high or low, output data
at D11–D0 and DOR are valid from 7.7ns before the ris-
ing edge of DAV to 4.2ns after the rising edge of DAV,
and the rising edge of DAV is synchronized to have a
DOR is high impedance when the MAX1208 is in
power-down (PD = high). DOR enters a high-imped-
ance state within 10ns after the rising edge of PD and
becomes active 10ns after PD’s falling edge.
Digital Output Data (D11–D0), Output Format (G/T)
The MAX1208 provides a 12-bit, parallel, tri-state out-
put bus. D11–D0 and DOR update on the falling edge
of DAV and are valid on the rising edge of DAV.
6.4ns (t
) delay from the falling edge of CLKP.
DAV
DAV is high impedance when the MAX1208 is in
power-down (PD = high). DAV is capable of sinking
and sourcing 600µA and has three times the drive
strength of D11–D0 and DOR. DAV is typically used to
latch the MAX1208 output data into an external back-
end digital circuit.
The MAX1208 output data format is either Gray code or
two’s complement, depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is two’s comple-
ment. See Figure 8 for a binary-to-Gray and Gray-to-
binary code-conversion example.
Keep the capacitive load on DAV as low as possible
(<25pF) to avoid large digital currents feeding back
into the analog portion of the MAX1208 and degrading
its dynamic performance. An external buffer on DAV
isolates it from heavy capacitive loads. Refer to the
MAX1211 evaluation kit schematic for an example of
DAV driving back-end digital circuitry through an exter-
nal buffer.
The following equations, Table 2, Figure 7, and Figure 8
define the relationship between the digital output and
the analog input:
CODE
− 2048
10
V
− V
= (V
− V
) × 2 ×
INP
INN
REFP
REFN
4096
for Gray code (G/T = 1)
Data Out-of-Range Indicator (DOR)
The DOR digital output indicates when the analog input
voltage is out of range. When DOR is high, the analog
input is out of range. When DOR is low, the analog
input is within range. The valid differential input range is
from (V
- V
) to (V
- V ). Signals out-
REFP
REFP
REFN
REFN
______________________________________________________________________________________ 17
12-Bit, 80Msps, 3.3V ADC
Keep the capacitive load on the MAX1208 digital outputs
D11–D0 as low as possible (<15pF) to avoid large digital
currents feeding back into the analog portion of the
MAX1208 and degrading its dynamic performance. The
addition of external digital buffers on the digital outputs
isolates the MAX1208 from heavy capacitive loading. To
improve the dynamic performance of the MAX1208, add
220Ω resistors in series with the digital outputs close to
the MAX1208. Refer to the MAX1211 evaluation kit
schematic for an example of the digital outputs driving a
digital buffer through 220Ω series resistors.
CODE
10
V
− V
= (V
− V
) × 2 ×
INP
INN
REFP
REFN
4096
for two’s complement (G/T = 0)
where CODE is the decimal equivalent of the digital
10
output code as shown in Table 2.
Digital outputs D11–D0 are high impedance when the
MAX1208 is in power-down (PD = high). D11–D0 transi-
tion high 10ns after the rising edge of PD and become
active 10ns after PD’s falling edge.
Power-Down Input (PD)
The MAX1208 has two power modes that are controlled
with the power-down digital input (PD). With PD low, the
Table 2. Output Codes vs. Input Voltage
GRAY CODE OUTPUT CODE (G/T = 1)
TWO’S-COMPLEMENT OUTPUT CODE (G/T = 0)
DECIMAL
EQUIVALENT
OF
DECIMAL
EQUIVALENT
OF
D11➝D0
(CODE )
10
V
REFP
REFN
- V
INN
= 2.162V
= 1.138V
INP
HEXADECIMAL
EQUIVALENT
OF
HEXADECIMAL
EQUIVALENT
OF
V
BINARY
D11➝D0
BINARY
D11➝D0
DOR
DOR
(
)
V
D11➝D0
D11➝D0
D11➝D0
(CODE
)
10
>+1.0235V
(DATA OUT OF
RANGE)
1000 0000 0000
1
0x800
+4095
0111 1111 1111
1
0x7FF
+2047
1000 0000 0000
1000 0000 0001
0
0
0x800
0x801
+4095
+4094
0111 1111 1111
0111 1111 1110
0
0
0x7FF
0x7FE
+2047
+2046
+1.0235V
+1.0230V
1100 0000 0011
1100 0000 0001
1100 0000 0000
0100 0000 0000
0100 0000 0001
0
0
0
0
0
0xC03
0xC01
0xC00
0x400
0x401
+2050
+2049
+2048
+2047
+2046
0000 0000 0010
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
0
0
0
0
0
0x002
0x001
0x000
0xFFF
0xFFE
+2
+1
0
+0.0010V
+0.0005V
+0.0000V
-0.0005V
-0.0010V
-1
-2
0000 0000 0001
0000 0000 0000
0
0
0x001
0x000
+1
0
1000 0000 0001
1000 0000 0000
0
0
0x801
0x800
-2047
-2048
-1.0235V
-1.0240V
<-1.0240V
(DATA OUT OF
RANGE)
0000 0000 0000
1
0x000
0
1000 0000 0000
1
0x800
-2048
18 ______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
2 x V
2 x V
REF
REF
V
REF
= V
- V
V
REF
= V
- V
1 LSB =
1 LSB =
REFP REFN
REFP REFN
V
REF
4096
4096
V
REF
V
REF
V
REF
0x7FF
0x7FE
0x7FD
0x800
0x801
0x803
0x001
0x000
0xFFF
0xC01
0xC00
0x400
0x803
0x802
0x002
0x003
0x801
0x800
0x001
0x000
-2047
-2045
-1
0
+1
+2045
+2047
-2047
-2045
-1
0
+1
+2045
+2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 7. Two’s Complement Transfer Function (G/T = 0)
Figure 8. Gray Code Transfer Function (G/T = 1)
MAX1208 is in normal operating mode. With PD high,
the MAX1208 is in power-down mode.
The wake-up time from power-down mode is dominat-
ed by the time required to charge the capacitors at
REFP, REFN, and COM. In internal reference mode and
buffered external reference mode, the wake-up time is
typically 10ms with the recommended capacitor array
(Figure 13). When operating in unbuffered external ref-
erence mode, the wake-up time is dependent on the
external reference drivers.
The power-down mode allows the MAX1208 to efficient-
ly use power by transitioning to a low-power state when
conversions are not required. Additionally, the
MAX1208 parallel output bus is high impedance in
power-down mode, allowing other devices on the bus
to be accessed.
In power-down mode, all internal circuits are off, the
analog supply current reduces to 1µA, and the digital
supply current reduces to 0.9µA. The following list
shows the state of the analog inputs and digital outputs
in power-down mode:
Applications Information
Using Transformer Coupling
In general, the MAX1208 provides better SFDR and THD
performance with fully differential input signals as
opposed to single-ended input drive. In differential input
mode, even-order harmonics are lower as both inputs are
balanced, and each of the ADC inputs only requires half
the signal swing compared to single-ended input mode.
• INP, INN analog inputs are disconnected from the
internal input amplifier (Figure 3).
• REFOUT has approximately 17kΩ to GND.
• REFP, COM, and REFN go high impedance with
An RF transformer (Figure 10) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX1208
for optimum performance. Connecting the center tap of
respect to V
and GND, but there is an internal 4kΩ
DD
resistor between REFP and COM, as well as an inter-
nal 4kΩ resistor between REFN and COM.
• D11–D0, DOR, and DAV go high impedance.
• CLKP and CLKN go high impedance (Figure 5).
the transformer to COM provides a V
/ 2 DC level
DD
shift to the input. Although a 1:1 transformer is shown, a
______________________________________________________________________________________ 19
12-Bit, 80Msps, 3.3V ADC
BINARY-TO-GRAY CODE CONVERSION
GRAY-TO-BINARY CODE CONVERSION
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE
MOST SIGNIFICANT GRAY-CODE BIT.
D11
D7
D3
D0
0
BIT POSITION
BINARY
D11
D7
D3
D0
0
BIT POSITION
GRAY CODE
0
1
1
1
0
1
0
0
1
1
0
0
1
0
0
1
1
1
0
1
0
1
0
GRAY CODE
0
BINARY
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO
THE FOLLOWING EQUATION:
+
GRAY = BINARY
BINARY
BINARY = BINARY
+
GRAY
X+1 X
X
X
X + 1
X
+
+
WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
WHERE
IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
+
GRAY = BINARY
10
BINARY
BINARY = BINARY
10 11
+
GRAY
10
10
11
GRAY = 1
10
+
0
BINARY = 0
10
+
1
GRAY = 1
10
BINARY = 1
10
D11
D7
D3
1
D0
0
BIT POSITION
BINARY
D11
D7
1
D3
1
D0
0
BIT POSITION
GRAY CODE
0
0
+
1
1
1
1
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
+
GRAY CODE
BINARY
3) REPEAT STEP 2 UNTIL COMPLETE:
3) REPEAT STEP 2 UNTIL COMPLETE:
+
GRAY = BINARY
BINARY
10
9
9
+
BINARY = BINARY
GRAY
9
9
10
+
GRAY = 1
1
9
+
BINARY = 1
0
9
GRAY = 0
9
BINARY = 1
9
D11
D7
D3
1
D0
0
BIT POSITION
BINARY
D11
D7
1
D3
1
D0
0
BIT POSITION
GRAY CODE
0
0
1
1
+
1
1
0
1
0
0
1
0
0
0
1
1
0
1
0
1
1
0
0
1
+
0
GRAY CODE
BINARY
4) THE FINAL GRAY CODE CONVERSION IS:
4) THE FINAL BINARY CONVERSION IS:
D11
0
D7
0
D3
1
D0
0
BIT POSITION
BINARY
D11
0
D7
1
D3
1
D0
0
BIT POSITION
GRAY CODE
1
1
1
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
GRAY CODE
0
0
1
0
BINARY
EXCLUSIVE OR TRUTH TABLE
A
B
Y
=
A
+
B
0
0
1
1
0
1
0
1
0
1
1
0
Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion
20 ______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
24.9Ω
MAX4108
V
IN
INP
0.1µF
0.1µF
6
5
4
12pF
1
2
3
V
INP
IN
T1
MAX1208
5.6pF
100Ω
100Ω
24.9Ω
24.9Ω
MAX1208
N.C.
COM
INN
2.2µF
24.9Ω
COM
INN
2.2µF
MINICIRCUITS
TT1-6 OR T1-1T
12pF
5.6pF
Figure 10. Transformer-Coupled Input Drive for Input
Frequencies Up to Nyquist
Figure 12. Single-Ended, AC-Coupled Input Drive
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion. The configuration of Figure 10 is good
tion resistors connects to COM, providing the correct
input common-mode voltage. Two 0Ω resistors in series
with the analog inputs allow high IF input frequencies.
These 0Ω resistors can be replaced with low-value
resistors to limit the input bandwidth.
for frequencies up to Nyquist (f
/ 2).
CLK
The circuit of Figure 11 converts a single-ended input
signal to fully differential just as Figure 10. However,
Figure 11 utilizes an additional transformer to improve
the common-mode rejection, allowing high-frequency
signals beyond the Nyquist frequency. The two sets of
termination resistors provide an equivalent 75Ω termi-
nation to the signal source. The second set of termina-
Single-Ended AC-Coupled Input Signal
Figure 12 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.
0Ω*
INP
0.1µF
6
5
4
1
2
3
6
5
4
5.6pF
1
2
3
V
IN
75Ω
110Ω
T1
T2
MAX1208
0.5%
0.1%
N.C.
N.C.
N.C.
COM
INN
2.2µF
75Ω
0.5%
110Ω
0.1%
0Ω*
MINICIRCUITS
ADT1-1WT
MINICIRCUITS
ADT1-1WT
5.6pF
*0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE
RESISTORS TO LIMIT THE INPUT BANDWIDTH.
Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
______________________________________________________________________________________ 21
12-Bit, 80Msps, 3.3V ADC
+3.3V
2.2µF
0.1µF
0.1µF
+3.3V
1
2
V
DD
1
MAX6029EUK21
REFP
REFN
COM
38
0.1µF
REFOUT
5
0.1µF
1µF*
10µF
2.048V
MAX1208
2
3
NOTE: ONE FRONT-END REFERENCE
CIRCUIT IS CAPABLE OF SOURCING 15mA
AND SINKING 30mA OF OUTPUT CURRENT.
0.1µF
+3.3V
0.1µF
39
REFIN
16.2kΩ
1µF
2.2µF
GND
MAX4230
1
3
2.048V
5
2
47Ω
4
+3.3V
10µF
6V
330µF
6V
0.1µF
2.2µF
0.1µF
1.47kΩ
V
DD
1
REFP
REFN
COM
38
*PLACE THE 1µF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
REFOUT
0.1µF
1µF*
10µF
MAX1208
2
3
0.1µF
39
REFIN
2.2µF
GND
Figure 13. External Buffered Reference Driving Multiple ADCs
Figure 13 uses the MAX6029EUK21 precision 2.048V
reference as a common reference for multiple convert-
ers. The 2.048V output of the MAX6029 passes through
a one-pole, 10Hz lowpass filter to the MAX4230. The
MAX4230 buffers the 2.048V reference and provides
additional 10Hz lowpass filtering before its output is
applied to the REFIN input of the MAX1208.
Buffered External Reference
Drives Multiple ADCs
The buffered external reference mode allows for more
control over the MAX1208 reference voltage and allows
multiple converters to use a common reference. The
REFIN input impedance is >50MΩ.
22 ______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
+3.3V
1
2
0.1µF
MAX6029EUK30
+3.3V
+3.3V
5
0.1µF
2.2µF
3.000V
0.1µF
0.1µF
MAX4230
1
3
2.157V
5
2
47Ω
24.3kΩ
1%
V
4
DD
1
REFP
38
REFOUT
10µF
6V
330µF
6V
0.1µF
20kΩ
1%
10µF
1µF*
MAX1208
2
3
1.47kΩ
REFN
COM
+3.3V
0.1µF
0.47µF
0.1µF
26.7kΩ
1%
39
REFIN
MAX4230
1
3
1.649V
GND
5
2
2.2µF
47Ω
4
26.7kΩ
1%
+3.3V
10µF
6V
330µF
6V
2.2µF
0.1µF
20kΩ
0.1µF
1%
1.47kΩ
+3.3V
0.1µF
20kΩ
1%
V
DD
1
REFP
38
REFOUT
MAX4230
1
3
1.141V
0.1µF
5
2
20kΩ
1%
10µF
1µF*
47Ω
MAX1208
4
2
3
REFN
COM
10µF
6V
330µF
6V
0.1µF
39
1.47kΩ
REFIN
GND
2.2µF
*PLACE THE 1µF REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
Figure 14. External Unbuffered Reference Driving Multiple ADCs
Figure 14 uses the MAX6029EUK30 precision 3.000V
reference as a common reference for multiple convert-
ers. A five-component resistive divider chain follows the
MAX6029 voltage reference. The 0.47µF capacitor along
this chain creates a 10Hz lowpass filter. Three MAX4230
operational amplifiers buffer taps along this resistor
chain providing 2.157V, 1.649V, and 1.141V to the
MAX1208’s REFP, COM, and REFN reference inputs,
Unbuffered External
Reference Drives Multiple ADCs
The unbuffered external reference mode allows for pre-
cise control over the MAX1208 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal refer-
ence, and allows REFP, REFN, and COM to be driven
directly by a set of external reference sources.
______________________________________________________________________________________ 23
12-Bit, 80Msps, 3.3V ADC
respectively. The feedback around the MAX4230 op
amps provides additional 10Hz lowpass filtering. The
2.157V and 1.141V reference voltages set the full-scale
analog input range to 1.016V.
A common power source for all active components
removes any concern regarding power-supply sequenc-
ing when powering up or down.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. For
the MAX1208, DNL deviations are measured at every
step of the transfer function and the worst-case devia-
tion is reported in the Electrical Characteristics table.
Grounding, Bypassing, and
Board Layout
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally the midscale
MAX1208 transition occurs at 0.5 LSB above midscale.
The offset error is the amount of deviation between the
measured midscale transition point and the ideal mid-
scale transition point.
The MAX1208 requires high-speed board layout design
techniques. Refer to the MAX1211 evaluation kit data
sheet for a board layout reference. Locate all bypass
capacitors as close to the device as possible, prefer-
ably on the same side of the board as the ADC, using
surface-mount devices for minimum inductance.
Bypass V
to GND with a 0.1µF ceramic capacitor in
DD
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope of
the ideal transfer function. The slope of the actual trans-
fer function is measured between two data points: posi-
tive full scale and negative full scale. Ideally, the positive
full-scale MAX1208 transition occurs at 1.5 LSBs below
positive full scale, and the negative full-scale transition
occurs at 0.5 LSB above negative full scale. The gain
error is the difference of the measured transition points
minus the difference of the ideal transition points.
parallel with a 2.2µF ceramic capacitor. Bypass OV
DD
to GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF ceramic capacitor.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All MAX1208
GNDs and the exposed backside paddle must be con-
nected to the same ground plane. The MAX1208 relies on
the exposed backside paddle connection for a low-induc-
tance ground connection. Use multiple vias to connect
the top-side ground to the bottom-side ground. Isolate
the ground plane from any noisy digital system ground
planes such as a DSP or output buffer ground.
Small-Signal Noise Floor (SSNF)
Small-signal noise floor is the integrated noise and dis-
tortion power in the Nyquist band for small-signal
inputs. The DC offset is excluded from this noise calcu-
lation. For this converter, a small signal is defined as a
single tone with an amplitude less than -35dBFS. This
parameter captures the thermal and quantization noise
characteristics of the converter and can be used to
help calculate the overall noise figure of a receive
channel. Go to www.maxim-ic.com for application
notes on thermal + quantization noise floor.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.
Ensure that the differential analog input network layout
is symmetric and that all parasitics are balanced equal-
ly. Refer to the MAX1211 evaluation kit data sheet for
an example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For the
MAX1208, this straight line is between the end points of
the transfer function, once offset and gain errors have
been nullified. INL deviations are measured at every
step of the transfer function and the worst-case devia-
tion is reported in the Electrical Characteristics table.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR
= 6.02 × N + 1.76
[max]
24 ______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first six harmonics (HD2–HD7), and
the DC offset.
2
2
2
2
V
+ V
IM2
+.......+ V
IM13
+ V
IM14
IM1
IMD = 20 × log
2
2
V
+ V
2
1
The fundamental input tone amplitudes (V and V ) are
at -7dBFS. Fourteen intermodulation products (V _)
1
2
IM
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal
to the RMS noise plus distortion. RMS noise plus distor-
tion includes all spectral components to the Nyquist fre-
quency excluding the fundamental and the DC offset.
are used in the MAX1208 IMD calculation. The inter-
modulation products are the amplitudes of the output
spectrum at the following frequencies, where f
and
IN1
f
are the fundamental input tone frequencies:
IN2
• Second-order intermodulation products:
+ f , f - f
f
IN1
IN2 IN2 IN1
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
• Third-order intermodulation products:
2 x f - f , 2 x f - f , 2 x f + f , 2 x f + f
IN1 IN2
IN2 IN1
IN1
IN2
IN2
IN1
IN1
• Fourth-order intermodulation products:
3 x f - f , 3 x f - f , 3 x f + f , 3 x f + f
IN1 IN2
IN2 IN1
IN1
IN2
IN2
• Fifth-order intermodulation products:
SINAD − 1.76
ENOB =
3 x f
3 x f
- 2 x f , 3 x f
- 2 x f , 3 x f
+ 2 x f
,
IN2
IN1
IN2
IN2
IN2
IN1
IN1
6.02
+ 2 x f
IN1
Third-Order Intermodulation (IM3)
Single-Tone Spurious-Free Dynamic Range
(SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS amplitude of the next-largest spurious
component, excluding DC offset.
IM3 is the total power of the third-order intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones f
and f . The
IN2
IN1
individual input tone levels are at -7dBFS. The third-
order intermodulation products are 2 x f - f , 2 x
IN1
IN2
f
- f , 2 x f
+ f , 2 x f
+ f
.
IN1
IN2 IN1
IN1
IN2
IN2
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
Two-Tone Spurious-Free Dynamic Range
(SFDR
)
TT
SFDR represents the ratio, expressed in decibels, of
TT
the RMS amplitude of either input tone to the RMS ampli-
tude of the next-largest spurious component in the spec-
trum, excluding DC offset. This spurious component can
occur anywhere in the spectrum up to Nyquist and is usu-
ally an intermodulation product or a harmonic.
2
2
2
2
2
2
V
+ V
+ V
+ V
+ V
+ V
7
2
3
4
5
6
THD = 20 × log
V
1
Aperture Delay
The MAX1208 samples data on the falling edge of its
sampling clock. In actuality, there is a small delay
between the falling edge of the sampling clock and the
where V is the fundamental amplitude, and V through
7
harmonics (HD2–HD7).
1
2
V
are the amplitudes of the 2nd- through 7th-order
Intermodulation Distortion (IMD)
actual sampling instant. Aperture delay (t ) is the time
AD
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
defined between the falling edge of the sampling clock
and the instant when an actual sample is taken (Figure 4).
Aperture Jitter
Figure 4 depicts the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
______________________________________________________________________________________ 25
12-Bit, 80Msps, 3.3V ADC
Output Noise (n
)
OUT
Pin Configuration
The output noise (n
) parameter is similar to the ther-
OUT
mal + quantization noise parameter and is an indication
of the ADC’s overall noise performance.
TOP VIEW
No fundamental input tone is used to test for n
; INP,
OUT
INN, and COM are connected together and 1024k data
points collected. n is computed by taking the RMS
40 39 38 37 36 35 34 33 32 31
OUT
REFP
1
2
3
4
5
6
7
8
9
30 D0
29 D1
28 D2
27 D3
26 D4
25 D5
24 D6
23 D7
22 D8
21 D9
value of the collected data points.
REFN
COM
GND
INP
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX1208 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by 10%.
MAX1208
INN
GND
DCE
CLKN
EXPOSED PADDLE (GND)
CLKP 10
11 12 13 14 15 16 17 18 19 20
THIN QFN
6mm x 6mm x 0.8mm
26 ______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
1
E
21-0141
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
2
E
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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