MAX1213EVKIT_技术文档

19-3408; Rev 1; 4/05

MAX1213/MAX1214/MAX1215 Evaluation Kits

General Description

Features

ꢀ Up to 170Msps/210Msps/250Msps Sampling Rate

ꢀ Low-Voltage and Low-Power Operation

ꢀ Fully Differential Signal Input Configuration

ꢀ On-Board Differential Output Drivers

The MAX1213/MAX1214/MAX1215 evaluation kits (EV

kits) are a fully assembled and tested circuit board that

contains all the components necessary to evaluate the

performance of the MAX1213/MAX1214/MAX1215 ana-

log-to-digital converters (ADCs). The MAX1213/

MAX1214/MAX1215 accept differential analog inputs;

however, the EV kits generate this signal from a user-

provided single-ended signal source. The digital out-

puts produced by the ADC can be easily captured with

a user-provided high-speed logic analyzer or data-

acquisition system. The EV kits operate from 1.8V

power supplies and includes circuitry that generates a

clock signal from a user-provided AC signal.

ꢀ Fully Assembled and Tested

Ordering Information

PART

TEMP RANGE

0°C to +X0°C

IC PACKAGE

68 QFN-EP*

MAX1213EVKIT

MAX1214EVKIT

MAX1215EVKIT

*EP = Exposed pad.

Component List

DESIGNATION

QTY

DESCRIPTION

DESIGNATION

QTY

21

0

DESCRIPTION

0.01µF ±±0ꢀ% ±5ꢁ ꢂX7

ceramic capacitor (040±)

TDK C1005ꢂX71E103M

C1–C11, C13, C15,

C16, C18, C19, C20,

C36–C39

0.1µF 10ꢀ, 10V X5ꢁ ceramic

capacitors (0402)

TDK C1005X5ꢁ1A104K

C35

1

C12, C14, C17

Not installed, capacitors (0402)

SMA PC board vertical-mount

connectors

J1% CLK

J±

±

0

0.22µF 10ꢀ, 6.3V X5ꢁ

ceramic capacitors (0402)

TDK C1005X5ꢁ0J224K

C21–C24

4

Not installed% vertical SMA

connector

J3

1

4

3

Dual-row 8-pin header

Dual-row 40-pin headers

3-pin headers

Not installed, shorted by PC

trace (0603)

C25, C26

0

3

J4–JX

JU1% JU±% JU3

47µF 10ꢀ, 10V tantalum

capacitors (C case)

AVX TAJC476K010

C27, C28, C40

71% 73% 76% 7X% 711%

713% 714% 715% 743

0

Not installed% resistors (0603)

7±

1

±

49.9Ω ±1ꢀ resistor (0603)

150Ω ±5ꢀ resistors (0603)

10µF 20ꢀ, 6.3V X5ꢁ ceramic

capacitors (0805)

74% 75

C29, C41

2

TDK C2012X5ꢁ0J106M

±4.9Ω ±0.1ꢀ resistors (0603)

I7C PFC-W06037-0±-±479-B

78% 79

±

22µF 10ꢀ, 6.3V X5ꢁ ceramic

capacitor (0805)

TDK C2012X5ꢁ0J226K

710% 71±

716% 71X

±

0Ω resistors (0603)

C30

C31

1

0

2

10Ω ±1ꢀ resistors (0603)

Not installed, capacitor (0805)

718–7±4% 7±8–73±%

14

100Ω ±1ꢀ resistors (0603)

734% 735

1.0µF 10ꢀ, 10V X5ꢁ ceramic

capacitors (0603)

TDK C1608X5ꢁ1A105K

7±5% 7±6% 7±X% 733

736% 73X

4

±

100Ω ±5ꢀ resistors (0603)

510Ω ±5ꢀ resistors (0603)

C32, C42

738% 739% 741%

2.2µF 10ꢀ, 6.3V X5ꢁ ceramic

capacitor (0603)

±8

510Ω ±5ꢀ resistors (040±)

744–768

C33

C34

1

0

TDK C1608X5ꢁ0J225K

100kΩ% 1±-turn% 1/4in

potentiometer

740

74±

1

Not installed, capacitor (0603)

13kΩ ±1ꢀ resistor (0603)

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

MAX1213/MAX1214/MAX1215 Evaluation Kits

Component List (continued)

DESIGNATION

T1% T±

QTY

DESCRIPTION

DESIGNATION

QTY

DESCRIPTION

3.3ꢁ ECL quad differential

receivers (±0-pin SO)

ON Semiconductor

1:1 800MHz 7F transformers

Mini-Circuits ADT1-1WT

±

1

U3–U6

4

TP1% TP±

U1

Test points (black)

MC100LꢁEL1XDW

MAꢂ1±13/14/15EGK (68-pin

QFN% 10mm x 10mm)

Y1

0

1

Not installed% clock oscillator

MAꢂ1±13/14/15 PC board

None

3.3ꢁ ECL differential receiver

(8-pin SO)

ON Semiconductor

MC100LꢁEL16D

U±

1

Component Suppliers

SUPPLIER

PHONE

FAX

WEBSITE

www.avxcorp.com

www.irctt.com

Aꢁꢂ

I7C

843-946-0±38

361-99±-X900

84X-803-6100

843-6±6-31±3

361-99±-33XX

84X-390-4405

TDK

www.component.tdk.com

Note: Indicate that you are using the MAX1213/MAX1214/MAX1215 when contacting these component suppliers.

1) ꢁerify that shunts are installed in the following

locations:

JU± (1-±) → divide-by-two disabled

JU3 (±-3) → two’s-complement output selected

J3 (3-4) → internal reference enabled

±) Connect the clock signal generator to the SMA

connector labeled CLK.

Quick Start

Recommended Equipment

• DC power supplies:

Analog

(ꢁCC)

(ꢁCLK)

1.8ꢁ% 1A

3.3ꢁ% ±00mA

Clock

Buffers

(ꢁLPEL) 3.3ꢁ% 400mA

• Signal generator with low-phase noise and low jitter

3) Connect the analog input signal generator to the

SMA connector labeled J1.

for clock input (e.g.% HP 866±A% HP 8644B)

• Signal generator for analog signal input (e.g.% HP

4) Connect the logic analyzer with high-speed card

probe to either headers J4/J5 (LꢁDS-compatible

signals) or J6/JX (LꢁPECL-compatible signals).

See Table 4 for header connections.

866±A% HP 8644B)

• Logic analyzer or data-acquisition system (e.g.% HP

16500C with high-speed state card HP 1651XA)

• Digital voltmeter

5) Connect a 1.8ꢁ% 1A power supply to ꢁCC.

Connect the ground terminal of this supply to GND

closest to the ꢁCC pad.

Procedure

The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 Eꢁ kits are a fully

assembled and tested surface-mount board. Follow the

steps below for board operation. Do not turn on power

supplies or enable signal generators until all connec-

tions are completed:

6) Connect a 3.3ꢁ% ±00mA power supply to ꢁCLK.

Connect the ground terminal of this supply to GND

closest to the ꢁCLK pad.

X) Connect a 3.3ꢁ% 400mA power supply to ꢁLPEL.

Connect the ground terminal of this supply to GND

closest to the ꢁLPEL pad.

2

_______________________________________________________________________________________

MAX1213/MAX1214/MAX1215 Evaluation Kits

8) Turn on all power supplies.

Clock

The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 require a differential

clock signal. However% if only a single-ended clock sig-

nal source is available% the Eꢁ kit’s on-board level

translator helps to convert a singled-ended clock signal

to the required differential signal. An on-board clock-

shaping circuit generates a differential clock signal

from an AC sine-wave signal applied to the clock input

SMA connector (CLK). The input signal should not

9) Enable the signal generators. Set the clock signal

generator to output a 1X0MHz/±10MHz/±50MHz

signal% with an amplitude of ±.4ꢁ . Set the ana-

P-P

log input signal generator to output the desired fre-

quency with an amplitude ≤ ±ꢁ . The signal gen-

P-P

erators should be synchronized.

10) Enable the logic analyzer.

11) Collect data using the logic analyzer.

exceed an amplitude of ±.6ꢁ . The frequency of the

P-P

sinusoidal input clock signal determines the sampling

Detailed Description

frequency (f

) of the ADC. A differential line receiver

CLK

The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 Eꢁ kits are a fully

assembled and tested circuit board that contains all the

components necessary to evaluate the performance of

the MAꢂ1±13/MAꢂ1±14/MAꢂ1±15% 1±-bit LꢁDS output

ADCS. The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 can be eval-

(U±) processes the input signal to generate the

required clock signal. The frequency of the clock signal

should not exceed 1X0MHz/±10MHz/±50MHz.

Clock Divider

The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 feature an inter-

nal divide-by-two clock divider. Use jumper JU±

to enable/disable this feature. See Table 1 for

shunt positions.

uated with a maximum clock frequency (f

1X0MHz/±10MHz/±50MHz .

) of

CLK

The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 accept differential

inputs. Applications that only have a single-ended sig-

nal source available can use the on-board transformer

(T±) to convert the singled-ended signal to a differential

signal.

Table 1. Clock-Divider Shunt Settings

(JU2)

Output level translators (U3–U6) buffer and convert the

LꢁDS output signals of the MAꢂ1±13/MAꢂ1±14/

MAꢂ1±15 to higher voltage LꢁPECL signals that can be

captured by a wide variety of logic analyzers. The

LꢁDS outputs are accessed at headers J4 and J5. The

LꢁPECL outputs are accessed at headers J6 and JX.

SHUNT

POSITION

MAX1213/14/15

CLKDIV PIN

DESCRIPTION

Connected to

ꢁCC

1-± (default)

±-3

Clock signal divided by 1

Clock signal divided by ±

Connected to

GND

The Eꢁ kits are designed as a four-layer PC board to

optimize the performance of the MAꢂ1±13/MAꢂ1±14/

MAꢂ1±15. Separate analog% clock% and buffer power

planes minimize noise coupling between analog and

digital signals; 50Ω coplanar transmission lines are

used for analog and clock inputs and 100Ω differential

coplanar transmission lines are used for all digital LꢁDS

outputs. All LꢁDS differential outputs are properly termi-

nated with 100Ω termination resistors between true and

complementary digital outputs. The trace lengths of the

100Ω differential LꢁDS lines are matched to within a

few thousandths of an inch to minimize layout-depen-

dent delays.

Input Signal

The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 accept differential

analog input signals. However% the Eꢁ kits only require

a single-ended analog input signal with an amplitude of

less than ±ꢁ

provided by the user. An on-board

P-P

transformer then takes the single-ended analog input

and generates a differential analog signal% which is

applied to the ADC’s differential input pins.

Optional Input Transformer

The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 Eꢁ kits use a sec-

ond transformer to enhance THD and SFD7 perfor-

mance at high input frequencies (>100MHz). This

transformer helps to reduce the increase of even-order

harmonics at high frequencies. To use only the primary

transformer% follow the directions below:

Power Supplies

The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 Eꢁ kits require sep-

arate analog% clock% and buffer power supplies for best

performance. A 1.8ꢁ power supply is used to power the

analog and digital portion of the MAꢂ1±13/

MAꢂ1±14/MAꢂ1±15. The on-board clock circuitry is

powered by a 3.3ꢁ power supply. A separate 3.3ꢁ

power supply is used to power the output buffers

(U3–U6) on the Eꢁ kit.

1) 7emove 710 and 71±.

±) Install a 0.1µF capacitor on C14.

3) Connect the analog signal source to J± instead of J1.

_______________________________________________________________________________________

3

MAX1213/MAX1214/MAX1215 Evaluation Kits

Output Format

Reference Voltage

There are two methods to set the full-scale range of the

MAꢂ1±13/MAꢂ1±14/MAꢂ1±15. The MAꢂ1±13/

MAꢂ1±14/MAꢂ1±15 Eꢁ kits can be configured to use

the ADC’s internal reference% or a stable% low-noise%

external reference can be applied to the 7EFIO pad.

Jumper J3 controls which reference source is used.

See Table ± for shunt settings.

The digital output coding can be chosen to be either in

two’s complement or straight offset binary format by

configuring jumper JU3. See Table 3 for shunt settings.

Table 3. Output-Format Shunt Settings

(JU3)

SHUNT

POSITION

MAX1213/14/15 T/B

DESCRIPTION

Table 2. Reference Shunt Settings (J3)

Digital output in straight

offset binary

SHUNT

1-±

Connected to ꢁCC

Connected to GND

DESCRIPTION

POSITION

Digital output in two's

complement

Internal reference disabled. Apply an external

reference voltage to the 7EFIO pad.

±-3 (default)

1-±

3-4 (default) Internal reference enabled.

Output Bit Locations

Increases FS7 through the trim potentiometer

740.

5-6

The digital outputs of the ADC are connected to two 40-

pin headers (J4 and J5). PC board trace lengths are

matched to minimize output skew and improve perfor-

mance of the device. In addition% four drivers (U3–U6)

buffer and level translate the ADC’s digital outputs to

LꢁPECL-compatible signals. The drivers increase the

differential voltage swing and are able to drive large

capacitive loads% which may be present at the logic

analyzer connection. The outputs of the buffers are

connected to two 40-pin headers (J6 and JX). See

Table 4 for headers J4–JX bit locations.

Decreases FS7 through the trim potentiometer

740.

X-8

Output Signal

The MAꢂ1±13/MAꢂ1±14/MAꢂ1±15 feature a single 1±-

bit% parallel% LꢁDS-compatible% digital output bus. The

digital outputs also feature a clock bit (DCOP/N) for

data synchronization% and a data overrange bit

(O7P/N). See Table 4 for header connections.

4

_______________________________________________________________________________________

MAX1213/MAX1214/MAX1215 Evaluation Kits

Table 4. Output Bit Locations

UNBUFFERED

(LVDS)

BUFFERED

(LVPECL)

BIT

DESCRIPTION

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

J6-10

J6-9

J4-10

J4-9

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

P

N

D11

LD11

MSB

J6-16

J6-15

J6-±±

J6-±1

J6-±8

J6-±X

J6-34

J6-33

J6-40

J6-39

JX-8

J4-16

J4-15

J4-±±

J4-±1

J4-±8

J4-±X

J4-34

J4-33

J4-40

J4-39

J5-8

D10

D9

LD10

LD9

LD8

LDX

LD6

LD5

LD4

LD3

LD±

LD1

LD0

LO7

LDC0

D8

DX

D6

Data bits

D5

JX-X

J5-X

JX-14

JX-13

JX-±0

JX-19

JX-±6

JX-±5

JX-3±

JX-31

JX-38

JX-3X

J6-4

J5-14

J5-13

J5-±0

J5-19

J5-±6

J5-±5

J5-3±

J5-31

J5-38

J5-3X

J4-4

D4

D3

D±

D1

D0

LSB

O7

DCO

Overrange bit

Clock output signal

J6-3

J4-3

JX-±

J5-±

JX-1

J5-1

_______________________________________________________________________________________

5

MAX1213/MAX1214/MAX1215 Evaluation Kits

VCC

J4

C1

C2

C22

C23

C6

C7

C24

C8

J4-4

J4-3

J4-1

J4-2

J4-5

J4-6

ORP

ORN

1

6

11 12 13 14 20 25 62 63 65

27 28 41 44 60

0.1µF

0.22µF

0.1µF

0.22µF

0.1µF

PLACE CAPACITORS NEXT TO PINS 1, 6, 11/12, 13/14, 20, 25, 62/63, 65 OF U1.

59

ORP

R16

10Ω

1%

R18

100Ω

1%

J4-10

J4-9

J4-8

J4-7

J4-12

D11P

D11N

C9

C25

SHORT

R10

0Ω

R11

OPEN

0.1µF

J1

8

58

57

INP

ORN

J4-11

C12

OPEN

1

5

4

2

R6

3

5

1

6

2

4

R8

T1

T2

R1

OPEN

R43

OPEN

D11P

TP1

OPEN

24.9Ω

R19

100Ω

1%

J4-16

J4-15

J4-17

J4-14

J4-13

J4-18

D10P

D10N

0.1%

56

55

C11

0.1µF

D11N

D10P

D11N

D10P

C10

0.1µF

R9

24.9Ω

0.1%

R7

3

6

OPEN

J4-22

J4-21

J4-23

J4-20

J4-19

J4-24

D9P

D9N

R20

100Ω

1%

9

INN

C14

OPEN

C17

R12

0Ω

R13

OPEN

R17

10Ω

1%

54

53

C26

OPEN

J2

D10N

D9P

D10N

D9P

SHORT

CLKP

J4-28

J4-27

J4-29

J4-26

J4-25

J4-30

D8P

D8N

R21

100Ω

1%

R3

OPEN

22

VCLK

CLKP

CLKN

C15

0.1µF

52

51

D9N

D8P

D9N

D8P

C16

0.1µF

J4-34

J4-33

J4-35

J4-32

J4-31

J4-36

D7P

D7N

1

N.C.

8

C13

R22

100Ω

1%

0.1µF

CLK

V

CC

7

2

3

Q

D

50

49

D8N

D7P

D8N

D7P

R4

150Ω

R2

49.9Ω

1%

U2

MC100LVEL16

23

J4-40

J4-39

J4-38

J4-37

D6P

D6N

CLKN

R23

100Ω

1%

U1

C19

0.1µF

6

48

47

Q

R37

R36

510Ω

D7N

D6P

D7N

D6P

V

5

BB

EE

510Ω

MAX1213

MAX1214

MAX1215

R5

150Ω

J5

4

R24

100Ω

1%

J5-2

J5-1

J5-5

J5-3

J5-4

J5-6

DCOP

DCON

C35

0.01µF

46

43

D6N

DCOP

DC0P

VCLK

6

VCLK

J5-8

J5-7

J5-11

J5-9

C18

R28

100Ω

1%

D5P

D5N

0.1µF

J5-10

J5-12

42

40

R25

100Ω

DC0N

D5P

DCON

D5P

R14

OPEN

V

CC

4

5

1

2

J5-14

J5-13

J5-17

J5-15

J5-16

J5-18

D4P

D4N

R29

100Ω

1%

OUT

CLKP

CLKN

N.C.

OE

VCLK

R26

100Ω

39

38

Y1

VF561E

OPEN

D5N

D4P

D5N

D4P

VCLK

R27

100Ω

R15

OPEN

J5-20

J5-19

J5-23

J5-21

J5-22

J5-24

1

2

D3P

D3N

R30

100Ω

1%

JU1

OUT

VCC

GND

3

37

36

3

D4N

D3P

D4N

D3P

R33

100Ω

1

2

JU3

68

17

J5-26

J5-25

J5-29

J5-27

J5-28

J5-30

D2P

D2N

T/B

R31

100Ω

1%

3

VCC

35

34

D3N

D2P

1

2

D3N

D2P

JU2

J5-32

J5-31

J5-35

J5-33

J5-34

J5-36

CLKDIV

D1P

D1N

R32

100Ω

1%

3

VCC

J3

33

32

D2N

D1P

D2N

D1P

J3-1

J3-3

J3-2

J3-4

REFADJ

RJ

J5-38

J5-37

J5-39

J5-40

D0P

D0N

REFI0

REFADJ

R34

100Ω

1%

3

4

REFI0

C20

0.1µF

J3-5

J3-7

J3-6

J3-8

31

30

VCLK

VCC

D1N

D0P

D1N

D0P

R42

13kΩ

1%

VCLK

3

1

R40

100kΩ

REFADJ

R35

100Ω

1%

C27

C29

C32

1.0µF

GND

VCC

47µF

10µF

2

10V

29

RJ

D0N

C21

0.22µF

C3

0.1µF

C4

0.1µF

C5

0.1µF

TP2

REFADJ

VCC

GND

PLACE CAPACITORS NEXT TO PINS 27/28, 41, 44, 60, OF U1.

16

2

5

7

10 15 18 19 21 24 64 66 67

26 45 61

C28

47µF

10V

C30

C33

2.2µF

C31

OPEN

C34

OPEN

22µF

Figure 1. MAX1213/MAX1214/MAX1215 EV Kit Schematic (Sheet 1 of 2)

6

_______________________________________________________________________________________

MAX1213/MAX1214/MAX1215 Evaluation Kits

VLPEL

20

VLPEL

20

VLPEL

20

VLPEL

20

C36

0.1µF

C38

0.1µF

C37

0.1µF

C39

0.1µF

1

V

D0

V

D0

V

D0

V

D0

V

CC

Q0

CC

Q0

CC

Q0

CC

Q0

2

3

4

5

6

7

8

9

19

2

3

4

5

6

7

8

9

19

2

3

4

5

6

7

8

9

19

2

3

4

5

6

7

8

9

19

BORP

BD8P

BDCOP

BD2P

ORP

ORN

D8P

D8N

D7P

D7N

D6P

D6N

DCOP

DCON

D5P

D2P

D2N

D1P

D1N

D0P

D0N

R41

R38

R57

R55

510Ω

D0

D1

D2

D3

D0

D1

D2

D3

D0

D1

D2

D3

D0

D1

D2

D3

R44

510Ω

R39

510Ω

R58

510Ω

R56

510Ω

18

17

18

17

18

17

18

17

D11P

D11N

D10P

D10N

D9P

BORN

BD8N

BD7P

BDCON

BD5P

BD2N

BD1P

Q0

Q1

Q0

Q1

Q0

Q1

Q0

Q1

BD11P

R45

510Ω

R51

510Ω

R59

510Ω

R65

510Ω

D5N

D4P

U3

MC100LVEL17

U4

MC100LVEL17

U5

MC100LVEL17

U6

MC100LVEL17

R46

510Ω

R52

510Ω

R60

510Ω

R66

510Ω

16

15

16

15

16

15

16

15

BD11N

BD10P

BD7N

BD6P

BD5N

BD4P

BD1N

BD0P

Q1

D4N

D3P

Q2

R47

510Ω

R53

510Ω

R61

510Ω

R67

510Ω

R48

510Ω

R54

510Ω

R62

510Ω

R68

510Ω

D9N

D3N

14

13

14

13

14

13

14

13

BD10N

BD9P

BD6N

BD4N

BD3P

BD0N

Q2

Q3

Q2

Q3

Q2

Q3

Q2

Q3

R49

510Ω

R63

510Ω

R50

510Ω

R64

510Ω

12

BD9N

BD3N

Q3

EE

Q3

EE

Q3

EE

Q3

EE

V

BB

V

BB

10

11

10

11

10

11

10

11

J6

J7

VLPEL

J6-4

J6-3

J6-1

J6-2

J7-2

J7-1

J7-5

J7-3

J7-4

J7-6

BORP

BORN

BDC0P

VLPEL

GND

J6-5

J6-6

BDC0N

C40

C41

10µF

C42

1.0µF

47µF

10V

J6-10

J6-9

J6-8

J6-7

J6-12

J7-8

J7-7

J7-9

BD11P

BD11N

BD5P

BD5N

J7-10

J7-12

J6-11

J7-11

J6-16

J6-15

J6-17

J6-14

J6-13

J6-18

J7-14

J7-13

J7-17

J7-15

J7-16

J7-18

BD10P

BD10N

BD4P

BD4N

J6-22

J6-21

J6-23

J6-20

J6-19

J6-24

J7-20

J7-19

J7-23

J7-21

J7-22

J7-24

BD9P

BD9N

BD3P

BD3N

J6-28

J6-27

J6-29

J6-26

J6-25

J6-30

J7-26

J7-25

J7-29

J7-27

J7-28

J7-30

BD8P

BD8N

BD2P

BD2N

J6-34

J6-33

J6-35

J6-32

J6-31

J6-36

J7-32

J7-31

J7-35

J7-33

J7-34

J7-36

BD7P

BD7N

BD1P

BD1N

J6-40

J6-39

J6-38

J6-37

J7-38

J7-37

J7-39

J7-40

BD6P

BD6N

BD0P

BD0N

Figure 1. MAX1213/MAX1214/MAX1215 EV Kit Schematic (Sheet 2 of 2)

_______________________________________________________________________________________

7

MAX1213/MAX1214/MAX1215 Evaluation Kits

Figure 2. MAX1213/MAX1214/MAX1215 EV Kit Component Placement Guide—Component Side

8

_______________________________________________________________________________________

MAX1213/MAX1214/MAX1215 Evaluation Kits

Figure 3. MAX1213/MAX1214/MAX1215 EV Kit PC Board Layout—Component Side

_______________________________________________________________________________________

9

MAX1213/MAX1214/MAX1215 Evaluation Kits

Figure 4. MAX1213/MAX1214/MAX1215 EV Kit PC Board Layout—Ground Plane (Layer 2)

10 ______________________________________________________________________________________

MAX1213/MAX1214/MAX1215 Evaluation Kits

Figure 5. MAX1213/MAX1214/MAX1215 EV Kit PC Board Layout—Power Plane (Layer 3)

______________________________________________________________________________________ 11

MAX1213/MAX1214/MAX1215 Evaluation Kits

Figure 6. MAX1213/MAX1214/MAX1215 EV Kit PC Board Layout—Solder Side

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products% Inc.


型号：	MAX1213EVKIT
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Up to 170Msps/210Msps/250Msps Sampling Rate
文件：	总12页 (文件大小：562K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1213EVKIT [MAXIM]

相关型号：

MAX1213N

MAX1213NEGK+D

MAX1213NEGK+TD

MAX1213NEGK-D

MAX1213NEGK-TD

MAX1213_09

MAX1214

MAX1214EGK

MAX1214EGK+D

MAX1214EGK+TD

MAX1214EGK-D

MAX1214EGK-TD