MAX1214NEGK+D [MAXIM]
1.8V, Low-Power, 12-Bit, 210Msps ADC for Broadband Applications; 1.8V ，低功耗， 12位，210Msps ADC，用于宽带应用
| 型号： | MAX1214NEGK+D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1.8V, Low-Power, 12-Bit, 210Msps ADC for Broadband Applications |
| 文件： | 总21页 (文件大小：740K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3866; Rev 0; 4/06
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
General Description
Features
♦ 210Msps Conversion Rate
The MAX1214N is a monolithic, 12-bit, 210Msps ana-
log-to-digital converter (ADC) optimized for outstanding
dynamic performance at high-IF frequencies beyond
300MHz. The product operates with conversion rates
up to 210Msps while consuming only 799mW.
♦ Excellent Low-Noise Characteristics
SNR = 67dB at f = 100MHz
IN
SNR = 65dB at f = 250MHz
IN
♦ Excellent Dynamic Range
At 210Msps and an input frequency up to 100MHz, the
MAX1214N achieves an 81.3dBc spurious-free dynam-
ic range (SFDR) with excellent 67dB signal-to-noise
ratio (SNR) that remains flat (within 2dB) for input tones
up to 250MHz. This makes it ideal for wideband appli-
cations such as communications receivers, cable-head
end receivers, and power-amplifier predistortion in cel-
lular base-station transceivers.
SFDR = 81.3dBc at f = 100MHz
IN
SFDR = 84.9dBc at f = 250MHz
IN
♦ Single 1.8V Supply
♦ 799mW Power Dissipation at f
= 210Msps
SAMPLE
and f = 100MHz
IN
♦ On-Chip Track-and-Hold Amplifier
♦ Internal 1.24V-Bandgap Reference
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ LVDS Digital Outputs with Data Clock Output
♦ MAX1214NEVKIT Available
The MAX1214N operates from a single 1.8V power sup-
ply. The analog input is designed for AC-coupled differ-
ential or single-ended operation. The ADC also features
a selectable on-chip divide-by-2 clock circuit that
accepts clock frequencies as high as 420MHz. A low-
voltage differential signal (LVDS) sampling clock is rec-
ommended for best performance. The converter
provides LVDS-compatible digital outputs with data for-
mat selectable to be either two’s complement or offset
binary.
Ordering Information
PIN-
PKG
PART
TEMP RANGE
The MAX1214N is available in a 68-pin QFN package
with exposed paddle (EP) and is specified over the
industrial (-40°C to +85°C) temperature range.
PACKAGE CODE
MAX1214NEGK-D -40°C to +85°C 68 QFN-EP* G6800-4
MAX1214NEGK+D -40°C to +85°C 68 QFN-EP* G6800-4
See the Pin-Compatible Versions table for a complete
selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in
this family.
*EP = Exposed paddle.
+Denotes lead-free package.
D = Dry pack.
Applications
Pin-Compatible Versions
Base-Station Power-Amplifier Linearization
SPEED
GRADE
(Msps)
RESOLUTION
(BITS)
ON-CHIP
BUFFER
PART
Cable-Head End Receivers
Wireless and Wired Broadband Communications
Communications Test Equipment
MAX1121
MAX1122
MAX1123
MAX1124
MAX1213
MAX1214
MAX1215
MAX1213N
MAX1214N
MAX1215N
8
250
170
210
250
170
210
250
170
210
250
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
10
10
10
12
12
12
12
12
12
Radar and Satellite Subsystems
No
No
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
ABSOLUTE MAXIMUM RATINGS
AV
to AGND ......................................................-0.3V to +2.1V
to OGND .....................................................-0.3V to +2.1V
Current into Any Pin.......................................................... 50mA
CC
OV
Continuous Power Dissipation (T = +70°C, multilayer board)
A
CC
AV
to OV .......................................................-0.3V to +2.1V
68-Pin QFN-EP (derate 41.7mW/°C above +70°C)....3333mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering,10s) ..................................+300°C
CC
CC
AGND to OGND ....................................................-0.3V to +0.3V
INP, INN to AGND....................................-0.3V to (AV + 0.3V)
All Digital Inputs to AGND........................-0.3V to (AV + 0.3V)
CC
CC
CC
REFIO, REFADJ to AGND........................-0.3V to (AV + 0.3V)
All Digital Outputs to OGND....................-0.3V to (OV + 0.3V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 210MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
CC
CC
SAMPLE
erence, digital output pins differential R = 100Ω. Limits are for T = -40°C to +85°C, unless otherwise noted. Typical values are at
L
A
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
12
-2.1
-1.0
-3
Bits
LSB
LSB
mV
Integral Nonlinearity
INL
f
= 10MHz (Note 2)
0.75
0.3
+2.1
+1.3
+3
IN
Differential Nonlinearity
Transfer Curve Offset
Offset Temperature Drift
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
DNL
No missing codes (Note 2)
(Note 2)
V
OS
15
µV/°C
V
1150
1390
60
mV
P-P
FS
Full-Scale Range Temperature
Drift
ppm/°C
Common-Mode Input Voltage
Differential Input Capacitance
Differential Input Resistance
Full-Power Analog Bandwidth
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
Reference Temperature Drift
REFADJ Input High Voltage
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
Minimum Sampling Rate
Clock Duty Cycle
V
Internally self-biased
0.7
2.5
1.8
700
V
pF
CM
C
IN
IN
R
kΩ
FPBW
MHz
V
REFADJ = AGND
1.18
1.24
90
1.30
V
ppm/°C
V
REFIO
V
Used to disable the internal reference
AV - 0.3
CC
REFADJ
f
f
210
MHz
MHz
%
SAMPLE
SAMPLE
20
Set by clock-management circuit
Figures 5, 11
40 to 60
620
Aperture Delay
t
ps
AD
Aperture Jitter
t
Figure 11
0.15
ps
RMS
AJ
2
_______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 210MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
CC
CC
SAMPLE
erence, digital output pins differential R = 100Ω. Limits are for T = -40°C to +85°C, unless otherwise noted. Typical values are at
L
A
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 3)
Internally self-biased
200
500
1.15 0.25
11 25%
5
mV
P-P
Clock Input Common-Mode
Voltage Range
V
Clock Differential Input
R
C
kΩ
CLK
Clock Differential Input
Capacitance
pF
CLK
DYNAMIC CHARACTERISTICS (at A = -1dBFS)
IN
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 10MHz
65.5
65.2
67.3
67
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 100MHz
= 200MHz
= 250MHz
= 10MHz
Signal-to-Noise Ratio
SNR
SINAD
SFDR
dB
dB
65.3
65.0
67.2
66.6
65.2
64.9
88.5
81.3
82.8
84.9
-88.5
-81.3
-82.8
-84.9
65.3
64.9
= 100MHz
= 200MHz
= 250MHz
= 10MHz
Signal-to-Noise and Distortion
Spurious-Free Dynamic Range
77.0
76.0
= 100MHz
= 200MHz
= 250MHz
= 10MHz
dBc
-77.0
-76.0
= 100MHz
= 200MHz
= 250MHz
Worst Harmonics
(HD2 or HD3)
dBc
dBc
Two-Tone Intermodulation
Distortion
f
f
= 97MHz at -7dBFS,
= 100MHz at -7dBFS
IN1
TTIMD
-79
IN2
LVDS DIGITAL OUTPUTS (D0P/N–D11P/N, ORP/N)
Differential Output Voltage
Output Offset Voltage
|V
|
R = 100Ω
280
440
mV
V
OD
L
OV
R = 100Ω
L
1.110
1.370
OS
_______________________________________________________________________________________
3
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 210MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
CC
CC
SAMPLE
erence, digital output pins differential R = 100Ω. Limits are for T = -40°C to +85°C, unless otherwise noted. Typical values are at
L
A
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input-Voltage Low
V
0.2 x AV
V
V
IL
CC
Digital Input-Voltage High
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay
CLK-to-DCLK Propagation Delay
DCLK-to-Data Propagation Delay
LVDS Output Rise Time
V
0.8 x AV
IH
CC
t
Figure 5
Figure 5
2.05
3.95
1.9
ns
ns
ns
ps
ps
PDL
t
CPDL
t
- t
Figure 5 (Note 3)
1.8
2.0
CPDL PDL
t
20% to 80%, C = 5pF
450
450
RISE
FALL
L
LVDS Output Fall Time
t
20% to 80%, C = 5pF
L
Clock
cycles
Output Data Pipeline Delay
t
Figure 5
11
LATENCY
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
AV
1.70
1.70
1.80
1.80
379
65
1.90
1.90
410
71
V
V
CC
OV
CC
I
f
f
f
= 100MHz
= 100MHz
= 100MHz
mA
AVCC
IN
IN
IN
Digital Supply Current
I
mA
OVCC
Analog Power Dissipation
P
799
1.8
866
mW
mV/V
%FS/V
DISS
Offset
Gain
Power-Supply Rejection Ratio
(Note 4)
PSRR
1.5
Note 1: Values at T ≥ +25°C guaranteed by production test, values at T < +25°C guaranteed by design and characterization.
A
A
Note 2: Static linearity and offset parameters are computed from an end-point curve fit.
Note 3: Parameter guaranteed by design and characterization: T = -40°C to +85°C.
A
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
4
_______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Typical Operating Characteristics
(AV = OV = 1.8V, AGND = OGND = 0, f
= 210MHz, A = -1dBFS; see each TOC for detailed information on test condi-
IN
CC
CC
SAMPLE
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R = 100Ω, T = +25°C.)
L
A
FFT PLOT
(8192-POINT DATA RECORD)
FFT PLOT
(8192-POINT DATA RECORD)
FFT PLOT
(8192-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
f
A
= 210MHz
= 12.484MHz
= -0.97dBFS
SAMPLE
IN
IN
f
f
A
= 210MHz
= 199.771MHz
= -0.961dBFS
f
f
A
= 210MHz
= 100.155MHz
= -0.954dBFS
SAMPLE
IN
IN
SAMPLE
IN
IN
SNR = 67.3dB
SNR = 65.4dB
SNR = 67dB
SINAD = 67.2dB
THD = -83.4dBc
SFDR = 88.5dB
HD2 = -90.4dBc
HD3 = -96.7dBc
SINAD = 65.1dB
THD = -78.5dBc
SFDR = 82.8dBc
HD2 = -82.8dBc
HD3 = -84.6dBc
SINAD = 66.6dB
THD = -76.8dBc
SFDR = 81.2dBc
HD2 = -81.2dBc
HD3 = -81.8dBc
2
3
3
9
2
4
5
7
5
8
2
6
5
3
4
4
10
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
TWO-TONE IMD PLOT
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(8192-POINT DATA RECORD)
(8192-POINT DATA RECORD)
(f
= 210MHz, A = -1dBFS)
SAMPLE
IN
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
70
65
60
55
50
45
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
f
A
= 210MHz
= 249.913MHz
= -0.994dBFS
f
f
f
= 210MHz
= 96.8737793MHz
= 100.1550293MHz
SAMPLE
IN
IN
f
IN1
SAMPLE
IN1
IN2
SNR
f
IN2
SNR = 65dB
IMD = -79dBc
SINAD = 64.9dB
THD = -79.3dBc
SFDR = 85dBc
HD2 = -85dBc
HD3 = -86dBc
SINAD
f
+ f
IN2 IN1
2f + f
IN2 IN1
f
- f
IN2 IN1
2f + f
IN1 IN2
2f - f
IN2 IN1
3
2
4
5
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
0
50
100
150
200
250
300
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
f
(MHz)
IN
HD2/HD3 vs. ANALOG INPUT FREQUENCY
SFDR/(-THD) vs. ANALOG INPUT FREQUENCY
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(f
= 210MHz, A = -1dBFS)
(f
= 210MHz, A = -1dBFS)
SAMPLE
IN
(f
= 210MHz, f = 65.087MHz)
SAMPLE
IN
SAMPLE
IN
-50
-55
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
45
SNR
-60
SFDR
-65
-70
HD2
SINAD
-75
-80
-THD
-85
-90
-95
HD3
-100
-105
-110
0
50
100
150
200
250
300
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
0
50
100
150
200
250
300
f (MHz)
IN
f
IN
(MHz)
_______________________________________________________________________________________
5
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Typical Operating Characteristics (continued)
(AV = OV = 1.8V, AGND = OGND = 0, f
= 210MHz, A = -1dBFS; see each TOC for detailed information on test condi-
IN
CC
CC
SAMPLE
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R = 100Ω, T = +25°C.)
L
A
SFDR/(-THD) vs. ANALOG INPUT AMPLITUDE
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
SNR/SINAD vs. SAMPLE FREQUENCY
(f = 65.087MHz, A = -1dBFS)
(f
= 210MHz, f = 65.087MHz)
(f
= 210MHz, f = 65.087MHz)
SAMPLE
IN
SAMPLE
IN
IN
IN
-30
-40
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
75
70
65
60
55
50
45
40
SNR
HD2
-50
SFDR
-60
SINAD
-70
HD2
-80
-THD
-90
-100
-110
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
0
20 40 60 80 100 120 140 160 180 200 220
(MHz)
f
SAMPLE
TOTAL POWER DISSIPATION vs. SAMPLE
FREQUENCY (f = 65.087MHz, A = -1dBFS)
SFDR/(-THD) vs. SAMPLE FREQUENCY
(f = 65.087MHz, A = -1dBFS)
HD2/HD3 vs. SAMPLE FREQUENCY
(f = 65.087MHz, A = -1dBFS)
IN
IN
IN
IN
IN
IN
0.875
0.850
0.825
0.800
0.775
0.750
0.725
0.700
-60
-65
100
95
90
85
80
75
70
65
60
55
50
SFDR
-70
-75
HD3
-80
-85
-90
-THD
-95
-100
-105
-110
-115
-120
HD2
20 39 58 77 96 115 134 153 172 191 210
(MHz)
0
20 40 60 80 100 120 140 160 180 200 220
(MHz)
0
20 40 60 80 100 120 140 160 180 200 220
(MHz)
f
f
f
SAMPLE
SAMPLE
SAMPLE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
GAIN BANDWIDTH PLOT
= 210MHz, A = -1dBFS)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
(f
SAMPLE
IN
0.7
0.4
1
0
0.8
0.5
-1
-2
-3
-4
-5
-6
-7
0.1
0.2
-0.2
-0.5
-0.8
-0.1
-0.4
-0.7
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
1
10
100
1000
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
ANALOG INPUT FREQUENCY (MHz)
6
______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Typical Operating Characteristics (continued)
(AV = OV = 1.8V, AGND = OGND = 0, f
= 210MHz, A = -1dBFS; see each TOC for detailed information on test condi-
IN
CC
CC
SAMPLE
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R = 100Ω, T = +25°C.)
L
A
HD2/HD3 vs. TEMPERATURE
SFDR/(-THD) vs. TEMPERATURE
SNR/SINAD vs. TEMPERATURE
(f
= 210MHz, f = 100MHz, A = -1dBFS)
(f
= 210MHz, f = 100MHz, A = -1dBFS)
(f
= 210MHz, f = 100MHz, A = -1dBFS)
SAMPLE
100
IN
IN
SAMPLE
IN
IN
SAMPLE
IN
IN
90
70.5
69.5
68.5
67.5
66.5
65.5
64.5
63.5
62.5
61.5
60.5
95
90
85
80
75
70
65
60
55
85
80
75
70
65
HD2
SFDR
SNR
HD3
SINAD
-THD
50
60
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SNR/SINAD vs. SUPPLY VOLTAGE
(f = 65.087MHz, A = -1dBFS)
SFDR/(-THD) vs. SUPPLY VOLTAGE
(f = 65.087MHz, A = -1dBFS)
IN
IN
IN
IN
70
69
68
67
66
65
64
63
62
61
60
100
97
94
91
88
85
82
79
76
73
70
SNR
SFDR
SINAD
-THD
1.70
1.75
1.80
1.85
1.90
1.70
1.75
1.80
1.85
1.90
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(f = 65.087MHz, A = -1dBFS)
HD2/HD3 vs. SUPPLY VOLTAGE
(f = 65.087MHz, A = -1dBFS)
IN
IN
IN
IN
1.248
1.247
1.246
1.245
1.244
1.243
1.242
1.241
1.240
-70
-75
-80
HD3
HD2
-85
-90
-95
-100
-105
-110
-115
-120
1.70
1.75
1.80
1.85
1.90
1.70
1.75
1.80
1.85
1.90
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Pin Description
PIN
NAME
FUNCTION
Analog Supply Voltage. Bypass AV
capacitors for best decoupling results. Connect all AV
Bypassing, and Board Layout Considerations section.
to AGND with a parallel combination of 0.1µF and 0.22µF
CC
1, 6, 11–14, 20,
25, 62, 63, 65
AV
inputs together. See the Grounding,
CC
CC
2, 5, 7, 10, 15, 16,
18, 19, 21, 24,
64, 66, 67
AGND
REFIO
Analog Converter Ground. Connect all AGND inputs together.
Reference Input/Output. Pull REFADJ high to allow REFIO to accept an external reference. Pull
REFADJ low to activate the internal 1.24V-bandgap reference. Connect a 0.1µF capacitor from
REFIO to AGND for both internal and external reference.
3
Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases
FSR). Connect REFADJ to AV to override the internal reference with an external source
CC
4
REFADJ
connected to REFIO. Connect REFADJ to AGND to allow the internal reference to determine the
FSR of the data converter. See the FSR Adjustment Using the Internal Bandgap Reference
section.
8
9
INP
INN
Positive Analog Input Terminal. Internally self-biased to 0.7V.
Negative Analog Input Terminal. Internally self-biased to 0.7V.
Clock Divider Input. CLKDIV controls the sampling frequency relative to the input clock
frequency. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: Sampling frequency is at one-half the input clock frequency.
CLKDIV = 1: Sampling frequency is equal to the input clock frequency.
17
CLKDIV
22
23
CLKP
CLKN
True Clock Input. Apply an LVDS-compatible input level to CLKP. Internally self-biased to 1.15V.
Complementary Clock Input. Apply an LVDS-compatible input level to CLKN. Internally self-
biased to 1.15V.
Digital Converter Ground. Ground connection for digital circuitry and output drivers. Connect all
OGND inputs together.
26, 45, 61
OGND
Digital Supply Voltage. Bypass OV
with a 0.1µF capacitor to OGND. Connect all OV
inputs
CC
CC
27, 28, 41, 44, 60
OV
CC
together. See the Grounding, Bypassing, and Board Layout Considerations section.
Complementary Output Bit 0 (LSB)
True Output Bit 0 (LSB)
29
30
31
32
33
34
35
36
D0N
D0P
D1N
D1P
D2N
D2P
D3N
D3P
Complementary Output Bit 1
True Output Bit 1
Complementary Output Bit 2
True Output Bit 2
Complementary Output Bit 3
True Output Bit 3
8
_______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Pin Description (continued)
PIN
37
NAME
D4N
D4P
FUNCTION
Complementary Output Bit 4
True Output Bit 4
38
39
D5N
D5P
Complementary Output Bit 5
True Output Bit 5
40
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock.
42
43
DCLKN
DCLKP
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock.
46
47
48
49
50
51
52
53
54
55
56
57
D6N
D6P
Complementary Output Bit 6
True Output Bit 6
D7N
D7P
Complementary Output Bit 7
True Output Bit 7
D8N
D8P
Complementary Output Bit 8
True Output Bit 8
D9N
D9P
Complementary Output Bit 9
True Output Bit 9
D10N
D10P
D11N
D11P
Complementary Output Bit 10
True Output Bit 10
Complementary Output Bit 11 (MSB)
True Output Bit 11 (MSB)
Complementary Out-of-Range Control Bit Output. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
58
59
ORN
ORP
True Out-of-Range Control Bit Output. If an out-of-range condition is detected, bit ORP flags
this condition by transitioning high.
Output Format Select. This LVCMOS-compatible input controls the digital output format of the
MAX1214N. T/B has an internal pulldown resistor.
T/B = 0: Two’s-complement output format.
68
—
T/B
T/B = 1: Binary output format.
Exposed Paddle. The exposed paddle is located on the backside of the chip and must be
connected to AGND.
EP
_______________________________________________________________________________________
9
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
OV
CC
AV
CC
INP
12-BIT PIPELINE
T/H
MAX1214N
ADC
INN
900Ω
900Ω
DCLKP
DCLKN
COMMON-
MODE BUFFER
D0P/N
D1P/N
D2P/N
CLOCK
MANAGEMENT
REFIO
REFERENCE
DIV1/DIV2
REFADJ
LVDS
DATA
PORT
D11P/N
CLKP
CLKN
ORP/ORN
CLKDIV
T/B
OGND
AGND
Figure 1. Block Diagram
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. The result is a 12-bit parallel
digital output word in user-selectable two’s-complement
or offset binary output formats with LVDS-compatible
output levels. See Figure 1 for a more detailed view of
the MAX1214N architecture.
Detailed Description—
Theory of Operation
The MAX1214N uses a fully differential pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy, and linearity while minimizing power
consumption.
Both positive (INP) and negative/complementary ana-
log input terminals (INN) are centered around a 0.7V
common-mode voltage, and accept a differential ana-
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1214N. Differential inputs usually feature good
rejection of even-order harmonics, which allows for
enhanced AC performance as the signals are progress-
ing through the analog stages. The MAX1214N analog
inputs are self-biased at a 0.7V common-mode voltage
log input voltage swing of V / 4 each, resulting in a
FS
typical 1.39V
differential full-scale signal swing.
P-P
Inputs INP and INN are sampled when the differential
sampling clock signal transitions high. When using
the clock-divide mode, the analog inputs are sampled
at every other high transition of the differential sam-
pling clock.
and allow a 1.39V
differential input voltage swing
P-P
(Figure 2). Both inputs are self-biased through 900Ω
resistors, resulting in a typical differential input resis-
tance of 1.8kΩ. Drive the analog inputs of the
MAX1214N in AC-coupled configuration to achieve the
best dynamic performance. See the Transformer-
Coupled, Differential Analog Input Drive section.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
10 ______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
AV
CC
T/H
C
MAX1214N
INP
INN
C
C
P
P
S
900Ω
900Ω
12-BIT PIPELINE
ADC
C
S
FROM CLOCK-
MANAGEMENT BLOCK
TO COMMON MODE
C
C
IS THE SAMPLING CAPACITANCE.
IS THE PARASITIC CAPACITANCE ~ 1pF.
S
P
V
+ V / 4
FS
CM
INP
V
CM
INN
V
- V / 4
FS
CM
GND
+V / 2
FS
INP - INN
GND
-V / 2
FS
Figure 2. Simplified Analog Input Architecture and Allowable Input Voltage Range
______________________________________________________________________________________ 11
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
The MAX1214N also features an internal clock-manage-
On-Chip Reference Circuit
The MAX1214N features an internal 1.24V-bandgap refer-
ence circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the FSR
of the MAX1214N. Bypass REFIO with a 0.1µF capacitor
to AGND. To compensate for gain errors or increase/de-
crease the ADC’s FSR, the voltage of this bandgap refer-
ence can be indirectly adjusted by adding an external
resistor (e.g., 100kΩ trim potentiometer) between
REFADJ and AGND or REFADJ and REFIO. See the
Applications Information section for a detailed description
of this process.
ment circuit (duty-cycle equalizer) that ensures the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty-cycle clock signal
that desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum 20MHz
clock frequency to allow the device to meet data sheet
specifications.
Data Clock Outputs (DCLKP, DCLKN)
The MAX1214N features a differential clock output,
which can be used to latch the digital output data with
an external latch or receiver. Additionally, the clock out-
put can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
3.95ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 5 for timing details.
To disable the internal reference, connect REFADJ to
AV . Apply an external, stable reference to set the
CC
converter’s full scale. To enable the internal reference,
connect REFADJ to AGND.
Clock Inputs (CLKP, CLKN)
Drive the clock inputs of the MAX1214N with an LVDS- or
LVPECL-compatible clock to achieve the best dynamic
performance. The clock signal source must be of high
quality and low phase noise to avoid any degradation in
the noise performance of the ADC. The clock inputs
(CLKP, CLKN) are internally biased to 1.15V and accept
Divide-by-2 Clock Control (CLKDIV)
The MAX1214N offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at one-
half the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that require this divide-by-2 mode. Connecting CLKDIV
a typical 0.5V
differential signal swing (Figure 4). See
P-P
the Differential, AC-Coupled LVPECL-Compatible Clock
Input section for more circuit details on how to drive
CLKP and CLKN appropriately. Although not recom-
mended, the clock inputs also accept a single-ended
input signal.
to OV
disables the divide-by-2 mode.
CC
REFERENCE-
SCALING AMPLIFIER
REFT
ADC FULL SCALE = REFT - REFB
G
REFB
REFERENCE
BUFFER
REFIO
1V
0.1µF
REFADJ*
CONTROL LINE TO
DISABLE REFERENCE BUFFER
100Ω*
*REFADJ MAY
BE SHORTED TO
AGND DIRECTLY.
MAX1214N
AV
CC
AV / 2
CC
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
Figure 3. Simplified Reference Architecture
12 ______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Digital Outputs (D0P/N–D11P/N, DCLKP/N,
ORP/N) and Control Input T/B
AV
DD
Digital outputs D0P/N–D11P/N, DCLKP/N, and ORP/N
are LVDS compatible, and data on D0P/N–D11P/N is
presented in either binary or two’s-complement format
(Table 1). The T/B control line is an LVCMOS-compati-
ble input, which allows the user to select the desired
2.89kΩ
CLKP
output format. Pulling T/B low outputs data in two’s
complement and pulling it high presents data in offset
binary format on the 12-bit parallel bus. T/B has an
internal pulldown resistor and may be left unconnected
in applications using only two’s-complement output for-
mat. All LVDS outputs provide a typical 0.325V voltage
swing around a 1.2V common-mode voltage, and must
be terminated at the far end of each transmission line pair
(true and complementary) with 100Ω. Apply a 1.7V to
5.35kΩ
5.35kΩ
CLKN
5.35kΩ
1.9V voltage supply at OV to power the LVDS outputs.
CC
AGND
The MAX1214N offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out-of-range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Figure 4. Simplified Clock Input Architecture
Note: Although a differential LVDS output architecture
reduces single-ended transients to the supply and
ground planes, capacitive loading on the digital out-
puts should still be kept as low as possible. Using
LVDS buffers on the digital outputs of the ADC when
driving larger loads may improve overall performance
and reduce system-timing constraints.
System Timing Requirements
Figure 5 shows the relationship between the clock input
and output, analog input, sampling event, and data out-
put. The MAX1214N samples on the rising (falling)
edge of CLKP (CLKN). Output data is valid on the next
rising (falling) edge of the DCLKP (DCLKN) clock, but
has an internal latency of 11 clock cycles.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INP
INN
t
AD
CLKN
N
N + 1
N + 10
N - 1
N + 11
N + 12
CLKP
t
t
CL
CH
t
CPDL
DCLKN
N + 1
N - 11
N - 10
N
DCLKP
t
LATENCY
t
PDL
D0P/D0N–
D11P/D11N
ORP/N
N - 11
N - 10
N - 9
N - 1
N
N + 1
t
- t ~ 0.4 x t
CPDL PDL
WITH t
= 1 / f
SAMPLE SAMPLE
SAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 5. System and Output Timing Diagram
______________________________________________________________________________________ 13
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Table 1. MAX1214N Digital Output Coding
INP ANALOG
INPUT VOLTAGE
LEVEL
INN ANALOG
INPUT VOLTAGE
LEVEL
OUT-OF-RANGE
ORP (ORN)
BINARY DIGITAL OUTPUT
CODE (D11P/N–D0P/N)
TWO’S-COMPLEMENT DIGITAL
OUTPUT CODE (D11P/N–D0P/N)
1111 1111 1111
(exceeds +FS, OR set)
0111 1111 1111
(exceeds +FS, OR set)
> V
+ V / 4
< V
- V / 4
1 (0)
0 (1)
0 (1)
0 (1)
1 (0)
CM
FS
CM
FS
V
+ V / 4
V
- V / 4
1111 1111 1111 (+FS)
0111 1111 1111 (+FS)
CM
FS
CM
CM
FS
1000 0000 0000 or
0111 1111 1111 (FS/2)
0000 0000 0000 or
1111 1111 1111 (FS/2)
V
V
CM
V
- V / 4
V
+ V / 4
0000 0000 0000 (-FS)
1000 0000 0000 (-FS)
CM
FS
CM
FS
0000 0000 0000
(exceeds -FS, OR set)
1000 0000 0000
(exceeds -FS, OR set)
< V
+ V / 4
> V
- V / 4
CM FS
CM
FS
CONFIGURATION TO INCREASE THE FSR OF THE MAX1214N
CONFIGURATION TO DECREASE THE FSR OF THE MAX1214N
REFERENCE-
SCALING
AMPLIFIER
REFERENCE-
SCALING
AMPLIFIER
ADC FULL SCALE = REFT - REFB
ADC FULL SCALE = REFT - REFB
REFT
REFB
REFT
REFB
G
G
REFERENCE
BUFFER
REFERENCE
BUFFER
1V
1V
REFIO
REFIO
0.1µF
0.1µF
13kΩ TO
1MΩ
REFADJ
REFADJ
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
13kΩ TO
1MΩ
MAX1214N
MAX1214N
AV
CC
AV / 2
CC
AV
CC
AV / 2
CC
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
Figure 6a. Circuit Suggestions to Adjust the ADC’s Full-Scale Range
tor value between REFADJ and REFIO increases the
FSR of the data converter. Figure 6a shows the two
possible configurations and their impact on the overall
full-scale range adjustment of the MAX1214N. Do not
use resistor values of less than 13kΩ to avoid instability
of the internal gain regulation loop for the bandgap ref-
erence. See Figure 6b for the resulting FSR for a series
of resistor values.
Applications Information
FSR Adjustments Using the Internal
Bandgap Reference
The MAX1214N supports a 10% ( 5%) full-scale
adjustment range. To decrease the full-scale signal
range, add an external resistor value ranging from
13kΩ to 1MΩ between REFADJ and AGND. Adding a
variable resistor, potentiometer, or predetermined resis-
14 ______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Differential, AC-Coupled,
LVPECL-Compatible Clock Input
The MAX1214N dynamic performance depends on the
use of a very clean clock source. The phase noise floor
FS VOLTAGE
vs. ADJUST RESISTOR
of the clock source has a negative impact on the SNR
performance. Spurious signals on the clock signal
source also affect the ADC’s dynamic range. The pre-
ferred method of clocking the MAX1214N is differential-
ly with LVDS- or LVPECL-compatible input levels. The
fast data transition rates of these logic families minimize
the clock-input circuitry’s transition uncertainty, thereby
improving the SNR performance. To accomplish this, a
50Ω reverse-terminated clock signal source with low
phase noise is AC-coupled into a fast differential
receiver such as the MC100LVEL16 (Figure 7). The
receiver produces the necessary LVPECL output levels
to drive the clock inputs of the data converter.
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND REFIO INCREASES V
FS
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND AGND DECREASES V
FS
0
100 200 300 400 500 600 700 800 900 1000
Transformer-Coupled,
Differential Analog Input Drive
FS ADJUST RESISTOR (kΩ)
The MAX1214N provides the best SFDR and THD with
fully differential input signals and it is not recommend-
ed to drive the ADC inputs in single-ended configura-
tion. In differential input mode, even-order harmonics
are usually lower since INP and INN are balanced, and
Figure 6b. FS Adjustment Range vs. FS Adjustment Resistor
V
CLK
8
0.1µF
10kΩ
0.1µF
SINGLE-ENDED
INPUT TERMINAL
0.1µF
2
3
7
6
150Ω
0.1µF
50Ω
MC100LVEL16D
150Ω
510Ω
510Ω
AV
CC
OV
CC
4
5
0.01µF
CLKN CLKP
INP
INN
D0P/N–D11P/N, 0RP/N
MAX1214N
12
AGND
OGND
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
______________________________________________________________________________________ 15
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
each of the ADC inputs only requires half the signal
swing compared to a single-ended configuration.
To further enhance THD and SFDR performance at high
input frequencies (> 100MHz), a second transformer
(Figure 8) should be placed in series with the single-
ended-to-differential conversion transformer. This trans-
former reduces the increase of even-order harmonics
at high frequencies.
Wideband RF transformers provide an excellent solu-
tion to convert a single-ended signal to a fully differen-
tial signal, required by the MAX1214N to reach its
optimum dynamic performance. Apply a secondary-
side termination of a 1:1 transformer (e.g., Mini-Circuit’s
ADT1-1WT) into two separate 24.9Ω resistors. Higher
source impedance values can be used at the expense
of degradation in dynamic performance. This configu-
ration optimizes THD and SFDR performance of the
ADC by reducing the effects of transformer parasitics.
However, the source impedance combined with the
shunt capacitance provided by a PC board and the
ADC’s parasitic capacitance limit the ADC’s full-power
input bandwidth.
Single-Ended, AC-Coupled Analog Inputs
Although not recommended, the MAX1214N can be used
in single-ended mode (Figure 9). AC-couple the analog
signals to the positive input INP through a 0.1µF capacitor
terminated with a 49.9Ω resistor to AGND. Terminate the
negative input INN with a 49.9Ω resistor in series with a
0.1µF capacitor to AGND. In single-ended mode, the
input range is limited to approximately half of the FSR of
the device, and dynamic performance usually degrades.
AV
CC
OV
CC
0.1µF
SINGLE-ENDED
INPUT TERMINAL
6
INP
0.1µF
4
ADT1-1WT
ADT1-1WT
1
5
3
3
5
D0P/N–D11P/N,
0RP/N
10Ω
10Ω
24.9Ω
24.9Ω
12
2
2
4
MAX1214N
6
1
12
INN
0.1µF
OGND
AGND
Figure 8. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
AV
CC
OV
CC
SINGLE-ENDED
INPUT TERMINAL
0.1µF
0.1µF
INP
INN
D0P/N–D11P/N, 0RP/N
49.9Ω
1%
MAX1214N
12
49.9Ω
1%
AGND
OGND
Figure 9. Single-Ended, AC-Coupled Analog Input Configuration
16 ______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
match the physical location of analog and digital
Grounding, Bypassing, and
Board Layout Considerations
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. The dynamic currents that may need to travel
long distances before they are recombined at a com-
mon source ground, resulting in large and undesirable
ground loops, are a major concern with this approach.
Ground loops can degrade the input noise by coupling
back to the analog front-end of the converter, resulting
in increased spurious activity, leading to decreased
noise performance.
The MAX1214N requires board-layout design tech-
niques suitable for high-speed data converters. This
ADC provides separate analog and digital power sup-
plies. The analog and digital supply voltage pins
accept 1.7V to 1.9V input voltage ranges. Although
both supply types can be combined and supplied from
one source, it is recommended to use separate sources
to cut down on performance degradation caused by dig-
ital switching currents, which can couple into the analog
supply network. Isolate analog and digital supplies
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
coupling of the digital output signals from the analog
input, segregate the digital output bus carefully from the
analog input circuitry. To further minimize the effects of
digital noise coupling, ground return vias can be posi-
tioned throughout the layout to divert digital switching
currents away from the sensitive analog sections of the
ADC. This approach does not require split ground
planes, but can be accomplished by placing substantial
ground connections between the analog front-end and
the digital outputs.
(AV
and OV ) where they enter the PC board with
CC
separate networks of ferrite beads and capacitors to
their corresponding grounds (AGND, OGND).
CC
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor
and parallel combinations of 10µF and 1µF ceramic
capacitors. Additionally, the ADC requires each supply
pin to be bypassed with separate 0.1µF ceramic
capacitors (Figure 10). Locate these capacitors directly
at the ADC supply pins or as close as possible to the
MAX1214N. Choose surface-mount capacitors, whose
preferred location should be on the same side as the
converter to save space and minimize the inductance.
If close placement on the same side is not possible,
these bypassing capacitors may be routed through
vias to the bottom side of the PC board.
The MAX1214N is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal dissipation, and
optimized AC performance of the ADC. The exposed
paddle (EP) must be soldered down to AGND.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
BYPASSING—ADC LEVEL
BYPASSING—BOARD LEVEL
AV
OV
AV
CC
CC
CC
0.1µF
0.1µF
ANALOG POWER-
SUPPLY SOURCE
10µF
47µF
1µF
AGND
OGND
D0P/N–D11P/N, 0RP/N
OV
CC
MAX1214N
12
DIGITAL/OUTPUT
DRIVER POWER-
SUPPLY SOURCE
10µF
47µF
1µF
NOTE: EACH POWER-SUPPLY PIN (ANALOG
AND DIGITAL) SHOULD BE DECOUPLED WITH
AN INDIVIDUAL 0.1µF CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADC.
AGND
OGND
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1214N
______________________________________________________________________________________ 17
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
at the package bottom surface, facing the PC board
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
side of the package. This allows a solid attachment of
the package to the board with standard infrared (IR)
flow soldering techniques.
Thermal efficiency is one of the factors for selecting a
package with an exposed paddle for the MAX1214N.
The exposed paddle improves thermal and ensures a
solid ground connection between the ADC and the PC
board’s analog ground layer.
SNR
= 6.02 x N + 1.76
[max]
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities also contribute to the SNR calculation and
should be considered when determining the signal-to-
noise ratio in ADC. The SNR for the MAX1214N is speci-
fied in decibels (dB), however, SNR can also be
specified in dBFS. To obtain the SNR in dBFS, simply
subtract the amplitude of the input tone (this number is
given in dBFS) at which the SNR is measured from the
SNR number in dB. For example, an ADC having an
SNR of 67dB resulting from an input tone with amplitude
-1dBFS will have an SNR of 67 - (-1) = 68dBFS.
Considerable care must be taken when routing the digi-
tal output traces for a high-speed, high-resolution data
converter. Keep trace lengths at a minimum and place
minimal capacitive loading (less than 5pF) on any digi-
tal trace to prevent coupling to sensitive analog sec-
tions of the ADC. It is recommended running the LVDS
output traces as differential lines with 100Ω matched
impedance from the ADC to the LVDS load device.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once off-
set and gain errors have been nullified. The static linearity
parameters for the MAX1214N are measured using the
histogram method with a 10MHz input frequency.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components excluding the fundamen-
tal and the DC offset. In the case of the MAX1214N,
SINAD is computed from a curve fit.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1214N’s DNL specification is measured with the
histogram method based on a 10MHz input tone.
CLKP
CLKN
ANALOG
INPUT
t
AD
t
AJ
Dynamic Parameter Definitions
SAMPLED
Aperture Jitter
DATA (T/H)
Figure 11 shows the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
HOLD
TRACK
TRACK
T/H
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Figure 11. Aperture Jitter/Delay Specifications
18 ______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
The fundamental input tone amplitudes (V1 and V2) are
at -7dBFS. The intermodulation products are the ampli-
tudes of the output spectrum at the following frequencies:
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the carrier
frequency (maximum signal component) to the RMS
value of the next-largest noise or harmonic distortion
component. SFDR is usually measured in dBc with
respect to the carrier frequency amplitude or in dBFS
with respect to the ADC’s full-scale range.
• Second-order intermodulation products: f
+ f
,
,
,
,
IN1
IN2
f
- f
IN2 IN1
• Third-order intermodulation products: 2 x f
- f
IN1
IN2
2 x f
- f , 2 x f
IN2 IN1
+ f , 2 x f
+ f
IN2 IN1
IN1
IN2
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
• Fourth-order intermodulation products: 3 x f
- f
IN1 IN2
3 x f
- f , 3 x f
IN2 IN1
+ f , 3 x f
+ f
IN2 IN1
IN1
IN2
• Fifth-order intermodulation products: 3 x f
- 2 x f
IN1
IN2
IN1
3 x f
- 2 x f , 3 x f
+ 2 x f , 3 x f
+ 2 x f
IN2
IN1
IN1
IN2
IN2
2
2
2
2
Full-Power Bandwidth
V
+ V
+......+ V
+ V
IM1
IM2
IM3 IMn
IMD = 20 × log
A large -1dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. The -3dB point is defined as
the full-power input bandwidth frequency of the ADC.
2
2
V
+ V
2
1
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
AV
1
2
3
4
5
6
7
8
9
51 D8P
50 D8N
49 D7P
48 D7N
47 D6P
46 D6N
45 OGND
CC
AGND
REFIO
EP
REFADJ
AGND
AV
CC
AGND
INP
44 OV
CC
INN
43 DCLKP
42 DCLKN
MAX1214N
AGND 10
AV
AV
AV
AV
11
12
13
14
41 OV
CC
CC
CC
CC
CC
40 D5P
39 D5N
38 D4P
37 D4N
36 D3P
35 D3N
AGND 15
AGND 16
CLKDIV 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
EP = EXPOSED PADDLE
______________________________________________________________________________________ 19
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
For the MAX1214N, the package code is G6800-4.
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
20 ______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
Heaney
相关型号：
MAX1214NEGK+TD
ADC, Proprietary Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.9 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
MAXIM
MAX1214NEGK-TD
ADC, Proprietary Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
MAXIM
MAX1215EGK
ADC, Proprietary Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, MO-220, TQFN-68
MAXIM
MAX1215EGK+D
ADC, Proprietary Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
MAXIM
MAX1215EGK+TD
ADC, Proprietary Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
MAXIM
MAX1215EGK-D
ADC, Proprietary Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
MAXIM
MAX1215EGK-TD
ADC, Proprietary Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
MAXIM
©2020 ICPDF网 联系我们和版权申明