MAX1219EVKIT [MAXIM]
On-Board LVDS/LVPECL Differential Level Translators;型号: | MAX1219EVKIT |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | On-Board LVDS/LVPECL Differential Level Translators |
文件: | 总21页 (文件大小:982K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
19-4018; Rev 0; 3/06
MAX1217/MAX1218/MAX1219 Evaluation Kits
General Description
Features
♦ ADC Sampling Rates from 125Msps to 210Msps
♦ Low Voltage and Power Operation
The MAX1217/MAX1218/MAX1219 evaluation kits (EV kits)
are fully assembled and tested circuit boards that contain
all the components necessary to evaluate the perfor-
mance of the MAX1217/MAX1218/MAX1219 dual, 12-bit,
125Msps/170Msps/210Msps analog-to-digital converters
(ADCs). These ADCs accept differential analog inputs,
which the EV kit generates from user-provided single-
ended input sources. The digital outputs produced by the
ADC can be easily sampled using a high-speed logic
analyzer or data-acquisition system. The EV kit operates
from 1.8V/3.3V power supplies and includes circuitry that
generates a differential clock signal from a single-ended
AC source provided by the user.
♦ On-Board Clock-Shaping Circuitry
♦ On-Board LVDS/LVPECL Differential Level
Translators
♦ Fully Assembled and Tested
Ordering Information
PART
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
IC PACKAGE
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
MAX1217EVKIT
MAX1218EVKIT
MAX1219EVKIT
EV Kit Specific Component List
EV KIT PART
NUMBER
DESIGNATION
DESCRIPTION
Maxim MAX1217ECQ
(100-pin TQFP)
Part Selection Table
MAX1217EVKIT
PART
SPEED (Msps)
Maxim MAX1218ECQ
(100-pin TQFP)
MAX1218EVKIT
MAX1219EVKIT
U1
MAX1219ECQ
210
170
125
MAX1218ECQ
MAX1217ECQ
Maxim MAX1219ECQ
(100-pin TQFP)
Common Component List
DESIGNATION QTY
DESCRIPTION
DESIGNATION QTY
DESCRIPTION
220µF 20ꢀ, 6.3V tantalum
capacitors (C-case)
AVX TPSC227M006ꢁ0250
C1, C3, C5, C6,
C12, C13, C18,
C42, C43
0.1µF 20ꢀ, 25V X7ꢁ ceramic
capacitors (0603)
TDK C1608X7ꢁ1E104M
0.1µF 20ꢀ, 6.3V X5ꢁ ceramic
capacitors (0201)
C71–C74
C76–C79
C81–C84
4
0
4
9
Not installed (C-case)
C2, C4,
C115–C123
11
10µF 20ꢀ, 6.3V X5ꢁ ceramic
capacitors (0805)
TDK C0603X5ꢁ0J104M
C7, C19, C20,
C33–C41,
C112, C113,
C114
TDK C2012X5ꢁ0J106M
0.1µF 20ꢀ, 10V X5ꢁ ceramic
capacitors (0402)
TDK C1005X5ꢁ1A104M
1.0µF 20ꢀ, 6.3V X5ꢁ ceramic
17 capacitors (0402)
15
C86–C89,
C91–C103
TDK C1005X5ꢁ0J105M
2.0pF 0.25pF, 50V C0ꢂ ceramic
capacitors (0402)
TDK C1005C0ꢂ1H2ꢁ0C
4.7µF 20ꢀ, 6.3V X5ꢁ ceramic
capacitors (0603)
TDK C1608X5ꢁ0J475M
C14–C17
4
C104–C107
4
0.01µF 5ꢀ, 25V C0ꢂ ceramic
capacitors (0603)
TDK C1608C0ꢂ1E103J
J1, J3, J7, J15
J5, J6, J14
J8, J10, J11, J13
J9, J12
4
3
4
2
2
1
2
SMA PC mount connectors
2-pin headers
C21–C32,
C108–C111
16
Dual-row, 50-pin headers
Dual-row, 6-pin headers
Triple-row, 75-pin headers
Triple-row, 9-pin header
Jumpers, dual-row, 8-pin headers
0.01µF 10ꢀ, 25V X7ꢁ ceramic
27 capacitors (0402)
TDK C1005X7ꢁ1E103K
C44–C70
J16, J18
J17
JU1, JU2
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX1217/MAX1218/MAX1219 Evaluation Kits
Common Component List (continued)
DESIGNATION QTY
DESCRIPTION
DESIGNATION QTY
DESCRIPTION
ꢁ122–ꢁ147, ꢁ153 27 100Ω 1ꢀ resistors (0603)
JU3–JU8
6
Jumpers, 3-pin headers
ꢁ1, ꢁ3,
ꢁ23–ꢁ26, ꢁ121,
ꢁ148, ꢁ151, ꢁ152
ꢁ149, ꢁ156
ꢁ154, ꢁ155
2
0
510Ω 5ꢀ resistors (0603)
10 49.9Ω 1ꢀ resistors (0603)
Not installed (T93YB)
1:1, 800MHz ꢁF transformers
Mini-Circuits ADT1-1WT
ꢁ2, ꢁ4, ꢁ5–ꢁ10,
ꢁ13–ꢁ18,
ꢁ112, ꢁ113, ꢁ150
T1–T4
TP1–TP6
U1
4
6
1
1
0
4
Not installed (0603)
Test points (black)
24.9Ω 0.1ꢀ resistors (0603)
Vishay/Dale TNPW060324ꢁ9BEEA
IꢁC PFC-W0603ꢁ-02-24ꢁ9-B
Note: See the EV Kit Specific
Component List
ꢁ19–ꢁ22
U2
Maxim MAX9388EUP (20-pin TSSOP)
ꢁ27–ꢁ107
81 49.9Ω 1ꢀ resistors (0402)
3.3V, ECL, quad differential
receivers (SO-20)
On Semiconductor
MC100LVEL17DW
10Ω 0.1ꢀ resistors (0603)
Vishay/Dale TNPW060310ꢁ0BEEA
ꢁ108–ꢁ111
4
U3–U9
7
ꢁ114
ꢁ115
1
1
1
2
2
4.02kΩ 1ꢀ resistor (0603)
2kΩ 1ꢀ resistor (0603)
Y1
—
0
8
Not installed (VF561E)
Shunts
ꢁ116
5kΩ potentiometer, 19-turn, 3/8in
13.0kΩ 1ꢀ resistors (0603)
100kΩ potentiometers, 19-turn, 3/8in
MAX1217/MAX1218/MAX1219
PC board
ꢁ117, ꢁ118
ꢁ119, ꢁ120
—
1
Component Suppliers
SUPPLIER
PHONE
FAX
WEBSITE
www.avxcorp.com
www.irctt.com
AVX
843-946-0238
361-992-7900
718-934-4500
847-803-6100
402-564-3131
843-626-3123
IꢁC
361-992-3377
718-332-4661
847-390-4405
402-563-6296
Mini-Circuits
TDK
www.minicircuits.com
www.component.tdk.com
www.vishay.com
Vishay
Note: Indicate that you are using the MAX1217/MAX1218/MAX1219 when contacting these component suppliers.
•
•
Analog bandpass filters (e.g., Allen Avionics, K&L
Quick Start
Recommended Equipment
Microwave) for input signal and clock signal
Digital voltmeter
•
DC power supplies:
Procedure
Analog (AVCC)
Output drive (OVCC)
Clock (VCLK)
1.8V, 1A
The MAX1217/MAX1218/MAX1219 EV kits are fully
assembled and tested surface-mount boards. Follow
the steps below for board operation. Do not turn on
power supplies or enable function generators until
all connections are completed.
1.8V, 250mA
3.3V, 100mA
3.3V, 1A
Buffer (VPECL)
•
•
•
Signal generator with low phase noise and low jitter
for clock input (e.g., HP/Agilent 8644B)
1) Verify that shunts are installed in the following locations:
JU1 (3-4) → Internal reference enabled (channel A)
JU2 (3-4) → Internal reference enabled (channel B)
Two signal generators for analog signal inputs
(e.g., HP/Agilent 8644B)
Logic analyzer or data-acquisition system
(e.g., HP/Agilent 16500C, TLA621)
JU3 (2-3) → Channel A output in two’s-comple-
ment format
2
_______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
JU4 (2-3) → Channel B output in two’s-comple-
18) Set the analog input signal generators to output the
desired test frequency. The amplitude of the gener-
ator should produce a signal that is no larger than
ment format
JU5 (1-2) → Divide-by-two clock disabled
JU6, JU7 (2-3) → Variable duty-cycle input selected
2) Connect a 1.8V, 1A power supply to AVCC.
Connect the ground terminal of this supply to ꢂND.
11dBm (793mV ) as measured at the SMA input
P-P
of the EV kit. Insertion losses due to the series-con-
nected filter (steps 8 and 10) and the interconnect-
ing cables decrease the amount of power seen at
the EV kit input. Account for these losses when set-
ting the signal generator amplitude.
3) Connect a 1.8V, 250mA power supply to OVCC.
Connect the ground terminal of this supply to ꢂND.
19) Enable the logic analyzer.
4) Connect a 3.3V, 100mA power supply to VCLK.
Connect the ground terminal of this supply to ꢂND.
20) Collect data using the logic analyzer.
5) Connect a 3.3V, 1A power supply to VPECL.
Connect the ground terminal of this supply to ꢂND.
Detailed Description
The MAX1217/MAX1218/MAX1219 EV kits are fully
assembled and tested circuit boards that contain all the
components necessary to evaluate the performance of
the MAX1217/MAX1218/MAX1219 dual, 12-bit parallel
output ADCs.
6) Connect the clock signal generator to the input of
the clock bandpass filter.
7) Connect the output of the clock bandpass filter to
the EV kit SMA connector labeled J7. Monitor the
clock signal using a differential oscilloscope probe
at connector J14.
The MAX1217/MAX1218/MAX1219 accept differential
inputs; however, on-board transformers (T1, T3) con-
vert readily available single-ended source outputs to
the required differential signals. Measure the inputs of
the MAX1217/MAX1218/MAX1219 at headers J5 and
J6 using a differential oscilloscope probe.
8) Connect the first analog signal generator to the
input of the desired bandpass filter.
9) Connect the output of the first bandpass filter to the
EV kit SMA connector labeled J1.
Output level translators (U3–U8) buffer and convert the
LVDS output signals of the MAX1217/MAX1218/MAX1219
to higher-voltage LVPECL signals, which can be captured
by a wide variety of logic analyzers. The LVDS outputs
are accessed at headers J8, J9, J10. The LVPECL out-
puts are accessed at headers J11, J12, J13. Additionally,
the LVPECL outputs can be captured with a single-ended
logic-analyzer probe at headers J16, J17, and J18.
10) Connect the second analog signal generator to the
input of the desired bandpass filter.
11) Connect the output of the second bandpass filter to
the EV kit SMA connector labeled J3.
12) Ensure that all signal generators are phase-locked
to a common reference frequency.
13) Connect the logic analyzer to either headers J8 to
J10 (LVDS-compatible signals), J11 to J13
(LVPECL-compatible signals), or J16 to J18 (single-
ended capture). See the Output Bit Locations sec-
tion for header descriptions and connections.
The EV kit is designed as a four-layer PC board to opti-
mize the performance of the MAX1217/MAX1218/
MAX1219. Separate analog, digital, clock, and buffer
power planes minimize noise coupling between analog
and digital signals. 50Ω coplanar transmission lines are
used for analog and clock inputs. 100Ω-differential
coplanar transmission lines are used for all digital LVDS
outputs. All differential outputs are properly terminated
with 100Ω termination resistors between true and com-
plementary digital outputs. The trace lengths of the
100Ω-differential LVDS lines are matched to within a
few thousandths of an inch to minimize layout-depen-
dent data skew.
14) Turn on all the power supplies.
15) With a voltmeter, verify that 1.32V is measured
across test points TP3 and TP4. If the voltage is not
1.32V, adjust potentiometer ꢁ116 until 1.32V is
obtained.
16) Enable the function generators.
17) Set the clock signal generator to output a 210MHz
signal. The amplitude of the generator should be
sufficient to produce a 13.8dBm (1.09V ) signal
P-P
Power Supplies
The MAX1217/MAX1218/MAX1219 EV kits require sep-
arate analog, output-drive, clock, and buffer power
supplies for best performance. Two 1.8V power sup-
plies are used to power the analog (AVCC) and output-
driver (OVCC) circuitry of the MAX1217/MAX1218/
at the SMA input of the EV kit. Insertion losses due
to the series-connected filter (step 7) and the inter-
connecting cables decrease the amount of power
seen at the EV kit input. Account for these losses
when setting the signal generator amplitude.
_______________________________________________________________________________________
3
MAX1217/MAX1218/MAX1219 Evaluation Kits
MAX1219. The clock circuitry (VCLK) is powered by a
3.3V power supply. A separate 3.3V power supply
(VPECL) is used to power the output buffers (U3–U9) of
the EV kit.
crystal oscillator. To use this function, install a three-pin
header at location JU8. Also, install a crystal oscillator with
the desired frequency at location Y1.
Jumper JU8 controls the enable function of the oscilla-
tor. See Table 3 for shunt settings. To improve perfor-
mance of the EV kit, disable the crystal oscillator when
not in use.
Clock
The MAX1217/MAX1218/MAX1219 EV kits feature a
variety of clock input methods. A differential clock signal
can be generated from a single-ended sine wave
applied to J15. A variable-duty-cycle differential clock
signal can be generated from a single-ended sine wave
applied to J7 (see the Variable-Duty-Cycle Clock-
Shaping Circuit section). Alternatively, the on-board
crystal oscillator can be utilized instead of a user-pro-
vided signal source (see the On-Board Crystal Oscillator
section). U2 multiplexes all three of these inputs onto
the MAX1217/MAX1218/MAX1219 clock input lines.
Jumpers JU6 and JU7 control the multiplexer. See Table
1 for shunt settings.
Table 3. Crystal Oscillator Shunt Settings
(JU8)
SHUNT POSITION
DESCRIPTION
Crystal oscillator enabled.
Crystal oscillator disabled.
1-2
2-3*
*Default configuration: JU8 (2-3).
Variable-Duty-Cycle Clock-Shaping Circuit
A differential multiplexer (U2) processes the single-
ended sine wave (applied at J7) and generates the
required differential clock signal. The clock signal’s duty
cycle can be adjusted with potentiometer ꢁ116. A clock
signal with a 50ꢀ duty cycle (recommended setting)
can be achieved by adjusting ꢁ116 until 1.32V is pro-
duced across test points TP3 and TP4 when the clock
voltage supply (VCLK) is set to 3.3V. Measure the clock
signal with a differential oscilloscope probe at J14.
Table 1. Clock Multiplexer Shunt Settings
(JU6, JU7)
JUMPER
DESCRIPTION
JU6
JU7
Variable-duty-cycle clock selected.
Apply a signal to J7. Measure the duty
cycle at J14.
Input Signal
The MAX1217/MAX1218/MAX1219 accept differential
analog input signals; however, the EV kits only require
a single-ended analog input signal, with an amplitude
2-3*
2-3*
Differential clock signal selected.
Apply a signal to J15.
1-2
2-3
1-2
1-2
1-2
2-3
of less than 11dBm (793mV ) provided by the user.
P-P
On-board transformers (T1, T3) convert the single-
ended analog inputs and generate differential analog
signals at the ADC’s differential input pins.
Clock disabled.
On-board crystal oscillator selected.
Enable crystal using JU8.
Reference Voltage
There are three methods to set the full-scale range of the
MAX1217/MAX1218/MAX1219. The EV kits can be con-
figured to use the MAX1217/MAX1218/MAX1219’s inter-
nal reference, a stable low-noise external reference, or
the on-board reference adjustment circuitry.
*Default configuration: JU6 (2-3), JU7 (2-3).
Divide-by-Two Clock
The MAX1217/MAX1218/MAX1219 feature internal
divide-by-two clock circuitry. Jumper JU5 controls this
function. See Table 2 for shunt settings.
The MAX1217/MAX1218/MAX1219 feature an internal
1.23V bandgap reference circuit, which, in combination
with an internal reference-scaling amplifier, determines
the full-scale range of the MAX1217/MAX1218/MAX1219.
To compensate for gain errors or increase/decrease the
ADC’s full-scale range, the voltage of this bandgap refer-
ence can be indirectly adjusted by configuring JU1/JU2
and adjusting potentiometer ꢁ119/ꢁ120 on the
MAX1217/MAX1218/MAX1219 EV kits. Connecting a
potentiometer between ꢁEFADJ and ꢁEFIO increases
the full-scale range of the ADC. Conversely, connecting
the potentiometer between ꢁEFADJ and ꢂND decreases
Table 2. Divide-by-Two Shunt Settings (JU5)
MAX1217/
MAX1218/MAX1219
CLKDIV PIN
SHUNT
POSITION
DESCRIPTION
1-2*
2-3
AVCC
ꢂND
Clock signal is divided by 1.
Clock signal is divided by 2.
*Default configuration: JU5 (1-2).
On-Board Crystal Oscillator
To facilitate easy evaluation, the MAX1217/MAX1218/
MAX1219 EV kits feature an open location for an on-board
4
_______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
the full-scale range. The MAX1217/MAX1218/MAX1219
feature two sets of pins to calibrate each channel
independently; thus, the MAX1217/MAX1218/MAX1219
EV kits feature two sets of reference circuitry. Jumper
JU1 and potentiometer ꢁ119 control the reference of
channel A. Jumper JU2 and potentiometer ꢁ120 control
the reference of channel B. See Table 4 for shunt settings.
improve the dynamic performance of the device. In addi-
tion, seven drivers (U3–U9) buffer and level-translate the
ADC’s digital outputs to LVPECL-compatible signals.
The drivers increase the differential voltage swing, and
are able to support large capacitive loads, which may be
present at the logic analyzer connection. The outputs of
the buffers are connected to headers J11, J12, and J13.
See Table 6 for bit location of headers J8–J13.
Table 4. Reference Shunt Settings (JU1, JU2)
Table 6. Output Bit Locations (Differential
Capture)
SHUNT
DESCRIPTION
POSITION
CHANNEL A
CHANNEL B
Internal reference disabled. Apply a
reference voltage at the ꢁEFIO pad.
1-2
SIGNAL
UNBUFFERED = J8
BUFFERED = J11
UNBUFFERED = J10
BUFFERED = J13
3-4*
5-6
Internal reference enabled.
P
1
49
50
45
46
41
42
37
38
33
34
29
30
25
26
21
22
17
18
13
14
9
ꢁEFADJ connected through potentiometer
ꢁ119/ꢁ120 to ꢁEFIO.
Oꢁ
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
2
5
ꢁEFADJ connected through potentiometer
ꢁ119/ꢁ120 to ꢂND.
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
7-8
6
9
*Default configuration: JU1 (3-4), JU2 (3-4).
10
13
14
17
18
21
22
25
26
29
30
33
34
37
38
41
42
45
46
Output Signal
The MAX1217/MAX1218/MAX1219 feature two, parallel
LVDS-compatible, digital output buses. Each output
bus transmits the digitized analog input signals of
channels A and B. An additional output (CLK) is provid-
ed for data synchronization. ꢁefer to the MAX1217,
MAX1218, MAX1219 data sheets for more details.
Output Format
The digital output coding can be set to either two’s
complement or straight offset binary by configuring
jumper JU3 and JU4. Each channel can be set inde-
pendently. Jumper JU3 controls the output format of
channel A. Jumper JU4 controls the output format of
channel B. See Table 5 for shunt positions.
Table 5. Output Format Shunt Settings
(JU3, JU4)
SHUNT
POSITION
T/B PIN
AVCC
ꢂND
DESCRIPTION
10
5
Digital output in straight
offset binary format.
1-2
6
49
50
1
2
Digital output in two’s-
complement format.
2-3*
SIGNAL
UNBUFFERED
J9-3
BUFFERED
J12-3
*Default configuration: JU3 (2-3), JU4 (2-3).
P
CLK
Output Bit Locations
N
J9-4
J12-4
The digital outputs of the MAX1217/MAX1218/MAX1219
are connected to headers J8, J9, and J10. PC board
trace lengths are matched to minimize data skew and
P: True.
N: Complementary.
Note: Requires differential logic analyzer.
_______________________________________________________________________________________
5
MAX1217/MAX1218/MAX1219 Evaluation Kits
Output Bit Locations (Single-Ended Capture)
The MAX1217/MAX1218/MAX1219 EV kits feature a third
set of headers (J16, J17, J18) that allow a single-ended
logic analyzer to capture the output data of the MAX1217/
MAX1218/MAX1219. The single-ended outputs are
buffered by U3–U9. The output data has a typical 2V com-
mon-mode voltage and a single-ended 750mV voltage
swing. For best results, adjust the logic analyzer’s trigger
threshold to the common-mode voltage. See Table 7 for
single-ended bit locations.
P-P
Table 7. Output Bit Locations (Single-Ended Capture)
CHANNEL A
CHANNEL B
SIGNAL
J16
J18
73
67
61
55
49
43
37
31
25
19
13
7
Oꢁ
D11
D10
D9
1
7
13
19
25
31
37
43
49
55
61
67
73
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
SIGNAL
CLK
CHANNEL A AND B
J17-4
6
_______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
O G N D
O G N D
C C
O V
O V
O V
C C
C C
A G N D
A G N D
A G N D
A G N D
C C
C C
A V
A V
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
C C
A V
C C
C C
C C
C C
A V
A V
A V
A V
A V
A V
A V
A V
A V
C C
C C
C C
C C
C C
Figure 1a. MAX1217 EV Kit Schematic (Sheet 1 of 7)
_______________________________________________________________________________________
7
MAX1217/MAX1218/MAX1219 Evaluation Kits
O G N D
O G N D
C C
O V
O V
O V
C C
C C
A G N D
A G N D
A G N D
A G N D
C C
C C
A V
A V
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
C C
A V
C C
C C
C C
C C
A V
A V
A V
A V
A V
A V
A V
A V
A V
AM2X18
C C
C C
C C
C C
C C
Figure 1b. MAX1218 EV Kit Schematic (Sheet 1 of 7)
_______________________________________________________________________________________
8
MAX1217/MAX1218/MAX1219 Evaluation Kits
O G N D
O G N D
C C
O V
O V
O V
C C
C C
A G N D
A G N D
A G N D
A G N D
C C
C C
A V
A V
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
C C
A V
C C
C C
C C
C C
A V
A V
A V
A V
A V
A V
A V
A V
A V
AM2X19
C C
C C
C C
C C
C C
Figure 1c. MAX1219 EV Kit Schematic (Sheet 1 of 7)
_______________________________________________________________________________________
9
MAX1217/MAX1218/MAX1219 Evaluation Kits
AM9X38
FV651E
Figure 1d. MAX1217/MAX1218/MAX1219 EV Kit Schematic (Sheet 2 of 7)
10 ______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 1e. MAX1217/MAX1218/MAX1219 EV Kit Schematic (Sheet 3 of 7)
______________________________________________________________________________________ 11
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 1f. MAX1217/MAX1218/MAX1219 EV Kit Schematic (Sheet 4 of 7)
12 ______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 1g. MAX1217/MAX1218/MAX1219 EV Kit Schematic (Sheet 5 of 7)
______________________________________________________________________________________ 13
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 1h. MAX1217/MAX1218/MAX1219 EV Kit Schematic (Sheet 6 of 7)
14 ______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
VPECL
C39
0.1μF
C30
0.01μF
1
20
VCC
VCC
2
3
19
DA00P
DA00N
BDA00P
D0
D0
Q0
C68
0.01μF
R99
49.9Ω
1%
R101
49.9Ω
1%
R100
49.9Ω
1%
18
17
BDA00N
BDC0P
Q0
Q1
4
5
DC0P
DC0N
D1
D1
C69
0.01μF
U9
MC100LVEL17
R102
49.9Ω
1%
R104
49.9Ω
1%
R103
49.9Ω
1%
16
15
BDC0N
Q1
Q2
6
7
D2
D2
14
13
Q2
Q3
8
9
DB00N
DB00P
BDB00N
C70
D3
D3
0.01μF
R105
49.9Ω
1%
R107
49.9Ω
1%
R106
49.9Ω
1%
12
BDB00P
Q3
VBB
10
VEE
11
Figure 1i. MAX1217/MAX1218/MAX1219 EV Kit Schematic (Sheet 7 of 7)
______________________________________________________________________________________ 15
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 2. MAX1217/MAX1218/MAX1219 EV Kit Component Placement Guide—Component Side
16 ______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 3. MAX1217/MAX1218/MAX1219 EV Kit PC Board Layout—Component Side
______________________________________________________________________________________ 17
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 4. MAX1217/MAX1218/MAX1219 EV Kit PC Board Layout—Ground Planes
18 ______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 5. MAX1217/MAX1218/MAX1219 EV Kit PC Board Layout—Power Planes
______________________________________________________________________________________ 19
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 6. MAX1217/MAX1218/MAX1219 EV Kit PC Board Layout—Solder Side
20 ______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
Figure 7. MAX1217/MAX1218/MAX1219 EV Kit Component Placement Guide—Solder Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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