MAX1224 [MAXIM]
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs; 1.5Msps的，单电源，低功耗，真差分， 12位ADC
| 型号： | MAX1224 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs |
| 文件： | 总18页 (文件大小：1305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3271; Rev 0; 5/04
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
General Description
Features
The MAX1224/MAX1225 low-power, high-speed, serial-
output, 12-bit, analog-to-digital converters (ADCs) oper-
ate at up to 1.5Msps. These devices feature true-differen-
tial inputs, offering better noise immunity, distortion
improvements, and a wider dynamic range over single-
ended inputs. A standard SPI™/QSPI™/MICROWIRE™
interface provides the clock necessary for conversion.
These devices easily interface with standard digital signal
processor (DSP) synchronous serial interfaces.
♦ 1.5Msps Sampling Rate
♦ Only 18mW (typ) Power Dissipation
♦ Only 1µA (max) Shutdown Current
♦ High-Speed, SPI-Compatible, 3-Wire Serial Interface
♦ 69dB S/(N + D) at 525kHz Input Frequency
♦ Internal True-Differential Track/Hold (T/H)
♦ External Reference
The MAX1224/MAX1225 operate from a single +2.7V to
+3.6V supply voltage and require an external reference.
The MAX1224 has a unipolar analog input, while the
MAX1225 has a bipolar analog input. These devices fea-
ture a partial power-down mode and a full power-down
mode for use between conversions, which lower the sup-
ply current to 1mA (typ) and 1µA (max), respectively. Also
♦ No Pipeline Delays
♦ Small 12-Pin TQFN Package
featured is a separate power-supply input (V ), which
L
allows direct interfacing to +1.8V to V
digital logic. The
DD
Ordering Information
fast conversion speed, low-power dissipation, good AC
performance, and DC accuracy ( 1.5 LSꢀ IꢁL) make the
MAX1224/MAX1225 ideal for industrial process control,
motor control, and base-station applications.
PIN-
PART
TEMP RANGE
INPUT
PACKAGE
MAX1224CTC-T
MAX1224ETC-T
MAX1225CTC-T
MAX1225ETC-T
0°C to +70°C 12 TQFꢁ-12
-40°C to +85°C 12 TQFꢁ-12
0°C to +70°C 12 TQFꢁ-12
-40°C to +85°C 12 TQFꢁ-12
Unipolar
Unipolar
ꢀipolar
ꢀipolar
The MAX1224/MAX1225 come in a 12-pin TQFꢁ pack-
age, and are available in the commercial (0°C to +70°C)
and extended (-40°C to +85°C) temperature ranges.
Applications
Data Acquisition
ꢀill Validation
Motor Control
Communications
Portable Instruments
Pin Configuration
Typical Operating Circuit
TOP VIEW
AIN+
12
N.C.
11
SCLK
10
+1.8V TO V
DD
+2.7V TO +3.6V
0.01µF
0.01µF
10µF
10µF
AIN-
REF
1
2
3
9
8
7
CNVST
DOUT
V
V
L
DD
DIFFERENTIAL
INPUT
+
-
DOUT
AIN+
AIN-
MAX1224
MAX1225
VOLTAGE
µC/DSP
MAX1224
MAX1225
RGND
V
L
CNVST
SCLK
4
5
6
REF
4.7µF
REF
V
N.C.
GND
DD
RGND
GND
0.01µF
TQFN
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
to GꢁD..............................................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
DD
V to GꢁD ................-0.3V to the lower of (V
L
+ 0.3V) and +6V
Continuous Power Dissipation (T = +70°C)
DD
A
Digital Inputs
to GꢁD .................-0.3V to the lower of (V
Digital Output
to GꢁD....................-0.3V to the lower of (V + 0.3V) and +6V
Analog Inputs and
REF to GꢁD..........-0.3V to the lower of (V
RGꢁD to GꢁD .......................................................-0.3V to +0.3V
12-Pin TQFꢁ (derate 16.9mW/°C above +70°C) ......1349mW
Operating Temperature Ranges
MAX127_ CTC ...................................................0°C to +70°C
MAX127_ ETC.................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V) and +6V
DD
L
+ 0.3V) and +6V
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +2.7V to +3.6V, V = V , V
= 2.048V, f
= 24.0MHz, 50% duty cycle, T = T
A
to T , unless otherwise noted.
MAX
L
DD REF
SCLK
MIꢁ
Typical values are at V = 3V and T = +25°C.)
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
12
ꢀits
LSꢀ
LSꢀ
LSꢀ
Relative Accuracy
Differential ꢁonlinearity
Offset Error
IꢁL
(ꢁote 1)
-1.5
-1.0
+1.5
+1.5
8.0
DꢁL
Guaranteed no missing codes (ꢁote 2)
Offset-Error Temperature
Coefficient
1
2
ppm/°C
Gain Error
Offset nulled
6.0
LSꢀ
Gain Temperature Coefficient
ppm/°C
DYNAMIC SPECIFICATIONS (f = 525kHz sine wave, V = V , unless otherwise noted.)
REF
IN
IN
SIꢁAD
THD
66
69
-80
-83
-78
15
dꢀ
dꢀ
Signal-to-ꢁoise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power ꢀandwidth
Up to the 5th harmonic
= 250kHz, f = 300kHz
-76
-76
SFDR
IMD
dꢀ
f
dꢀ
Iꢁ1
Iꢁ2
-3dꢀ point
MHz
MHz
Full-Linear ꢀandwidth
S/(ꢁ + D) > 68dꢀ, single ended
1.2
CONVERSION RATE
Minimum Conversion Time
Maximum Throughput Rate
Minimum Throughput Rate
t
(ꢁote 3)
0.667
µs
Msps
ksps
ns
COꢁV
1.5
10
(ꢁote 4)
(ꢁote 5)
Track-and-Hold Acquisition Time
Aperture Delay
t
125
5
ACQ
ns
Aperture Jitter
(ꢁote 6)
(ꢁote 7)
30
ps
External Clock Frequency
f
24.0
MHz
SCLK
2
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V, V = V , V
= 2.048V, f
= 24.0MHz, 50% duty cycle, T = T
to T , unless otherwise noted.
MAX
L
DD REF
SCLK
A
MIꢁ
Typical values are at V = 3V and T = +25°C.)
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (AIN+, AIN-)
AIꢁ+ - AIꢁ-, MAX1224
AIꢁ+ - AIꢁ-, MAX1225
0
V
REF
Differential Input Voltage Range
V
V
Iꢁ
-V
/ 2
+V
/ 2
REF
REF
Absolute Input Voltage Range
DC Leakage Current
0
V
V
DD
1
µA
pF
µA
Input Capacitance
Per input pin
16
50
Input Current (Average)
REFERENCE INPUT (REF)
Time averaged at maximum throughput rate
V
+
DD
REF Input Voltage Range
V
1.0
V
REF
50mV
Input Capacitance
20
pF
µA
µA
DC Leakage Current
1
Input Current (Average)
DIGITAL INPUTS (SCLK, CNVST)
Input-Voltage Low
Time averaged at maximum throughput rate
200
VIL
0.3 x V
10
V
V
L
Input-Voltage High
VIH
0.7 x V
L
Input Leakage Current
DIGITAL OUTPUT (DOUT)
Output Load Capacitance
Output-Voltage Low
I
IL
0.05
0.2
µA
C
For stated timing performance
30
pF
V
OUT
V
I
I
= 5mA, V ≥ 1.8V
0.4
OL
OH
OL
SIꢁK
L
Output-Voltage High
V
= 1mA, V ≥ 1.8V
V - 0.5V
L
V
SOURCE
L
Output Leakage Current
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
I
Output high impedance
10
µA
V
2.7
1.8
3.6
V
V
DD
V
V
L
DD
7
Static, f
= 24.0MHz
5
4
SCLK
Analog Supply Current,
ꢁormal Mode
I
Static, no SCLK
5
mA
DD
Operational, 1.5Msps
6
8
f
= 24.0MHz
1
SCLK
Analog Supply Current,
Partial Power-Down Mode
I
I
mA
µA
DD
ꢁo SCLK
= 24.0MHz
1
f
1
SCLK
Analog Supply Current,
Full Power-Down Mode
DD
ꢁo SCLK
0.3
0.3
0.15
1
1
Operational, full-scale input at 1.5Msps
Static, f
= 24.0MHz
0.5
0.3
1
SCLK
mA
Digital Supply Current (ꢁote 8)
Positive-Supply Rejection
Partial/full power-down mode,
= 24.0MHz
0.1
f
SCLK
Static, no SCLK, all modes
0.1
0.2
µA
PSR
Full-scale input, 3V +20%, -10%
3.0
mV
_______________________________________________________________________________________
3
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +3.6V, V = V , V
= 2.048V, f
= 24.0MHz, 50% duty cycle, T = T
A
to T , unless otherwise noted.
MAX
L
DD REF
SCLK
MIꢁ
Typical values are at V = 3V and T = +25°C.)
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V = 2.7V to V
18.7
18.7
L
DD
SCLK Pulse-Width High
t
ns
CH
V = 1.8V to V
L
minimum recommended
minimum recommended
DD,
22.5
22.5
(ꢁote 7)
V = 2.7V to V
L
DD
SCLK Pulse-Width Low
t
ns
ns
CL
V = 1.8V to V
L
DD,
(ꢁote 7)
C = 30pF, V = 2.7V to V
L
17
24
L
DD
SCLK Rise to DOUT Transition
t
DOUT
C = 30pF, V = 1.8V to V
L
L
DD
DOUT Remains Valid After SCLK
CꢁVST Fall to SCLK Fall
t
V = 1.8V to V
4
ns
ns
DHOLD
L
DD
DD
DD
t
V = 1.8V to V
L
10
20
SETUP
CꢁVST Pulse Width
t
V = 1.8V to V
L
ns
CSW
Power-Up Time; Full Power-Down
Restart Time; Partial Power-Down
t
2
ms
PWR-UP
t
16
Cycles
RCV
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: ꢁo missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CꢁST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SIꢁAD performance.
Note 7: 1.5Msps operation guaranteed for V > 2.7V. See the Typical Operating Characteristics section for recommended sampling
L
speeds for V < 2.7V.
L
Note 8: Digital supply current is measured with the V level equal to V , and the V level equal to GꢁD.
IH
L
IL
V
L
CNVST
SCLK
t
CSW
6kΩ
t
CL
t
SETUP
t
CH
DOUT
DOUT
6kΩ
C
C
L
L
t
DHOLD
t
DOUT
DOUT
GND
b) HIGH-Z TO V , V TO V ,
OL
GND
a) HIGH-Z TO V , V TO V
,
OH OL
OH
OL OH
AND V TO HIGH-Z
OH
AND V TO HIGH-Z
OL
Figure 1. Detailed Serial-Interface Timing
Figure 2. Load Circuits for Enable/Disable Times
4
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Typical Operating Characteristics
(V
= +3V, V = V , V
= 2.048V, f
= 24MHz, f
= 1.5Msps, T = T
to T
, unless otherwise noted. Typical val-
MAX
MIꢁ
DD
L
DD REF
SCLK
SAMPLE
A
ues are measured at T = +25°C)
A
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1224)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1225)
MAXIMUM RECOMMENDED f
vs. V
L
SCLK
25
23
21
19
17
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
1.8
2.1
2.4
2.7
V (V)
3.0
3.3
3.6
0
1024
2048
3072
4096
-2048
-1024
0
1024
2048
L
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1225)
OFFSET ERROR
vs. TEMPERATURE (MAX1224)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1224)
1.00
0.75
0.50
0.25
0
0
-1
-2
-3
-4
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-2048
-1024
0
1024
2048
-40
-15
10
35
60
85
0
1024
2048
3072
4096
DIGITAL OUTPUT CODE
TEMPERATURE (°C)
DIGITAL OUTPUT CODE
GAIN ERROR
vs. TEMPERATURE (MAX1225)
OFFSET ERROR
vs. TEMPERATURE (MAX1225)
GAIN ERROR
vs. TEMPERATURE (MAX1224)
2
2
1
2
1
1
0
0
0
-1
-2
-1
-2
-1
-2
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Typical Operating Characteristics (continued)
(V
= +3V, V = V , V
= 2.048V, f
= 24MHz, f
= 1.5Msps, T = T
to T
, unless otherwise noted. Typical val-
MAX
MIꢁ
DD
L
DD REF
SCLK
SAMPLE
A
ues are measured at T = +25°C)
A
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1224)
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1225)
70.00
69.75
69.50
69.25
69.00
69.50
69.25
69.00
68.75
68.50
SNR
SNR
SINAD
SINAD
100
200
300
400
500
100
200
300
400
500
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
SFDR vs. INPUT FREQUENCY
THD vs. INPUT FREQUENCY
92
90
88
86
84
82
-82
-84
-86
-88
-90
-92
MAX1224
MAX1225
MAX1225
MAX1224
400
100
200
300
500
100
200
300
400
500
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
FFT PLOT (MAX1224)
FFT PLOT (MAX1225)
0
-20
0
-20
f
= 500kHz
f = 500kHz
IN
SINAD = 69.2dB
SNR = 69.3dB
THD = -90.5dB
SFDR = 88.15dB
IN
SINAD = 69.4dB
SNR = 69.6dB
THD = -83.9dB
SFDR = 84.3dB
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
125
250
375
500
625
750
0
125
250
375
500
625
750
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
6
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Typical Operating Characteristics (continued)
(V
= +3V, V = V , V
= 2.048V, f
= 24MHz, f
= 1.5Msps, T = T
to T
, unless otherwise noted. Typical val-
MAX
MIꢁ
DD
L
DD REF
SCLK
SAMPLE
A
ues are measured at T = +25°C)
A
TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDANCE
TWO-TONE IMD PLOT (MAX1224)
0
-20
-50
-60
f
f
= 250.102kHz
= 299.966kHz
IN1
IN2
IMD = -88.4dB
-40
f
IN
= 500kHz
f
IN1
f
IN2
-60
-70
-80
-80
-100
-120
-140
f
= 100kHz
IN
-90
-100
0
125
250
375
500
625
750
10
100
SOURCE IMPEDANCE (Ω)
1000
ANALOG INPUT FREQUENCY (kHz)
V
/V FULL POWER-DOWN
L
DD
TWO-TONE IMD PLOT (MAX1225)
SUPPLY CURRENT vs. TEMPERATURE
0
-20
1.0
0.8
0.6
0.4
0.2
0
f
f
= 250.102kHz
= 299.966kHz
IN1
IN2
IMD = -85.2dB
-40
f
IN1
f
IN2
-60
V
, f
= 24MHz
DD SCLK
-80
-100
-120
-140
V , NO SCLK
L
V
DD
, NO SCLK
60
0
125
250
375
500
625
750
-40
-15
10
35
85
ANALOG INPUT FREQUENCY (kHz)
TEMPERATURE (°C)
V PARTIAL/FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
L
V
SUPPLY CURRENT vs. TEMPERATURE
DD
9
6
3
0
100
75
50
25
0
CONVERSION
V = 3V, f
= 24MHz
SCLK
L
V = 1.8V, f
L
= 24MHz
SCLK
PARTIAL POWER-DOWN
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Typical Operating Characteristics (continued)
(V
= +3V, V = V , V
= 2.048V, f
= 24MHz, f
= 1.5Msps, T = T
to T
, unless otherwise noted. Typical val-
MIꢁ
MAX
DD
L
DD REF
SCLK
SAMPLE
A
ues are measured at T = +25°C)
A
V SUPPLY CURRENT
L
vs. CONVERSION RATE
V
SUPPLY CURRENT
DD
V SUPPLY CURRENT vs. TEMPERATURE
L
vs. CONVERSION RATE
0.5
0.4
0.3
0.2
0.1
0
250
200
150
100
50
9
6
3
0
CONVERSION, V = 3V
L
V = 3V
L
CONVERSION, V = 1.8V
L
V = 1.8V
L
0
-40
-15
10
35
60
85
0
250
500
750
100 1250 1500
0
250
500
750 1000 1250 1500
(kHz)
TEMPERATURE (°C)
f
(kHz)
SAMPLE
f
SAMPLE
Pin Description
PIN
NAME
FUNCTION
1
AIꢁ-
ꢁegative Analog Input
External Reference Voltage Input. V
sets the analog input range. ꢀypass REF with a 0.01µF
REF
2
3
4
REF
capacitor and a 4.7µF capacitor to RGꢁD.
RGꢁD
Reference Ground. Connect RGꢁD to GꢁD.
Positive Analog Supply Voltage (+2.7V to +3.6V). ꢀypass V
capacitor to GꢁD.
with a 0.01µF capacitor and a 10µF
DD
V
DD
5, 11
6
ꢁ.C.
ꢁo Connection
GꢁD
Ground. GꢁD is internally connected to EP.
Positive Logic Supply Voltage (1.8V to V ). ꢀypass V with a 0.01µF capacitor and a 10µF capacitor
to GꢁD.
DD
L
7
8
9
V
L
DOUT
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CꢁVST high prepares the part for a conversion. Conversion begins on the
falling edge of CꢁVST. The sampling instant is defined by the falling edge of CꢁVST.
CꢁVST
10
12
—
SCLK
AIꢁ+
EP
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GꢁD.
8
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
CAPACITIVE
DAC
C
IN+
V
L
V
R
DD
IN+
AIN+
REF
CONTROL
LOGIC
V
AZ
COMP
AIN+
12-BIT
SAR
ADC
OUTPUT
BUFFER
T/H
DOUT
AIN-
AIN+
AIN-
R
IN-
C
IN-
ACQUISITION MODE
CAPACITIVE
DAC
CNVST
SCLK
CONTROL
LOGIC AND
TIMING
C
IN+
R
IN+
MAX1224
MAX1225
CONTROL
LOGIC
V
AZ
COMP
AIN-
RGND
GND
R
IN-
C
IN-
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
Figure 3. Functional Diagram
the signal to be acquired. It is calculated by the follow-
ing equation:
Detailed Description
The MAX1224/MAX1225 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CꢁVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1224/MAX1225.
t
≥ 9 x (RS + R ) x 16pF
Iꢁ
ACQ
where R = 200Ω, and RS is the source impedance of
Iꢁ
the input signal.
Note: t
is never less than 125ns, and any source
ACQ
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1224/MAX1225, which is composed
of a T/H, a comparator, and a switched-capacitor digi-
tal-to-analog converter (DAC). The T/H enters its track-
ing mode on the 14th SCLK rising edge of the previous
conversion. Upon power-up, the T/H enters its tracking
mode immediately. The positive input capacitor is con-
nected to AIꢁ+. The negative input capacitor is con-
nected to AIꢁ-. The T/H enters its hold mode on the
falling edge of CꢁVST and the difference between the
sampled positive and negative input voltages is con-
verted. The time required for the T/H to acquire an input
signal is determined by how quickly its input capaci-
tance is charged. If the input signal’s source imped-
ance is high, the acquisition time lengthens. The
Input Bandwidth
The ADC’s input-tracking circuitry has a 15MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sam-
pling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended.
Analog Input Protection
Internal protection diodes that clamp the analog input
to V
and GꢁD allow the analog input pins to swing
DD
from GꢁD - 0.3V to V
+ 0.3V without damage. ꢀoth
DD
inputs must not exceed V
accurate conversions.
or be lower than GꢁD for
DD
acquisition time, t
, is the minimum time needed for
ACQ
_______________________________________________________________________________________
9
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
A CꢁVST falling edge initiates a conversion sequence:
Serial Interface
Initialization After Power-Up
and Starting a Conversion
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the conver-
sion is determined.
Upon initial power-up, the MAX1224/MAX1225 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions t
after each
DOUT
SCLK’s rising edge and remains valid 4ns (t
)
DHOLD
after the next rising edge. The 4th rising clock edge
produces the MSꢀ of the conversion at DOUT, and the
MSꢀ remains valid 4ns after the 5th rising edge. Since
there are 12 data bits and 3 leading zeros, at least 16
rising clock edges are needed to shift out these bits.
For continuous operation, pull CꢁVST high between the
14th and the 16th SCLK rising edges. If CꢁVST stays
low after the falling edge of the 16th SCLK cycle, the
DOUT line goes to a high-impedance state on either
CꢁVST’s rising edge or the next SCLK’s rising edge.
To start a conversion, pull CꢁVST low. At CꢁVST’s
falling edge, the T/H enters its hold mode and a conver-
sion is initiated. SCLK runs the conversion and the data
can then be shifted out serially on DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CꢁVST and SCLK digital inputs. Figures 1
and 5 show timing diagrams, which outline the serial-
interface operation.
CNVST
t
SETUP
t
POWER-MODE SELECTION WINDOW
8
ACQUIRE
16
CONTINUOUS-CONVERSION
SELECTION WINDOW
1
2
3
4
14
SCLK
HIGH IMPEDANCE
DOUT
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. Interface-Timing Sequence
CONVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
CNVST
SCLK
ONE 8-BIT TRANSFER
1ST SCLK RISING EDGE
DOUT
MODE
0
0
0
D11
D10
D9
D8
D7
NORMAL
PPD
Figure 6. SPI Interface—Partial Power-Down Mode
10 ______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Partial Power-Down and
Applications Information
Full Power-Down Modes
External Reference
An external reference is required for the MAX1224/
MAX1225. Use a 4.7µF and 0.01µF bypass capacitor on
the REF pin for best performance. The reference input
Power consumption can be reduced significantly by plac-
ing the MAX1224/MAX1225 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wake-
up time applications. Pull CꢁVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 1mA. Drive CꢁVST
low and allow at least 14 SCLK cycles to elapse before
driving CꢁVST high to exit partial power-down mode.
structure allows a voltage range of +1V to V
.
DD
How to Start a Conversion
An analog-to-digital conversion is initiated by CꢁVST and
clocked by SCLK, and the resulting data is clocked out
on DOUT by SCLK. With SCLK idling high or low, a falling
edge on CꢁVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CꢁVST is low during
the 16th falling SCLK edge, DOUT returns to high imped-
ance on the next rising edge of CꢁVST or SCLK,
enabling the serial interface to be shared by multiple
devices. If CꢁVST returns high after the 14th, but before
the 16th SCLK rising edge, DOUT remains active so con-
tinuous conversions can be sustained. The highest
throughput is achieved when performing continuous con-
versions. Figure 10 illustrates a conversion using a typical
serial interface.
Full power-down mode is ideal for infrequent data sam-
pling and very low supply-current applications. The
MAX1224/MAX1225 have to be in partial power-down
mode in order to enter full power-down mode. Perform
the SCLK/CꢁVST sequence described above to enter
partial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CꢁVST low, and allow at least 14 SCLK cycles
to elapse before driving CꢁVST high to exit full power-
down mode. In partial/full power-down mode, maintain
a logic low or a logic high on SCLK to minimize power
consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1224. Figure 9 shows the bipolar transfer function for
the MAX1225. The MAX1224 output is straight binary,
while the MAX1225 output is two’s complement.
EXECUTE PARTIAL POWER-DOWN TWICE
SECOND 8-BIT TRANSFER
CNVST
FIRST 8-BIT TRANSFER
SCLK
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
1ST SCLK RISING EDGE
1ST SCLK RISING EDGE
D8 D7
DOUT
0
0
0
D11
D10
D9
0
0
0
0
0
0
0
0
MODE
NORMAL
PPD
RECOVERY
FPD
Figure 7. SPI Interface—Full Power-Down Mode
______________________________________________________________________________________ 11
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Connection to
Standard Interfaces
OUTPUT CODE
The MAX1224/MAX1225 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 28.8MHz.
FULL-SCALE
TRANSITION
111...111
111...110
111...101
SPI and MICROWIRE
When using SPI or MICROWIRE, the MAX1224/MAX1225
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CꢁVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
12 bits from the ADC. DOUT transitions on SCLK rising
FS = V
REF
REF
ZS = 0
V
1 LSB =
4096
000...011
000...010
000...001
000...000
edges. DOUT is guaranteed to be valid t
later and
DOUT
remains valid until t
after the following SCLK rising
DHOLD
edge. When using CPOL = 0 and CPHA = 0, or CPOL =
1 and CPHA = 1, the data is clocked into the µP on the
following rising edge. When using CPOL = 0 and CPHA
= 1, or CPOL = 1 and CPHA = 0, the data is clocked
into the µP on the next falling edge. See Figure 11 for
connections and Figures 12 and 13 for timing. See the
Timing Characteristics section to determine the best
mode to use.
0
1
2
3
FS
FS - 3/2 LSB
DIFFERENTIAL INPUT
VOLTAGE (LSB)
Figure 8. Unipolar Transfer Function (MAX1224 Only)
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1224/MAX1225 require 16 clock cycles
from the µP to clock out the 12 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
12 data bits, and a trailing zero with the data in MSꢀ-
first format.
OUTPUT CODE
V
FULL-SCALE
TRANSITION
REF
2
FS =
ZS = 0
-V
011...111
011...110
REF
2
- FS =
V
REF
1 LSB =
000...010
000...001
4096
000...000
111...111
DSP Interface to the TMS320C54_
The MAX1224/MAX1225 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1224/MAX1225 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CꢁVST.
111...110
111...101
100...001
100...000
-FS
0
FS
FS - 3/2 LSB
DIFFERENTIAL INPUT
VOLTAGE (LSB)
For continuous conversion, set the serial port to trans-
mit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port config-
uration (SPC) register should be set up with internal
Figure 9. Bipolar Transfer Function (MAX1225 Only)
12 ______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
CNVST
SCLK
DOUT
1
14
16
1
0
0
0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 10. Continuous Conversion with Burst/Continuous Clock
I/O
CNVST
SCLK
SCK
MISO
DOUT
+3V TO +5V
MAX1224
MAX1225
SS
A) SPI
CS
CNVST
SCLK
SCK
MISO
DOUT
+3V TO +5V
MAX1224
MAX1225
SS
B) QSPI
I/O
SK
SI
CNVST
SCLK
DOUT
MAX1224
MAX1225
C) MICROWIRE
Figure 11. Common Serial-Interface Connections to the MAX1224/MAX1225
______________________________________________________________________________________ 13
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
CNVST
8
9
16
1
SCLK
DOUT
HIGH-Z
HIGH-Z
D11
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK
DOUT
14
16
1
1
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
2
16
SCLK
DOUT
HIGH-Z
HIGH-Z
D1
D11
D8
D7
D6
D5
D4
D3
D2
D0
D10 D9
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
word length can be set to 8 bits with FO = 1 to imple-
ment the power-down modes. The CꢁVST pin must idle
high to remain in either power-down state.
This setup allows continuous conversions provided that
the data-transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
Another method of connecting the MAX1224/MAX1225
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16, where serial clock (CLOCK) drives the
CLKR, and SCLK and the convert signal (COꢁVERT)
drive the FSR and CꢁVST.
read the data without CPU intervention. Connect the V
L
pin to the TMS320C54_ supply voltage when the
MAX1224/MAX1225 are operating with an analog sup-
ply voltage higher than the DSP supply voltage. The
The serial port must be set up to accept an external
receive-clock and external receive-frame sync.
14 ______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
The SPC register should be written as follows:
TXM = 0, external frame sync
intervention. Connect the V pin to the TMS320C54_
L
supply voltage when the MAX1224/MAX1225 are oper-
ating with an analog supply voltage higher than the
DSP supply voltage.
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
The MAX1224/MAX1225 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CꢁVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CꢁVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion, provided that
the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
DSP Interface to the ADSP21_ _ _
The MAX1224/MAX1225 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc. Figure 19 shows the direct connection of the
MAX1224/MAX1225 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1224/MAX1225. For continuous conver-
sions, idle CꢁVST low and pulse it high for one clock
cycle during the LSꢀ of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CꢁVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
ters should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEꢁ = 1001).
V
L
DV
DD
MAX1224
MAX1225
TMS320C54_
SCLK
CNVST
DOUT
CLKX
CLKR
FSX
FSR
DR
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
V
L
DV
DD
MAX1224
MAX1225
TMS320C54_
SCLK
CNVST
DOUT
CLKR
FSR
DR
Connect the V pin to the ADSP21_ _ _ supply voltage
L
when the MAX1224/MAX1225 are operating with a sup-
ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
CLOCK
CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
CNVST
SCLK
DOUT
1
1
D0
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 17. DSP Interface—Continuous Conversion
______________________________________________________________________________________ 15
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
CNVST
SCLK
DOUT
1
1
0
0
0
0
0
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GꢁD, separate from the logic
ground. Connect all other analog grounds and DGꢁD
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
V
L
VDDINT
TCLK
RCLK
TFS
MAX1224
MAX1225
SCLK
ADSP21_ _ _
CNVST
DOUT
RFS
DR
High-frequency noise in the V
power supply can
DD
affect the ADC’s high-speed comparator. ꢀypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Figure 19. Interfacing to the ADSP21_ _ _
Definitions
Integral Nonlinearity
Integral nonlinearity (IꢁL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1224/MAX1225 are mea-
sured using the end-points method.
SUPPLIES
GND
V
L
10µF
10µF
0.1µF
0.1µF
Differential Nonlinearity
Differential nonlinearity (DꢁL) is the difference between
an actual step width and the ideal value of 1 LSꢀ. A DꢁL
error specification of 1 LSꢀ or less guarantees no missing
codes and a monotonic transfer function.
V
V
L
DD
GND RGND
DGND
V
L
DIGITAL
CIRCUITRY
MAX1224
MAX1225
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Figure 20. Power-Supply Grounding Condition
Aperture Delay
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards are not recommended. ꢀoard layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Aperture delay (t ) is the time defined between the
AD
falling edge of CꢁVST and the instant when an actual
sample is taken.
16 ______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
where V is the fundamental amplitude, and V
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SꢁR) is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The theoretical minimum analog-to-
digital noise is caused by quantization error, and results
directly from the ADC’s resolution (ꢁ bits):
1
2
through V are the amplitudes of the 2nd- through 5th-
5
order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
SꢁR = (6.02 x ꢁ + 1.76)dꢀ
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the
input signal amplitude attenuates by 3dꢀ for a full-scale
input.
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SꢁR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the sig-
nal-to-noise plus distortion (SIꢁAD) is equal to 68dꢀ.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SIꢁAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
Intermodulation Distortion (IMD)
Any device with nonlinearities creates distortion prod-
ucts when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the ꢁyquist frequency rela-
tive to the total input power of the two input tones, f1
and f2. The individual input tone levels are at -7dꢀFS.
The intermodulation products are as follows:
SIꢁAD(dꢀ) = 20 x log (Signal
/ ꢁoise
)
RMS
RMS
Effective Number of Bits
Effective number of bits (EꢁOꢀ) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the EꢁOꢀ as follows:
• 2nd-order intermodulation products (IM2): f + f ,
1
2
f - f
2
1
• 3rd-order intermodulation products (IM3): 2f - f ,
1
2
(SIꢁAD − 1.76)
EꢁOꢀ =
2f - f , 2f + f , 2f + f
1
2
1
1
2
2
6.02
• 4th-order intermodulation products (IM4): 3f - f ,
1
2
3f - f , 3f + f , 3f + f
1
2
1
1
2
2
• 5th-order intermodulation products (IM5): 3f - 2f ,
1
2
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
3f - 2f , 3f + 2f , 3f + 2f
1
2
1
1
2
2
Chip Information
TRAꢁSISTOR COUꢁT: 13,016
PROCESS: ꢀiCMOS
2
2
2
2
V
+ V + V + V
3 4 5
2
THD = 20 x log
V
1
______________________________________________________________________________________ 17
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
1
C
21-0139
2
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
2
C
21-0139
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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