MAX12554ETL/GG8 [MAXIM]
ADC, Proprietary Method,;
| 型号： | MAX12554ETL/GG8 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Proprietary Method, 转换器 |
| 文件： | 总28页 (文件大小：1052K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3440; Rev 0; 10/04
14-Bit, 80Msps, 3.3V ADC
General Description
Features
♦ Direct IF Sampling Up to 400MHz
The MAX12554 is a 3.3V, 14-bit, 80Msps analog-to-digi-
tal converter (ADC) featuring a fully differential wideband
track-and-hold (T/H) input amplifier, driving a low-noise
internal quantizer. The analog input stage accepts sin-
gle-ended or differential signals. The MAX12554 is opti-
mized for high dynamic performance, low power, and
small size. Excellent dynamic performance is maintained
from baseband to input frequencies of 175MHz and
beyond, making the MAX12554 ideal for intermediate-
frequency (IF) sampling applications.
♦ Excellent Dynamic Performance
72.4dB/70.9dB SNR at f = 3MHz/175MHz
IN
86.2dBc/82.5dBc SFDR at f = 3MHz/175MHz
IN
♦ Low Noise Floor: -74.8dBFS
♦ 3.3V Low-Power Operation
396mW (Single-Ended Clock Mode)
429mW (Differential Clock Mode)
300µW (Power-Down Mode)
Powered from a single 3.3V supply, the MAX12554 con-
sumes only 429mW while delivering a typical 70.9dB
signal-to-noise ratio (SNR) performance at a 175MHz
input frequency. In addition to low operating power, the
MAX12554 features a 300µW power-down mode to
conserve power during idle periods.
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Full-Scale Analog Input Range
0.35V to 1.10V
♦ Common-Mode Reference
A flexible reference structure allows the MAX12554 to use
the internal 2.048V bandgap reference or accept an
externally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from 0.35V to 1.10V. The MAX12554 provides a com-
mon-mode reference to simplify design and reduce exter-
nal component count in differential analog input circuits.
The MAX12554 supports either a single-ended or differ-
ential input clock. Wide variations in the clock duty
cycle are compensated with the ADC’s internal duty-
cycle equalizer (DCE).
ADC conversion results are available through a 14-bit,
parallel, CMOS-compatible output bus. The digital out-
put format is pin selectable to be either two’s comple-
ment or Gray code. A data-valid indicator eliminates
external components that are normally required for reli-
able digital interfacing. A separate digital power input
accepts a wide 1.7V to 3.6V supply, allowing the
MAX12554 to interface with various logic levels.
♦ CMOS-Compatible Outputs in Two’s Complement
or Gray Code
♦ Data-Valid Indicator Simplifies Digital Interface
♦ Data Out-of-Range Indicator
♦ Miniature, 6mm x 6mm x 0.8mm 40-Pin Thin QFN
Package with Exposed Paddle
♦ Evaluation Kit Available (Order MAX12555EVKIT)
Ordering Information
PART*
PIN-PACKAGE
40 Thin QFN
40 Thin QFN
PKG CODE
T4066-3
MAX12554ETL
MAX12554ETL+
T4066-3
+Denotes lead-free package.
*All devices specified over the -40°C to +85°C operating range.
The MAX12554 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to
+85°C) temperature range.
See the Pin-Compatible Versions table for a complete
family of 14-bit and 12-bit high-speed ADCs.
Pin-Compatible Versions
SAMPLING
RESOLUTION
(BITS)
TARGET
RATE
(Msps)
PART
APPLICATION
MAX12555
MAX12554
MAX12553
MAX19538
MAX1209
MAX1211
MAX1208
MAX1207
MAX1206
95
80
65
95
80
65
80
65
40
14
14
14
12
12
12
12
12
12
IF/Baseband
IF/Baseband
IF/Baseband
IF/Baseband
IF
Applications
IF and Baseband Communication Receivers
Cellular, Point-to-Point Microwave, HFC, WLAN
Medical Imaging Including Positron Emission
Tomography (PET)
IF
Video Imaging
Baseband
Baseband
Baseband
Portable Instrumentation
Low-Power Data Acquisition
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
14-Bit, 80Msps, 3.3V ADC
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND...........................................................-0.3V to +3.6V
Continuous Power Dissipation (T = +70°C)
A
OV
to GND........-0.3V to the lower of (V
+ 0.3V) and +3.6V
+ 0.3V) and +3.6V
40-Pin Thin QFN 6mm x 6mm x 0.8mm
DD
DD
DD
INP, INN to GND ...-0.3V to the lower of (V
REFIN, REFOUT, REFP, REFN, COM
to GND................-0.3V to the lower of (V
CLKP, CLKN, CLKTYP, G/T, DCE,
(derated 26.3mW/°C above +70°C)........................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
+ 0.3V) and +3.6V
+ 0.3V) and +3.6V
DD
DD
PD to GND ........-0.3V to the lower of (V
D13–D0, DAV, DOR to GND....................-0.3V to (OV
+ 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle, 1.4V square wave), T = -40°C to +85°C, unless otherwise noted. Typical values are at
P-P A
CLK
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 2)
Resolution
14
Bits
LSB
Integral Nonlinearity
INL
f
f
= 3MHz (Note 3)
2.4
0.5
4.9
IN
= 3MHz, no missing codes over
IN
Differential Nonlinearity
DNL
-1
+1.3
LSB
temperature (Note 4)
Offset Error
V
V
= 2.048V
= 2.048V
0.1
0.5
0.72
4.9
%FS
%FS
REFIN
REFIN
Gain Error
ANALOG INPUT (INP, INN)
Differential Input Voltage Range
Common-Mode Input Voltage
V
Differential or single-ended inputs
1.024
V
V
DIFF
V
/ 2
DD
2
C
Fixed capacitance to ground
Switched capacitance
PAR
Input Capacitance
(Figure 3)
pF
C
4.5
SAMPLE
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
f
80
MHz
MHz
CLK
5
Clock
cycles
Data Latency
Figure 6
8.0
DYNAMIC CHARACTERISTICS (Differential Inputs) (Note 2)
Small-Signal Noise Floor
SSNF
Input at less than -35dBFS
-74.8
72.4
72.0
71.9
70.9
72.1
71.7
71.6
70.3
dBFS
dB
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 3MHz at -0.5dBFS (Note 5)
= 40MHz at -0.5dBFS
69.0
Signal-to-Noise Ratio
SNR
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS (Note 5)
= 3MHz at -0.5dBFS (Note 5)
= 40MHz at -0.5dBFS
68.0
68.9
Signal-to-Noise and Distortion
SINAD
dB
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS (Note 5)
66.2
2
_______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle, 1.4V square wave), T = -40°C to +85°C, unless otherwise noted. Typical values are at
P-P A
CLK
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
= 3MHz at -0.5dBFS (Note 5)
= 40MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS (Note 5)
= 3MHz at -0.5dBFS
MIN
TYP
86.2
84.6
85.4
82.5
-84.8
-84.0
-82.6
-79.4
-91
MAX
UNITS
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
76.5
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Spurious-Free Dynamic Range
Total Harmonic Distortion
Second Harmonic
SFDR
dBc
69.0
-75.9
-69.0
= 40MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS
= 3MHz at -0.5dBFS
THD
HD2
HD3
IMD
IM3
dBc
dBc
dBc
dBc
dBc
= 40MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS
= 3MHz at -0.5dBFS
-91
-86
-85
-89
= 40MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS
-85
Third Harmonic
-88
-85
f
f
= 68.5MHz at -7dBFS
= 71.5MHz at -7dBFS
IN1
IN2
-83
-80
-87
-84
84
Intermodulation Distortion
Third-Order Intermodulation
f
f
= 172.5MHz at -7dBFS
= 177.5MHz at -7dBFS
IN1
IN2
f
f
= 68.5MHz at -7dBFS
= 71.5MHz at -7dBFS
IN1
IN2
f
f
= 172.5MHz at -7dBFS
= 177.5MHz at -7dBFS
IN1
IN2
f
f
= 68.5MHz at -7dBFS
= 71.5MHz at -7dBFS
IN1
IN2
Two-Tone Spurious-Free
Dynamic Range
SFDR
dBc
ns
TT
f
f
= 172.5MHz at -7dBFS
= 177.5MHz at -7dBFS
IN1
80
IN2
Aperture Delay
Aperture Jitter
Output Noise
t
Figure 4
1.2
AD
t
AJ
Figure 4
<0.2
1.05
ps
RMS
n
INP = INN = COM
LSB
RMS
OUT
Clock
cycles
Overdrive Recovery Time
10% beyond full scale
1
_______________________________________________________________________________________
3
14-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle, 1.4V square wave), T = -40°C to +85°C, unless otherwise noted. Typical values are at
P-P A
CLK
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
, and V are generated internally)
COM
MIN
TYP
MAX
UNITS
INTERNAL REFERENCE (REFIN = REFOUT; V
, V
REFP REFN
REFOUT Output Voltage
COM Output Voltage
V
1.979
2.048
1.65
2.068
V
V
REFOUT
V
V
V
/ 2
DD
COM
Differential-Reference Output
Voltage
V
= V
- V
= V x 3/4
REFIN
1.536
V
REF
REF
REFP
REFN
REFOUT Load Regulation
-1.0mA < I
< +0.1mA
35
+50
0.24
2.1
mV/mA
ppm/°C
REFOUT
REFOUT Temperature Coefficient
TC
REF
Short to V —sinking
DD
REFOUT Short-Circuit Current
mA
Short to GND—sourcing
BUFFERED EXTERNAL REFERENCE (REFIN driven externally; V
= 2.048V, V
, V
, and V
are generated internally)
REFIN
REFP REFN
COM
REFIN Input Voltage
REFP Output Voltage
REFN Output Voltage
COM Output Voltage
V
2.048
V
V
V
V
REFIN
V
(V / 2) + (V
x 3/8)
2.418
0.882
1.65
REFP
DD
REFIN
V
(V / 2) - (V
DD
x 3/8)
REFN
REFIN
V
V
/ 2
DD
1.60
1.70
COM
Differential-Reference Output
Voltage
V
V
= V
- V
= V x 3/4
REFIN
1.462
1.595
V
REF
REF
REFP
REFN
Differential-Reference
Temperature Coefficient
25
ppm/°C
REFIN Input Resistance
>50
MΩ
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; V
, V
, and V
are applied externally)
REFP REFN
COM
COM Input Voltage
REFP Input Voltage
REFN Input Voltage
V
V
V
V
/2
DD
1.65
0.768
-0.768
V
V
V
COM
- V
REFP
REFN
COM
- V
COM
Differential-Reference Input
Voltage
V
V
= V
- V
= V x 3/4
REFIN
1.536
V
REF
REF
REFP
REFN
REFP Sink Current
I
V
V
V
= 2.418V
= 0.882V
= 1.650V
1.2
0.85
0.85
13
mA
mA
mA
pF
REFP
REFP
REFN
COM
REFN Source Current
COM Sink Current
I
REFN
I
COM
REFP, REFN Capacitance
COM Capacitance
6
pF
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold
0.8 x
V
CLKTYP = GND, CLKN = GND
CLKTYP = GND, CLKN = GND
CLKTYP = high
V
V
IH
V
DD
Single-Ended Input Low
Threshold
0.2 x
V
IL
V
DD
Minimum Differential Input
Voltage Swing
0.2
V
P-P
4
_______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle, 1.4V square wave), T = -40°C to +85°C, unless otherwise noted. Typical values are at
P-P A
CLK
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
CLKTYP = high
Figure 5
MIN
TYP
MAX
UNITS
Differential Input Common-Mode
Voltage
V
/ 2
V
DD
Input Resistance
R
C
5
2
kΩ
CLK
Input Capacitance
pF
CLK
T
DIGITAL INPUTS (CLKTYP, G/ , PD)
0.8 x
Input High Threshold
V
V
V
IH
OV
DD
0.2 x
OV
Input Low Threshold
V
IL
DD
V
V
= OV
= 0
5
5
IH
IL
DD
Input Leakage Current
Input Capacitance
µA
pF
C
5
DIN
DIGITAL OUTPUTS (D13–D0, DAV, DOR)
D13–D0, DOR, I
= 200µA
0.2
0.2
SINK
Output-Voltage Low
V
V
V
OL
DAV, I
= 600µA
SINK
OV
0.2
-
DD
D13–D0, DOR, I
= 200µA
SOURCE
Output-Voltage High
V
OH
OV
0.2
-
DD
DAV, I
= 600µA
SOURCE
Tri-State Leakage Current
I
(Note 6)
(Note 6)
(Note 6)
5
µA
pF
pF
LEAK
D13–D0, DOR Tri-State Output
Capacitance
C
3
6
OUT
DAV
DAV Tri-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
C
V
3.15
1.7
3.3
1.8
3.60
V
V
DD
V
+
DD
0.3V
Digital Output Supply Voltage
OV
DD
Normal operating mode,
= 175MHz at -0.5dBFS,
f
IN
120
CLKTYP = GND, single-ended clock
Analog Supply Current
I
mA
VDD
Normal operating mode,
f
= 175MHz at -0.5dBFS,
130
0.1
145
IN
CLKTYP = OV
differential clock
DD,
Power-down mode clock idle, PD = OV
DD
_______________________________________________________________________________________
5
14-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
= 80MHz (50% duty cycle, 1.4V square wave), T = -40°C to +85°C, unless otherwise noted. Typical values are at
P-P A
CLK
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Normal operating mode,
f
IN
= 175MHz at -0.5dBFS,
396
CLKTYP = GND, single-ended clock
Analog Power Dissipation
P
mW
DISS
Normal operating mode,
f
= 175MHz at -0.5dBFS,
429
0.3
8.6
8
479
IN
CLKTYP = OV , differential clock
DD
Power-down mode clock idle, PD = OV
DD
DD
Normal operating mode,
f
IN
= 175MHz at -0.5dBFS,
mA
µA
Digital Output Supply Current
I
OVDD
OV
= 1.8V, C ≈ 5pF
L
DD
Power-down mode clock idle, PD = OV
TIMING CHARACTERISTICS (Figure 6)
Clock Pulse-Width High
Clock Pulse-Width Low
Data-Valid Delay
t
6.2
6.2
5.2
ns
ns
ns
CH
t
CL
t
C = 5pF (Note 7)
L
DAV
Data Setup Time Before Rising
Edge of DAV
t
C = 5pF (Note 3, Note 7)
5.5
5.5
ns
SETUP
L
Data Hold Time After Rising Edge
of DAV
t
C = 5pF (Note 3, Note 7)
L
ns
HOLD
Wake-Up Time from Power-Down
t
V
= 2.048V
10
ms
WAKE
REFIN
Note 1: Specifications ≥+25°C guaranteed by production test; <+25°C guaranteed by design and characterization.
Note 2: See definitions in the Parameter Definitions section at the end of this data sheet.
Note 3: Guaranteed by design and characterization.
Note 4: Specifications guaranteed by design and characterization. Devices tested to ensure no missing codes during production
test.
Note 5: Due to test-equipment-jitter limitations at 175MHz, 0.15% of the spectrum on each side of the fundamental is excluded from
the spectral analysis.
Note 6: During power-down, D13–D0, DOR, and DAV are high impedance.
Note 7: Digital outputs settle to V or V .
IH
IL
6
_______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
≈ 80MHz (50% duty cycle, 1.4V
square wave), T = +25°C, unless otherwise noted.)
A
P-P
CLK
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
f
A
= 80MHz
= 39.89257813MHz
= -0.4dBFS
SNR = 73.00dB
SINAD = 72.02dB
THD = -78.9dBc
SFDR = 79.6dBc
f
f
A
= 80MHz
= 69.87304688MHz
= -0.6dBFS
CLK
IN
IN
CLK
IN
IN
f
f
A
= 80MHz
= 2.99804688MHz
= -0.5dBFS
CLK
IN
IN
-10
-20
-30
SNR = 73.49dB
SINAD = 73.26dB
THD = -86.2dBc
SFDR = 89.2dBc
SNR = 72.65dB
SINAD = 72.23dB
THD = -82.6dBc
SFDR = 84.6dBc
-40
-50
-60
HD3
-70
HD2 HD3
HD3
HD2
-80
-90
-100
-110
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
0
0
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
f
A
= 80MHz
= 175.1074219MHz
= -0.5dBFS
CLK
IN
IN
f
f
A
= 80MHz
= 225.1074219MHz
= -0.5dBFS
f
f
A
= 80MHz
= 68.49121MHz
= -7.0dBFS
CLK
IN
IN
CLK
IN1
IN1
f
IN2
f
IN1
SNR = 71.17dB
SINAD = 70.50dB
THD = -78.9dBc
SFDR = 80.7dBc
SNR = 70.37dB
SINAD = 69.83dB
THD = -79.2dBc
SFDR = 83.6dBc
f
= 71.48926MHz
IN2
A
IN2
= -7.0dBFS
SFDR = 84.6dBc
TT
IMD = -81.5dBc
IM3 = -82.5dBc
2 x f - f
2 x f + f
IN2 IN1
IN2 IN1
HD5
HD2
HD5
HD2 HD3
2 x f - f
IN1 IN2
f + f
IN1 IN2
2 x f + f
IN1 IN2
HD3
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
3
2
1.0
f = 80.0017MHz
CLK
f = 172.4695MHz
IN1
0.8
0.6
f
IN1
A
= -7.0dBFS
IN1
f
= 177.4696MHz
IN2
0.4
A
= -7.0dBFS
TT
IN2
1
f
IN2
SFDR = 80.3dBc
0.2
IMD = -80.7dBc
IM3 = -95.3dBc
0
0
3 x f + 2 x f
IN1
IN2
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
f + f
IN1 IN2
0
4096
8192
12288
16384
0
4096
8192
12288
16384
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
_______________________________________________________________________________________
7
14-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics (continued)
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
≈ 80MHz (50% duty cycle, 1.4V
square wave), T = +25°C, unless otherwise noted.)
A
P-P
CLK
SNR, SINAD
vs. SAMPLING RATE
SFDR, -THD
vs. SAMPLING RATE
600
POWER DISSIPATION
vs. SAMPLING RATE
76
100
DIFFERENTIAL CLOCK
f = 70MHz
IN
C ≈ 5pF
L
f
= 70MHz
f
= 70MHz
IN
IN
74
72
70
68
66
64
62
60
95
90
85
80
75
70
65
60
550
500
450
400
350
300
250
200
ANALOG + DIGITAL POWER
ANALOG POWER
SNR
SINAD
SFDR
-THD
25
45
65
85
(MHz)
105
125
25
45
65
85
(MHz)
105
125
25
45
65
85
(MHz)
105
125
f
f
f
CLK
CLK
CLK
SNR, SINAD
vs. SAMPLING RATE
SFDR, -THD
vs. SAMPLING RATE
POWER DISSIPATION
vs. SAMPLING RATE
76
74
72
70
68
66
64
62
60
100
95
90
85
80
75
70
65
60
600
550
500
450
400
350
300
250
200
f
= 175MHz
f
= 175MHz
IN
DIFFERENTIAL CLOCK
= 175MHz
C ≈ 5pF
L
IN
f
IN
SNR
SINAD
SFDR
-THD
ANALOG + DIGITAL POWER
ANALOG POWER
25
45
65
85
(MHz)
105
125
25
45
65
85
(MHz)
105
125
25
45
65
85
(MHz)
105
125
f
f
CLK
CLK
f
CLK
SFDR, -THD
vs. ANALOG INPUT FREQUENCY
POWER DISSIPATION
vs. ANALOG INPUT FREQUENCY
SNR, SINAD
vs. ANALOG INPUT FREQUENCY
100
95
90
85
80
75
70
65
60
600
550
500
450
400
350
300
250
200
76
74
72
70
68
66
64
62
60
DIFFERENTIAL CLOCK
C ≈ 5pF
L
SFDR
-THD
ANALOG + DIGITAL POWER
ANALOG POWER
SNR
SINAD
0
50 100 150 200 250 300 350 400
ANALOG INPUT FREQUENCY (MHz)
0
50 100 150 200 250 300 350 400
ANALOG INPUT FREQUENCY (MHz)
0
50 100 150 200 250 300 350 400
ANALOG INPUT FREQUENCY (MHz)
8
_______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics (continued)
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
≈ 80MHz (50% duty cycle, 1.4V
square wave), T = +25°C, unless otherwise noted.)
A
P-P
CLK
SNR, SINAD
vs. ANALOG INPUT AMPLITUDE
SFDR, -THD
vs. ANALOG INPUT AMPLITUDE
POWER DISSIPATION
vs. ANALOG INPUT AMPLITUDE
76
71
66
61
56
51
46
41
36
31
26
90
85
80
75
70
65
60
55
50
600
550
500
450
400
350
300
250
200
f
= 175MHz
IN
DIFFERENTIAL CLOCK
f
= 175MHz
IN
f
= 175MHz
IN
C ≈ 5pF
L
SNR
SINAD
ANALOG + DIGITAL POWER
ANALOG POWER
SFDR
-THD
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
SNR, SINAD
vs. ANALOG SUPPLY VOLTAGE
SFDR, -THD
vs. ANALOG SUPPLY VOLTAGE
POWER DISSIPATION
vs. ANALOG SUPPLY VOLTAGE
76
74
72
70
68
66
64
62
60
100
95
90
85
80
75
70
65
60
600
550
500
450
400
350
300
250
200
f
= 175MHz
f
= 175MHz
DIFFERENTIAL CLOCK
IN
IN
f
= 175MHz
IN
C ≈ 5pF
L
SFDR
-THD
SNR
SINAD
ANALOG + DIGITAL POWER
ANALOG POWER
2.8
3.0
3.2
3.4
3.6
2.8
3.0
3.2
3.4
3.6
2.8
3.0 3.2
AV (V)
3.4
3.6
AV (V)
DD
AV (V)
DD
DD
SNR, SINAD
vs. DIGITAL SUPPLY VOLTAGE
SFDR, -THD
vs. DIGITAL SUPPLY VOLTAGE
POWER DISSIPATION
vs. DIGITAL SUPPLY VOLTAGE
76
74
72
70
68
66
64
62
60
100
95
90
85
80
75
70
65
60
600
550
500
450
400
350
300
250
200
f
= 175MHz
f
= 175MHz
IN
IN
DIFFERENTIAL CLOCK
f
= 175MHz
IN
C ≈ 5pF
L
SNR
SINAD
SFDR
-THD
ANALOG + DIGITAL POWER
ANALOG POWER
1.4
1.8
2.2
2.6
OV (V)
3.0
3.4
3.8
1.4
1.8
2.2
2.6
OV (V)
3.0
3.4
3.8
1.4
1.8 2.2 2.6
OV (V)
3.0
3.4
3.8
DD
DD
DD
_______________________________________________________________________________________
9
14-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics (continued)
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
≈ 80MHz (50% duty cycle, 1.4V
square wave), T = +25°C, unless otherwise noted.)
A
P-P
CLK
POWER DISSIPATION
vs. TEMPERATURE
SNR, SINAD vs. TEMPERATURE
SFDR, -THD vs. TEMPERATURE
600
72
71
70
69
68
67
66
65
64
63
62
100
95
90
85
80
75
70
65
60
f
= 175MHz
DIFFERENTIAL CLOCK
= 175MHz
IN
f
= 175MHz
IN
f
550
500
450
400
350
300
250
200
IN
L
C ≈ 5pF
SNR
SINAD
ANALOG + DIGITAL POWER
ANALOG POWER
SFDR
-THD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
0.5
0.4
2.0
V
= 2.048V
V
= 2.048V
REFIN
REFIN
1.5
1.0
0.3
0.2
0.5
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.5
-1.0
-1.5
-2.0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
10 ______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
Typical Operating Characteristics (continued)
(V = 3.3V, OV = 1.8V, GND = 0, REFIN = REFOUT (internal reference), V = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
DD
DD
IN
G/T = low, f
≈ 80MHz (50% duty cycle, 1.4V
square wave), T = +25°C, unless otherwise noted.)
A
P-P
CLK
REFERENCE OUTPUT VOLTAGE
LOAD REGULATION
REFERENCE OUTPUT VOLTAGE
SHORT-CIRCUIT PERFORMANCE
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
2.05
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
3.5
2.039
2.037
2.035
2.033
2.031
2.029
3.0
2.5
2.0
1.5
1.0
0.5
0
+85°C
+85°C
+25°C
-40°C
-40°C
+25°C
1.95
-2.0
-1.5
-1.0
-0.5
0
0.5
-3.0
-2.0
-1.0
0
1.0
-40
-15
10
35
60
85
I
SINK CURRENT (mA)
I
REFOUT
SINK CURRENT (mA)
REFOUT
TEMPERATURE (°C)
REFP, COM, REFN
LOAD REGULATION
REFP, COM, REFN
SHORT-CIRCUIT PERFORMACE
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
REFP
V
COM
V
REFP
V
V
REFN
COM
V
REFN
INTERNAL REFERENCE
MODE AND BUFFERED EXTERNAL
REFERENCE MODE
INTERNAL REFERENCE
MODE AND BUFFERED
EXTERNAL REFERENCE MODE
-2
-1
0
1
2
-8
-4
0
4
8
12
SINK CURRENT (mA)
SINK CURRENT (mA)
______________________________________________________________________________________ 11
14-Bit, 80Msps, 3.3V ADC
Pin Description
PIN
NAME
FUNCTION
Positive Reference I/O. The full-scale analog input range is (V
- V
) x 2/3. Bypass REFP to
REFP
REFN
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same
side of the PC board.
1
REFP
Negative Reference I/O. The full-scale analog input range is (V
- V
) x 2/3. Bypass REFN to
REFP
REFN
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same
side of the PC board.
2
3
REFN
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to
GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the
opposite side of the PC board and connected to the MAX12554 through a via.
COM
GND
4, 7, 16,
35
Ground. Connect all ground pins and EP together.
5
6
INP
INN
Positive Analog Input
Negative Analog Input
Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
8
DCE
Connect DCE high (OV
or V ) to enable the internal duty-cycle equalizer.
DD
DD
Negative Clock Input. In differential clock input mode (CLKTYP = OV
or V ), connect the differential
DD
DD
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
9
CLKN
Positive Clock Input. In differential clock input mode (CLKTYP = OV
or V ), connect the differential
DD
DD
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
10
CLKP
Clock-Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect
11
CLKTYP
CLKTYP to OV
or V
to define the differential clock input.
DD
DD
Analog Power Input. Connect V
capacitor combination of ≥2.2µF and 0.1µF. Connect all V
to a 3.15V to 3.60V power supply. Bypass V
to GND with a parallel
DD
DD
12–15, 36
17, 34
V
DD
pins to the same potential.
DD
Output-Driver Power Input. Connect OV
parallel capacitor combination of ≥2.2µF and 0.1µF.
to a 1.7V to V
power supply. Bypass OV
to GND with a
DD
DD
DD
OV
DD
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog
input is within its full-scale range (Figure 6).
18
DOR
19
20
21
22
23
24
25
26
27
D13
D12
D11
D10
D9
CMOS Digital Output Bit 13 (MSB)
CMOS Digital Output Bit 12
CMOS Digital Output Bit 11
CMOS Digital Output Bit 10
CMOS Digital Output Bit 9
CMOS Digital Output Bit 8
CMOS Digital Output Bit 7
CMOS Digital Output Bit 6
CMOS Digital Output Bit 5
D8
D7
D6
D5
12 ______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
Pin Description (continued)
PIN
28
29
30
31
32
NAME
D4
FUNCTION
CMOS Digital Output Bit 4
CMOS Digital Output Bit 3
CMOS Digital Output Bit 2
CMOS Digital Output Bit 1
CMOS Digital Output Bit 0 (LSB)
D3
D2
D1
D0
Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for
any input clock duty-cycle variations. DAV is typically used to latch the MAX12554 output data into an
external back-end digital circuit.
33
37
38
DAV
PD
Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN
or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a
≥0.1µF capacitor.
REFOUT
Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
39
40
—
REFIN
G/T
GND with a ≥0.1µF capacitor. In these modes, V
- V
= V
x 3/4. For unbuffered external
REFIN
REFP
REFN
reference mode operation, connect REFIN to GND.
Output-Format-Select Input. Connect G/T to GND for the two’s-complement digital output format.
Connect G/T to OV or V for the Gray code digital output format.
DD
DD
Exposed Paddle. The MAX12554 relies on the exposed paddle connection for a low-inductance ground
connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the
top-side PC board ground plane to the bottom-side PC board ground plane.
EP
+
MAX12554
T/H
Σ
−
FLASH
DAC
ADC
INP
INN
STAGE 10
END OF PIPE
STAGE 1
STAGE 2
STAGE 9
T/H
DIGITAL ERROR CORRECTION
D13–D0
OUTPUT
DRIVERS
D13–D0
Figure 1. Pipeline Architecture—Stage Blocks
______________________________________________________________________________________ 13
14-Bit, 80Msps, 3.3V ADC
V
DD
BOND WIRE
INDUCTANCE
1.5nH
CLOCK
GENERATOR
AND
DUTY-CYCLE
EQUALIZER
CLKP
CLKN
MAX12554
V
MAX12554
DD
GND
DCE
INP
CLKTYP
*C
SAMPLE
C
PAR
OV
DD
4.5pF
2pF
D13–D0
DAV
14-BIT
PIPELINE
ADC
INP
INN
OUTPUT
DRIVERS
T/H
DEC
DOR
V
DD
BOND WIRE
INDUCTANCE
1.5nH
G/T
PD
REFOUT
REFIN
REFP
INN
*C
4.5pF
C
2pF
REFERENCE
SYSTEM
POWER CONTROL
AND
BIAS CIRCUITS
SAMPLE
PAR
COM
REFN
SAMPLING
CLOCK
Figure 2. Simplified Functional Diagram
Detailed Description
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS: R
1
The MAX12554 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output, the total clock-cycle latency is 8.0
clock cycles.
=
SAMPLE
f
x C
SAMPLE
CLK
Figure 3. Simplified Input T/H Circuit
capacitors must be charged to one-half LSB accuracy
within one-half of a clock cycle.
The analog input of the MAX12554 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to mid-
Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12554 functional diagram.
supply (V
/ 2). The MAX12554 provides the optimum
DD
common-mode voltage of V
/ 2 through the COM
DD
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 10, 11, and 12.
Input Track-and-Hold (T/H) Circuit
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high ana-
log input frequencies of 175MHz and beyond and sup-
Reference Output (REFOUT)
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX12554. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX12554 or when PD transitions from
high to low. REFOUT has approximately 17kΩ to GND
when the MAX12554 is in power-down.
ports a common-mode input voltage of V / 2 0.5V.
DD
The MAX12554 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure 3) allowing
the analog input signal to be stored as a charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and open (hold) when
the sampling clock is low (Figure 4). The analog input
signal source must be capable of providing the dynam-
ic current necessary to charge and discharge the sam-
pling capacitors. To avoid signal degradation, these
The internal bandgap reference and its buffer generate
V
to be 2.048V. The reference temperature coeffi-
REFOUT
cient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.
14 ______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
CLKP
CLKN
t
AD
ANALOG
INPUT
t
AJ
SAMPLED
DATA
T/H
TRACK
HOLD
TRACK
HOLD
TRACK
HOLD
TRACK
HOLD
Figure 4. T/H Aperture Timing
REFOUT sources up to 1.0mA and sinks up to 0.1mA
for external circuits with a load regulation of 35mV/mA.
resistive divider, use resistances ≥10kΩ to avoid load-
ing REFOUT.
Short-circuit protection limits I
to a 2.1mA
REFOUT
Buffered external reference mode is virtually identical to
internal reference mode except that the reference
source is derived from an external reference and not
the MAX12554 REFOUT. In buffered external reference
mode, apply a stable 0.7V to 2.2V source at REFIN. In
this mode, COM, REFP, and REFN are low-impedance
source current when shorted to GND and a 0.24mA
sink current when shorted to V
.
DD
Analog Inputs and Reference
Configurations
The MAX12554 full-scale analog input range is adjustable
outputs with V
= V
DD
/ 2, V
= V
/ 2 + V
COM
DD
/ 2 - V
REFP
DD REFIN
x 3/8.
from 0.35V to 1.10V with a V
/ 2 0.5V common-
DD
x 3/8, and V
= V
REFN
REFIN
mode input range. The MAX12554 provides three modes
To operate the MAX12554 in unbuffered external refer-
ence mode, connect REFIN to GND. Connecting REFIN
to GND deactivates the on-chip reference buffers for
COM, REFP, and REFN. With the respective buffers
deactivated, COM, REFP, and REFN become high-
impedance inputs and must be driven through sepa-
of reference operation. The voltage at REFIN (V
sets the reference operation mode (Table 1).
)
REFIN
To operate the MAX12554 with the internal reference,
connect REFOUT to REFIN either with a direct short or
through a resistive divider. In this mode, COM, REFP,
and REFN are low-impedance outputs with V
=
=
COM
x 3/8, and V
REFIN REFN
rate, external reference sources. Drive V
to V
/ 2
COM
DD
V
V
/ 2, V
= V
/ 2 + V
DD
DD
REFP
DD
5%, and drive REFP and REFN so V
= (V
+
COM
REFP
/ 2 - V
x 3/8. The REFIN input impedance is
REFIN
V
) / 2. The full-scale analog input range is (V
REFN
- V
REFP
very large (>50MΩ). When driving REFIN through a
) x 2/3.
REFN
Table 1. Reference Modes
V
REFERENCE MODE
Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider.
The full-scale analog input range is / 2:
REFIN
V
REFIN
35% V
to 100%
REFOUT
V
V
V
= V / 2
DD
COM
REFP
REFN
V
REFOUT
= V / 2 + V
x 3/8
x 3/8
DD
REFIN
REFIN
= V / 2 - V
DD
Buffered External Reference Mode. Apply an external 0.7V to 2.2V reference voltage to REFIN.
The full-scale analog input range is / 2:
V
REFIN
0.7V to 2.2V
<0.4V
V
V
V
= V / 2
DD
COM
REFP
REFN
= V / 2 + V
x 3/8
x 3/8
DD
REFIN
= V / 2 - V
DD
REFIN
Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources.
The full-scale analog input range is (V - V ) x 2/3.
REFP
REFN
______________________________________________________________________________________ 15
14-Bit, 80Msps, 3.3V ADC
All three modes of reference operation require the
same bypass capacitor combinations. Bypass COM
with a 2.2µF capacitor to GND. Bypass REFP and
REFN each with a 0.1µF capacitor to GND. Bypass
REFP to REFN with a 1µF capacitor in parallel with a
10µF capacitor. Place the 1µF capacitor as close to
the device as possible on the same side of the PC
board. Bypass REFIN and REFOUT to GND with a
0.1µF capacitor.
V
DD
S
1H
MAX12554
10kΩ
For detailed circuit suggestions, see Figure 13 and
Figure 14.
CLKP
10kΩ
Clock Input and Clock Control Lines
(CLKP, CLKN, CLKTYP)
DUTY-CYCLE
EQUALIZER
S
2H
The MAX12554 accepts both differential and single-
ended clock inputs. For single-ended clock input oper-
ation, connect CLKTYP to GND, CLKN to GND, and
drive CLKP with the external single-ended clock signal.
For differential clock input operation, connect CLKTYP
S
1L
10kΩ
CLKN
to OV
or V , and drive CLKP and CLKN with the
DD
10kΩ
SWITCHES S AND S ARE OPEN
DURING POWER-DOWN, MAKING
CLKP AND CLKN HIGH IMPEDANCE.
DD
external differential clock signal. To reduce clock jitter,
the external single-ended clock must have sharp falling
edges. Consider the clock input as an analog input and
route it away from any other analog inputs and digital
signal lines.
1_
2_
S
2L
SWITCHES S ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
2_
GND
CLKP and CLKN are high impedance when the
MAX12554 is powered down (Figure 5).
Figure 5. Simplified Clock Input Circuit
Low clock jitter is required for the specified SNR perfor-
mance of the MAX12554. Analog input sampling
occurs on the falling edge of the clock signal, requiring
this edge to have the lowest possible jitter. Jitter limits
the maximum SNR performance of any ADC according
to the following relationship:
Clock Duty-Cycle Equalizer (DCE)
Connect DCE high to enable the clock duty-cycle
equalizer (DCE = OV or V ). Connect DCE low to
disable the clock duty-cycle equalizer (DCE = GND).
With the clock duty-cycle equalizer enabled, the
MAX12554 is insensitive to the duty cycle of the signal
applied to CLKP and CLKN. Duty cycles from 35% to
65% are acceptable with the clock duty-cycle equalizer
enabled.
DD
DD
1
SNR = 20 × log
2 × π f × t
IN
J
where f represents the analog input frequency and t
IN
J
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 70.9dB of SNR with a 175MHz
input frequency, the system must have less than 0.26ps
of clock jitter. In actuality, there are other noise sources
such as thermal noise and quantization noise that con-
tribute to the system noise, requiring the clock jitter to
be less than 0.14ps to obtain the specified 70.9dB of
SNR at 175MHz.
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the
MAX12554 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.
Although not recommended, disabling the clock duty-
cycle equalizer reduces the analog supply current by
1.5mA. With the clock duty-cycle equalizer disabled, the
MAX12554’s dynamic performance varies depending on
the duty cycle of the signal applied to CLKP and CLKN.
16 ______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
N + 4
N + 5
DIFFERENTIAL ANALOG INPUT (INP–INN)
N + 3
N + 6
(V
(V
- V
- V
) x 2/3
) x 2/3
REFP
REFN
N - 3
N - 2
N +2
N + 7
N + 9
N - 1
N
N + 1
N + 8
REFN
REFP
t
AD
CLKN
CLKP
t
CL
t
CH
t
DAV
DAV
t
t
HOLD
SETUP
D0–D11
DOR
N - 3 N - 2 N - 1
8.0 CLOCK-CYCLE DATA LATENCY
N
N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9
t
SETUP
t
HOLD
Figure 6. System Timing Diagram
With the duty-cycle equalizer enabled (DCE = high), the
DAV signal has a fixed pulse width that is independent of
CLKP. In either case, with DCE high or low, output data
at D13–D0 and DOR are valid from 5.5ns before the ris-
ing edge of DAV to 5.5ns after the rising edge of DAV,
and the rising edge of DAV is synchronized to have a
System-Timing Requirements
Figure 6 shows the relationship between the clock, ana-
log inputs, DAV indicator, DOR indicator, and the result-
ing output data. The analog input is sampled on the
falling edge of the clock signal and the resulting data
appears at the digital outputs 8.0 clock cycles later.
5.2ns (t
) delay from the falling edge of CLKP.
DAV
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
cuitry can be latched with the rising edge of the con-
version clock (CLKP-CLKN).
DAV is high impedance when the MAX12554 is in
power-down (PD = high). DAV is capable of sinking
and sourcing 600µA and has three times the drive
strength of D13–D0 and DOR. DAV is typically used to
latch the MAX12554 output data into an external back-
end digital circuit.
Data-Valid Output (DAV)
DAV is a single-ended version of the input clock (CLKP)
Keep the capacitive load on DAV as low as possible
(<25pF) to avoid large digital currents feeding back
into the analog portion of the MAX12554 and degrading
its dynamic performance. An external buffer on DAV
isolates it from heavy capacitive loads. Refer to the
MAX12555 evaluation kit schematic for an example of
DAV driving back-end digital circuitry through an exter-
nal buffer.
with a delay (t ). Output data changes on the falling
DAV
edge of DAV, and DAV rises once output data is valid
(Figure 6).
The state of the duty-cycle equalizer input (DCE)
changes the waveform at DAV. With the duty-cycle
equalizer disabled (DCE = low), the DAV signal is a sin-
gle-ended version of CLKP delayed by 5.2ns (t
).
DAV
______________________________________________________________________________________ 17
14-Bit, 80Msps, 3.3V ADC
Data Out-of-Range Indicator (DOR)
The DOR digital output indicates when the analog input
voltage is out of range. When DOR is high, the analog
input is out of range. When DOR is low, the analog
input is within range. The valid differential input range is
4
3
CODE
10
16384
V
− V
INN
= (V
− V
) ×
×
INP
REFP REFN
for two’s complement (G/T = 0).
from (V
- V
) x 3/4 to (V
- V
) x 3/4.
REFP
REFP
REFN
REFN
where CODE is the decimal equivalent of the digital
10
Signals outside this valid differential range cause DOR
to assert high as shown in Table 2 and Figure 6.
output code as shown in Table 2.
Digital outputs D13–D0 are high impedance when the
MAX12554 is in power-down (PD = high). D13–D0 tran-
sition high 10ns after the rising edge of PD and
become active 10ns after PD’s falling edge.
DOR is synchronized with DAV and transitions along
with the output data D13–D0. There is an 8.0 clock-
cycle latency in the DOR function as is with the output
data (Figure 6).
Keep the capacitive load on the MAX12554 digital out-
puts D13–D0 as low as possible (<15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX12554 and degrading its dynamic perfor-
mance. The addition of external digital buffers on the
digital outputs isolates the MAX12554 from heavy
capacitive loading. To improve the dynamic perfor-
mance of the MAX12554, add 220Ω resistors in series
with the digital outputs close to the MAX12554. Refer to
the MAX12555 evaluation kit schematic for an example
of the digital outputs driving a digital buffer through
220Ω series resistors.
DOR is high impedance when the MAX12554 is in
power-down (PD = high). DOR enters a high-imped-
ance state within 10ns after the rising edge of PD and
becomes active 10ns after PD’s falling edge.
Digital Output Data (D13–D0), Output Format (G/T)
The MAX12554 provides a 14-bit, parallel, tri-state out-
put bus. D13–D0 and DOR update on the falling edge
of DAV and are valid on the rising edge of DAV.
The MAX12554 output data format is either Gray code
or two’s complement, depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is two’s comple-
ment. See Figure 9 for a binary-to-Gray and Gray-to-
binary code-conversion example.
Power-Down Input (PD)
The MAX12554 has two power modes that are con-
trolled with the power-down digital input (PD). With PD
low, the MAX12554 is in normal operating mode. With
PD high, the MAX12554 is in power-down mode.
The following equations, Table 2, Figure 7, and Figure 8
define the relationship between the digital output and
the analog input:
The power-down mode allows the MAX12554 to effi-
ciently use power by transitioning to a low-power state
when conversions are not required. Additionally, the
MAX12554 parallel output bus is high impedance in
power-down mode, allowing other devices on the bus
to be accessed.
4
3
CODE
− 8192
10
V
− V
INN
= (V
− V
) ×
×
INP
REFP REFN
16384
for Gray code (G/T = 1).
18 ______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
______________________________________________________________________________________ 19
14-Bit, 80Msps, 3.3V ADC
V
- V
16384
V
- V
16384
4
3
4
3
REFP
REFN
REFP REFN
1 LSB =
1 LSB =
x
x
(V
REFP
- V ) x 2/3
REFN
(V
REFP
- V
REFN
) x 2/3
(V
REFP
- V ) x 2/3
REFN
(V
REFP
- V
REFN
) x 2/3
0x1FFF
0x1FFE
0x1FFD
0x2000
0x2001
0x2003
0x0001
0x0000
0x3FFF
0x3001
0x3000
0x1000
0x2003
0x2002
0x2001
0x2000
0x0002
0x0003
0x0001
0x0000
-8191 -8189
-1
0
+1
+8189 +8191
-8191 -8189
-1
+1
+8189 +8191
0
DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 7. Two’s-Complement Transfer Function (G/T = 0)
Figure 8. Gray-Code Transfer Function (G/T = 1)
In power-down mode, all internal circuits are off, the
analog supply current reduces to 0.1mA, and the digi-
tal supply current reduces to 0.008mA. The following
list shows the state of the analog inputs and digital out-
puts in power-down mode:
Applications Information
Using Transformer Coupling
In general, the MAX12554 provides better SFDR and
THD performance with fully differential input signals as
opposed to single-ended input drive. In differential
input mode, even-order harmonics are lower as both
inputs are balanced, and each of the ADC inputs only
requires half the signal swing compared to single-
ended input mode.
• INP, INN analog inputs are disconnected from the
internal input amplifier (Figure 3).
• REFOUT has approximately 17kΩ to GND.
• REFP, COM, REFN go high impedance with respect
to V
and GND, but there is an internal 4kΩ resistor
DD
An RF transformer (Figure 10) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX12554
for optimum performance. Connecting the center tap of
between REFP and COM, as well as an internal 4kΩ
resistor between REFN and COM.
• D13–D0, DOR, and DAV go high impedance.
• CLKP, CLKN go high impedance (Figure 5).
the transformer to COM provides a V
/ 2 DC level
DD
shift to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion. The configuration of Figure 10 is good
The wake-up time from power-down mode is dominat-
ed by the time required to charge the capacitors at
REFP, REFN, and COM. In internal reference mode and
buffered external reference mode, the wake-up time is
typically 10ms with the recommended capacitor array
(Figure 13). When operating in unbuffered external ref-
erence mode, the wake-up time is dependent on the
external reference drivers.
for frequencies up to Nyquist (f
/ 2).
CLK
The circuit of Figure 11 converts a single-ended input
signal to fully differential just as Figure 10. However,
Figure 11 utilizes an additional transformer to improve
the common-mode rejection, allowing high-frequency
20 ______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
BINARY-TO-GRAY-CODE CONVERSION
GRAY-TO-BINARY-CODE CONVERSION
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME
AS THE MOST SIGNIFICANT GRAY-CODE BIT.
D13
D11
D7
0
D3
1
D0
0
D13
D11
D7
1
D3
1
D0
0
BIT POSITION
BINARY
BIT POSITION
GRAY CODE
0
0
1
1
0
1
1
1
0
0
1
0
0
0
1
0
1
1 0
1
1
0
0 1
GRAY CODE
BINARY
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
GRAY = BINARY
BINARY
BINARY = BINARY
GRAY
X
X
X
X+1
X
X+1
WHERE
IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
WHERE
IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION.
TABLE BELOW) AND X IS THE BIT POSITION.
GRAY = BINARY
BINARY
BINARY = BINARY GRAY
12
12
12
13
12
13
GRAY = 1
0
BINARY = 0
1
12
12
GRAY = 1
12
BINARY = 1
12
D13
D11
D7
0
D3
1
D0 BIT POSITION
D13
D11
D7
1
D3
1
D0 BIT POSITION
0
1
1
0
0
1
1
0
1
1
1
0
0
1
0
0
BINARY
0
1
1
0
1
1
0
0
1
0
GRAY CODE
BINARY
1
GRAY CODE
0
3) REPEAT STEP 2 UNTIL COMPLETE.
GRAY = BINARY BINARY
3) REPEAT STEP 2 UNTIL COMPLETE.
BINARY = BINARY GRAY
11
11
11
12
11
12
GRAY = 1
1
BINARY = 1
0
11
11
GRAY = 0
11
BINARY = 1
11
D13
D13
D11
D7
D3
1
D0
0
BIT POSITION
BINARY
D11
D7
D3
1
D0
0
BIT POSITION
GRAY CODE
0
1
0
1
1
0
1
1
1
0
0
1
0
0
1
1
1
0
1
1
0
1
0
0
1
0
0
GRAY CODE
0
1
1
BINARY
4) THE FINAL GRAY-CODE CONVERSION IS:
4) THE FINAL GRAY-CODE CONVERSION IS:
D13
D11
D7
0
D3
1
D0
0
BIT POSITION
BINARY
D13
D11
D7
1
D3
1
D0
0
BIT POSITION
GRAY CODE
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
1
0
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
1
1
0
GRAY CODE
0
1
1
0
0
1
0
BINARY
EXCULSIVE OR TRUTH TABLE
A
0
0
1
1
B
0
1
0
1
Y = A
B
0
1
1
0
Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion
______________________________________________________________________________________ 21
14-Bit, 80Msps, 3.3V ADC
MAX4108
V
IN
24.9Ω
0.1µF
24.9Ω
INP
0.1µF
INP
6
5
4
12pF
1
2
3
V
IN
5.6pF
T1
MAX12554
100Ω
MAX12554
N.C.
COM
INN
COM
INN
2.2µF
2.2µF
100Ω
24.9Ω
24.9Ω
MINI-CIRCUITS
TT1-6 OR T1-1T
12pF
5.6pF
Figure 12. Single-Ended, AC-Coupled Input Drive
Figure 10. Transformer-Coupled Input Drive for Input
Frequencies Up to Nyquist
0Ω*
INP
0.1µF
6
5
4
6
5
4
5.6pF
1
2
3
1
2
3
V
IN
75Ω
110Ω
T1
T2
MAX12554
0.5%
0.1%
N.C.
N.C.
N.C.
COM
INN
2.2µF
75Ω
0.5%
110Ω
0.1%
0Ω*
MINI-CIRCUITS
ADT1-1WT
MINI-CIRCUITS
ADT1-1WT
5.6pF
*0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE
RESISTORS TO LIMIT THE BANDWIDTH.
Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
signals beyond the Nyquist frequency. The two sets of
termination resistors provide an equivalent 50Ω termi-
nation to the signal source. The second set of termina-
tion resistors connects to COM, providing the correct
input common-mode voltage. Two 0Ω resistors in series
with the analog inputs allow high IF input frequencies.
These 0Ω resistors can be replaced with low-value
resistors to limit the input bandwidth.
Single-Ended, AC-Coupled Input Signal
Figure 12 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.
22 ______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
+3.3V
0.1µF
2.2µF
0.1µF
+3.3V
1
2
V
DD
1
MAX6029EUK21
REFP
REFN
COM
38
0.1µF
REFOUT
5
0.1µF
1µF*
10µF
2.048V
MAX12554
2
3
NOTE: ONE FRONT-END REFERENCE
CIRCUIT IS CAPABLE OF SOURCING 15mA
AND SINKING 30mA OF OUTPUT CURRENT.
0.1µF
+3.3V
0.1µF
39
REFIN
16.2kΩ
1µF
2.2µF
GND
MAX4230
1
3
2.048V
5
2
47Ω
4
+3.3V
10µF
6V
330µF
6V
0.1µF
2.2µF
0.1µF
1.47kΩ
V
DD
1
REFP
REFN
COM
38
*PLACE THE 1µF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
REFOUT
0.1µF
1µF*
10µF
MAX12554
2
3
0.1µF
39
REFIN
2.2µF
GND
Figure 13. External Buffered Reference Driving Multiple ADCs
Figure 13 uses the MAX6029EUK21 precision 2.048V
reference as a common reference for multiple convert-
ers. The 2.048V output of the MAX6029 passes through
a one-pole 10Hz lowpass filter to the MAX4230. The
MAX4230 buffers the 2.048V reference and provides
additional 10Hz lowpass filtering before its output is
applied to the REFIN input of the MAX12554.
Buffered External Reference
Drives Multiple ADCs
The buffered external reference mode allows for more
control over the MAX12554 reference voltage and
allows multiple converters to use a common reference.
The REFIN input impedance is >50MΩ.
______________________________________________________________________________________ 23
14-Bit, 80Msps, 3.3V ADC
+3.3V
1
0.1µF
MAX6029EUK30
2
+3.3V
2.2µF
0.1µF
+3.3V
5
0.1µF
3.000V
0.1µF
MAX4230
1
2.413V
5
2
47Ω
20kΩ
V
4
DD
1
2
3
1%
REFP
38
REFOUT
3
10µF
6V
330µF
6V
20kΩ
1%
0.1µF
10µF
1µF*
MAX12554
REFN
1.47kΩ
+3.3V
0.1µF
0.47µF
0.1µF
52.3kΩ
1%
39
REFIN
COM
MAX4230
1
1.647V
GND
5
2
2.2µF
47Ω
4
52.3kΩ
1%
3
+3.3V
10µF
6V
330µF
6V
2.2µF
0.1µF
20kΩ
0.1µF
1%
1.47kΩ
+3.3V
0.1µF
20kΩ
1%
V
DD
1
REFP
38
REFOUT
MAX4230
1
0.880V
0.1µF
5
2
20kΩ
1%
10µF
1µF*
47Ω
MAX12554
4
2
3
3
REFN
10µF
6V
330µF
6V
0.1µF
39
1.47kΩ
REFIN
COM
GND
2.2µF
*PLACE THE 1µF REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
Figure 14. External Unbuffered Reference Driving Multiple ADCs
Figure 14 uses the MAX6029EUK30 precision 3.000V
reference as a common reference for multiple convert-
ers. A seven-component resistive divider chain follows
the MAX6029 voltage reference. The 0.47µF capacitor
along this chain creates a 10Hz lowpass filter. Three
MAX4230 operational amplifiers buffer taps along this
resistor chain providing 2.413V, 1.647V, and 0.880V to
the MAX12554’s REFP, COM, REFN reference inputs,
Unbuffered External
Reference Drives Multiple ADCs
The unbuffered external reference mode allows for pre-
cise control over the MAX12554 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal refer-
ence, allowing REFP, REFN, and COM to be driven
directly by a set of external reference sources.
24 ______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
respectively. The feedback around the MAX4230 op
amps provides additional 10Hz lowpass filtering. The
2.413V and 0.880V reference voltages set the full-scale
analog input range to 1.022V = (VREFP - VREFN) x
2/3. A common power source for all active components
removes any concern regarding power-supply
sequencing when powering up or down.
missing codes and a monotonic transfer function. For
the MAX12554, DNL deviations are measured at every
step of the transfer function and the worst-case devia-
tion is reported in the Electrical Characteristics table.
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally the midscale
MAX12554 transition occurs at 0.5 LSB above mid-
scale. The offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.
Grounding, Bypassing, and
Board Layout
The MAX12554 requires high-speed board layout
design techniques. Refer to the MAX12555 evaluation
kit data sheet for a board layout reference. Locate all
bypass capacitors as close to the device as possible,
preferably on the same side of the board as the ADC,
using surface-mount devices for minimum inductance.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. The slope of the actual
transfer function is measured between two data points:
positive full scale and negative full scale. Ideally, the
positive full-scale MAX12554 transition occurs at 1.5
LSBs below positive full scale, and the negative full-
scale transition occurs at 0.5 LSB above negative full
scale. The gain error is the difference of the measured
transition points minus the difference of the ideal transi-
tion points.
Bypass V
to GND with a 0.1µF ceramic capacitor in
DD
parallel with a 2.2µF ceramic capacitor. Bypass OV
to GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF ceramic capacitor.
DD
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All
MAX12554 GNDs and the exposed back-side paddle
must be connected to the same ground plane. The
MAX12554 relies on the exposed back-side paddle
connection for a low-inductance ground connection.
Use multiple vias to connect the top-side ground to the
bottom-side ground. Isolate the ground plane from any
noisy digital system ground planes such as a DSP or
output buffer ground.
Small-Signal Noise Floor (SSNF)
Small-signal noise floor is the integrated noise and dis-
tortion power in the Nyquist band for small-signal
inputs. The DC offset is excluded from this noise calcu-
lation. For this converter, a small signal is defined as a
single tone with an amplitude less than -35dBFS. This
parameter captures the thermal and quantization noise
characteristics of the converter and can be used to
help calculate the overall noise figure of a receive
channel. Go to www.maxim-ic.com for application
notes on thermal + quantization noise floor.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.
Ensure that the differential analog input network layout
is symmetric and that all parasitics are balanced equal-
ly. Refer to the MAX12555 evaluation kit data sheet for
an example of symmetric input layout.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For the
MAX12554, this straight line is between the end points
of the transfer function, once offset and gain errors have
been nullified. INL deviations are measured at every
step of the transfer function and the worst-case devia-
tion is reported in the Electrical Characteristics table.
SNR
= 6.02 x N + 1.76
[max]
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
______________________________________________________________________________________ 25
14-Bit, 80Msps, 3.3V ADC
fundamental, the first six harmonics (HD2–HD7), and
the DC offset:
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
SIGNAL
NOISE
RMS
RMS
SNR = 20 × log
2
2
2
2
V
+ V
+.......+ V
+ V
IM14
IM1
IM2
IM13
MD = 20 × log
2
2
V
+ V
2
1
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus the RMS distortion. RMS
noise includes all spectral components to the Nyquist
frequency excluding the fundamental, the first six har-
monics (HD2–HD7), and the DC offset. RMS distortion
includes the first six harmonics (HD2–HD7):
The fundamental input tone amplitudes (V and V ) are
1
2
at -7dBFS. Fourteen intermodulation products (V _)
IM
are used in the MAX12554 IMD calculation. The inter-
modulation products are the amplitudes of the output
spectrum at the following frequencies, where f
IN2
and
IN1
f
are the fundamental input tone frequencies:
• Second-order intermodulation products:
+ f , f - f
SIGNAL
2
f
RMS
IN1
IN2 IN2 IN1
SINAD = 20 × log
2
• Third-order intermodulation products:
2 x f - f , 2 x f - f , 2 x f + f , 2 x f + f
NOISE
+ DISTORTION
RMS
RMS
IN1 IN2
IN2 IN1
IN1
IN2
IN2
IN1
IN1
• Fourth-order intermodulation products:
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
3 x f - f , 3 x f - f , 3 x f + f , 3 x f + f
IN1 IN2
IN2 IN1
IN1
IN2
IN2
• Fifth-order intermodulation products:
3 x f - 2 x f , 3 x f - 2 x f , 3 x f + 2 x
IN1
IN1
, 3 x f
IN2
IN2
+ 2 x f
IN2 IN1
IN1
f
IN2
Third-Order Intermodulation (IM3)
SINAD − 1.76
IM3 is the total power of the third-order intermodulation
products to the Nyquist frequency relative to the total
ENOB =
6.02
input power of the two input tones f
and f . The
IN2
IN1
individual input tone levels are at -7dBFS. The third-
order intermodulation products are 2 x f - f , 2 x
Single-Tone Spurious-Free Dynamic
Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS amplitude of the next-largest spurious
component, excluding DC offset.
IN1
IN2
f
- f , 2 x f
+ f , 2 x f
+ f
.
IN1
IN2 IN1
IN1
IN2
IN2
Two-Tone Spurious-Free Dynamic Range
(SFDR
)
TT
SFDR represents the ratio, expressed in decibels, of
TT
the RMS amplitude of either input tone to the RMS
amplitude of the next-largest spurious component in the
spectrum, excluding DC offset. This spurious compo-
nent can occur anywhere in the spectrum up to Nyquist
and is usually an intermodulation product or a harmonic.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
Aperture Delay
The MAX12554 samples data on the falling edge of its
sampling clock. In actuality, there is a small delay
between the falling edge of the sampling clock and the
2
2
2
2
2
2
V
+ V
+ V
+ V
+ V
+ V
7
2
3
4
5
6
THD = 20 × log
V
1
actual sampling instant. Aperture delay (t ) is the
AD
where V is the fundamental amplitude, and V through
1
2
time defined between the falling edge of the sampling
clock and the instant when an actual sample is taken
(Figure 4).
V
are the amplitudes of the 2nd- through 7th-order
7
harmonics (HD2–HD7).
26 ______________________________________________________________________________________
14-Bit, 80Msps, 3.3V ADC
Aperture Jitter
Pin Configuration
Figure 4 depicts the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
TOP VIEW
Output Noise (n
)
OUT
The output noise (n
mal + quantization noise parameter and is an indication
of the ADC’s overall noise performance.
) parameter is similar to the ther-
OUT
40 39 38 37 36 35 34 33 32 31
REFP
REFN
COM
GND
INP
1
2
3
4
5
6
7
8
9
30 D2
29 D3
28 D4
27 D5
26 D6
25 D7
24 D8
23 D9
22 D10
21 D11
No fundamental input tone is used to test for n
; INP,
OUT
INN, and COM are connected together and 1024k data
points collected. n is computed by taking the RMS
OUT
value of the collected data points after the mean is
removed.
MAX12554
INN
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX12554 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by 10%.
GND
DCE
CLKN
EXPOSED PADDLE (GND)
CLKP 10
11 12 13 14 15 16 17 18 19 20
THIN QFN
6mm x 6mm x 0.8mm
______________________________________________________________________________________ 27
14-Bit, 80Msps, 3.3V ADC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
1
E
21-0141
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
2
E
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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