MAX1273EUA
更新时间：2024-09-18 01:55:35
品牌：MAXIM
描述：Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range
概述
规格参数
数据手册MAX1273EUA 概述
Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range 故障保护， 12位ADC，具有软件可选的输入范围 模数转换器
MAX1273EUA 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | TSSOP | 包装说明： | MO-187CAA, USOP-8 |
| 针数： | 8 | Reach Compliance Code： | not_compliant |
| ECCN代码： | EAR99 | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.81 | Is Samacsys： | N |
| 最大模拟输入电压： | 4.096 V | 最小模拟输入电压： | -4.096 V |
| 转换器类型： | ADC, SUCCESSIVE APPROXIMATION | JESD-30 代码： | S-PDSO-G8 |
| JESD-609代码： | e0 | 长度： | 3 mm |
| 最大线性误差 (EL)： | 0.0244% | 湿度敏感等级： | 1 |
| 模拟输入通道数量： | 1 | 位数： | 12 |
| 功能数量： | 1 | 端子数量： | 8 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出位码： | BINARY, 2'S COMPLEMENT BINARY | 输出格式： | SERIAL |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | TSSOP |
| 封装等效代码： | TSSOP8,.19 | 封装形状： | SQUARE |
| 封装形式： | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | 峰值回流温度（摄氏度）： | 245 |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 采样并保持/跟踪并保持： | TRACK | 座面最大高度： | 1.1 mm |
| 子类别： | Analog to Digital Converters | 标称供电电压： | 5 V |
| 表面贴装： | YES | 技术： | BICMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | GULL WING | 端子节距： | 0.65 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 3 mm | Base Number Matches： | 1 |
MAX1273EUA 数据手册
通过下载MAX1273EUA数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载19-2921; Rev 1; 12/03
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
General Description
Features
o Four Software-Selectable Input Ranges
MAX1272: 0 to 10V, 0 to 5V, 10V, 5V
MAX1273: 0 to V , 0 to V / 2, V ,
REF
The MAX1272/MAX1273 multirange 12-bit data-acquisi-
tion systems (DAS) operate with a single 5V supply. The
software-programmable analog input accepts a variety
of voltage ranges: 1ꢀVꢁ 5Vꢁ ꢀ to 1ꢀVꢁ ꢀ to 5V for the
REF
REF
V
/ 2
REF
MAX1272;
V
REF
ꢁ
V
/ 2ꢁ ꢀ to V
ꢁ ꢀ to V
/ 2 for
REF
REF
REF
o 12-Bit Resolution, No Missing Codes
o 5V Single-Supply Operation
the MAX1273. The software-selectable extended analog
input range increases the effective dynamic range to 14
bits and provides the flexibility to interface 4–2ꢀmA pow-
ered sensors directly to a single 5V system. In additionꢁ
the MAX1272 provides fault protection to 12V. ꢂther
features include a 5MHz track/hold (T/H) bandwidthꢁ
87ksps throughput rateꢁ and internal (4.ꢀ96V) or external
(2.4ꢀV to 4.18V) reference.
o SPI/QSPI/MICROWIRE-Compatible 3-Wire
Interface
o 87ksps Sampling Rate
o
12V Fault-Protected Analog Input ꢀMAX1272ꢁ
o Internal ꢀ4.096Vꢁ or External ꢀ2.4V to 4.18Vꢁ
The MAX1272/MAX1273 serial interfaces connect
directly to SPI™/QSPI™/MICRꢂWIRE™-compatible
devices without any external logic.
Reference
o Low Power
1.5mA at 87ksps
0.4mA at 10ksps
0.2mA at 1ksps
Four software-programmable power-down modes
(delayed standbyꢁ immediate standbyꢁ delayed full power-
downꢁ and immediate full power-down) provide low-cur-
rent shutdown between conversions. In standby modeꢁ the
internal reference buffer remains activeꢁ thus eliminating
startup delay.
o Four Power-Down Modes
o 8-Pin µMAX and PDIP Packages
The MAX1272/MAX1273 are available in 8-pin PDIP
and µMAX packages. Both devices are available in the
commercial (ꢀ°C to +7ꢀ°C) or extended (-4ꢀ°C to
+85°C) temperature range.
Ordering Information
TEMP
PIN-
INL
PART
RANGE
PACKAGE
ꢀLSBꢁ
Applications
MAX1272CPA
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 µMAX
1
1
1
1
1
1
1
1
MAX1272CUA
Industrial Control Systems
Data-Acquisition Systems
Robotics
MAX1272EPA -40°C to +85°C
MAX1272EUA -40°C to +85°C
8 Plastic DIP
8 µMAX
MAX1273CPA
MAX1273CUA
MAX1273EPA
0°C to +70°C
0°C to +70°C
-40°C to +85°C
8 Plastic DIP
8 µMAX
Automatic Testing
Battery-Powered Instruments
Medical Instruments
8 Plastic DIP
8 µMAX
MAX1273EUA -40°C to +85°C
Pin Configuration
TOP VIEW
SCLK
DIN
1
2
3
4
8
7
6
5
DOUT
CS
MAX1272
MAX1273
V
DD
REF
AIN
Typical Application Circuit appears at end of data sheet.
GND
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PDIP/µMAX
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND..............................................................-0.3V to +6V
Operating Temperature Ranges
AIN to GND (MAX1272)...................................................... 12V
AIN to GND (MAX1273)........................................................ 6V
MAX127_ C_ _ .....................................................0°C to +70°C
MAX127_ E_ _...................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Junction Temperature .....................................................+150°C
DOUT, CS, DIN, SCLK, REF to GND..........-0.3V to (V
+ 0.3V)
DD
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T = +70°C)
A
8-Pin Plastic DIP (derate 9.1mW/°C above +70°C) ......727mW
8-Pin µMAX (derate 4.5mW/°C above +70°C)..............362mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
DD
(V
= 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, V
= 4.096V, C
= 1.0µF, f
= 1.4MHz,
REF
REF
SCLK
50% duty cycle, C
= 50pF, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
LOAD
A
MIN
PARAMETERS
ACCURACY ꢀNote 1ꢁ
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
INL
0.3
1.0
1.00
5
DNL
No missing codes over temperature
0.35
Unipolar
Bipolar
Unipolar
Bipolar
Unipolar
Bipolar
Offset Error
LSB
LSB
10
10
Gain Error (Note 2)
10
3
5
Gain Error Temperature
Coefficient (Note 2)
ppm/°C
DYNAMIC SPECIFICATIONS ꢀ10kHz sine-wave input, 10V
ꢀMAX1272ꢁ, or 4.096V
ꢀMAX1273ꢁ, f
= 87kspsꢁ
P-P
P-P
SAMPLE
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Aperture Delay
SINAD
THD
69
72
dB
dB
dB
ns
Up to the 5th harmonic
-87
88
-78
SFDR
80
t
15
AD
Aperture Jitter
t
<50
ps
AJ
ANALOG INPUT
T/H Acquisition Time
t
2.85
µs
ACQ
2
_______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
ELECTRICAL CHARACTERISTICS ꢀcontinuedꢁ
DD
(V
= 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, V
= 4.096V, C
= 1.0µF, f
= 1.4MHz,
REF
REF
SCLK
50% duty cycle, C
= 50pF, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
LOAD
A
MIN
PARAMETERS
SYMBOL
CONDITIONS
10V (MAX1272) or (MAX1273)
range
5V (MAX1272) or
range
MIN
TYP
MAX
UNITS
V
REF
5
V
REF
/ 2 (MAX1273)
2.5
2.5
Small-Signal Bandwidth
BW
MHz
-3dB
0 to 10V (MAX1272) or 0 to V
range
(MAX1273)
REF
0 to 5V (MAX1272) or 0 to V
(MAX1273) range
/ 2
REF
1.25
RNG = 1
0
0
10
5
MAX1272
MAX1273
MAX1272
MAX1273
MAX1272
MAX1273
MAX1272
MAX1273
RNG = 0
Unipolar
Bipolar
Unipolar
Bipolar
RNG = 1
0
V
REF
RNG = 0
0
V
/ 2
REF
Input Voltage Range
(Tables 2, 3)
V
V
IN
RNG = 1
-10
-5
+10
+5
RNG = 0
RNG = 1
-V
+V
REF
REF
REF
RNG = 0
-V
/ 2
+V
/ 2
REF
0 to 10V range
0 to 5V range
-10
+860
-10
-10
+430
+10
0 to V
0 to V
range
REF
REF
/ 2 range
-10
+10
Input Current
I
µA
pF
IN
10V range
5V range
-1400
-720
-1400
-720
+860
+430
+10
V
V
range
REF
REF
/ 2 range
+10
Input Capacitance
40
INTERNAL REFERENCE
REF Output Voltage
V
4.036
4.096
15
4.156
V
REF
MAX127_ C
MAX127_ E
REF Output Tempco
TC V
ppm/°C
REF
30
Output Short-Circuit Current
Load Regulation
REF shorted to GND
40
mA
mV
µF
0 to 0.5mA output current
0.7
10
Capacitive Bypass at REF
1
REFERENCE INPUT ꢀReference buffer disabled, reference input applied to REFꢁ
Input Voltage Range
2.40
4.18
V
_______________________________________________________________________________________
3
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
ELECTRICAL CHARACTERISTICS ꢀcontinuedꢁ
DD
(V
= 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, V
= 4.096V, C
= 1.0µF, f
= 1.4MHz,
REF
REF
SCLK
50% duty cycle, C
= 50pF, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
LOAD
A
MIN
MAX
A
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Converting
400
850
Standby power-down
mode
Input Current
V
= 4.096V
5
10
1
µA
REF
Full power-down mode
POWER REQUIREMENTS
Supply Voltage
V
4.75
5
5.25
4
V
DD
Bipolar
2.4
2.2
400
1
Converting
mA
Unipolar
3
Supply Current
(Internal Reference Mode)
I
DD
Standby power-down mode
Full power-down mode
700
µA
mA
µA
Bipolar
Converting
1.5
1.2
200
1
2.5
2.0
Unipolar
Supply Current
(External Reference Mode)
I
DD
Standby power-down mode
Full power-down mode
External reference = 4.096V
Internal reference
450
0.3
1.0
1.4
Power-Supply Rejection
Ratio (Note 3)
PSRR
LSB
0.5
TIMING
Clock Frequency Range
T/H Acquisition Time
Conversion Time
f
0.1
MHz
µs
SCLK
t
(Note 4)
(Note 4)
2.85
8.57
ACQ
t
µs
CONV
Throughput Rate
87.5
ksps
ms
µs
Internal Reference Settling Time
Device Power-Up Time
REF bypass capacitor initially discharged
External reference mode
2
10
DIGITAL INPUTS ꢀDIN, SCLK, and CSꢁ
Input High-Threshold Voltage
Input Low-Threshold Voltage
Input Hysteresis
V
2.4
+10
0.4
V
V
IH
V
0.8
-10
IL
V
0.2
15
V
HYS
Input Leakage Current
Input Capacitance
I
V
= 0 to V
DD
µA
pF
IN
IN
C
IN
DIGITAL OUTPUT ꢀDOUTꢁ
I
I
= 10mA
= 16mA
SINK
Output Voltage Low
Output Voltage High
V
V
V
OL
0.6
15
SINK
V
DD
V
I
= 0.5mA
OH
SOURCE
- 0.5
Three-State Leakage Current
I
CS = V
CS = V
-10
+10
µA
pF
L
DD
DD
Three-State Output Capacitance
C
OUT
4
_______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
TIMING CHARACTERISTICS
DD
(V
= 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, V
= 4.096V, C
= 1.0µF, f = 1.4MHz,
SCLK
REF
REF
50% duty cycle, C
= 50pF, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Figures 1 and 4)
MAX A
LOAD
A
MIN
PARAMETERS
DIN to SCLK Setup
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
t
100
DS
DH
DO
DIN to SCLK Hold
t
0
ns
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
t
20
250
100
100
ns
t
ns
DV
t
ns
TR
t
100
0
ns
CSS
CSH
t
ns
t
200
200
ns
CH
t
ns
CL
Note 1: Accuracy specifications tested at V
= 5V. Performance at power-supply tolerance limit is guaranteed by power-supply
DD
rejection test.
Note 2: Offset error nulled. The ideal last-code transition is (FS - 1.5 LSB).
Note 3: PSRR measured at full scale. Tested at 10V (MAX1272) and 4.096V (MAX1273) input ranges.
Note 4: Acquisition and conversion times are dependent on the clock speed.
Typical Operating Characteristics
(Typical operating circuit, BIP = RNG = 1, V
= 5V, external reference mode, V
= 4.096V, C
= 1.0µF, f
= 1.4MHz,
DD
REF
REF
SCLK
50% duty cycle, 87ksps, T = +25°C, unless otherwise noted.)
A
CONVERTING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
CONVERTING SUPPLY CURRENT
vs. TEMPERATURE
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
V
AIN
= 0
V
AIN
= 0
V
AIN
= 0
INTERNAL
REFERENCE
INTERNAL
REFERENCE
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
EXTERNAL
REFERENCE
EXTERNAL
REFERENCE
0
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Typical Operating Characteristics (continued)
(Typical operating circuit, BIP = RNG = 1, V
= 5V, external reference mode, V
= 4.096V, C
= 1.0µF, f
= 1.4MHz,
DD
REF
REF
SCLK
50% duty cycle, 87ksps, T = +25°C, unless otherwise noted.)
A
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
FULL POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
V
AIN
= 0
V
AIN
= 0
V
= 0
AIN
INTERNAL
REFERENCE
INTERNAL/EXTERNAL
REFERENCE
INTERNAL/EXTERNAL
REFERENCE
EXTERNAL
REFERENCE
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
NORMALIZED INTERNAL REFERENCE
VOLTAGE vs. TEMPERATURE
NORMALIZED INTERNAL REFERENCE
VOLTAGE vs. SUPPLY VOLTAGE
1.0005
1.0010
1.0008
1.0006
1.0004
1.0002
1.0000
0.9998
0.9996
0.9994
0.9992
0.9990
1.0000
0.9995
0.9990
0.9985
0.9980
0.9975
0.9970
0.9965
0.9960
-40
-15
10
35
60
85
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DNL vs. CODE
INL vs. CODE
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
6
_______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Typical Operating Characteristics (continued)
(Typical operating circuit, BIP = RNG = 1, V
= 5V, external reference mode, V
= 4.096V, C
= 1.0µF, f
= 1.4MHz,
DD
REF
REF
SCLK
50% duty cycle, 87ksps, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. CONVERSION RATE
FFT PLOT
0
2500
2000
1500
1000
500
f
= 10kHz
V
AIN
= 0
AIN
-20
-40
STANDBY POWER-DOWN MODE
BETWEEN CONVERSIONS
-60
-80
EXTERNAL REFERENCE
INTERNAL REFERENCE
-100
-120
-140
-160
0
0
10
20
30
40
50
10
CONVERSION RATE (ksps)
0.1
1
100
FREQUENCY (kHz)
OFFSET ERROR vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
10
8
10
8
RNG = 1, BIP = 1
RNG = 0, BIP = 1
6
6
4
4
RNG = 1, BIP = 1
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
RNG = 0, BIP = 1
RNG = 1, BIP = 0
RNG = 0, BIP = 0
RNG = 0, BIP = 0
RNG = 1, BIP = 0
-40
-15
10
35
60
85
4.50
4.75
5.00
5.25
5.50
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
10
8
10
8
RNG = 0, BIP = 0
RNG = 0, BIP = 1
RNG = 0, BIP = 0
RNG = 0, BIP = 1
6
6
4
4
2
2
0
0
RNG = 1, BIP = 0
RNG = 1, BIP = 1
RNG = 1, BIP = 0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
RNG = 1, BIP = 1
-40
-15
10
35
60
85
4.50
4.75
5.00
5.25
5.50
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Pin Description
PIN
1
NAME
SCLK
DIN
FUNCTION
Serial Clock Input. Clocks data in and out of serial interface. SCLK sets the conversion speed.
2
Serial Data Input. Data clocks in on the rising edge of SCLK.
3
V
5V Supply. Bypass with a 0.1µF capacitor to GND.
DD
4
GND
AIN
Ground
5
Analog Input
Reference Buffer Output/Reference Input. Bypass REF with a 1µF capacitor to GND. In internal
reference mode, the reference buffer provides a 4.096V nominal output. For external reference mode,
disable the internal reference buffer through the serial interface and apply an external reference to REF.
6
REF
Active-Low Chip-Select Input. Drive CS low to clock data into the MAX1272/MAX1273. See the Input
Data Format section.
7
8
CS
Serial Data Output. Data clocks out on the falling edge of SCLK. DOUT is high impedance when CS is
high.
DOUT
to convert an analog signal to a 12-bit digital output.
Figure 2 shows a block diagram of the MAX1272/
MAX1273.
DOUT
C
LOAD
Analog-Input Track/Hold
The T/H tracking/acquisition mode begins on the falling
edge of the fourth clock cycle in the 8-bit input control
word and enters hold/conversion mode on the falling
edge of the eighth clock cycle.
1kΩ
A) TEST CIRCUIT FOR V
OH
The MAX1272/MAX1273 input architecture includes a
resistor-divider and a T/H system (Figure 3). When
operating in bipolar or unipolar mode, the resistor-
divider network formed by R1, R2, and R3 scales the
signal applied at the input channel. Use a low source
impedance (<4Ω) to minimize gain error.
DOUT
C
LOAD
1kΩ
Input Bandwidth
The ADC’s small-signal input bandwidth depends on
the selected input range and varies from 1.25MHz to
5MHz (see the Electrical Characteristics). The maxi-
mum sampling rate for the MAX1272/MAX1273 is
87ksps (16 clocks per conversion). Use undersampling
techniques to digitize high-speed transient events and
measure periodic signals with bandwidths exceeding
the ADC’s sampling rate.
5V
B) TEST CIRCUIT FOR V
OL
f
= 1.4MHz, C
= 50pF
LOAD
SCLK
Figure 1. Output Load Circuit for Timing Characteristics
Detailed Description
Converter Operation
The MAX1272/MAX1273 multirange ADCs use succes-
sive approximation and internal track/hold (T/H) circuitry
Use anti-alias filtering to avoid the aliasing of high-fre-
quency signals into the frequency band of interest. An
anti-aliasing filter must limit the input bandwidth to no
more than one half of the sampling frequency.
8
_______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
DIN DOUT CS
SCLK
SERIAL INTERFACE
LOGIC
V
DD
GND
MAX1272
MAX1273
OUT
12-BIT
SAR ADC
SIGNAL
CONDITIONING
T/H
AIN
IN
CLK
REF
REF
4.096V
REFERENCE
Figure 2. Simplified Block Diagram
Table 1. Control-Byte Format
BIT 7
ꢀMSBꢁ
BIT 0
ꢀLSBꢁ
BIT 6
BIT 5
BIT 4
Bit 3
BIT 2
BIT 1
RESERVED
START
RNG
BIP
PD
MODE1
MODE0
REF
BIT
NAME
START
RNG
DESCRIPTION
7 (MSB)
Write a logic 1 (see the Input Data Format section)
Selects the full-scale input voltage range (Tables 2, 3)
Selects unipolar or bipolar conversion mode (Tables 2, 3)
6
5
BIP
4
PD
Selects normal operation (PD = 1) or power-down (PD = 0) mode
Selects standby power-down (STBYPD) or full power-down (FULLPD) mode (Table 4)
Selects delayed or immediate power-down mode (Table 4)
Write a logic 0
3
MODE1
MODE0
RESERVED
REF
2
1
0 (LSB)
Selects external (REF = 0, default) or internal (REF = 1) reference mode
Overvoltage circuitry at the analog input provides 12V
fault protection for the MAX1272. This circuit limits the
current going into or out of the device to less than 2mA,
providing an added layer of protection from momentary
over/undervoltages at the analog input. The overvoltage
protection activates when the device enters power-
Input Range and Protection
The MAX1272/MAX1273 provide software-selectable
analog input voltage ranges. Program the analog input
to one of four ranges by setting the appropriate control
bits (RNG, BIP) in the control byte (Table 1). The
MAX1272 has selectable input voltage ranges extend-
✕
ing to 10V ( V
2.4414), while the MAX1273 has
REF
down mode or if V
= 0.
DD
selectable input voltage ranges extending to
Figure 3 shows the equivalent input circuit.
V
.
REF
_______________________________________________________________________________________
9
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Table 2. Input Range and Polarity Selection for MAX1272
NEGATIVE
FULL SCALE
INPUT RANGE
RNG
BIP
ZERO SCALE
FULL SCALE
0 to 5V
5V
0
0
1
1
0
1
0
1
—
0
0
0
0
V
V
V
V
× 1.2207
× 1.2207
× 2.4414
× 2.4414
REF
REF
REF
REF
-V
REF
-V
REF
× 1.2207
—
0 to 10V
10V
× 2.4414
Table 3. Input Range and Polarity Selection for MAX1273
NEGATIVE
FULL SCALE
INPUT RANGE
RNG
BIP
ZERO SCALE
FULL SCALE
0 to V / 2
0
0
1
1
0
1
0
1
—
0
0
0
0
V
V
/ 2
/ 2
REF
REF
REF
V
REF
/ 2
-V
/ 2
REF
0 to V
—
V
V
REF
REF
REF
V
REF
-V
REF
Table 4. Power-Down Selection
PD
MODE1
MODE0
MODE
Normal operation (ADCs always active). Automatically enters delayed
standby power-down mode between conversions.
1
X
X
0
1
0
1
Delayed standby power-down mode.
Immediate standby power-down mode.
Delayed full power-down mode.
0
1
0
Immediate full power-down mode.
Input Data Format
Input data (control byte) clocks in at DIN on the rising
edge of SCLK. CS enables communication with the
MAX1272/MAX1273. After CS falls, the first arriving 1
represents the start bit (MSB) of the input control byte.
The start bit is defined as follows:
BIPOLAR
VOLTAGE
REFERENCE
S1
UNIPOLAR
OFF
R3
4.8kΩ
1) The first high bit clocked into DIN with CS low any
time the converter is idle (e.g., after applying V ).
DD
R1
C
HOLD
2) The first high bit clocked into DIN after bit 4 (D4) of a
conversion in progress clocks out on DOUT.
See Table 1 for programming the control byte. Figure 4
shows the detailed serial interface timing.
AIN
S2
R2
T/H
OUT
ON
HOLD
S3
TRACK
HOLD
TRACK
S4
Output Data Format
Output data (DOUT) clocks out MSB first on the falling
edge of SCLK. The unipolar mode provides a straight
binary output. The bipolar mode provides a two’s com-
plement binary output. For output binary codes, see the
Transfer Function section.
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 11.3kΩ (MAX1272)
or 4.8kΩ (MAX1273)
R2 = 7.8kΩ (MAX1272)
or ∞ (OPEN) (MAX1273)
Figure 3. Equivalent Input Circuit
10 ______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
• • •
CS
t
t
t
CSH
t
CL
CSS
CH
t
CSH
SCLK
• • •
t
DS
t
DH
DIN
• • •
• • •
t
t
DV
t
TR
DO
DOUT
Figure 4. Detailed Serial Interface Timing
CS
DIN
HI-Z
MSB
LSB
HI-Z
DOUT
SCLK
AUTO STANDBY
ACQUISITION
4 SCLKs
CONVERSION
12 SCLKs
Figure 5. Conversion Timing, 21 Clocks/Conversion
______________________________________________________________________________________ 11
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
CS
CONTROL BYTE 2
CONTROL BYTE 0
CONTROL BYTE 1
DIN
DOUT
SCLK
HI-Z
MSB
LSB
MSB
LSB
RESULT 0
RESULT 1
ACQUISITION
4 SCLKs
CONVERSION
12 SCLKs
ACQUISITION
4 SCLKs
CONVERSION
12 SCLKs
Figure 6. Conversion Timing, 16 Clocks/Conversion
Starting a Conversion
The MAX1272/MAX1273 use the serial clock to complete
an acquisition. The falling edge of CS does not start a
conversion on the MAX1272/MAX1273. Each conversion
requires a control byte. Programming the fourth bit in the
control byte starts the acquisition sequence. Conversion
starts on the falling edge of the eighth clock cycle after
the start bit.
To achieve the maximum throughput, keep CS low, and
start the control byte after bit 4 (D4) of the conversion in
progress clocks out on DOUT.
If CS is low and SCLK is continuous, guarantee a start
bit by first clocking in 16 zeros.
Applications Information
Keep CS low during successive conversions. If a start bit
is received after CS transitions from high to low, but before
the output bit 4 (D4) becomes available, the current con-
version terminates and a new conversion begins. DOUT
enters high-impedance state when CS transitions high.
Power-On Reset
The MAX1272/MAX1273 power-up in normal operating
mode (all internal circuitry active), and external reference
mode. The MAX1272/MAX1273 require a start bit to initi-
ate a conversion. The contents of the output data register
clear during power-up.
SCLK shifts data in and out of the MAX1272/MAX1273
and controls both acquisition and conversion timing.
Conversion begins immediately after the end of the
acquisition cycle. Successive-approximation bit deci-
sions appear at DOUT on each of the following 12 clock
falling edges (Figure 5). Additional clock falling edges
result in trailing zeros at DOUT.
Internal or External Reference
Operate the MAX1272/MAX1273 with an internal or an
external reference. Configure REF as an internal refer-
ence output or an external reference input using the
serial interface. When changing from external reference
mode to internal reference mode, allow 2ms (C
=
REF
1µF) for the reference to stabilize before taking any
measurement.
The maximum running rate of the MAX1272/MAX1273 is
16 clocks per conversion. A clock speed of 1.4MHz
allows for a maximum sampling rate of 87ksps (Figure 6).
Internal Reference
The internally trimmed reference provides 4.096V at REF.
Bypass REF to GND with a 1.0µF capacitor (Figure 7a).
12 ______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
5V
IN
MAX6064
REF
OUT
REF
C
REF
MAX1272
MAX1273
1.0µF
REF
MAX1272
MAX1273
1.0µF
C
GND
Figure 7a. Internal Reference Configuration
Figure 7b. External Reference Configuration
External Reference
To use an external reference, disable the internal buffer
by setting the REF bit in the 8-bit control word to zero
(see Table 1), and apply a reference voltage to REF. Use
an external reference voltage ranging from 2.40V to
4.18V. External reference voltages less than 4.096V
increase the ratio of RMS noise to the LSB value (full
scale / 4096) resulting in performance degradation (loss
of effective bits—ENOB).
serial clock cycle and no conversion takes place
(Figure 9). In all power-down modes, the interface
remains active with the conversion results available at
DOUT. Additionally, the input overvoltage protection
remains active in all power-down modes (MAX1272).
The first high bit on DIN after CS falls (start condition)
powers up the MAX1272/MAX1273 from any software-
selected power-down condition. With external refer-
ence mode, device power-up time from full power-
down is typically 10µs. Send a control byte and allow
10µs for the device to wake up from full power-down.
The next received control byte initiates a conversion.
The REF input impedance is a minimum of 4.8kΩ for
DC currents; therefore, the external reference must be
able to source 850µA during conversions and have an
output impedance of less than 10Ω. Bypass REF with a
1µF capacitor to GND as close to REF as possible
(Figure 7b).
When in internal reference mode, full power-down
mode disables the internal reference and reference
buffer. Only the interface circuitry remains active for
reading conversion results. Send a control byte and
Power-Down Modes
To save power, configure the ADC for a low-current
shutdown mode by setting the PD bit in the control
byte. The MAX1272/MAX1273 features four program-
mable power-down modes: delayed standby power-
down, immediate standby power-down, delayed full
power-down, and immediate full power-down. Select
standby or full power-down by programming MODE1 in
the input control byte (Table 4). Select delayed or
immediate power-down by programming MODE0 in the
input control byte. Use the MODE0 bit to choose when
the part enters the power-down state. For example,
when MODE0 of the control byte is 0, the device
remains powered up until after the current conversion
ends (Figure 8). On the other hand, if MODE0 = 1, the
device powers down on the falling edge of the eighth
allow 2ms (C
= 1µF) for the internal reference to set-
REF
tle and the MAX1272/MAX1273 to wake up from full
power-down mode. The next received control byte initi-
ates a conversion.
AutoShutdown™
The MAX1272/MAX1273 automatically enter standby
power-down mode after each conversion without requir-
ing any startup time on the next conversion.
Digital Interface
The MAX1272/MAX1273 feature a fully compatible
SPI/QSPI and MICROWIRE serial interface. For SPI and
QSPI, clear CPOL and CPHA in the microcontroller’s
SPI control registers.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
______________________________________________________________________________________ 13
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
CS
DIN
HI-Z
MSB
LSB
HI-Z
DOUT
SCLK
ACQUISITION
4 SCLKs
CONVERSION
12 SCLKs
POWERED UP
POWERED UP
POWERED DOWN
Figure 8. Delayed Power-Down Timing
CS
DIN
HI-Z
HI-Z
DOUT
SCLK
ACQUISITION
4 SCLKs
POWERED DOWN
POWERED UP
POWERED UP
Figure 9. Immediate Power-Down Timing
bit data stream contains all leading zeros. The second
8-bit data stream contains a leading zero followed by
the MSB through D5. The third 8-bit data stream con-
tains D4–D0 followed by trailing zeros.
SPI and MICROWIRE Interface
When using the SPI (Figure 10a) or MICROWIRE (Figure
10b) interfaces, set CPOL = 0 and CPHA = 0 in the SPI
master. Conversion begins with a falling edge on CS.
Three consecutive 8-bit readings are necessary to
obtain the entire 12-bit result from the ADC. DOUT data
transitions on the serial clock’s falling edge. The first 8-
14 ______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
µC on SCLK’s rising edge. The first 8-bit data stream
contains all zeros. The second 8-bit data stream con-
tains a leading zero followed by the MSB through D5.
The third 8-bit data stream contains bits D4–D0 fol-
lowed by trailing zeros.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1272/MAX1273 support a max-
imum f
of 1.4MHz. Figure 11 shows the MAX1272/
SCLK
MAX1273 connected to a QSPI master.
Transfer Function
Output data coding for the MAX1272/MAX1273 is bina-
ry in unipolar mode with:
PIC16 with SSP Module and
PIC17 Interface
The MAX1272/MAX1273 are compatible with a
PIC16/PIC17 controller (µC) using the synchronous ser-
ial-port (SSP) module.
FS
1LSB=
4096
To establish SPI communication, connect the controller
as shown in Figure 12 and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 5 and 6.
and two’s complement binary in bipolar mode with:
2 × |FS|
4096
1LSB=
Code transitions occur halfway between successive
integer LSB values. Figures 13a and 13b show the
input/output transfer functions for uni-polar and bipolar
operations, respectively. For full-scale (FS) values, see
Tables 2 and 3.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be transmitted and received simultaneously. Three
consecutive 8-bit readings are necessary to obtain the
entire 12-bit result from the ADC. DOUT data transitions
on the serial clock’s falling edge and is clocked into the
I/O
SCK
CS
I/O
SCK
SI
CS
SCLK
DOUT
SCLK
DOUT
MISO
SPI
MICROWIRE
V
DD
MAX1272
MAX1273
MAX1272
MAX1273
SS
Figure 10a. SPI Connections
Figure 10b. MICROWIRE Connections
V
V
DD
DD
SCK
SDI
SCLK
DOUT
CS
SCK
CS
SCLK
DOUT
I/O
CS
MISO
QSPI
V
DD
PIC16/PIC17
MAX1272
MAX1273
MAX1272
MAX1273
SS
GND
Figure 12. SPI Interface Connection for a PIC16/PIC17
______________________________________________________________________________________ 15
Figure 11. QSPI Connections
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Table 5. Detailed SSPCON Register Contents—PIC16/PIC17
CONTROL BIT
BIT7
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
Write Collision Detection Bit
WCOL
SSPOV
X
X
BIT6
Receive Overflow Detection Bit
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
SSPEN
CKP
BIT5
BIT4
1
0
Clock Polarity Select Bit. CKP = 0 for SPI master mode section.
SSPM3
SSPM2
BIT3
BIT2
0
0
Synchronous Serial-Port Mode-Select Bit. Sets SPI master mode and selects f
= f
OSC
/ 16.
CLK
SSPM1
SSPM0
BIT1
BIT0
0
1
X = Don’t care.
Table 6. Detailed SSPSTAT Register Contents—PIC16/PIC17
CONTROL BIT
SYNCHRONOUS SERIAL-PORT STATUS REGISTER ꢀSSPSTATꢁ
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
SMP
BIT7
0
CKE
D/A
P
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
1
X
X
X
X
X
X
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the serial clock.
Data Address Bit
Stop Bit
S
Start Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer Full Status Bit
X = Don’t care.
2FS
4096
FS
4096
OUTPUT CODE
(TWO’S COMPLEMENT)
1 LSB =
1 LSB =
OUTPUT CODE
0…111
0…110
0…101
0…100
1…111
1…110
1…101
1…100
0…001
0…000
1…111
1…011
0…011
1…010
1…001
1…000
0…010
0…001
0…000
-2048 -2046
+2045 +2047
4092 4094
FS
-1
0 +1
0
1
2
3
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 13b. Bipolar Transfer Function
Figure 13a. Unipolar Transfer Function
16 ______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
The ideal, theoretical minimum analog-to-digital noise is
caused by quantization noise error only and results
directly from the ADC’s resolution (N-bits):
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one star point (Figure 14), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure that the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
SNR = (6.02 ✕ N + 1.76) dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
High-frequency noise in the power supply (V ) can
DD
degrade the performance of the ADC’s fast compara-
SINAD (dB) = 20 ✕ log [Signal
/ (Noise +
RMS
tor. Bypass V
to the star ground with a 0.1µF capaci-
DD
Distortion)
]
RMS
tor located as close as possible to the MAX1272/
MAX1273’s power-supply input. Minimize capacitor lead
length for best supply-noise rejection. Add an attenua-
tion resistor (5Ω) to extremely noisy power supplies.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1272/MAX1273
are measured using the endpoint method.
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1 LSB. A
DNL error specification of 1 LSB guarantees no missing
codes and a monotonic transfer function.
2
2
2
2
V
+ V + V + V
3 4 5
2
THD = 20 × log
V
1
where V is the fundamental amplitude and V through
V are the 2nd- through 5th-order harmonics.
5
1
2
Aperture Definitions
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between samples. Aperture delay (t ) is the
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
AD
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component, excluding DC offset.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error).
______________________________________________________________________________________ 17
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Typical Operating Circuit
5V
SUPPLIES
0.1µF
5V
V
LOGIC
= 5V
GND
V
DD
AIN
REF
CS
SCLK
DIN
I/O
R* = 5Ω
SCK
MOSI
µP
0.1µF
MAX1272
MAX1273
DOUT
MISO
V
DD
GND
5V
DGND
GND
1.0µF
MAX1272
MAX1273
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 14. Power-Supply Grounding Connections
Chip Information
TRANSISTOR COUNT: 6146
PROCESS: BiCMOS
18 ______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 19
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
4X S
8
8
MILLIMETERS
INCHES
DIM MIN
MAX
MAX
MIN
-
-
0.043
0.006
0.037
0.014
0.007
0.120
1.10
0.15
0.95
0.36
0.18
3.05
A
0.002
0.030
0.010
0.005
0.116
0.05
0.75
0.25
0.13
2.95
A1
A2
b
E
H
ÿ 0.50 0.1
c
D
e
0.0256 BSC
0.65 BSC
0.6 0.1
E
H
0.116
0.188
0.016
0∞
0.120
2.95
4.78
0.41
0∞
3.05
5.03
0.66
6∞
0.198
0.026
6∞
L
1
1
α
S
0.6 0.1
0.0207 BSC
0.5250 BSC
BOTTOM VIEW
D
TOP VIEW
A1
A2
A
c
α
e
L
b
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0036
J
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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| MAX1274 | MAXIM | 1.8Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs | 获取价格 |
|
| MAX1274ACTC+ | MAXIM | ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, MO-220, TQFN-12 | 获取价格 |
|
| MAX1274ACTC+T | MAXIM | 暂无描述 | 获取价格 |
|
| MAX1274ACTC-T | MAXIM | 1.8Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs | 获取价格 |
|
| MAX1274AETC+ | MAXIM | ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, MO-220, TQFN-12 | 获取价格 |
|
| MAX1274AETC+T | MAXIM | 1.8Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs | 获取价格 |
|
| MAX1274AETC-T | MAXIM | 1.8Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs | 获取价格 |
|
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