MAX1300AEUG+ [MAXIM]
8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs;
| 型号： | MAX1300AEUG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs 信息通信管理 光电二极管 转换器 |
| 文件： | 总31页 (文件大小：2467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
Serial 16-Bit ADCs
REF
General Description
Features
●
Software-Programmable Input Range for Each Channel
The MAX1300/MAX1301 multirange, low-power, 16-bit,
successive-approximation, analog-to-digital converters
(ADCs) operate from a single +5V supply and achieve
throughput rates up to 115ksps. A separate digital sup-
ply allows digital interfacing with 2.7V to 5.25V systems
● Single-Ended Input Ranges (V
= 4.096V)
REF
)/2 to 0, 0 to 3 x V
0 to (3 x V
)/2, (-3 x V
,
REF
REF
REF
-3 x V
to 0, (±3 x V
REF
)/4, (±3 x V
, ±6 x V
REF
)/2, ±3 x V
REF
REF
REF
● Differential Input Ranges
(±3 x V )/2, ±3 x V
®
using the SPI-/QSPI™-/MICROWIRE -compatible serial
REF
REF
interface. Partial power-down mode reduces the supply
current to 1.3mA (typ). Full power-down mode reduces
the power-supply current to 1µA (typ).
● Eight Single-Ended or Four Differential Analog Inputs
(MAX1300)
● Four Single-Ended or Two Differential Analog Inputs
(MAX1301)
The MAX1300 provides eight (single-ended) or four (true
differential) analog input channels. The MAX1301 pro-
vides four (single-ended) or two (true differential) analog
input channels. Each analog input channel is indepen-
dently software programmable for seven single-ended
● ±16.5V Overvoltage Tolerant Inputs
● Internal or External Reference
● 115ksps Maximum Sample Rate
● Single +5V Power Supply
input ranges [0 to (3 x V
)/2, (-3 x V
)/2 to 0, 0 to 3
REF
REF
● 20-/24-Pin TSSOP Package
x V
x V
, -3 x V
to 0, (±3 x V
)/4, (±3 x V )/2, ±3
REF
REF
REF
REF
REF
] and three differential input ranges [(±3 x V
)/2,
Ordering Information
REF
±3 x V
, ±6 x V
].
REF
REF
PIN-
PACKAGE
PART
TEMP RANGE
CHANNELS
An on-chip +4.096V reference offers a small convenient
ADC solution. The MAX1300/MAX1301 also accept an
external reference voltage between 3.800V and 4.136V.
MAX1300AEUG+ -40°C to +85°C 24 TSSOP
MAX1300BEUG+ -40°C to +85°C 24 TSSOP
MAX1301AEUP+ -40°C to +85°C 20 TSSOP
8
8
4
4
The MAX1300 is available in a 24-pin TSSOP package
and the MAX1301 is available in a 20-pin TSSOP pack-
age. Each device is specified for operation from -40°C to
+85°C.
MAX1301BEUP+ -40°C to +85°C 20 TSSOP
+Denotes lead(Pb)-free/RoHS-compliant package.
Pin Configurations
Applications
● Industrial Control Systems
● Data-Acquisition Systems
● Avionics
TOP VIEW
+
AVDD1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
3
4
5
6
7
8
9
24 AGND1
23 AGND2
22 AVDD2
21 AGND3
20 REF
● Robotics
MAX1300
19 REFCAP
18 DVDD
17 DVDD0
16 DGND
15 DGNDO
14 DOUT
13 SCLK
CS 10
DIN 11
SSTRB 12
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
TSSOP
Pin Configurations continued at end of data sheet.
19-3575; Rev 3; 12/11
MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Absolute Maximum Ratings
AVDD1 to AGND1 ...................................................-0.3V to +6V
AVDD2 to AGND2 ...................................................-0.3V to +6V
DVDD to DGND.......................................................-0.3V to +6V
DVDDO to DGNDO.................................................-0.3V to +6V
DVDD to DVDDO ....................................................-0.3V to +6V
DVDD, DVDDO to AVDD1.......................................-0.3V to +6V
AVDD1, DVDD, DVDDO to AVDD2.........................-0.3V to +6V
DGND, DGNDO, AGND3, AGND2 to AGND1 .....-0.3V to +0.3V
CS, SCLK, DIN, DOUT, SSTRB to
CH0–CH7 to AGND1........................................-16.5V to +16.5V
REF, REFCAP to AGND1................... -0.3V to (V + 0.3V)
Continuous Current (any pin)...........................................±50mA
AVDD1
Continuous Power Dissipation (T = +70°C)
A
20-Pin TSSOP (derate 11mW/°C above +70°C).........879mW
24-Pin TSSOP (derate 12.2mW/°C above +70°C)......976mW
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DGNDO ......................................... -0.3V to (V
+ 0.3V)
DVDDO
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range (±3 x V
), C
= 50pF, C
= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
REF
DOUT
SSTRB
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Notes 1, 2)
Resolution
16
Bits
LSB
LSB
MAX130_A
MAX130_B
±1.0
±1.0
±2
±4
+2
Integral Nonlinearity
INL
Differential Nonlinearity
Transition Noise
DNL
No missing codes
-1
External or internal reference
1
LSB
RMS
Unipolar
Bipolar
Bipolar
0
±20
±12
±20
Single-ended inputs
Offset Error
-1.0
-2.0
mV
Differential inputs (Note 3)
Unipolar or bipolar
Channel-to-Channel Gain
Matching
0.025
1.0
%FSR
mV
Channel-to-Channel Offset Error
Matching
Unipolar or bipolar
Unipolar
3
1
2
Offset Temperature Coefficient
Gain Error
Bipolar
µV/°C
%FSR
ppm/°C
Fully differential
Unipolar
±0.5
±0.8
±1
Bipolar
Fully differential
Unipolar
2
1
2
Gain Temperature Coefficient
Bipolar
Fully differential
DYNAMIC SPECIFICATIONS f
= 5kHz, V = FSR - 0.05dB (Notes 1, 2)
IN
IN(SINE-WAVE)
Differential inputs, FSR = ±6 x V
91
89
86
83
REF
Single-ended inputs, FSR = ±3 x V
REF
Signal-to-Noise Plus Distortion
SINAD
dB
Single-ended inputs, FSR = (±3 x V
Single-ended inputs, FSR = (±3 x V
)/2
)/4
REF
REF
80
Maxim Integrated
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Electrical Characteristics (continued)
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range (±3 x V
), C
= 50pF, C
= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
REF
DOUT
SSTRB A A
PARAMETER
SYMBOL
CONDITIONS
Differential inputs, FSR = ±6 x V
MIN
TYP
91
MAX
UNITS
REF
Single-ended inputs, FSR = ±3 x V
89
REF
Signal-to-Noise Ratio
SNR
dB
Single-ended inputs, FSR = (±3 x V
Single-ended inputs, FSR = (±3 x V
)/2
)/4
86
REF
REF
83
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-97
dB
Spurious-Free Dynamic Range
Aperture Delay
SFDR
92
99
15
dB
ns
ps
dB
t
Figure 21
Figure 21
AD
Aperture Jitter
t
100
105
AJ
Channel-to-Channel Isolation
CONVERSION RATE
External clock mode, Figure 2
External acquisition mode, Figure 3
Internal clock mode, Figure 4
114
84
Byte-Wide Throughput Rate
f
ksps
SAMPLE
106
ANALOG INPUTS (CH0–CH3 MAX1301, CH0–CH7 MAX1300, AGND1)
Small-Signal Bandwidth
Full-Power Bandwidth
All input ranges, V = 100mV
(Note 2)
P-P
2
MHz
kHz
IN
All input ranges, V = 4V
IN
(Note 2)
700
P-P
(-3 x V
4
)/
(+3 x V
)/
REF
REF
R[2:1] = 001
R[2:1] = 010
R[2:1] = 011
R[2:1] = 100
4
(-3 x V
2
)/
REF
0
(+3 x V
2
)/
)/
REF
0
Input Voltage Range (Table 6)
V
V
CH_
(-3 x V
2
)/
(+3 x V
2
REF
REF
R[2:1] = 101
R[2:1] = 110
R[2:1] = 111
-3 x V
0
0
REF
+3 x V
+3 x V
REF
-3 x V
REF
REF
True-Differential Analog Common-
Mode Voltage Range
V
DIF/SGL = 1 (Note 4)
DIF/SGL = 1,
-14
+9
V
CMDR
Common-Mode Rejection
Ratio
CMRR
75
dB
input voltage range = (±3 x V
)/4
REF
Input Current
I
-3 x V
< V
< +3 x V
REF
-1250
+900
µA
pF
kΩ
CH_
REF
CH_
Input Capacitance
Input Resistance
C
5
CH_
CH_
R
17
Maxim Integrated
│ 3
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Electrical Characteristics (continued)
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range (±3 x V
), C
= 50pF, C
= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
REF
DOUT
SSTRB A A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL REFERENCE (Bypass REFCAP with 0.1µF to AGND1 and REF with 1.0µF to AGND1)
Reference Output Voltage
V
4.056
4.096
±30
4.136
V
REF
Reference Temperature
Coefficient
TC
ppm/°C
REF
REF shorted to AGND1
REF shorted to AVDD
10
-1
Reference Short-Circuit Current
Reference Load Regulation
I
mA
mV
REFSC
I
= 0 to 0.5mA
0.1
10
REF
EXTERNAL REFERENCE (REFCAP = AVDD)
Reference Input Voltage Range
V
3.800
4.136
V
V
REF
REFCAP Buffer Disable
Threshold
V
V
AVDD1
- 0.4
AVDD1
- 0.1
V
(Note 5)
= +4.096V, external clock mode,
external acquisition mode, internal clock
mode, or partial power-down mode
RCTH
V
REF
90
±0.1
45
200
±10
Reference Input Current
I
µA
REF
V
= +4.096V, full power-down mode
REF
External clock mode, external acquisition
mode, internal clock mode, or partial
power-down mode
20
kΩ
Reference Input Resistance
R
REF
Full power-down mode
40
MΩ
DIGITAL INPUTS (DIN, SCLK, CS)
0.7 x
DVDDO
Input High Voltage
V
V
V
IH
V
0.3 x
DVDDO
Input Low Voltage
V
IL
V
Input Hysteresis
V
0.2
10
V
HYST
Input Leakage Current
Input Capacitance
I
V
= 0 to V
DVDDO
-10
+10
µA
pF
IN
IN
C
IN
DIGITAL OUTPUTS (DOUT, SSTRB)
V
V
= 4.75V, I
= 10mA
0.4
0.4
DVDDO
SINK
Output Low Voltage
V
V
OL
= 2.7V, I
= 5mA
DVDDO
SINK
V
DVDDO
- 0.4
Output High Voltage
V
I
= 0.5mA
V
OH
SOURCE
DOUT Tri-State Leakage Current
I
CS = V
-10
+10
µA
DDO
DVDDO
POWER REQUIREMENTS (AVDD1 and AGND1, AVDD2 and AGND2, DVDD and DGND, DVDDO and DGNDO)
Analog Supply Voltage
Digital Supply Voltage
AVDD1
DVDD
4.75
4.75
5.25
5.25
V
V
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Electrical Characteristics (continued)
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range (±3 x V
), C
= 50pF, C
= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
REF
DOUT
SSTRB A A
PARAMETER
SYMBOL
AVDD2
CONDITIONS
MIN
4.75
2.70
TYP
MAX
5.25
5.25
UNITS
Preamplifier Supply Voltage
V
V
Digital I/O Supply Voltage
DVDDO
External clock mode,
external acquisition
mode, or internal
clock mode
Internal reference
External reference
3
3.5
3
AV
Supply Current
I
mA
DD1
AVDD1
2.3
External clock mode, external acquisition
mode, or internal clock mode
DV
Supply Current
Supply Current
I
0.8
2
20
1
mA
mA
mA
DD
DVDD
External clock mode, external acquisition
mode, or internal clock mode
AV
I
13.5
0.01
DD2
AVDD2
External clock mode, external acquisition
mode, or internal clock mode
DV
Supply Current
I
DDO
DVDDO
Partial power-down mode
Full power-down mode
All analog input ranges
1.3
0.5
mA
µA
Total Supply Current
Power-Supply Rejection Ratio
PSRR
±0.5
LSB
TIMING CHARACTERISTICS (Figures 15 and 16)
External clock mode
0.272
0.228
0.1
109
92
62
62
SCLK Period
t
External acquisition mode
Internal clock mode
µs
ns
ns
CP
External clock mode
External acquisition mode
Internal clock mode
SCLK High Pulse Width (Note 6)
SCLK Low Pulse Width (Note 6)
t
CH
40
External clock mode
External acquisition mode
Internal clock mode
109
92
t
CL
40
DIN to SCLK Setup
t
40
ns
ns
ns
ns
DS
DH
DO
DIN to SCLK Hold
t
0
SCLK Fall to DOUT Valid
CS Fall to DOUT Enable
t
40
40
t
DV
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Electrical Characteristics (continued)
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range (±3 x V
), C
= 50pF, C
= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
REF
DOUT
SSTRB
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
CS Rise to DOUT Disable
t
40
TR
CS Fall to SCLK Rise Setup
CS High Minimum Pulse Width
SCLK Fall to CS Rise Hold
SSTRB Rise to CS Fall Setup
DOUT Rise/Fall Time
t
40
40
0
ns
CSS
t
ns
CSPW
t
ns
CSH
(Note 4)
40
ns
C = 50pF
10
10
ns
L
SSTRB Rise/Fall Time
C = 50pF
ns
L
Note 1: Parameter tested at V
= V
= V
= V
= 5V.
AVDD1
AVDD2
DVDD
DVDDO
Note 2: See definitions in the Parameter Definitions section at the end of the data sheet.
Note 3: Guaranteed by correlation with single-ended measurements.
Note 4: Not production tested. Guaranteed by design.
Note 5: To ensure external reference operation, V
must exceed (V
- 0.1V). To ensure internal reference operation,
REFCAP
AVDD1
V
must be below (V
- 0.4V). Bypassing REFCAP with a 0.1μF or larger capacitor to AGND1 sets V
≈
REFCAP
REFCAP
AVDD1
4.096V. The transition point between internal reference mode and external reference mode lies between the REFCAP buffer
disable threshold minimum and maximum values (Figures 17 and 18).
Note 6: The SCLK duty cycle can vary between 40% and 60%, as long as the t and t
timing requirements are met.
CL
CH
Typical Operating Characteristics
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range, C
= 50pF, C
= 50pF; unless otherwise noted.)
DOUT
SSTRB
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGE
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
2.6
2.5
2.4
2.3
2.2
18
17
16
15
14
13
12
11
10
0.95
0.90
0.85
0.80
0.75
EXTERNAL CLOCK MODE
EXTERNAL CLOCK MODE
DATA RATE = 115ksps
T
= +85°C
A
A
T
A
= +85°C
T
A
= +25°C
T
= +25°C
= -40°C
T
= -40°C
A
T
= +85°C
A
T
A
T
A
= +25°C
EXTERNAL CLOCK MODE
AIN1–AIN7 = AGND2
AIN0 = +FS
T
A
= -40°C
4.85
2.1
4.75
4.85
4.95
5.05
(V)
5.15
5.25
4.75
4.85
4.95
5.05
(V)
5.15
5.25
4.75
4.95
5.05
(V)
5.15
5.25
V
V
V
DVDD
AVDD1
AVDD2
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range, C
= 50pF, C
= 50pF; unless otherwise noted.)
DOUT
SSTRB
DIGITAL I/O SUPPLY CURRENT
ANALOG SUPPLY CURRENT
vs. DIGITAL I/O SUPPLY VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
21
20
19
18
17
16
0.46
0.45
0.44
0.43
0.42
0.41
0.40
EXTERNAL CLOCK MODE
DATA RATE = 115ksps
T
= +85°C
A
T
A
= +25°C
= -40°C
T
A
= +85°C
T
A
T
A
= +25°C
T
= -40°C
4.85
A
PARTIAL POWER-DOWN MODE
4.75
4.95
5.05
(V)
5.15
5.25
4.75
4.85
4.95
5.05
(V)
5.15
5.25
V
V
AVDD1
DVDDO
PREAMPLIFIER SUPPLY CURRENT
DIGITAL SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGE
vs. DIGITAL SUPPLY VOLTAGE
0.20
0.18
0.16
0.14
0.12
0.10
0.115
0.114
0.113
0.112
0.111
0.110
PARTIAL POWER-DOWN MODE
AIN1 - AIN7 = AGND2
AIN0 = +FS
PARTIAL POWER-DOWN MODE
T
A
= +85°C
T
A
= +85°C
T
= +25°C
A
T
A
= +25°C
T
A
= -40°C
T
= -40°C
5.05
A
4.75
4.85
4.95
5.15
5.25
4.75
4.85
4.95
5.05
(V)
5.15
5.25
V
(V)
V
DVDD
AVDD2
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range, C
= 50pF, C
= 50pF; unless otherwise noted.)
DOUT
SSTRB
ANALOG SUPPLY CURRENT
vs. CONVERSION RATE
ANALOG SUPPLY CURRENT
vs. CONVERSION RATE
2.39
13.95
13.94
13.93
13.92
13.91
13.90
13.89
13.88
13.87
13.86
13.85
CONTINUOUS EXTERNAL CLOCK MODE
CONTINUOUS EXTERNAL CLOCK MODE
2.38
2.37
2.36
2.35
2.34
2.33
2.32
0
20
40
60
80
100
120
0
20
40
60
80
100
120
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
DIGITAL SUPPLY CURRENT
vs. CONVERSION RATE
DIGITAL I/O SUPPLY CURRENT
vs. CONVERSION RATE
1.0
0.8
0.6
0.4
0.2
0
0.10
0.08
0.06
0.04
0.02
0
CONTINUOUS EXTERNAL CLOCK MODE
CONTINUOUS EXTERNAL CLOCK MODE
0
20
40
60
80
100
120
0
20
40
60
80
100
120
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
Note 7: For partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples.
Partial power-down or full power-down modes were entered thereafter. By using this method, the conversion rate was found
by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down
or full power-down modes.
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range, C
= 50pF, C
= 50pF; unless otherwise noted.)
DOUT
SSTRB
EXTERNAL REFERENCE INPUT CURRENT
vs. EXTERNAL REFERENCE INPUT VOLTAGE
GAIN DRIFT vs. TEMPERATURE
OFFSET DRIFT vs. TEMPERATURE
85
0.10
0.08
0.06
0.04
0.02
0
1.0
0.8
0.6
0.4
0.2
0
83
81
79
77
75
±3 x V
BIPOLAR RANGE
REF
±3 x V
BIPOLAR RANGE
REF
-0.02
-0.04
-0.06
-0.08
-0.10
-0.2
-0.4
-0.6
-0.8
-1.0
(±3 x V )/4 BIPOLAR RANGE
REF
(±3 x V )/4 BIPOLAR RANGE
REF
3.8
3.9
4.0
4.1
4.2
-40
-15
10
35
60
85
-40
-15
10
35
60
85
EXTERNAL REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
CHANNEL-TO-CHANNEL ISOLATION
vs. INPUT FREQUENCY
0
-20
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
2.0
1.5
1.0
0.5
0
f
= 115ksps
f
= 115ksps
f
= 115ksps
SAMPLE
SAMPLE
SAMPLE
±3 x V
CH0 TO CH2
BIPOLAR RANGE
±3 x V
BIPOLAR RANGE
±3 x V
BIPOLAR RANGE
REF
REF
REF
-40
-60
-0.5
-1.0
-1.5
-2.0
-80
-100
-120
1
10
100
1000
10,000
1
10
100
1000
10,000
0
13,107 26,214 39,321 52,428 65,535
DIGITAL OUTPUT CODE
FREQUENCY (kHz)
FREQUENCY (kHz)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
FFT AT 5kHz
2.0
1.5
1.0
0.5
0
0
f
= 115ksps
f
f
= 115ksps
SAMPLE
SAMPLE
IN(SINE WAVE)
±3 x V
BIPOLAR RANGE
= 5kHz
REF
-20
±3 x V
BIPOLAR RANGE
REF
-40
-60
-80
-0.5
-1.0
-1.5
-2.0
-100
-120
-140
0
13,107 26,214 39,321 52,428 65,535
DIGITAL OUTPUT CODE
0
10
20
30
40
50
FREQUENCY (kHz)
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range, C
= 50pF, C
= 50pF; unless otherwise noted.)
DOUT
SSTRB
SNR, SINAD, ENOB
vs. ANALOG INPUT FREQUENCY
SNR, SINAD, ENOB vs. SAMPLE RATE
MAX1300 toc21
MAX1300 toc20
100
80
60
40
20
0
16
14
12
10
8
100
16
15
14
13
12
11
10
9
SNR, SINAD
SNR
90
80
70
60
50
40
30
20
10
0
ENOB
SINAD
ENOB
8
f = 5kHz
IN(SINE WAVE)
f
= 115ksps
SAMPLE
7
±3 x V BIPOLAR RANGE
±3 x V
BIPOLAR RANGE
REF
REF
6
6
0.1
1
10
100
1000
1
10
100
1000
SAMPLE RATE (ksps)
FREQUENCY (kHz)
-SFDR, THD
-SFDR, THD vs. SAMPLE RATE
vs. ANALOG INPUT FREQUENCY
0
-20
0
-20
f
= 5kHz
BIPOLAR RANGE
f
= 115ksps
IN(SINE WAVE)
SAMPLE
±3 x V
±3 x V
BIPOLAR RANGE
REF
REF
-40
-40
-60
-60
-80
-80
THD
-SFDR
-100
-120
-100
-120
THD
-SFDR
100
0.1
1
10
1000
1
10
100
1000
SAMPLE RATE (ksps)
FREQUENCY (kHz)
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
SMALL-SIGNAL BANDWIDTH
1.0
0.6
0
-5
ALL MODES
V
REF
= 4.096V
-10
-15
-20
-25
-30
-35
-40
-45
0.2
-0.2
-0.6
-1.0
-3 x V
(-3 x V )/2
0
(+3 x V )/2 +3 x V
REF
1
10
100
1000
10,000
REF
REF
REF
ANALOG INPUT VOLTAGE (V)
FREQUENCY (kHz)
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
(V
= V
= V
= V
= 5V, V
= V
= V
= V
= V
= 0V, f
= 3.5MHz (50% duty
AVDD1
AVDD2
DVDD
DVDDO
AGND1
DGND
DGNDO
AGND2
AGND3
CLK
cycle), external clock mode, V
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
REF
range, C
= 50pF, C
= 50pF; unless otherwise noted.)
DOUT
SSTRB
FULL-POWER BANDWIDTH
REFERENCE VOLTAGE vs. TIME
MAX1300 toc27
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
1V/div
0V
4ms/div
1
10
100
1000
10,000
FREQUENCY (kHz)
NOISE HISTOGRAM
(CODE EDGE)
NOISE HISTOGRAM
(CODE CENTER)
35,000
30,000
25,000
20,000
15,000
10,000
5,000
0
40,000
35,000
30,000
25,000
20,000
15,000
10,000
5,000
0
65,534 SAMPLES
65,534 SAMPLES
32,785
32,787
32,789
32,774
32,776
32,778
32,780
32,786
32,788
CODE
32,790
32,775
32,777
CODE
32,779
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Pin Description
PIN
NAME
FUNCTION
MAX1300 MAX1301
Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass
AVDD1 to AGND1 with a 0.1µF capacitor.
1
2
AVDD1
2
3
4
5
6
7
8
9
3
4
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Analog Input Channel 0
Analog Input Channel 1
Analog Input Channel 2
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Analog Input Channel 6
Analog Input Channel 7
5
6
—
—
—
—
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the
rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK.
When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance.
10
11
7
8
CS
Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is
high, transitions on DIN are ignored.
DIN
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that
data is ready to be read from the device. When operating in external clock mode, SSTRB is
always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.
12
9
SSTRB
Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT.
When CS is high, transitions on SCLK are ignored.
13
14
10
11
SCLK
DOUT
Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK
transition. When CS is high, DOUT is high impedance.
15
16
12
13
DGNDO Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
DGND Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
Digital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage.
Bypass DVDDO to DGNDO with a 0.1µF capacitor.
17
18
14
15
DVDDO
Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage.
Bypass DVDD to DGND with a 0.1µF capacitor.
DVDD
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD.
REFCAP For internal reference operation, bypass REFCAP with a 0.01µF capacitor to AGND1
19
20
16
17
(V
≈ 4.096V).
REFCAP
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an
external reference voltage from 3.800V to 4.136V to REF. For internal reference operation,
REF
bypassing REF with a 1µF capacitor to AGND1 sets V
= 4.096V ±1%.
REF
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1300 MAX1301
Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to
AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
21
22
18
19
AGND3
AVDD2
AGND2
Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass
AVDD2 to AGND2 with a 0.1µF capacitor.
Analog Ground 2. This ground carries approximately five times more current than AGND1.
DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
23
24
20
1
AGND1 Analog Ground 1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
5.0V
5.0V
5.0V
0.1µF
0.1µF
0.1µF
AVDD2
CHO
AVDD1
DVDD
3.3V
CH1
DVDDO
V
DD
4–20mA
PLC
CH2
0.1µF
MC68HCXX
µC
CH3
ACCELERATION
PRESSURE
MAX1300
CH4
CH5
SCLK
CS
SCK
I/O
TEMPERATURE
WHEATESTONE
WHEATESTONE
CH6
CH7
DIN
MOSI
I/O
REF
SSTRB
DOUT
AGND1
REFCAP
AGND2
MISO
1µF
V
SS
AGND3 DGND DGNDO
0.1µF
Figure 1. Typical Application Circuit
The MAX1300 has eight single-ended analog input chan-
nels or four differential channels (see the Block Diagram
at the end of the data sheet). The MAX1301 has four
single-ended analog input channels or two differential
channels. Each analog input channel is independently
software programmable for seven single-ended input
Detailed Description
The MAX1300/MAX1301 multirange, low-power, 16-bit
successive-approximation ADCs operate from a single
+5V supply and have a separate digital supply allowing
digital interface with 2.7V to 5.25V systems. These 16-bit
ADCs have internal track-and-hold (T/H) circuitry that sup-
ports single-ended and fully differential inputs. For single-
ended conversions, the valid analog input voltage range
ranges [0 to (+3 x V
)/2, (-3 x V
)/2 to 0, 0 to +3 x
REF
REF
V
V
, -3 x V
to 0, (±3 x V
)/4, (±3 x V
)/2, ±3 x
REF
REF
REF
REF
REF
] and three differential input ranges [(±3 x V
)/2,
REF
spans from -3 x V
below ground to +3 x V
above
REF
REF
±3 x V
, ±6 x V
]. Additionally, all analog input chan-
REF
REF
ground. The maximum allowable differential input voltage
spans from -6 x V to +6 x V . Data can be con-
nels are fault tolerant to ±16.5V. A fault condition on an
idle channel does not affect the conversion result of other
channels.
REF
REF
verted in a variety of software-programmable channel and
data-acquisition configurations. Microprocessor (μP) con-
trol is made easy through an SPI-/QSPI-/ MICROWIRE-
compatible serial interface.
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Power Supplies
Track-and-Hold Circuitry
The MAX1300/MAX1301 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for each
operating mode. The MAX1300/MAX1301 analog input
circuitry buffers the input signal from the sampling capaci-
tors, resulting in a constant input impedance with varying
input voltage (Figure 5).
To maintain a low-noise environment, the MAX1300
and MAX1301 provide separate power supplies for
each section of circuitry. Table 1 shows the four sepa-
rate power supplies. Achieve optimal performance using
separate AVDD1, AVDD2, DVDD, and DVDDO supplies.
Alternatively, connect AVDD1, AVDD2, and DVDD togeth-
er as close to the device as possible for a convenient
power connection. Connect AGND1, AGND2, AGND3,
DGND, and DGNDO together as close to the device
as possible. Bypass each supply to the corresponding
ground using a 0.1μF capacitor (Table 1). If significant
low-frequency noise is present, add a 10μF capacitor in
parallel with the 0.1μF bypass capacitor.
Analog Input Circuitry
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2). The
analog input signal source must be capable of driving the
ADC’s 17kΩ input resistance (Figure 6).
Converter Operation
Figure 6 shows the simplified analog input circuit. The ana-
log inputs are ±16.5V fault tolerant and are protected by
The MAX1300/MAX1301 ADCs feature a fully differen-
tial, successive-approximation register (SAR) conversion
technique and an on-chip T/H block to convert voltage
signals into a 16-bit digital result. Both single-ended and
differential configurations are supported with program-
mable unipolar and bipolar signal ranges.
back-to-back diodes. The summing junction voltage, V
,
SJ
is a function of the channel’s input common-mode voltage:
R1
R1
V
=
× 2.375V + 1+
× V
CM
SJ
R1 + R 2
R1 + R 2
As a result, the analog input impedance is relatively con-
stant over input voltage as shown in Figure 5.
Table 1. MAX1300/MAX1301 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)
CIRCUIT SECTION
BYPASSING
DVDDO/DGNDO
AVDD2/AGND2
AVDD1/AGND1
DVDD/DGND
2.7 to 5.25
4.75 to 5.25
4.75 to 5.25
4.75 to 5.25
0.03
135
3.0
Digital I/O
0.1µF to DGNDO
0.1µF to AGND2
0.1µF to AGND1
0.1µF to DGND
Analog Circuitry
Analog Circuitry
0.8
Digital Control Logic and Memory
Table 2. Analog Input Configuration Byte
BIT
NUMBER
NAME
DESCRIPTION
7
6
5
4
START
C2
Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
C1
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
C0
Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended
DIF/SGL mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
3
2
1
0
R2
R1
R0
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32
SCLK
BYTE 2
BYTE 3
BYTE 4
BYTE 1
SSTRB
S
C2 C1 C0
0
0
0
0
DIN
f
f
/ 32
SAMPLE SCLK
SAMPLING INSTANT
t
ACQ
ANALOG INPUT
TRACK AND HOLD*
HOLD
TRACK
HOLD
HIGH
IMPEDANCE
HIGH
IMPEDANCE
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DOUT
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
Figure 2. External Clock-Mode Conversion (Mode 0)
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
Analog Input Bandwidth
The MAX1300/MAX1301 input-tracking circuitry has a
2MHz small-signal bandwidth. The 2MHz input band-
width makes it possible to digitize high-speed transient
events. Harmonic distortion increases when digitizing
signal frequencies above 15kHz as shown in the THD and
-SFDR vs. Input Frequency plot in the Typical Operating
Characteristics.
For example, to configure CH2 and CH3 for a ±3 x V
REF
differential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±3 x V range
REF
(1010 1100). To initiate a conversion for the CH2 and CH3
differential pair, issue the command 1010 0000.
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable single-ended
analog input voltage range that produces a valid digital
output. Each analog input channel can be independently
programmed to one of seven single-ended input ranges
by setting the R[2:0] control bits with DIF/SGL = 0.
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
CS
SSTRB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCLK
BYTE 1
BYTE 2
BYTE 3
BYTE 4
S
C2 C1 C0
0
0
0
0
DIN
HIGH IMPEDANCE
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DOUT
f
f
/ 32 + f
/ 17
INTCLK
SAMPLE SCLK
SAMPLING INSTANT
t
ACQ
ANALOG INPUT
TRACK AND HOLD*
HOLD
TRACK
HOLD
100ns to 400ns
1
2
3
14
15
16
17
INTCLK**
f
4.5MHz
INTCLK
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
Figure 3. External Acquisition-Mode Conversion (Mode 1)
Figure 8 illustrates the software-selectable differential
analog input voltage range that produces a valid digital
output. Each analog input differential pair can be inde-
pendently programmed to one of three differential input
ranges by setting the R[2:0] control bits with DIF/SGL = 1.
range, applied to an analog input results in a full-scale
output voltage for that channel.
Clamping diodes with breakdown thresholds in excess of
16.5V protect the MAX1300/MAX1301 analog inputs dur-
ing ESD and other transient events (Figure 6). The clamp-
ing diodes do not conduct during normal device opera-
tion, nor do they limit the current during such transients.
When operating in an environment with the potential for
high-energy voltage and/or current transients, protect the
MAX1300/MAX1301 externally.
Regardless of the specified input voltage range and
whether the channel is selected, each analog input is
±16.5V fault tolerant. The analog input fault protection is
active whether the device is unpowered or powered. Any
voltage beyond FSR, but within the ±16.5V fault tolerant
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
CS
SSTRB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SCLK
BYTE 1
BYTE 2
BYTE 3
S
C2 C1 C0
0
0
0
0
DIN
HIGH IMPEDANCE
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DOUT
f
f
/ 24 + f
/ 28
INTCLK
SAMPLE SCLK
SAMPLING INSTANT
t
ACQ
ANALOG INPUT
TRACK AND HOLD*
HOLD
TRACK
HOLD
100ns to 400ns
1
2
3
10
11
12
13
14
25
26
27
28
INTCLK**
f
4.5MHz
INTCLK
*TRACK AND HOLD TIMING IS CONTROLLED BY INTCLK, AND IS NOT ACCESSIBLE TO THE USER.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
Figure 4. Internal Clock-Mode Conversion (Mode 2)
R2
MAX1300
MAX1301
1.0
*R
SOURCE
R1
ALL MODES
IN_+
0.6
0.2
ANALOG
SIGNAL
SOURCE
V
SJ
R2
-0.2
-0.6
-1.0
*R
R1
SOURCE
IN_+
ANALOG
SIGNAL
SOURCE
V
SJ
-3 x V
(-3 x V )/2
0
+3 x V
(+3 x V )/2
REF
REF
REF
REF
ANALOG INPUT VOLTAGE (V)
*MINIMIZE R
TO AVOID GAIN ERROR AND DISTORTION.
SOURCE
Figure 5. Analog Input Current vs. Input Voltage
Figure 6. Simplified Analog Input Circuit
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8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Table 3. Input Data Word Formats
DATA BIT
OPERATION
D7
(START)
D6
C2
C2
M2
D5
C1
C1
M1
D4
C0
C0
M0
D3
D2
D1
0
D0
0
Conversion-Start Byte
(Tables 4 and 5)
1
1
1
0
0
R2
0
Analog-Input Configuration Byte
R1
0
R0
0
DIF/SGL
(Table 2)
Mode-Control Byte
1
(Table 7)
Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0)
CHANNEL-SELECT BIT
CHANNEL
CH4
C2
0
C1
0
C0
0
CH0
CH1
CH2
CH3
CH5
CH6
CH7
AGND1
+
-
-
-
-
-
-
-
-
0
0
1
+
0
1
0
+
0
1
1
+
1
0
0
+
1
0
1
+
1
1
0
+
1
1
1
+
Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)
CHANNEL-SELECT BIT
CHANNEL
CH4
C2
0
C1
0
C0
0
CH0
CH1
CH2
CH3
CH5
CH6
CH7
AGND1
+
-
0
0
1
RESERVED
0
1
0
+
-
0
1
1
RESERVED
+
1
0
0
-
1
0
1
RESERVED
1
1
0
+
-
1
1
1
RESERVED
The range-select bits R[2:0] in the analog input con-
figuration bytes determine the full-scale range for the
corresponding channel (Tables 2 and 6). Figures 9, 10,
and 11 show the valid analog input voltage ranges for
the MAX1300/MAX1301 when operating with FSR = (±3
Differential Common-Mode Range
The MAX1300/MAX1301 differential common-mode
range (V ) must remain within -14V to +10V to obtain
CMDR
valid conversion results. The differential common-mode
range is defined as:
x V
)/2, FSR = ±3 x V
, and FSR = ±6 x V
,
REF
REF
REF
CH_+ + CH_−
(
)
(
)
respectively. The shaded area contains the valid com-
mon-mode voltage ranges that support the entire FSR.
V
=
CMDR
2
In addition to the common-mode input voltage limitations,
each individual analog input must be limited to ±16.5V
with respect to AGND1.
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8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
+3 x V
+6 x V
+3 x V
REF
REF
(+3 x V )/2
REF
REF
0
0
(-3 x V )/2
-3 x V
-6 x V
REF
REF
REF
-3 x V
REF
INPUT RANGE SELECTION BITS, R[2:0]
INPUT RANGE SELECTION BITS, R[2:0]
EACH INPUT IS FAULT TOLERANT TO 16.5V.
EACH INPUT IS FAULT TOLERANT TO 16.5V.
V
= 4.096V.
V
REF
= 4.096V.
REF
Figure 7. Single-Ended Input Voltage Ranges
Figure 8. Differential Input Voltage Ranges
Chip Select (CS)
Digital Interface
CS enables communication with the MAX1300/MAX1301.
When CS is low, data is clocked into the device from DIN
on the rising edge of SCLK and data is clocked out of
DOUT on the falling edge of SCLK. When CS is high,
activity on SCLK and DIN is ignored and DOUT is high
impedance allowing DOUT to be shared with other periph-
erals. SSTRB is never high impedance and therefore can-
not be shared with other peripherals.
The MAX1300/MAX1301 feature a serial interface that
is compatible with SPI/QSPI and MICROWIRE devices.
DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirectional
communication between the MAX1300/MAX1301 and
the master at SCLK rates up to 10MHz (internal clock
mode, mode 2), 3.67MHz (external clock mode, mode
0), or 4.39MHz (external acquisition mode, mode 1). The
master, typically a microcontroller, should use the CPOL =
0, CPHA = 0, SPI transfer format, as shown in the timing
diagrams of Figures 2, 3, and 4.
Serial Strobe Output (SSTRB)
As shown in Figures 3 and 4, the SSTRB transitions high
to indicate that the ADC has completed a conversion
and results are ready to be read by the master. SSTRB
remains low in the external clock mode (Figure 2) and
consequently may be left unconnected. SSTRB is driven
high or low regardless of the state of CS, therefore SSTRB
cannot be shared with other peripherals.
The digital interface is used to:
•
Select single-ended or true-differential input channel
configurations
•
•
Select the unipolar or bipolar input range
Select the mode of operation:
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
•
Initiate conversions and read results
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Table 6. Range-Select Bits
R2
R1
R0
MODE
TRANSFER FUNCTION
DIF/SGL
0
0
0
0
No Range Change*
—
Single-Ended
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
Bipolar (-3 x V
Full-Scale Range (FSR) = (3 x V
)/4 to (+3 x V
)/4
Figure 12
Figure 13
Figure 14
Figure 12
Figure 13
Figure 14
REF
REF
)/2
REF
Single-Ended
Unipolar (-3 x V
)/2 to 0
REF
FSR = (3 x V
)/2
REF
Single-Ended
Unipolar 0 to (+3 x V
FSR = (+3 x V
)/2
REF
)/2
REF
Single-Ended
Bipolar (-3 x V
)/2 to (+3 x V
)/2
REF
REF
FSR = 3 x V
REF
Single-Ended
Unipolar -3 x V
to 0
REF
REF
FSR = 3 x V
Single-Ended
Unipolar 0 to +3 x V
REF
FSR = 3 x V
REF
DEFAULT SETTING
Single-Ended
0
1
1
1
Figure 12
Bipolar -3 x V
to +3 x V
REF
REF
FSR = 6 x V
REF
1
1
0
0
0
0
0
1
No Range Change**
Differential
—
Bipolar (-3 x V
)/2 to (+3 x V
)/2
Figure 12
REF
REF
FSR = 3 x V
REF
1
1
0
0
1
1
0
1
Reserved
Reserved
—
—
Differential
1
1
0
0
Bipolar -3 x V
to +3 x V
Figure 12
REF
REF
FSR = 6 x V
REF
1
1
1
1
0
1
1
0
Reserved
Reserved
—
—
Differential
1
1
1
1
Bipolar -6 x V
FSR = 12 x V
to +6 x V
Figure 12
REF
REF
REF
*Conversion-Start Byte (see Table 3).
**Mode-Control Byte (see Table 3).
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
12
8
12
8
4
4
0
0
-4
-8
-12
-16
-4
-8
-12
-16
-18
-12
-6
0
6
12
18
-18
-12
-6
0
6
12
18
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = 3 x V
)
Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 6 x V
)
REF
REF
Output Data Format
12
8
Output data is clocked out of DOUT in offset binary format
on the falling edge of SCLK, MSB first (B15). For output
binary codes, see the Transfer Function section and
Figures 12, 13, and 14.
4
0
Configuring Analog Inputs
-4
-8
-12
-16
Each analog input has two configurable parameters:
•
•
Single-ended or true-differential input
Input voltage range
These parameters are configured using the analog input
configuration byte as shown in Table 2. Each analog input
has a dedicated register to store its input configuration
information. The timing diagram of Figure 15 shows how
to write to the analog input configuration registers. Figure
16 shows DOUT and SSTRB timing.
-18
-12
-6
0
6
12
18
INPUT VOLTAGE (V)
Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 12 x V
)
REF
Start Bit
Transfer Function
Communication with the MAX1300/MAX1301 is accom-
plished using the three input data word formats shown in
Table 3. Each input data word begins with a start bit. The
start bit is defined as the first high bit clocked into DIN with
CS low when any of the following are true:
An ADC’s transfer function defines the relationship
between the analog input voltage and the digital out-
put code. Figures 12, 13, and 14 show the MAX1300/
MAX1301 transfer functions. The transfer function is
determined by the following characteristics:
•
Data conversion is not in process and all data from the
previous conversion has clocked out of DOUT.
•
•
•
Analog input voltage range
Single-ended or differential configuration
Reference voltage
•
The device is configured for operation in external clock
mode (mode 0) and previous conversion-result bits
B15–B3 have clocked out of DOUT.
The axes of an ADC transfer function are typically in least
significant bits (LSBs). For the MAX1300/MAX1301, an
LSB is calculated using the following equation:
•
•
The device is configured for operation in external
acquisition mode (mode 1) and previous conversion-
result bits B15–B7 have clocked out of DOUT.
FSR × V
REF
1 L S B =
The device is configured for operation in internal clock
mode, (mode 2) and previous conversion result bits
B15–B4 have clocked out of DOUT.
N
2
× 4.096V
where N is the number of bits (N = 16) and FSR is the
full-scale range (see Figures 7 and 8).
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8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
FSR
FFFF
FFFE
FFFD
FSR
FFFF
FFFE
FFFD
8001
8000
7FFF
8001
8000
7FFF
0003
0002
0001
0000
0003
0002
0001
0000
FSR x V
REF
65,536 x 4.096V
1 LSB =
FSR x V
REF
65,536 x 4.096V
1 LSB =
-32,768 -32,766
-1
0
+1
+32,765 +32,767
0
1
2
3
32,768
INPUT VOLTAGE (LSB [DECIMAL])
65,533 65,535
(AGND1)
AGND1 (DIF/SGL = 0)
OV (DIF/SGL = 1)
INPUT VOLTAGE (LSB [DECIMAL])
Figure 12. Ideal Bipolar Transfer Function, Single-Ended or
Differential Input
Figure 13. Ideal Unipolar Transfer Function, Single-Ended
Input, -FSR to 0
Selecting the Conversion Method
FSR
The conversion method is selected using the mode-con-
trol byte (see the Mode Control section), and the conver-
sion is initiated using a conversion-start command (Table
3, and Figures 2, 3, and 4).The MAX1300/MAX1301
convert analog signals to digital data using one of three
methods:
FFFF
FFFE
FFFD
8001
8000
7FFF
•
•
External Clock Mode, Mode 0 (Figure 2)
• Highest maximum throughput (see the Electrical
Characteristics table)
• User controls the sample instant
• CS remains low during the conversion
0003
FSR x V
REF
65,536 x 4.096V
0002
0001
0000
1 LSB =
•
User supplies SCLK throughout the ADC conversion
and reads data at DOUT
External Acquisition Mode, Mode 1 (Figure 3)
• Lowest maximum throughput (see the Electrical
Characteristics table)
0
1
2
3
32,768
INPUT VOLTAGE (LSB [DECIMAL])
65,533 65,535
(AGND1)
• User controls the sample instant
Figure 14. Ideal Unipolar Transfer Function, Single-Ended
Input, 0 to +FSR
• User supplies two bytes of SCLK, then drives
CS high to relieve processor load while the ADC
converts
• After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
Mode Control
The MAX1300/MAX1301 contain one byte-wide mode-
control register. The timing diagram of Figure 15 shows
how to use the mode-control byte, and the mode-control
byte format is shown in Table 7. The mode-control byte is
used to select the conversion method and to control the
power modes of the MAX1300/MAX1301.
• Internal Clock Mode, Mode 2 (Figure 4)
• High maximum throughput (see the Electrical
Characteristics table)
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8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
t
CSPW
t
CSS
CS
t
CL
t
t
CSH
CH
SCLK
DIN
1
8
1
8
t
CP
t
DS
t
DH
START
SEL2
SEL1
SEL0 DIF/SGL
R2
R1
R0
START
M2
M1
M0
1
0
0
0
ANALOG INPUT CONFIGURATION BYTE
MODE CONTROL BYTE
t
t
TR
DV
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
DOUT
Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing
•
After SSTRB transitions high, the user supplies two
bytes of SCLK and reads data at DOUT
SSTRB
External Clock Mode (Mode 0)
t
SSCS
The MAX1300/MAX1301’s fastest maximum throughput
rate is achieved operating in external clock mode. SCLK
controls both the acquisition and conversion of the analog
signal, facilitating precise control over when the analog
signal is captured. The analog input sampling instant is at
the falling edge of the 14th SCLK (Figure 2).
CS
SCLK
DOUT
t
CSS
t
DO
Since SCLK drives the conversion in external clock mode,
the SCLK frequency should remain constant while the
conversion is clocked. The minimum SCLK frequency
prevents droop in the internal sampling capacitor voltages
during conversion.
HIGH
IMPEDANCE
MSB
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
Figure 16. DOUT and SSTRB Timing
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1300/ MAX1301
will always be used in the external clock mode.
•
•
The internal clock controls the sampling instant
User supplies one byte of SCLK, then drives CS high
to relieve processor load while the ADC converts
Table 7. Mode-Control Byte
BIT NUMBER
BIT NAME
DESCRIPTION
7
6
5
4
3
2
1
0
START
Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
M2
M1
M0
1
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
Bit 3 must be a logic 1 for the mode-control byte.
Bit 2 must be a logic 0 for the mode-control byte.
Bit 1 must be a logic 0 for the mode-control byte.
Bit 0 must be a logic 0 for the mode-control byte.
0
0
0
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8- and 4-Channel, ±3 x V
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Table 8. Mode-Control Bits M[2:0]
M2
0
M1
0
M0
0
MODE
External Clock (DEFAULT)
0
0
1
External Acquisition
Internal Clock
Reserved
0
1
0
0
1
1
1
0
0
Reset
1
0
1
Reserved
1
1
0
Partial Power-Down
Full Power-Down
1
1
1
External Acquisition Mode (Mode 1)
Reset (Mode 4)
The slowest maximum throughput rate is achieved with
the external acquisition method. SCLK controls the acqui-
sition of the analog signal in external acquisition mode,
facilitating precise control over when the analog signal is
captured. The internal clock controls the conversion of the
analog input voltage. The analog input sampling instant is
at the falling edge of the 16th SCLK (Figure 3).
As shown in Table 8, set M[2:0] = 100 to reset the
MAX1300/MAX1301 to its default conditions. The default
conditions are full power operation with each channel
configured for ±3 x V
, bipolar, single-ended conver-
REF
sions using external clock mode (mode 0).
Partial Power-Down Mode (Mode 6)
As shown in Table 8, when M[2:0] = 110, the device enters
partial power-down mode. In partial power-down, all ana-
log portions of the device are powered down except for
the reference voltage generator and bias supplies.
For the external acquisition mode, CS must remain low
for the first 15 clock cycles and the rise on or after the
falling edge of the 16th SCLK cycle as shown in Figure 3.
For optimal performance, idle DIN and SCLK during the
conversion. With careful board layout, transitions at DIN
and SCLK during the conversion have a minimal impact
on the conversion result.
To exit partial power-down, change the mode by issuing
one of the following mode-control bytes (see the Mode
Control section):
•
•
•
•
•
External-Clock-Mode Control Byte
External-Acquisition-Mode Control Byte
Internal-Clock-Mode Control Byte
Reset Byte
After the conversion is complete, SSTRB asserts high
and CS can be brought low to read the conversion result.
SSTRB returns low on the rising SCLK edge of the sub-
sequent start bit.
Internal Clock Mode (Mode 2)
Full Power-Down-Mode Control Byte
In internal clock mode, the internal clock controls both
acquisition and conversion of the analog signal. The inter-
nal clock starts approximately 100ns to 400ns after the
falling edge of the eighth SCLK and has a rate of about
4.5MHz. The analog input sampling instant occurs at the
falling edge of the 11th internal clock signal (Figure 4).
This prevents the MAX1300/MAX1301 from inadvertently
exiting partial power-down mode because of a CS glitch
in a noisy digital environment.
Full Power-Down Mode (Mode 7)
When M[2:0] = 111, the device enters full power-down
mode and the total supply current falls to 1μA (typ). In full
power-down, all analog portions of the device are powered
down. When using the internal reference, upon exiting full
power-down mode, allow 10ms for the internal reference
voltage to stabilize prior to initiating a conversion.
For the internal clock mode, CS must remain low for the
first seven SCLK cycles and then rise on or after the fall-
ing edge of the eighth SCLK cycle. After the conversion
is complete, SSTRB asserts high and CS can be brought
low to read the conversion result. SSTRB returns low on
the rising SCLK edge of the subsequent start bit.
To exit full power-down, change the mode by issuing one
of the following mode-control bytes (see the Mode Control
section):
•
External-Clock-Mode Control Byte
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8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
•
•
•
•
External-Acquisition-Mode Control Byte
Internal-Clock-Mode Control Byte
Reset Byte
External Reference
For external reference operation, disable the internal
reference and reference buffer by connecting REFCAP
to AVDD1. With AVDD1 connected to REFCAP, REF
becomes a high-impedance input and accepts an external
reference voltage. The MAX1300/MAX1301 can accept
an external reference voltage of 4.096V or less. However,
to meet all of the electrical characteristic specifications,
Partial Power-Down-Mode Control Byte
This prevents the MAX1300/MAX1301 from inadvertently
exiting full power-down mode because of a CS glitch in a
noisy digital environment.
V
must be > 38V. The MAX1300/ MAX1301 external
REF
Power-On Reset
reference current varies depending on the applied refer-
ence voltage and the operating mode (see the External
Reference Input Current vs. External Reference Input
Voltage graph in the Typical Operating Characteristics).
The MAX1300/MAX1301 power up in normal operation
configured for external clock mode with all circuitry active
(Tables 7 and 8). Each analog input channel (CH0–CH7) is
set for single-ended conversions with a ±3 x V
input range (Table 6).
bipolar
REF
Applications Information
Allow the power supplies to stabilize after power-up. Do not
initiate any conversions until the power supplies have sta-
bilized. Additionally, allow 10ms for the internal reference to
Noise Reduction
Additional samples can be taken and averaged (oversam-
pling) to remove the effect of transition noise on conver-
sion results. The square root of the number of samples
stabilize when C
= 1.0μF and C = 0.1μF. Larger
REF
REFCAP
reference capacitors require longer stabilization times.
determines the improvement in performance. For example,
2
with 2/3LSB
(4LSB ) transition noise, 16 (4 = 16)
P-P
Internal or External Reference
RMS
samples must be taken to reduce the noise to 1LSB
.
P-P
The MAX1300/MAX1301 operate with either an internal
or external reference. The reference voltage impacts the
ADC’s FSR (Figures 12, 13, and 14). An external refer-
ence is recommended if more accuracy is required than
the internal reference provides, and/or multiple converters
require the same reference voltage.
Interface with 0 to 10V Signals
In industrial control applications, 0 to 10V signaling is
common. For 0 to 10V applications, configure the selected
MAX1300/MAX1301 input channel for the single-ended 0
to 3 x V
input range (R[2:0] = 110, Table 6). The 0 to 3
REF
Internal Reference
x V
range accommodates 0 to 10V where the signals
REF
saturate at approximately 3 x V
if out of range.
The MAX1300/MAX1301 contain an internal 4.096V
bandgap reference. This bandgap reference is connected
to REFCAP through a nominal 5kΩ resistor (Figure 17).
The voltage at REFCAP is buffered creating 4.096V at
REF. When using the internal reference, bypass REFCAP
with a 0.1μF or greater capacitor to AGND1 and bypass
REF with a 1.0μF or greater capacitor to AGND1.
REF
Interface with 4–20mA Signals
Figure 19 illustrates a simple interface between the
MAX1300/MAX1301 and a 4–20mA signal. 4–20mA sig-
naling can be used as a binary switch (4mA represents
a logic-low signal, 20mA represents a logic-high signal),
or for precision communication where currents between
4mA and 20mA represent intermediate analog data. For
binary switch applications, connect the 4–20mA signal
to the MAX1300/MAX1301 with a resistor to ground. For
example, a 250Ω resistor converts the 4–20mA signal to
a 1V to 5V signal. Adjust the resistor value so the parallel
combination of the resistor and the MAX1300/MAX1301
source impedance is 250Ω. In this application, select the
4.096V
REF
SAR
ADC
REF
1.0µF
0.1µF
1x
REFCAP
MAX1300
MAX1301
single-ended 0 to (3 x V
)/2 range (R[2:0] = 011, Table
REF
5kΩ
6). For applications that require precision measurements
of continuous analog currents between 4mA and 20mA,
use a buffer to prevent the MAX1300/MAX1301 input from
diverting current from the 4–20mA signal.
V
RCTH
4.096V
BANDGAP
REFERENCE
AGND1
Figure 17. Internal Reference Operation
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Serial 16-Bit ADCs
V+
IN
1.0µF
4.096V
REF
SAR
OUT
REF
ADC
1.0µF
MAX6341
AV
DD1
1x
GND
REFCAP
MAX1300
MAX1301
5kΩ
V
RCTH
4.096V
BANDGAP
REFERENCE
AGND1
Figure 18. External Reference Operation
Bridge Application
Layout, Grounding, and Bypassing
The MAX1300/MAX1301 convert 1kHz signals more
accurately than a similar sigma-delta converter that might
be considered in bridge applications. The input impedance
of the MAX1300, in combination with the current-limiting
resistors, can affect the gain of the MAX1300. In many
applications this error is acceptable, but for applications
that cannot tolerate this error, the MAX1300 inputs can be
buffered (Figure 20). Connect the bridge to a low-offset
differential amplifier and then the true-differential inputs of
the MAX1300/MAX1301. Larger excitation voltages take
Careful PCB layout is essential for best system perfor-
mance. Boards should have separate analog and digital
ground planes and ensure that digital and analog signals
are separated from each other. Do not run analog and
digital (especially clock) lines parallel to one another, or
digital lines underneath the device package.
Figure 1 shows the recommended system ground con-
nections. Establish an analog ground point at AGND1
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground plane to the analog ground plane at one point.
For lowest noise operation, make the ground return to the
star ground’s power-supply low impedance and as short
as possible.
advantage of more of the (±3 x V
)/4 differential input
REF
voltage range. Select an input voltage range that matches
the amplifier output. Be aware of the amplifier offset and
offset-drift errors when selecting an appropriate amplifier.
Dynamically Adjusting the Input Range
High-frequency noise in the AVDD1 power supply
degrades the ADC’s high-speed comparator performance.
Bypass AVDD1 to AGND1 with a 0.1μF ceramic surface-
mount capacitor. Make bypass capacitor connections as
short as possible.
Software control of each channel’s analog input range
and the unipolar endpoint overlap specification make it
possible for the user to change the input range for a chan-
nel dynamically and improve performance in some appli-
cations. Changing the input range results in a small LSB
step-size over a wider output voltage range. For example,
Parameter Definitions
by switching between a (-3 x V
)/2 to 0V range and a 0
REF
to (+3 x V
)/2 range, an LSB is
REF
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. This straight line is either a
best straight-line fit or a line drawn between the endpoints
of the transfer function once offset and gain errors have
been nullified. The MAX1300/MAX1301 INL is measured
using the endpoint method.
(+3× V
) / 2× V
REF
REF
65,536× 4.096
but the input voltage range effectively spans from (-3 x
V
REF
)/2 to (+3 x V )/2 (FSR = 3 x V ).
REF
REF
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
4–20mA INPUT
CH0
µC
250Ω
MAX1300
4–20mA INPUT
CH8
250Ω
Figure 19. 4–20mA Application
LOW-OFFSET
CH0
DIFFERENTIAL
µP
CH1
AMPLIFIER
MAX1300
MAX1301
REF
BRIDGE
Figure 20. Bridge Application
Differential Nonlinearity (DNL)
Channel-to-Channel Isolation
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
greater than -1 LSB guarantees no missing codes and a
monotonic transfer function.
Channel-to-channel isolation indicates how well each
analog input is isolated from the others. The channel-
to-channel isolation for these devices is measured by
applying a near full-scale magnitude 5kHz sine wave
to the selected analog input channel while applying an
equal magnitude sine wave of a different frequency to all
unselected channels. An FFT of the selected channel out-
put is used to determine the ratio of the magnitudes of the
signal applied to the unselected channels and the 5kHz
signal applied to the selected analog input channel. This
ratio is reported, in dB, as channel-to-channel isolation.
Transition Noise
Transition noise is the amount of noise that appears at a
code transition on the ADC transfer function. Conversions
performed with the analog input right at the code transi-
tion can result in code flickering in the LSBs.
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Full-Power Bandwidth
Unipolar Offset Error
-FSR to 0V
A 95% of full-scale sine wave is applied to the ADC, and
the input frequency is then swept up to the point where
the amplitude of the digitized conversion result has
decreased by -3dB.
When a zero-scale analog input voltage is applied to the
converter inputs, the digital output is all ones (0xFFFF).
Ideally, the transition from 0xFFFF to 0xFFFE occurs at
AGND1 - 0.5 LSB. Unipolar offset error is the amount
of deviation between the measured zero-scale transition
point and the ideal zero-scale transition point, with all
untested channels grounded.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ability of a device to reject a signal that is
“common” to or applied to both input terminals. The com-
mon-mode signal can be either an AC or a DC signal or
a combination of the two. CMR is expressed in decibels.
Common-mode rejection ratio is the ratio of the differen-
tial signal gain to the common-mode signal gain. CMRR
applies only to differential operation.
0V to +FSR
When a zero-scale analog input voltage is applied to the
converter inputs, the digital output is all zeros (0x0000).
Ideally, the transition from 0x0000 to 0x0001 occurs at
AGND1 + 0.5 LSB. Unipolar offset error is the amount
of deviation between the measured zero-scale transition
point and the ideal zero-scale transition point, with all
untested channels grounded.
Power-Supply Rejection Ratio (PSRR)
PSRR is the ratio of the output-voltage shift to the
power-supply-voltage shift for a fixed input voltage. For
the MAX1300/MAX1301, AV
can vary from 4.75V to
DD1
5.25V. PSRR is expressed in decibels and is calculated
using the following equation:
Bipolar Offset Error
When a zero-scale analog input voltage is applied to the
converter inputs, the digital output is a one followed by
5.25V − 4.75V
all zeros (0x8000). Ideally, the transition from 0x7FFF to
PSRR[dB] = 20× log
N-1
V
(5.25V) − V
(4.75V)
OUT
0x8000 occurs at (2
- 0.5)LSB. Bipolar offset error is
OUT
the amount of deviation between the measured midscale
transition point and the ideal midscale transition point,
with untested channels grounded.
For the MAX1300/MAX1301, PSRR is tested in bipolar
operation with the analog inputs grounded.
Aperture Jitter
Gain Error
Aperture jitter, t , is the statistical distribution of the
variation in the sampling instant (Figure 21).
When a positive full-scale voltage is applied to the con-
verter inputs, the digital output is all ones (0xFFFF). The
transition from 0xFFFE to 0xFFFF occurs at 1.5 LSB
below full scale. Gain error is the amount of deviation
between the measured full-scale transition point and
the ideal full-scale transition point with the offset error
removed and all untested channels grounded.
AJ
Aperture Delay
Aperture delay, t , is the time from the falling edge of
AD
SCLK to the sampling instant (Figure 21).
Signal-to-Noise Ratio (SNR)
Unipolar Endpoint Overlap
SNR is computed by taking the ratio of the RMS signal to
the RMS noise. RMS noise includes all spectral compo-
nents to the Nyquist frequency excluding the fundamen-
tal, the first five harmonics, and the DC offset.
Unipolar endpoint overlap is the change in offset when
switching between complementary input voltage ranges.
For example, the difference between the voltage that
results in a 0xFFFF output in the -3 x V
voltage range and the voltage that results in a 0x0000
/2 to 0V input
REF
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal
to the RMS noise plus distortion. RMS noise plus dis-
tortion includes all spectral components to the Nyquist
frequency excluding the fundamental and the DC offset.
output in the 0 to +3 x V /2 input voltage range is the
REF
unipolar endpoint overlap. The unipolar endpoint overlap
is positive for the MAX1300/MAX1301, preventing loss of
signal or a dead zone when switching between adjacent
analog input voltage ranges.
Signal
Noise
RMS
RMS
SINAD(dB) = 20× log
Small-Signal Bandwidth
A 100mV
sine wave is applied to the ADC, and the
P-P
input frequency is then swept up to the point where
the amplitude of the digitized conversion result has
decreased by -3dB.
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. With an input
range equal to the ADC’s full-scale range, calculate the
ENOB as follows:
SCLK
(MODE 0)
14
15
13
SCLK
(MODE 1)
16
11
15
10
SINAD − 1.76
ENOB =
6.02
INTCLK
(MODE 2)
12
Total Harmonic Distortion (THD)
For the MAX1300/MAX1301, THD is the ratio of the RMS
sum of the input signal’s first four harmonic components
to the fundamental itself. This is expressed as:
t
AJ
t
AD
SAMPLE INSTANT
HOLD
2
2
2
2
ANALOG INPUT
TRACK AND HOLD
V
+ V + V + V
3 4 5
2
TRACK
THD = 20× log
V
1
Figure 21. Aperture Diagram
where V is the fundamental amplitude, and V through V
5
1
2
are the amplitudes of the 2nd- through 5th-order harmonic
components.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next-largest spectral component.
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Block Diagram
DVDDO
CS
DIN
CONTROL LOGIC AND REGISTERS
SERIAL I/O
SSTRB
DOUT
SCLK
DGNDO
CH0
CH1
AV
DD2
CLOCK
DVDD
ANALOG
INPUT MUX
AND
MULTIRANGE
CIRCUITRY
CH2
CH3
CH4
CH5
CH6
SAR
ADC
IN
OUT
FIFO
PGA
DGND
AVDD1
AGND3
REF
CH7
AGND1
AGND2
5kΩ
4.096V
BANDGAP
REFERENCE
1x
AVDD2
AGND2
MAX1300
REFCAP
REF
Pin Configurations (continued)
Chip Information
PROCESS: BiCMOS
TOP VIEW
AGND1
AVDD1
CH0
1
2
3
4
5
6
7
8
9
20 AGND2
19 AVDD2
18 AGND3
17 REF
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
CH1
MAX1301
CH2
16 REFCAP
15 DVDD
CH3
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
CS
14
DVDDO
PATTERN NO.
DIN
13 DGND
12 DGNDO
11 DOUT
20 TSSOP
24 TSSOP
U20+2
U24+1
90-0116
90-0118
SSTRB
21-0066
SCLK 10
TSSOP
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MAX1300/MAX1301
8- and 4-Channel, ±3 x V
Multirange Inputs,
REF
Serial 16-Bit ADCs
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES CHANGED
0
2
3
11/06
6/10
Initial release
1
1–10, 13, 14, 15, 17–21,
24, 25, 26, 28, 31
Updated Electrical Characteristics tables, TOCs to optimize yield.
Released MAX1300 and updated the Electrical Characteristics table.
12/11
1, 2
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2011 Maxim Integrated Products, Inc.
│ 31
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