MAX13032EEBE+T [MAXIM]
Interface Circuit, BICMOS, PBGA16, 2 X 2 MM, LEAD FREE, UCSP-16;
| 型号： | MAX13032EEBE+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Interface Circuit, BICMOS, PBGA16, 2 X 2 MM, LEAD FREE, UCSP-16 信息通信管理 |
| 文件： | 总20页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0626; Rev 0; 1/07
6-Channel High-Speed Logic-Level Translators
–MAX1035E
General Description
Features
The MAX13030E–MAX13035E 6-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13030E–MAX13035E are ideally suited for memo-
ry-card level translation, as well as generic level trans-
lation in systems with six channels. Externally applied
o Compatible with 4mA Input Drivers or Larger
o 100Mbps Guaranteed Data Rate
o Six Bidirectional Channels
o Clock Return Output (MAX13035E)
o Enable Input (MAX13030E–MAX13034E)
voltages, V
and V , set the logic levels on either side
L
CC
of the device. Logic signals present on the V side of
L
o
15kꢀ ESD ꢁrotection on IꢂO ꢀ
Lines
the device appear as a higher voltage logic signal on
CC
the V
side of the device and vice versa. The
CC
o +1.62ꢀ ≤ ꢀ ≤ +3.2ꢀ and +2.2ꢀ ≤ ꢀ
≤ +3.6ꢀ
L
CC
MAX13035E features a CLK_RET output that returns the
Supply ꢀoltage Range
same clock signal applied to the CLK_V input.
L
o Lead-Free, 16-Bump UCSꢁ (2mm x 2mm) and
The MAX13030E–MAX13035E operate at full speed
with external drivers that source as little as 4mA output
16-pin TQFN (4mm x 4mm) ꢁackages
current. Each I/O channel is pulled up to V
or V by
L
CC
an internal 30µA current source, allowing the
MAX13030E–MAX13035E to be driven by either push-
pull or open-drain drivers.
Typical Operating Circuits
The MAX13030E–MAX13034E feature an enable (EN)
input that places the device into a low-power shutdown
mode when driven low. The MAX13030E–MAX13035E
features an automatic shutdown mode that disables the
+3.3V
+1.8V
0.1μF
0.1μF
1μF
part when V
is less than V . The state of I/O V
L CC_
CC
V
V
L
CC
and I/O V during shutdown is chosen by selecting the
L_
+1.8V
SYSTEM
+3.3V
SD CARD
appropriate part version (see Ordering Information/
Selector Guide).
MAX13035E
CONTROLLER
DAT3
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
DAT3
L_
L_
L_
L_
L_
CC_
CC_
CC_
CC_
CC_
The MAX13030E–MAX13035E accept V
voltages
CC
I/O V
DAT2
DAT1
DAT2
DAT1
DAT0
CMD
from +2.2V to +3.6V and V voltages from +1.62V to
L
I/O V
I/O V
I/O V
+3.2V, making them ideal for data transfer between
low-voltage ASIC/PLDs and higher voltage systems.
The MAX13030E–MAX13035E are available in 16-bump
UCSP (2mm x 2mm) and 16-pin TQFN (4mm x 4mm)
packages, and operate over the extended -40°C to
+85°C temperature range.
DAT0
CMD
CLK_V
CC
CLOCK
CLOCK_IN
CLK_V
L
CLOCK
CLK_RET
GND
GND
GND
Applications
Typical Operating Circuits continued at end of data sheet.
SD Card Level Translation
MiniSD Card Level Translation
MMC Level Translation
Functional Diagram and ꢁin Configurations appear at end
of data sheet.
Transflash Level Translation
Memory Stick Card Level Translation
Ordering Information/Selector Guide
IꢂO ꢀ _ STATE DURING
IꢂO ꢀ _ STATE DURING
CC
L
ꢁART
ꢁIN-ꢁACKAGE
ꢁKG CODE
SHUTDOWN
SHUTDOWN
MAX13030EEBE+
16 UCSP
High impedance
High impedance
High impedance
High impedance
B16-1
MAX13030EETE+
16 TQFN-EP**
T1644-4
Ordering InformationꢂSelector guide continued at end of
data sheet.
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
+Denotes a lead-free package.
**EP = Exposed paddle.
________________________________________________________________ Maxim Integrated ꢁroducts
1
For pricing, delivery, and ordering information, please contact MaximꢂDallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
6-Channel High-Speed Logic-Level Translators
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Bump Temperature (soldering)........................................+235°C
Lead Temperature (soldering, 10s) .................................+300°C
V
I/O V
, V .....................................................................-0.3V to +4V
CC
L
, CLK_V ....................................-0.3V to (V
+ 0.3V)
CC
L
CC_
CC
I/O V , CLK_V , CLK_RET ..........................-0.3V to (V + 0.3V)
L_
L
EN.............................................................................-0.3V to +4V
Short-Circuit Duration I/O V , I/O V
,
CC_
L_
CLK_V , CLK_V , CLK_RET to GND.......................Continuous
CC
L
Continuous Power Dissipation (T = +70°C)
A
16-Bump UCSP (derate 8.2mW/°C)..............................660mW
16-Pin TQFN (derate 25.0mW/°C)...............................2000mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.2V to +3.6V, V = +1.62V to +3.2V, EN = V , T = -40°C to +85°C, unless otherwise noted. Typical values are at V
=
CC
CC
L
L
A
+3.3V, V = +1.8V and T = +25°C.) (Notes 1, 2)
L
A
ꢁARAMETER
ꢁOWER SUꢁꢁLIES
V Supply Range
SYMBOL
CONDITIONS
MIN
TYꢁ
MAX
UNITS
V
(Note 2)
1.62
2.2
3.20
3.6
25
V
L
L
V
Supply Range
V
V
CC
CC
Supply Current from V
Supply Current from V
I
I/O V _ = V , I/O V _ = V
16
6
µA
µA
CC
QVCC
CC
CC
L
L
–MAX1035E
I
I/O V _ = V , I/O V _ = V
10
L
QVL
CC
CC
L
L
T
= +25°C, EN = GND or V > V
+ 0.7V,
+ 0.7V,
A
L
CC
CC
2
2
4
4
MAX13030E–MAX13034E
V
Shutdown Supply Current
I
µA
µA
CC
SHDN-VCC
T
A
= +25°C, V > V + 0.7V,
L
CC
MAX13035E,
T
A
= +25°C, EN = GND or V > V
L
0.1
0.1
0.1
4
4
MAX13030E–MAX13034E
V Shutdown Supply Current
I
SHDN-VL
L
T
A
T
A
T
A
= +25°C, V > V
+ 0.7V, MAX13035E
CC
L
I/O V
, I/O V , CLK_V
L_ CC
CC_
I
= +25°C, EN = GND or V > V + 0.7V
CC
2
µA
µA
V
LEAK
L
Tri-State Leakage Current
EN Input Leakage Current
I
_
= +25°C, MAX13030E–MAX13034E
1
LEAK EN
V - V
L
High
Shutdown Threshold
Shutdown Threshold
Pulldown Resistance
CC
V
V
V
rising
falling
-0.2
-0.2
10
0.05V
L
0.7
TH_H
CC
CC
V - V
L
Low
CC
V
0.1V
0.7
23
23
23
V
TH_L
L
I/O V
CC_
R
R
_
_
EN = GND, MAX13032E/MAX13034E
EN = GND, MAX13031E
16.5
16.5
16.5
kΩ
kΩ
kΩ
VCC PD SD
During Shutdown
I/O V Pullup Resistance
CC_
_
_
10
VCC PU SD
During Shutdown
I/O V Pulldown Resistance
L_
During Shutdown
R
_
_
EN = GND, MAX13033E/MAX13034E
10
VL PD SD
2
_______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
–MAX1035E
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.2V to +3.6V, V = +1.62V to +3.2V, EN = V , T = -40°C to +85°C, unless otherwise noted. Typical values are at V
=
CC
L
L
A
CC
+3.3V, V = 1.8V and T = +25°C.) (Notes 1, 2)
L
A
ꢁARAMETER
SYMBOL
CONDITIONS
MIN
TYꢁ
MAX
UNITS
I/O V , CLK_V , CLK_RET
L_
L
Pullup Resistance During
Shutdown
R
_
_
(V > V
L
+ 0.7V), MAX13035E
45
75
105
kΩ
VL PU SD
CC
I/O V , CLK_V , CLK_RET
Pullup Current
L_
L
R
EN = V
EN = V
or V , I/O V = GND
20
20
µA
µA
kΩ
VL_PU
CC
CC
L
L_
I/O V
, CLK_V
Pullup
CC
CC_
R
or V , I/O V
= GND
VCC_PU
L
CC_
Current
I/O V to I/O V
L
DC
CC
R
(Note 3)
3
IOVL_IOVCC
Resistance
ESD ꢁROTECTION (Note 3)
Human Body Model, C
= 1.0µF
15
12
VCC
IEC 61000-4-2 Air-Gap Discharge,
= 1.0µF
C
I/O V
, CLK_V
VCC
kV
CC_
CC
IEC 61000-4-2 Contact Discharge,
= 1.0µF
8
C
VCC
LOGIC-LEꢀEL THRESHOLDS
I/O V CLK_V Input-Voltage
High Threshold
V -
L
0.2
L_,
L
V
(Note 4)
(Note 4)
(Note 4)
(Note 4)
V
V
V
V
IHL
I/O V CLK_V Input-Voltage
L_,
L
V
0.15
ILL
Low Threshold
I/O V
, CLK_V
Input-
V
-
CC
CC_
CC
V
IHC
Voltage High Threshold
0.4
I/O V , CLK_V Input-
CC_
CC
V
0.2
0.4
ILC
Voltage Low Threshold
EN Input-Voltage High
Threshold
V -
L
0.4
V
MAX13030E–MAX13034E
MAX13030E–MAX13034E
V
V
V
IH
EN Input-Voltage Low
V
IL
I/O V , CLK_V , CLK_RET
I/O V , CLK_V , CLK_RET source current
L_ L
= 20µA, I/O V _ ≥ V
L_
L
V
2/3 V
OHL
L
Output-Voltage High
- 0.4V
CC
CC
I/O V , CLK_V , CLK_RET
Output-Voltage Low
I/O V , CLK_V , CLK_RET sink current =
20µA, I/O V _ ≤ 0.2V
CC
L_
L
L_
L
V
1/3 V
V
V
OLL
L
I/O V _, CLK_V
CC
Output-
I/O V _, CLK_V
source current = 20µA,
2/3
V
CC
CC
CC
CC
V
OHC
Voltage High
I/O V _ ≥ V - 0.2V
L
L
_______________________________________________________________________________________
3
6-Channel High-Speed Logic-Level Translators
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.2V to +3.6V, V = +1.62V to +3.2V, EN = V , T = -40°C to +85°C, unless otherwise noted. Typical values are at V
=
CC
L
L
A
CC
+3.3V, V = 1.8V and T = +25°C.) (Notes 1, 2)
L
A
ꢁARAMETER
, CLK_V Output-
SYMBOL
CONDITIONS
, CLK_V sink current = 20µA,
MIN
TYꢁ
MAX
UNITS
I/O V
I/O V
1/3
V
CC
CC_
CC
CC_
CC
V
V
OLC
Voltage Low
RISEꢂFALL TIME ACCELERATOR STAGE (Note 3)
On falling edge
On rising edge
V = 1.62V
I/O V _ ≤ 0.15V
L
3
3
Accelerator Pulse Duration
ns
Ω
Ω
Ω
Ω
11
6
L
V -Output-Accelerator Source
L
Impedance
V = 3.2V
L
V
V
= 2.2V
= 3.6V
9
CC
CC
V
-Output-Accelerator Source
Impedance
CC
8
V = 1.62V
9
L
V -Output-Accelerator Sink
L
Impedance
V = 3.2V
8
L
V
V
= 2.2V
= 3.6V
10
9
CC
CC
V
-Output-Accelerator Sink
Impedance
CC
–MAX1035E
TIMING CHARACTERISTICS
(V
= +2.2V to +3.6V, V = +1.62V to +3.2V, C
≤ 15pF, C
≤ 15pF, R = 150Ω, EN = V , I/O V to I/O V
SOURCE L L_ CC_
CC
L
I/OVL
I/OVCC
rise/fall time = 3ns, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, V = 1.8V and T = +25°C.)
L A
A
CC
(Note 1)
ꢁARAMETER
SYMBOL
CONDITIONS
= 10pF, C =
CLK_VCC
MIN
TYꢁ
MAX
UNITS
R = 150Ω, C
S
I/OVCC
I/O V _, CLK_V
Rise Time
t
RVCC
2.5
ns
CC
CC
10pF, push-pull drivers (Figure 1)
R = 150Ω, C = 10pF, C =
CLK_VCC
S
I/OVCC
I/O V _, CLK_V
Fall Time
t
2.5
2.5
2.5
6.5
ns
ns
ns
ns
CC
CC
FVCC
10pF (Figures 1, 2)
R = 150Ω, C = 15pF, C
push-pull drivers (Figure 3)
= 15pF,
= 15pF
S
I/OVL
CLK_VL
CLK_VL
I/O V _, CLK_V Rise Time
t
RVL
L
L
R = 150Ω, C
= 15pF, C
S
I/OVL
I/O V _, CLK_V Fall Time
t
FVL
L
L
(Figures 3, 4)
Propagation Delay
R = 150Ω, C
S
= 10pF, C
CLK_VCC
=
I/OVCC
t
t
PVL-VCC
PVCC-VL
(Driving I/O V _, CLK_V )
10pF, push-pull drivers (Figure 1)
R = 150Ω, C = 15pF, C
CLK_VL
L
L
Propagation Delay
= 15pF,
= 15pF
S
I/OVL
6.5
0.8
ns
ns
µs
(Driving I/O V _, CLK_V
)
CC
push-pull drivers (Figure 3)
R = 150Ω, C = 10pF, C
I/OVL
CC
Channel-to-Channel Skew
t
SKEW
S
I/OVCC
Propagation Delay from
R
LOAD
= 1MΩ, C
= 10pF (Figure 5)
I/OVCC
t
5
EN-VCC
I/O V to I/O V
after EN
(MAX13030E–MAX13034E)
L_
CC_
4
_______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
–MAX1035E
TIMING CHARACTERISTICS (continued)
(V
= +2.2V to +3.6V, V = +1.62V to +3.2V, C
≤ 15pF, C
≤ 15pF, R = 150Ω, EN = V , I/O V to I/O V
SOURCE L L_ CC_
CC
L
I/OVL
I/OVCC
rise/fall time = 3ns, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, V = 1.8V and T = +25°C.)
L A
A
CC
(Note 1)
ꢁARAMETER
SYMBOL
CONDITIONS
= 1MΩ, C = 15pF (Figure 5)
MIN
TYꢁ
MAX
UNITS
Propagation Delay from
R
LOAD
I/OVL
t
5
µs
EN-VL
I/O V
to I/O V after EN
(MAX13030E–MAX13034E)
CC_
L_
Push-pull operation, R
= 150_,
SOURCE
Maximum Data Rate
C
C
= 10pF, C
= 15pF,
100
Mbps
I/OVCC_
I/OVL_
= 10pF, C
= 15pF
CLK_VCC
CLK_VL
Note 1: All units are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design
A
and not production tested.
Note 2: V must be less than or equal to V
- 0.2V during normal operation. However, V can be greater than V
during startup
L
CC
L
CC
and shutdown conditions and the part will not latch-up or be damaged.
Note 3: Guaranteed by design.
Note 4: Input thresholds are referenced to the boost circuit.
_______________________________________________________________________________________
5
6-Channel High-Speed Logic-Level Translators
Typical Operating Characteristics
(V
= 3.3V, V = 1.8V, C = 15pF, R
= 150Ω, data rate = 100Mbps, push-pull driver, T = +25°C, unless otherwise noted.)
CC
L
L
SOURCE A
V SUPPLY CURRENT vs. V SUPPLY
V SUPPLY CURRENT vs. V SUPPLY
V
SUPPLY CURRENT vs. V SUPPLY
L
CC
L
L
CC CC
VOLTAGE (DRIVING I/O V , V = 1.8V)
VOLTAGE (DRIVING I/O V , V = 3.6V)
VOLTAGE (DRIVING I/O V , V = 1.8V)
L_
L
CC_ CC
L_ L
10
9
8
7
6
5
4
3
2
1
0
25.0
22.5
20.0
17.5
15.0
12.5
10.0
7.5
850
840
830
820
810
800
790
780
770
760
750
DRIVING ONE I/O V
CC
DRIVING ONE I/O V
DRIVING ONE I/O V
L
L
5.0
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
V
V SUPPLY VOLTAGE (V)
L
V
CC
CC
V
SUPPLY CURRENT vs. V SUPPLY
SUPPLY CURRENT
vs. TEMPERATURE (DRIVING I/O V )
SUPPLY CURRENT
vs. TEMPERATURE (DRIVING I/O V
CC
L
VOLTAGE (DRIVING I/O V , V = 3.6V)
)
CC_ CC
L_
CC_
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
20
18
16
14
12
10
8
18
16
14
12
10
8
DRIVING ONE I/O V
CC
DRIVING ONE I/O V
L
DRIVING ONE I/O V
CC
–MAX1035E
I
CC
I
CC
6
6
I
L
4
4
I
L
2
2
0
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V SUPPLY VOLTAGE (V)
L
TEMPERATURE (°C)
TEMPERATURE (°C)
V
CC
SUPPLY CURRENT vs. CAPACITIVE
RISE/FALL TIME vs. CAPACITIVE
V SUPPLY CURRENT vs. CAPACITIVE
L
LOAD ON I/O V
(DRIVING I/O V
)
LOAD ON I/O V (DRIVING I/O V )
CC_ L_
LOAD ON I/O V (DRIVING I/O V
)
CC_
L_
L_
CC_
1500
1400
1300
1200
1100
1000
900
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
DRIVING ONE I/O V
L
DRIVING ONE I/O V
CC
t
RVCC
t
FVCC
800
700
600
500
10
15
20
25
30
35
40
10
15
20
25
30
35
40
10
15
20
25
30
35
40
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
6
_______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
–MAX1035E
Typical Operating Characteristics (continued)
(V
= 3.3V, V = 1.8V, C = 15pF, R
= 150Ω, data rate = 100Mbps, push-pull driver, T = +25°C, unless otherwise noted.)
CC
L
L
SOURCE A
RISE/FALL TIME vs. CAPACITIVE
LOAD ON I/O V (DRIVING I/O V
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O V (DRIVING I/O V
)
CC_
)
L_
L_
CC_
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
5.0
4.5
4.0
3.5
3.0
2.5
2.0
t
PLH
t
RVL
t
PHL
t
FVL
500
10
15
20
25
30
35
40
10
15
20
25
30
35
40
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O V (DRIVING I/O V
TYPICAL I/O V DRIVING
L_
)
CC_
(FREQUENCY = 26MHz, C
= 40pF)
L_
IOVCC
MAX13030E toc13
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
I/O V
1V/div
L_
t
PHL
t
PLH
I/O V
2V/div
CC_
10
15
20
25
30
35
40
10ns/div
CAPACITIVE LOAD (pF)
TYPICAL I/O V
(FREQUENCY = 26MHz, C
DRIVING
CC_
TYPICAL CLK_ V DRIVING
L
= 15pF)
IOVL
(FREQUENCY = 26MHz, C
= 40pF)
CLK_VCC
MAX13030E toc15
MAX13030E toc14
CLK_ V
1V/div
L
I/O V
CC_
2V/div
CLK_ V
2V/div
CC
I/O V
L_
1V/div
CLK_RET
1V/div
10ns/div
10ns/div
_______________________________________________________________________________________
7
6-Channel High-Speed Logic-Level Translators
Pin Description
ꢁIN
NAME
FUNCTION
MAX13030E–MAX13034E
MAX13035E
UCSꢁ TQFN
A1
UCSꢁ
A1
TQFN
4
6
4
I/O V 3
Input/Output 3. Referenced to V .
L
L
A2
A2
A3
A4
B1
B2
B3
B4
6
7
I/O V
3
Input/Output 3. Referenced to V
Input/Output 4. Referenced to V
.
.
CC
CC
CC
CC
A3
7
I/O V
4
A4
9
9
I/O V 4
Input/Output 4. Referenced to V .
L
L
B1
3
3
I/O V 2
Input/Output 2. Referenced to V .
L
L
B2
5
5
I/O V
I/O V
2
5
Input/Output 2. Referenced to V
Input/Output 5. Referenced to V
.
.
CC
CC
CC
B3
8
8
CC
B4
10
10
I/O V 5
Input/Output 5. Referenced to V .
L
L
Logic-Supply Voltage, +1.62V to +3.2V. Bypass V to GND with
L
a 0.1µF capacitor placed as close as possible to the device.
C1
C2
2
C1
2
V
L
Power-Supply Voltage, +2.2V to +3.6V. Bypass V
to GND with
CC
a 0.1µF ceramic capacitor. For full ESD protection, connect a
1µF ceramic capacitor from V to GND as close as possible to
16
C2
16
V
CC
CC
the V
input.
CC
C3
C4
13
11
C3
—
13
—
GND
EN
Ground
Enable Input. Drive EN to GND for shutdown mode, or drive EN to
V or V for normal operation.
–MAX1035E
L
CC
D1
D2
D3
D4
1
D1
D2
—
1
I/O V 1
Input/Output 1. Referenced to V .
L
L
15
14
12
15
—
—
I/O V
1
Input/Output 1. Referenced to V
Input/Output 6. Referenced to V
.
.
CC
CC
CC
CC
I/O V
6
—
I/O V 6
L
Input/Output 6. Referenced to V .
L
Clock Return Output. CLK_RET is the returned signal of a clock
—
—
C4
11
CLK_RET
applied to CLK_V . CLK_RET is referenced to V .
L
L
—
—
—
—
—
D3
D4
—
14
12
EP
CLK_V
Translator Channel for a Clock Applied to V
Translator Channel for a Clock Applied to V
CC
CC
CLK_V
EP
L
L
EP
Exposed Paddle. Connect exposed paddle to GND.
8
_______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
–MAX1035E
Test Circuits/Timing Diagrams
t
t
RVCC
FVCC
V
V
L
CC
90%
90%
V
EN**
V
CC
L
MAX13030E–
MAX13035E
I/O V
L
50%
50%
V
V
L
CC
50%
50%
I/O V
(CLK_V *)
L_
I/O V
(CLK_V *)
CC_
CC
L
10%
I/O V
10%
CC
150Ω
C
(C
*)
IOVCC
CLK_VCC
*MAX13035E ONLY
**MAX13030E–MAX13034E ONLY
t
t
PHL
PLH
t
= t OR t
PVL-VCC PLH PHL
Figure 1. Push-Pull Driving I/O V Test Circuit and Timing
L_
t
t
RVCC
FVCC
V
L
V
CC
I/O V
CC
90%
50%
90%
EN**
V
V
CC
L
MAX13030E–
MAX13035E
V
GATE
50%
V
V
L
CC
50%
50%
I/O V
(CLK_V *)
I/O V
(CLK_V *)
CC_
CC
L_
L
10%
10%
*)
C
(C
IOVCC
V
CLK_VCC
GATE
t
t
PHL
PLH
t
= t
PVL-VCC PHL
*MAX13035E ONLY
**MAX13030E–MAX13034E ONLY
Figure 2. Open-Drain Driving I/O VL_ Test Circuit and Timing
_______________________________________________________________________________________
9
6-Channel High-Speed Logic-Level Translators
Test Circuits/Timing Diagrams (continued)
t
t
FVL
RVL
V
V
L
CC
I/O V
CC
EN**
V
V
CC
L
MAX13030E–
MAX13035E
V
V
L
CC
90%
90%
50%
50%
50%
I/O V
(CLK_V *)
50%
CC_
CC
I/O V
(CLK_V *)
L_
L
10%
150Ω
10%
I/O V
L
C
IOVL
(C
*)
CLK_VL
t
t
PHL
PLH
t
= t OR t
PVCC-VL PLH PHL
*MAX13035E ONLY
**MAX13030E–MAX13034E ONLY
Figure 3. Push-Pull Driving I/O V
Test Circuit and Timing
CC_
–MAX1035E
t
t
RVL
V
L
V
FVL
CC
EN**
V
V
CC
L
I/O V
L
MAX13030E–
MAX13035E
90%
90%
10%
(C
*)
50%
50%
50%
CLK_VL
V
V
CC
L
50%
I/O V
I/O V
CC_
L_
(CLK_V *)
(CLK_V *)
10%
L
CC
C
IOVL
V
GATE
t
t
PHL
PLH
(C
*)
t
= t
CLK_VL
PVCC-VL PHL
*MAX13035E ONLY
**MAX13030E–MAX13034E ONLY
Figure 4. Open-Drain Driving I/O V
Test Circuit and Timing
CC_
10 ______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
–MAX1035E
Test Circuits/Timing Diagrams (continued)
V
L
L
EN
EN
MAX13030E–
MAX13034E
V
V
CC
L
t'
EN-VCC
0
V
0
I/O V
CC_
SOURCE
I/O V
L_
I/O V
L_
V
0
C
CC
IOVCC
R
LOAD
V
/ 2
I/O V
CC
CC_
V
L
V
CC
V
EN
L
EN
R
LOAD
t"
EN-VCC
MAX13030E–
MAX13034E
V
V
CC
L
0
V
0
SOURCE
L
I/O V
L_
I/O V
L_
I/O V
CC_
V
0
I/O V
CC
CC_
V
/ 2
CC
C
IOVCC
t
IS WHICHEVER IS LARGER BETWEEN t'
AND t"
.
EN-VCC
EN-VCC
EN-VCC
V
L
EN
EN
V
MAX13030E–
MAX13034E
V
t'
L
CC
EN-VL
0
V
0
SOURCE
CC
I/O V
CC_
I/O V
I/O V
CC_
L_
V
0
L
C
IOVL
V
CC
R
LOAD
V / 2
L
I/O V
L_
V
L
EN
EN
t"
EN-VL
0
V
0
V
MAX13030E–
MAX13034E
V
L
CC
CC
L
V
L
I/O V
CC_
SOURCE
R
LOAD
I/O V
CC_
V
0
I/O V
L_
I/O V
L_
V / 2
L
C
IOVL
t
IS WHICHEVER IS LARGER BETWEEN t'
AND t"
.
EN-VCC
EN-VCC
EN-VCC
Figure 5. Enable Test Circuit and Timing
______________________________________________________________________________________ 11
6-Channel High-Speed Logic-Level Translators
Detailed Description
V
V
L
CC
The MAX13030E–MAX13035E 6-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13030E–MAX13035E are ideally suited for memory
card level translation, as well as generic level translation
in systems with six channels. Externally applied volt-
ENABLE
ENABLE
ENABLE
30μA
30μA
ages, V
and V , set the logic levels on either side of
L
CC
I/O V
the device. Logic signals present on the V side of the
I/O V
L_
L
CC_
device appear as a higher voltage logic signal on the
V
side of the device, and vice versa. The MAX13035E
CC
features a CLK_RET output that returns the same clock
V
L
V
CC
signal applied to the CLK_V input.
L
BOOST
CIRCUIT
The MAX13030E–MAX13035E operate at full speed
with external drivers that source as little as 4mA output
V
L
V
CC
current. Each I/O channel is pulled up to V
or V by
L
CC
BOOST
CIRCUIT
an internal 30µA current source, allowing the
MAX13030E–MAX13035E to be driven by either push-
pull or open-drain drivers.
NOTES: 1) THE MAX13030E–MAX13034E ARE ENABLED WHEN
V < - 0.2V AND EN = V .
V
L
CC
L
The MAX13030E–MAX13034E feature an enable (EN)
input that places the device into a low-power shutdown
mode when driven low. The MAX13030E–MAX13035E
features an automatic shutdown mode that disables the
2) THE MAX13035E IS ENABLED WHEN V <
V
- 0.2V.
L
CC
Figure 6. Simplified Functional Diagram for One I/O Line
–MAX1035E
part when V
is less than V . The state of I/O V
and
CC
L
CC_
active during the one-shot pulse. This can lead to some
current feeding into the external source that is driving the
translator. However, this behavior helps to speed up the
transition on the driven side.
I/O V during shutdown is chosen by selecting the
L_
appropriate part version (see Ordering Information/
Selector Guide).
The MAX13030E–MAX13035E accept V
voltages from
CC
The MAX13030E–MAX13035E have internal current
sources capable of sourcing 30µA to pullup the I/O
lines. These internal pullup current sources allow the
inputs to be driven with open-drain drivers, as well as
push-pull drivers. It is not recommended to use exter-
nal pullup resistors on the I/O lines. The architecture of
the MAX13030E–MAX13035E permit either side to be
driven with a minimum of 4mA drivers or larger.
+2.2V to +3.6V and V voltages from +1.62V to +3.2V.
L
Level Translation
For proper operation, ensure that +2.2V ≤ V
≤ +3.6V,
CC
and +1.62V ≤ V ≤ V - 0.2V. When power is supplied to
L
CC
V
while V
is either missing or less than V ,
L
CC L
the MAX13030E–MAX13035E automatically enters a
low- power mode. In addition, the MAX13030E–
MAX13034E enters a low-power mode if EN = 0V. This
Output Load Requirements
The MAX13030E–MAX13035E I/O are designed to drive
CMOS inputs. Do not load the I/O lines with a resistive
load less than 25kΩ and do not place an RC circuit at
the input of these devices to slow down the edges. If a
slower rise/fall time is required, refer to the MAX3000E/
MAX3001E logic-level translator datasheet. For I2C
level translation, refer to the MAX3372E–MAX3379E/
MAX3390E–MAX3393E datasheet.
allows V
to be disconnected and still have a known
L_
CC
state on I/O V . The maximum data rate depends heavily
on the load capacitance (see the Typical Operating
Characteristics Rise/Fall Times), output impedance of the
driver, and the operating voltage range.
Input Driver Requirements
The MAX13030E–MAX13035E architecture is based on
an nMOS pass gate and output accelerator stages (see
Figure 6). Output accelerator stages are always in tri-
state mode except when there is a transition on any of
Shutdown Mode
The MAX13030E–MAX13034E feature an enable (EN)
input that places the device into a low-power shutdown
mode when driven low. The MAX13030E–MAX13035E
features an automatic shutdown mode that disables the
the translators on the input side, either I/O V , CLK_V ,
L_
L
I/O V
, or CLK_V . A short pulse is then generated
CC_
CC
during which the output accelerator stages become
active and charge/discharge the capacitances at the
I/Os. Due to its architecture, both input stages become
part when V
is missing or less than V .
L
CC
12 ______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
–MAX1035E
Clock Return (CLK_RET)
Open-Drain Signaling
The MAX13030E–MAX13035E are designed to pass
open-drain as well as CMOS push-pull signals. When
used with open-drain signaling, the rise time is domi-
nated by the interaction of the internal pullup current
source and the parasitic load capacitance. The
MAX13030E–MAX13035E include internal rise time
accelerators to speed up transitions, eliminating any
need for external pullup resistors.
The MAX13035E features a CLK_RET output that returns
the clock signal applied to CLK_V . CLK_V and
L
L
CLK_V
are identical to the other I/O channels, the only
CC
difference being that CLK_V
is internally tied to the
CC
V
CC
side of CLK_RET (see the Functional Diagram).
Application Information
Layout Recommendations
Use standard high-speed layout practices when laying
out a board with the MAX13030E–MAX13035E. For
example, to minimize line coupling, place all other signal
lines not connected to the MAX13030E–MAX13035E at
least 1x the substrate height of the PCB away from the
input and output lines of the MAX13030E–MAX13035E.
SD Card Detection
SD, MiniSD, MMC and similar types of cards provide
detection of a card through a pullup resistor on one of
the DAT lines, or by use of a mechanical switch. This
pullup resistor is internal to the memory card itself. The
MAX13030E–MAX13035E only support detection of
a memory card through a mechanical switch, and it
is recommended that the internal resistor for card
detection be switched off by the command interface.
For example, when using SD cards, the command
SET_CLR_CARD_DETECT (ACMD42) disables this
resistor.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass V and V
to ground with 0.1µF ceram-
CC
L
ic capacitors. Place all capacitors as close as possible
to the power-supply inputs. For full ESD protection,
bypass V
with a 1µF ceramic capacitor located as
CC
close as possible to the V
input.
CC
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow tempera-
ture profiles, as well as the latest information on reliabil-
ity testing results, go to Maxim’s web site at
www.maxim-ic.com/ucsp to find the Application Note:
UCSP – A Wafer-Level Chip-Scale Package.
Unidirectional vs. Bidirectional Level
Translator
The MAX13030E–MAX13035E bidirectional level trans-
lators can operate as a unidirectional device to trans-
late signals without inversion. These devices provide
the smallest solution (UCSP package) for unidirectional
level translation without inversion.
Use with External Pullup/Pulldown
Resistors
Chip Information
Due to the architecture of the MAX13030E–
MAX13035E, it is not recommended to use external
pullup or pulldown resistors on the bus. In certain appli-
cations, the use of external pullup or pulldown resistors
is desired to have a known bus state when there is no
active driver on the bus. For example, this may happen
when interfacing to a memory card slot with no memory
card inserted. The MAX13030E–MAX13035E include
internal pullup current sources that set the bus state
when the device is enabled. In shutdown mode,
Process: BiCMOS
the state of I/O V
and I/O V is dependent on
L_
CC_
the selected part version (see Ordering Information/
Selector Guide for further information).
______________________________________________________________________________________ 13
6-Channel High-Speed Logic-Level Translators
Functional Diagram
V
L
V
CC
V
L
V
CC
MAX13035E
MAX13030E–
MAX13034E
I/O V 1
L
I/O V
1
I/O V 1
L
I/O V
1
CC
CC
I/O V
I/O V
2
3
I/O V 2
L
I/O V
I/O V
2
3
CC
I/O V 2
L
CC
I/O V 3
L
CC
I/O V 3
L
CC
–MAX1035E
I/O V 4
L
I/O V
I/O V
4
5
I/O V 4
L
I/O V
I/O V
4
5
CC
CC
I/O V 5
L
I/O V 5
L
CC
CC
CLK_ V
L
CLK_ V
CC
I/O V 6
L
I/O V
6
CC
EN
GND
CLK_RET
GND
14 ______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
–MAX1035E
Pin Configurations
TOP VIEW
TOP VIEW
(BUMPS ON BOTTOM)
1
2
3
4
12
11
10
9
+
MAX13030E–MAX13034E
GND
13
14
15
16
A
8
7
6
5
I/O V
5
4
CC
I/O V 3
L
I/O V 4
CC
I/O V
3
I/O V 4
L
CC
I/O V
6
1
CC
I/O V
I/O V
I/O V
CC
MAX13030E–
MAX13034E
B
I/O V
CC
3
CC
CC
I/O V 2
L
I/O V
5
I/O V
2
I/O V 5
L
CC
CC
*EP
V
CC
2
C
D
+
1
2
3
4
V
L
GND
V
CC
EN
16 TQFN (4mm x 4mm)
I/O V 1
L
I/O V 6
CC
I/O V
1
I/O V 6
L
CC
*CONNECT EXPOSED PADDLE TO GROUND
16 UCSꢁ (2mm x 2mm)
TOP VIEW
TOP VIEW
(BUMPS ON BOTTOM)
1
2
3
4
12
11
10
9
+
MAX13035E
GND
13
14
15
16
A
8
7
6
5
I/O V
5
4
CC
I/O V 3
L
I/O V
4
I/O V
I/O V
3
I/O V 4
CC
CC
L
CLK_V
CC
1
I/O V
I/O V
I/O V
CC
MAX13035E
B
I/O V
CC
3
CC
CC
I/O V 2
L
I/O V
5
2
I/O V 5
L
CC
CC
*EP
V
CC
2
C
D
+
1
2
3
4
V
L
GND
V
CLK_RET
CC
16 TQFN (4mm x 4mm)
I/O V 1
L
CLK_V
CC
I/O V
1
CLK_V
L
CC
*CONNECT EXPOSED PADDLE TO GROUND
16 UCSꢁ (2mm x 2mm)
______________________________________________________________________________________ 15
6-Channel High-Speed Logic-Level Translators
Typical Operating Circuits (continued)
+3.3V
+1.8V
1μF
0.1μF
0.1μF
V
V
CC
L
+1.8V
+3.3V
SYSTEM
SYSTEM
CONTROLLER
MAX13030E–
MAX13034E
EN
DATA
EN
I/O V
I/O V
CC_
DATA
L_
6
6
GND
GND
GND
–MAX1035E
Ordering Information/Selector Guide (continued)
IꢂO ꢀ _ STATE DURING
L
IꢂO ꢀ _ STATE DURING
CC
ꢁART
ꢁIN-ꢁACKAGE
ꢁKG CODE
SHUTDOWN
SHUTDOWN
MAX13031EEBE+*
MAX13031EETE+*
MAX13032EEBE+
MAX13032EETE+
MAX13033EEBE+*
MAX13033EETE+*
MAX13034EEBE+*
MAX13034EETE+*
MAX13035EEBE+
MAX13035EETE+
16 UCSP
16 TQFN-EP**
16 UCSP
High impedance
High impedance
High impedance
High impedance
16.5kΩ to GND
16.5kΩ to GND
16.5kΩ to GND
16.5kΩ to GND
16.5kΩ to V
16.5kΩ to V
B16-1
T1644-4
B16-1
CC
CC
16.5kΩ to GND
16.5kΩ to GND
High impedance
High impedance
16.5kΩ to GND
16.5kΩ to GND
High impedance
High impedance
16 TQFN-EP**
16 UCSP
T1644-4
B16-1
16 TQFN-EP**
16 UCSP
T1644-4
B16-1
16 TQFN-EP**
16 UCSP
T1644-4
B16-1
75kΩ to V
75kΩ to V
L
L
16 TQFN-EP**
T1644-4
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
+Denotes a lead-free package.
**EP = Exposed paddle.
16 ______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
–MAX1035E
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.comꢂpackages.)
PACKAGE OUTLINE, 4x4 UCSP
1
21-0101
H
1
______________________________________________________________________________________ 17
6-Channel High-Speed Logic-Level Translators
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.comꢂpackages.)
–MAX1035E
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
1
E
21-0139
2
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
2
E
21-0139
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
Boblet
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* F u t u r e P r o d u c t
F o r a u t o m a t i c e - m a i l o n n e w p a r t s i n t h i s p r o d u c t l i n e , s u b s c r i b e t o E E - M a i l
Q u i c k V i e w
T e c h n i c a l D o c u m e n t s
O r d e r i n g I n f o
M o r e I n f o r m a t i o n
A l l
O r d e r i n g I n f o r m a t i o n
N o t e s :
1 . O t h e r o p t i o n s a n d l i n k s f o r p u r c h a s i n g p a r t s a r e l i s t e d a t : h t t p : / / w w w . m a x i m - i c . c o m / s a l e s .
2 . D i d n ' t F i n d W h a t Y o u N e e d ? A s k o u r a p p l i c a t i o n s e n g i n e e r s . E x p e r t a s s i s t a n c e i n f i n d i n g p a r t s , u s u a l l y w i t h i n o n e
b u s i n e s s d a y .
3 . P a r t n u m b e r s u f f i x e s : T o r T & R = t a p e a n d r e e l ; + = R o H S / l e a d - f r e e ; # = R o H S / l e a d - e x e m p t . M o r e : S e e F u l l D a t a
S h e e t o r P a r t N a m i n g C o n v e n t i o n s .
4 . * S o m e p a c k a g e s h a v e v a r i a t i o n s , l i s t e d o n t h e d r a w i n g . " P k g C o d e / V a r i a t i o n " t e l l s w h i c h v a r i a t i o n t h e p r o d u c t
u s e s .
D e v i c e s : 1 - 1 2 o f 1 2
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M a t e r i a l s A n a l y s i s
M A X 1 3 0 3 0 E E T E +
M A X 1 3 0 3 0 E E B E +
M A X 1 3 0 3 0 E E B E + T
T H I N Q F N ; 1 6 p i n ; 1 7 m m
D w g : 2 1 - 0 1 3 9 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : T 1 6 4 4 + 4 *
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M a t e r i a l s A n a l y s i s
U C S P ; 1 6 p i n ; 4 m m
D w g : 2 1 - 0 1 0 1 H ( P D F )
U s e p k g c o d e / v a r i a t i o n : B 1 6 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
U C S P ; 1 6 p i n ; 4 m m
D w g : 2 1 - 0 1 0 1 H ( P D F )
U s e p k g c o d e / v a r i a t i o n : B 1 6 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
M A X 1 3 0 3 2 E
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M A X 1 3 0 3 2 E E T E +
M A X 1 3 0 3 2 E E B E +
M A X 1 3 0 3 2 E E B E + T
M A X 1 3 0 3 5 E
T H I N Q F N ; 1 6 p i n ; 1 7 m m
D w g : 2 1 - 0 1 3 9 G ( P D F )
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U C S P ; 1 6 p i n ; 4 m m
D w g : 2 1 - 0 1 0 1 H ( P D F )
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M a t e r i a l s A n a l y s i s
U C S P ; 1 6 p i n ; 4 m m
D w g : 2 1 - 0 1 0 1 H ( P D F )
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- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
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T H I N Q F N ; 1 6 p i n ; 1 7 m m
D w g : 2 1 - 0 1 3 9 G ( P D F )
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M a t e r i a l s A n a l y s i s
T H I N Q F N ; 1 6 p i n ; 1 7 m m
D w g : 2 1 - 0 1 3 9 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : T 1 6 4 4 + 4 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
U C S P ; 1 6 p i n ; 4 m m
D w g : 2 1 - 0 1 0 1 H ( P D F )
U s e p k g c o d e / v a r i a t i o n : B 1 6 + 1 *
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M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : B 1 6 + 1 *
D i d n ' t F i n d W h a t Y o u N e e d ?
N e x t D a y P r o d u c t S e l e c t i o n A s s i s t a n c e f r o m A p p l i c a t i o n s E n g i n e e r s
P a r a m e t r i c S e a r c h
A p p l i c a t i o n s H e l p
Q u i c k V i e w
T e c h n i c a l D o c u m e n t s
O r d e r i n g I n f o
M o r e I n f o r m a t i o n
D e s c r i p t i o n
D a t a S h e e t
A p p l i c a t i o n N o t e s
D e s i g n G u i d e s
E n g i n e e r i n g J o u r n a l s
R e l i a b i l i t y R e p o r t s
S o f t w a r e / M o d e l s
E v a l u a t i o n K i t s
P r i c e a n d A v a i l a b i l i t y
S a m p l e s
B u y O n l i n e
P a c k a g e I n f o r m a t i o n
L e a d - F r e e I n f o r m a t i o n
R e l a t e d P r o d u c t s
N o t e s a n d C o m m e n t s
E v a l u a t i o n K i t s
K e y F e a t u r e s
A p p l i c a t i o n s / U s e s
K e y S p e c i f i c a t i o n s
D i a g r a m
D o c u m e n t R e f . : 1 9 - 0 6 2 6 ; R e v 0 ; 2 0 0 7 - 0 2 - 1 2
T h i s p a g e l a s t m o d i f i e d : 2 0 0 7 - 0 2 - 1 2
C O N T A C T U S : S E N D U S A N E M A I L
C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s S e m i c o n d u c t o r • L e g a l N o t i c e s • P r i v a c y P o l i c y
相关型号：
MAX13032EETE+
Interface Circuit, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WGGC, TQFN-16
MAXIM
MAX13034EETE+
Interface Circuit, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WGGC, TQFN-16
MAXIM
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