MAX13044EEBC+T [MAXIM]
Interface Circuit, BICMOS, PBGA12, 1.54 X 2.12 MM, LEAD FREE, UCSP-12;
| 型号： | MAX13044EEBC+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Interface Circuit, BICMOS, PBGA12, 1.54 X 2.12 MM, LEAD FREE, UCSP-12 信息通信管理 |
| 文件： | 总14页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0792; Rev 0; 4/07
1.62V to 3.6V Improved High-Speed LLT
General Description
Features
The MAX13042E–MAX13045E 4-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13042E–MAX13045E are ideally suited for level
translation in systems with four channels. Externally
♦ Compatible with 4mA Input Drivers or Larger
♦ 100Mbps Guaranteed Data Rate
♦ Four Bidirectional Channels
♦ Enable Input
applied voltages, V
and V , set the logic levels on
L
CC
either side of the device. Logic signals present on the
V side of the device appear as a high-voltage logic
♦
1ꢀ5k EꢁD ꢂrotection on Iꢃ/ k
Lines
CC_
L
♦ +1.62k ≤ k ≤ +3.2k and +2.2k ≤ k
≤ +3.6k
L
CC
signal on the V
side of the device and vice-versa.
CC
ꢁupply koltage Range
The MAX13042E–MAX13045E operate at full speed
with external drivers that source as little as 4mA output
current or larger. Each input/output (I/O) channel is
♦ 12-Bump UCꢁꢂ (1.ꢀ4mm x 2.12mm) and
14-ꢂin TDFN (3mm x 3mm) Lead-Free ꢂac5ages
pulled up to V
or V by an internal 30µA current
L
CC
source, allowing the MAX13042E–MAX13045E to be
driven by either push-pull or open-drain drivers.
Typical Operating Circuit
The MAX13042E–MAX13045E feature an enable (EN)
input that places the devices into a low-power shutdown
mode when driven low. The MAX13042E–MAX13045E
feature an automatic shutdown mode that disables the
+3.3V
+1.8V
0.1μF
1μF
0.1μF
part when V
is less than V . The state of I/O V
and
CC
L
CC_
I/O V during shutdown is chosen by selecting the
L_
V
V
appropriate part version. (See the Ordering Information/
Selector Guide).
L
CC
+1.8V
SYSTEM
+3.3V
SYSTEM
MAX13042E–
MAX13045E
CONTROLLER
The MAX13042E–MAX13045E operate with V
volt-
CC
ages from +2.2V to +3.6V and V voltages from +1.62V
L
EN
DATA
EN
to +3.2V, making them ideal for data transfer between
low-voltage ASIC/PLDs and higher voltage systems.
The MAX13042E–MAX13045E are available in 12-bump
UCSP™ (1.54mm x 2.12mm) and 14-pin TDFN (3mm x
3mm) packages, and operate over the extended -40°C
to +85°C temperature range.
I/O V
I/O V
CC_
DATA
L_
4
4
GND
GND
GND
Applications
Portable POS Systems
UCSP is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
CMOS Logic-Level
Translation
MICROWIRE is a trademark of National Semiconductor Corp.
Portable Communication
Devices
Low-Voltage ASIC Level
Translation
Pin Configurations appear at end of data sheet.
GPS
Cell Phones
Telecommunications
Equipment
Ordering Information/Selector Guide continued at end of
data sheet.
SPI™, MICROWIRE™
Level Translation
Ordering Information/Selector Guide
ꢂIN-
ꢂACKAGE
Iꢃ/ k ꢁTATE DURING
L_
Iꢃ/ k
ꢁTATE DURING
ꢁHUTD/WN
T/ꢂ
MARK
CC_
ꢂART
ꢂKG C/DE
ꢁHUTD/WN
High Impedance
High Impedance
MAX13042EEBC+T 12 UCSP-12
MAX13042EETD+T 14 TDFN-EP**
High Impedance
High Impedance
ADQ
ADE
B12-3
T1433-2
Note: All devices operate over the -40°C to +85°C temperature
range.
*Future product—contact factory for availability.
**EP = Exposed paddle.
+Denotes a lead-free package.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1.62V to 3.6V Improved High-Speed LLT
ABꢁ/LUTE MAXIMUM RATINGꢁ
(All voltages referenced to GND.)
Operating Temperature Range ...........................-40°C to +85°C
V
I/O V
, V .....................................................................-0.3V to +4V
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
L
..................................................... -0.3V to (V
+ 0.3V)
CC_
CC
I/O V ...........................................................-0.3V to (V + 0.3V)
L_
L
EN.............................................................................-0.3V to +4V
Short-Circuit Duration I/O V , I/O V to GND .......Continuous
L_
CC_
Continuous Power Dissipation (T = +70°C)
A
12-Bump UCSP (derate 6.5mW/°C above +70°C) ......519mW
14-Pin TDFN (derate 24.4mW/°C above +70°C) .......1951mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERIꢁTICꢁ
(V
= +2.2V to +3.6V, V = +1.62V to +3.2V, EN = V , T = -40°C to +85°C, unless otherwise noted. Typical values are at V
=
CC
CC
L
L
A
+3.3V, V = +1.8V, and T = +25°C.) (Notes 1, 2)
L
A
ꢂARAMETER
ꢂ/WER ꢁUꢂꢂLIEꢁ
V Supply Range
ꢁYMB/L
C/NDITI/Nꢁ
MIN
TYꢂ
MAX
UNITꢁ
V
1.62
2.2
3.2
3.6
25
10
1
V
L
L
V
Supply Range
V
V
CC
CC
Supply Current from V
Supply Current from V
I
I/O V
I/O V
= V , I/O V = V
L
µA
µA
µA
CC
QVCC
CC_
CC
L_
I
= V , I/O V = V
L
QVL
SHDN-VCC
CC_
CC
L_
L
V
Shutdown Supply Current
I
T
A
T
A
T
A
= +25°C, EN = GND
= +25°C, EN = GND
0.1
0.1
0.1
CC
1
V Shutdown-Mode Supply
L
Current
I
µA
SHDN-VL
= +25°C, EN = V , V
L
= GND
4
CC
I/O V
Leakage Current
, I/O V Tri-State
L_
CC_
I
T
T
= +25°C, EN = GND
= +25°C
0.1
2
1
µA
µA
V
LEAK
A
A
EN Input Leakage Current
I
LEAK_EN
V - V
L
High
Shutdown Threshold
Shutdown Threshold
Pulldown Resistance
CC
V
V
V
rising (Note 3)
falling (Note 3)
0
0
0.1V
L
0.8
TH_H
CC
CC
V - V
L
Low
CC
V
0.12V
16.5
0.8
23
23
V
TH_L
L
I/O V
CC_
R
R
MAX13043E/MAX13045E
MAX13044E/MAX13045E
10
10
kΩ
kΩ
VCC_PD_SD
During Shutdown
I/O V Pulldown Resistance
L_
During Shutdown
R
16.5
VL_PD_SD
I/O V Pullup Current
I
I/O V = GND, I/O V = GND
CC_
20
20
65
65
µA
µA
L_
VL_PU_
L_
I/O V
Pullup Current
I
I/O V
= GND, I/O V = GND
CC_ L_
CC_
VCC_PU_
I/O V to I/O V
L_
Resistance
DC
CC_
(Note 4)
3
kΩ
IOVL_IOVCC
2
_______________________________________________________________________________________
1.62V to 3.6V Improved High-Speed LLT
ELECTRICAL CHARACTERIꢁTICꢁ (continued)
(V
= +2.2V to +3.6V, V = +1.62V to +3.2V, EN = V , T = -40°C to +85°C, unless otherwise noted. Typical values are at V
=
CC
CC
L
L
A
+3.3V, V = +1.8V, and T = +25°C.) (Notes 1, 2)
L
A
ꢂARAMETER
EꢁD ꢂR/TECTI/N
ꢁYMB/L
C/NDITI/Nꢁ
MIN
TYꢂ
MAX
UNITꢁ
I/O V , EN
L_
Human Body Model
2
kV
Human Body Model, C
= 1µF
15
VCC
IEC 61000-4-2 Air-Gap Discharge,
= 1µF
15
8
C
I/O V
CC_
kV
VCC
IEC 61000-4-2 Contact Discharge,
= 1µF
C
VCC
L/GIC LEkELꢁ
I/O V Input-Voltage High
L_
Threshold
V
(Note 5)
(Note 5)
(Note 5)
(Note 5)
V - 0.2
V
V
V
V
V
V
IHL
L
I/O V Input-Voltage Low
L_
Threshold
V
0.15
0.2
ILL
I/O V
Input-Voltage High
V
-
CC
CC_
V
IHC
Threshold
0.4
I/O V Input-Voltage Low
CC_
V
ILC
Threshold
EN Input-Voltage-High
Threshold
V
V - 0.4
L
IH
EN Input-Voltage-Low
Threshold
V
0.4
IL
I/O V Output-Voltage High
V
I/O V source current = 20µA
2/3 V
V
V
V
L_
OHL
L_
L
I/O V Output-Voltage Low
V
I/O V sink current = 20µA, I/O V
< 0.2V
1/3 V
L_
OLL
L_
CC_
L
I/O V
Output-Voltage High
V
I/O V
source current = 20µA
2/3 V
CC
CC_
OHC
CC_
I/O V
I/O V < 0.15V
L_
sink current = 20µA,
CC_
I/O V
Output-Voltage Low
V
1/3 V
V
CC_
OLC
CC
RIꢁE-ꢃFALL-TIME ACCELERAT/R ꢁTAGE
On falling edge
On rising edge
3.5
3.5
24
11
13
9
Accelerator Pulse Duration
ns
Ω
Ω
Ω
Ω
V = 1.62V
L
V Output Accelerator Source
L
Impedance
V = 3.2V
L
V
V
= 2.2V
= 3.6V
CC
CC
V
Output Accelerator Source
CC
Impedance
V = 1.62V
L
14
10
11
9
V Output Accelerator Sink
L
Impedance
V = 3.2V
L
V
V
= 2.2V
= 3.6V
CC
CC
V
Output Accelerator Sink
CC
Impedance
_______________________________________________________________________________________
3
1.62V to 3.6V Improved High-Speed LLT
TIMING CHARACTERIꢁTICꢁ
(+2.2V ≤ V
≤ +3.6V, +1.62V ≤ V ≤ +3.2V; C
≤ 15pF, C
≤ 10pF; R
< 150Ω, rise/fall time < 3ns, EN = V ,
SOURCE L
CC
L
IOVL_
IOVCC_
T
= -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, V = +1.8V, and T = +25°C.) (Notes 1, 2)
A
CC
L
A
ꢂARAMETER
Rise Time
ꢁYMB/L
C/NDITI/Nꢁ
MIN
TYꢂ
MAX
2.5
UNITꢁ
ns
I/O V
I/O V
t
Figure 1
Figure 1
Figure 2
Figure 2
CC_
RVCC
Fall Time
t
2.5
ns
CC_
FVCC
I/O V Rise Time
t
2.5
ns
L_
RVL
I/O V Fall Time
L_
t
2.5
ns
FVL
Propagation Delay
t
t
Figure 1
6.5
ns
PVL-VCC
(Driving I/O V
)
L_
Propagation Delay
(Driving I/O V
Figure 2
(Note 4)
Figure 3
6.5
0.7
ns
ns
µs
PVCC-VL
)
CC_
Channel-to-Channel Skew
t
SKEW
Propagation Delay From I/O V
L_
t
5
5
EN-VCC
to I/O V
after EN
CC_
Propagation Delay From I/O V
to I/O V after EN
L_
CC_
t
Figure 3
µs
EN-VL
Maximum Data Rate
Push-pull operation
100
Mbps
Note 1: All units are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by
A
correlation and design and not production tested.
Note 2: V must be less than or equal to V
during normal operation. However, V can be greater than V
during startup and
L
CC
L
CC
shutdown conditions.
Note 3: When V
is below V by more than the V - V shutdown threshold, the device turns off its pullup generators and the I/Os
CC
L
L
CC
enter their respective shutdown states.
Note 4: Guaranteed by design.
Note ꢀ: Input thresholds are referenced to the boost circuit.
Typical Operating Characteristics
(V
= 3.3V, V = 1.8V, C
= 10pF, C
= 15pF, R
= 150Ω, data rate = 100Mbps, push-pull driver, T = +25°C,
CC
L
IOVCC_
IOVL_
SOURCE A
unless otherwise noted.)
V
CC
SUPPLY CURRENT vs. V SUPPLY
CC
V SUPPLY CURRENT vs. V SUPPLY
L
CC
V SUPPLY CURRENT vs. V SUPPLY
L L
VOLTAGE (DRIVING ONE I/O V
)
VOLTAGE (DRIVING ONE I/O V
)
L_
L_
VOLTAGE (DRIVING ONE I/O V
)
CC_
15
12
400
390
10
8
V
= 3.6V
CC
380
370
360
9
6
3
6
4
350
340
330
320
310
300
2
0
0
3.6
3.2 3.4
2.2
2.6 2.8 3.0
2.4
3.4 3.6
2.2 2.4
2.6 2.8
3.0 3.2
1.6
2.0
2.4
2.8
3.2
V SUPPLY VOLTAGE (V)
L
V
SUPPLY VOLTAGE (V)
V SUPPLY VOLTAGE (V)
L
CC
4
_______________________________________________________________________________________
1.62V to 3.6V Improved High-Speed LLT
Typical Operating Characteristics (continued)
(V
= 3.3V, V = 1.8V, C
= 10pF, C
= 15pF, R
= 150Ω, data rate = 100Mbps, push-pull driver, T = +25°C,
CC
L
IOVCC_
IOVL_
SOURCE A
unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
V
CC
SUPPLY CURRENT vs. V SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
L
(DRIVING ONE I/O V
)
L_
(DRIVING ONE I/O V _)
(DRIVING ONE I/O V
)
CC
CC_
10
8
10
7
6
5
4
3
2
1
0
V
= 3.6V
CC
9
8
7
6
5
4
I
I
VCC
VCC
6
I
VL
4
I
VL
3
2
1
0
2
0
85
-40
35
10
TEMPERATURE (°C)
60
-15
1.6
2.0
2.4
2.8
3.2
-40
-15
10
35
60
85
V SUPPLY VOLTAGE (V)
L
TEMPERATURE (°C)
V
SUPPLY CURRENT vs. CAPACITIVE
RISE/FALL TIME vs. CAPACITIVE LOAD ON
CC
LOAD ON I/O V
(DRIVING ONE I/O V )
I/O V
(DRIVING I/O V )
)
CC_
L_
CC_
L_
16
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5000
4000
3000
2000
1000
0
14
12
10
8
t
RVCC
t
FVCC
6
4
2
0
10
15
20
25
30
35
40
10
15
20
25
30
35
40
10
15
20
25
30
35
40
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD ON
I/O V (DRIVING I/O V
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O V (DRIVING I/O V
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O V (DRIVING I/O V
)
CC_
)
CC_
)
L_
L_
L_
CC_
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
5.0
4.5
4.0
3.5
3.0
2.5
t
PHL
t
RVL
t
PLH
t
FVL
2.0
1.5
1.0
t
PLH
t
PHL
0.5
0
40
10
15
20
25
30
35
40
10
20
25
30
35
15
10
15
20
25
30
35
40
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
_______________________________________________________________________________________
ꢀ
1.62V to 3.6V Improved High-Speed LLT
Typical Operating Characteristics (continued)
(V
= 3.3V, V = 1.8V, C
= 10pF, C
= 15pF, R
= 150Ω, data rate = 100Mbps, push-pull driver, T = +25°C,
CC
L
IOVCC_
IOVL_
SOURCE A
unless otherwise noted.)
TYPICAL I/O V DRIVING
TYPICAL I/O V
(FREQUENCY = 26MHz, C
DRIVING
L_
CC_
(FREQUENCY = 26MHz, C
= 40pF)
= 15pF)
IOVCC_
IOVL_
I/O V
2V/div
CC_
I/O V
1V/div
L_
I/O V
2V/div
CC_
I/O V
1V/div
L_
10ns/div
10ns/div
Pin Description
ꢂIN
NAME
FUNCTI/N
UCꢁꢂ
A1
TDFN
8
I/O V
I/O V
I/O V
I/O V
4
3
2
1
Input/Output 4. Referenced to V
Input/Output 3. Referenced to V
Input/Output 2. Referenced to V
Input/Output 1. Referenced to V
.
.
.
.
CC
CC
CC
CC
CC
CC
CC
CC
A2
10
A3
12
A4
14
Power-Supply Voltage, +2.2V to +3.6V. Bypass V
to GND with a
CC
0.1µF ceramic capacitor. For full ESD protection, connect an
additional 1µF ceramic capacitor from V to GND as close to the
B1
9
V
CC
CC
V
input as possible.
CC
Logic Supply Voltage, +1.62V to +3.2V. Bypass V to GND with a
L
0.1µF ceramic capacitor placed as close to the device as possible.
B2
B3
6
2
V
L
Enable Input. Drive EN to GND for shutdown mode, or drive EN to
EN
V or V
L
for normal operation.
CC
B4
C1
C2
C3
C4
—
13
7
GND
Ground
Input/Output 4. Referenced to V .
I/O V 4
L
L
5
I/O V 3
Input/Output 3. Referenced to V .
L
L
3
I/O V 2
Input/Output 2. Referenced to V .
L
L
1
I/O V 1
L
Input/Output 1. Referenced to V .
L
4, 11
EP
N.C.
EP
No Connection. Leave N.C. unconnected.
Exposed Pad. Connect exposed pad to GND.
—
6
_______________________________________________________________________________________
1.62V to 3.6V Improved High-Speed LLT
Test Circuits/Timing Diagrams
t
t
RVCC
FVCC
V
V
L
CC
90%
90%
V
EN
V
CC
L
I/O V
MAX13042E–MAX13045E
L_
50%
50%
V
V
L
CC
50%
50%
I/O V
I/O V
CC_
L_
10%
I/O V
10%
CC_
150Ω
C
IOVCC
t
t
PHL
PLH
t
= t OR t
PVL-VCC PLH PHL
Figure 1. Push-Pull Driving I/O V Test Circuit and Timing
L_
t
t
FVL
RVL
V
L
V
CC
I/O V
90%
CC_
EN
V
V
CC
L
MAX13042E–MAX13045E
V
V
L
CC
90%
50%
50%
50%
50%
I/O V
I/O V
CC_
L_
10%
150Ω
10%
I/O V
L_
C
IOVL
t
t
PHL
PLH
t = t OR t
PVCC-VL PLH PHL
Figure 2. Push-Pull Driving I/O V
Test Circuit and Timing
CC_
_______________________________________________________________________________________
7
1.62V to 3.6V Improved High-Speed LLT
Test Circuits/Timing Diagrams (continued)
V
L
EN
EN
MAX13042E–
MAX13045E
V
V
CC
L
t'
EN-VCC
0V
I/O V
CC_
SOURCE
V
L
I/O V
L_
I/O V
L_
0V
V
C
IOVCC
CC
R
LOAD
V
/ 2
I/O V
CC
CC_
V
L
0V
V
CC
V
L
EN
EN
R
LOAD
t"
MAX13042E–
MAX13045E
EN-VCC
V
V
CC
L
0V
SOURCE
V
L
I/O V
L_
0V
I/O V
L_
I/O V
CC_
V
I/O V
CC
CC_
V
/ 2
CC
C
IOVCC
0V
t
IS WHICHEVER IS LARGER BETWEEN t'
AND t"
.
EN-VCC
EN-VCC
EN-VCC
V
L
EN
EN
V
MAX13042E–
MAX13045E
V
CC
t'
L
EN-VL
0V
SOURCE
V
CC
I/O V
CC_
I/O V
I/O V
CC_
L_
0V
V
L
C
IOVL
V
CC
R
LOAD
V / 2
L
I/O V
L_
0V
V
L
EN
EN
t"
EN-VL
0V
V
MAX13042E–
MAX13045E
V
CC
L
V
CC
V
L
I/O V
CC_
SOURCE
0V
R
LOAD
I/O V
CC_
V
I/O V
L
L_
I/O V
L_
V / 2
L
0V
AND t"
C
IOVL
t
IS WHICHEVER IS LARGER BETWEEN t'
.
EN-VCC
EN-VCC
EN-VCC
Figure 3. Enable Test Circuit and Timing
8
_______________________________________________________________________________________
1.62V to 3.6V Improved High-Speed LLT
feature an automatic shutdown mode that disables the
Functional Diagram
part when V
is less than V . The state of I/O V
and
CC
L
CC_
I/O V during shutdown is chosen by selecting the
L_
V
V
L
CC
appropriate part version (see the Ordering Information/
Selector Guide).
The MAX13042E–MAX13045E operate with V
volt-
CC
MAX13042E–MAX13045E
ages from +2.2V to +3.6V and V voltages from +1.62V
L
to +3.2V.
Level Translation
I/O V 1
L
I/O V
1
CC
For proper operation, ensure that +2.2V ≤ V
CC
≤ +3.6V, +1.62V ≤ V ≤ V
- 0.2V. When power is
is missing or less than V , the
L
L
CC
supplied to V while V
L
CC
MAX13042E–MAX13045E automatically enter a low-
power mode. The devices will also enter shutdown mode
I/O V
I/O V
2
3
I/O V 2
L
CC
CC
when EN = 0V. This allows V
to be disconnected and
CC
still have a known state on I/O V . The maximum data
L_
rate depends heavily on the load capacitance (see the
Rise/Fall Time vs. Capacitive Load graphs in the Typical
Operating Characteristics), output impedance of the
driver, and the operating voltage range.
I/O V 3
L
Input Driver Requirements
The MAX13042E–MAX13045E architecture is based on
an nMOS pass gate and output accelerator stages
(Figure 6). The accelerators are active only when there
is a rising/falling edge on a given I/O. A short pulse is
then generated where the output accelerator stages
become active and charge/discharge the capacitances
at the I/Os. Due to its architecture, both input stages
become active during the one-shot pulse. This can lead
to current feeding into the external source that is driving
the translator. However, this behavior helps to speed
up the transition on the driven side.
I/O V 4
L
I/O V
4
CC
EN
GND
Detailed Description
The MAX13042E–MAX13045E 4-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13042E–MAX13045E are ideally suited for level
translation in systems with four channels. Externally
The MAX13042E–MAX13045E have internal current
sources capable of sourcing 30µA to pull up the I/O
lines. These internal-pullup current sources allow the
inputs to be driven with open-drain drivers as well as
push-pull drivers. It is not recommended to use external
pullup resistors on the I/O lines. The architecture of the
MAX13042E–MAX13045E permits either side to be dri-
ven with a minimum of 4mA drivers or larger.
applied voltages, V
and V , set the logic levels on
L
CC
either side of the device. Logic signals present on the
V side of the device appear as a high-voltage logic
L
signal on the V
side of the device and vice-versa.
CC
The MAX13042E–MAX13045E operate at full speed
with external drivers that source as little as 4mA output
Output Load Requirements
The MAX13042E–MAX13045E I/O are designed to drive
CMOS inputs. Do not load the I/O lines with a resistive
load less than 25kΩ and do not place an RC circuit at
the input of these devices to slow down the edges. If a
slower rise/fall time is required, refer to the MAX3000E/
MAX3001E logic-level translator data sheet.
current. Each I/O channel is pulled up to V
or V by
L
CC
an internal 30µA current source, allowing the
MAX13042E–MAX13045E to be driven by either push-
pull or open-drain drivers.
The MAX13042E–MAX13045E feature an enable (EN)
input that places the devices into a low-power shutdown
mode when driven low. The MAX13042E–MAX13045E
_______________________________________________________________________________________
9
1.62V to 3.6V Improved High-Speed LLT
late signals without inversion. These devices provide
the smallest solution (UCSP package) for unidirectional
level translation without inversion.
V
CC
V
L
ENABLE
ENABLE
ENABLE
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
30μA
30μA
I/O V
L_
I/O V
CC_
Use with External Pullup/
Pulldown Resistors
Due to the architecture of the MAX13042E–MAX13045E,
it is not recommended to use external pullup or pull-
down resistors on the bus. In certain applications, the
use of external pullup or pulldown resistors is desired to
have a known bus state when there is no active driver
on the bus. The MAX13042E–MAX13045E include inter-
nal pullup current sources that set the bus state when
the device is enabled. In shutdown mode, the state of
V
V
V
V
L
CC
BOOST
CIRCUIT
L
CC
BOOST
CIRCUIT
NOTE: THE MAX13042E–MAX13045E ARE ENABLED WHEN
V < AND EN = V .
I/O V
and I/O V is dependent on the selected part
L_
V
CC_
L
CC
L
version (see the Ordering Information/Selector Guide).
Figure 4. Simplified Functional Diagram for One I/O Line
Open-Drain Signaling
The MAX13042E–MAX13045E are designed to pass open-
drain as well as CMOS push-pull signals. When used with
open-drain signaling, the rise time will be dominated by the
interaction of the internal pullup current source and the par-
asitic load capacitance. The MAX13042E–MAX13045E
include internal rise-time accelerators to speed up transi-
tions, eliminating any need for external pullup resistors. For
Shutdown Mode
The MAX13042E–MAX13045E feature an enable (EN)
input that places the devices into a low-power shutdown
mode when driven low. The MAX13042E–MAX13045E
feature an automatic shutdown mode that disables the
part when V is unconnected or less than V .
CC
L
2
applications such as I C or 1-wire that require an external
Applications Information
Layout Recommendations
Use standard high-speed layout practices when
laying out a board with the MAX13042E–MAX13045E.
For example, to minimize line coupling, place all other
signal lines not connected to the MAX13042E–
MAX13045E at least 1x the substrate height of the
PCB away from the input and output lines of the
MAX13042E–MAX13045E.
pullup resistor, please consult the MAX3378E and
MAX3396E data sheets.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profiles, as well as the latest information on reliability testing
results, go to Maxim’s website at www.maxim-ic.com/ucsp
to find the Application Note: UCSP – A Wafer-Level Chip-
Scale Package.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass V and V
to ground with 0.1µF ceram-
CC
L
Chip Information
ic capacitors. Place all capacitors as close to the
power-supply inputs as possible. For full ESD protec-
PROCESS: BiCMOS
tion, bypass V
with a 1µF ceramic capacitor located
CC
CC
as close to the V
input as possible.
Unidirectional vs. Bidirectional
Level Translator
The MAX13042E–MAX13045E bidirectional level trans-
lators can operate as a unidirectional device to trans-
10 ______________________________________________________________________________________
1.62V to 3.6V Improved High-Speed LLT
Pin Configurations
TOP VIEW
TOP VIEW
(BUMPS ON BOTTOM)
1
2
3
4
+
+
MAX13042E–MAX13045E
14
13
I/O V
GND
1
I/O V 1
L
1
2
3
4
5
6
7
CC
A
EN
I/O V
4
I/O V 2
CC
I/O V
3
I/O V 1
CC
CC
CC
12 I/O V
11 N.C.
2
I/O V 2
L
CC
B
V
EN
N.C.
V
GND
CC
L
MAX13042E–MAX13045E
I/O V 3
L
I/O V
3
4
C
10
9
CC
I/O V 4
I/O V 2
L
I/O V 3
I/O V 1
L
L
L
V
V
L
CC
*EP
UCꢁꢂ
(1.ꢀ4mm x 2.12mm)
8
I/O V
I/O V 4
L
CC
TDFN
(3mm x 3mm)
*CONNECT EXPOSED PAD TO GROUND
Ordering Information/Selector Guide (continued)
ꢂIN-
ꢂACKAGE
Iꢃ/ k ꢁTATE DURING
L_
Iꢃ/ k
ꢁTATE DURING
ꢁHUTD/WN
T/ꢂ
MARK
CC_
ꢂART
ꢂKG C/DE
ꢁHUTD/WN
MAX13043EEBC+T 12 UCSP-12
MAX13043EETD+T 14 TDFN-EP**
High Impedance
High Impedance
16.5kΩ to GND
16.5kΩto GND
16.5kΩ to GND
16.5kΩ to GND
16.5kΩ to GND
16.5kΩ to GND
ADR
ADF
ADS
ADG
ADT
ADH
B12-3
T1433-2
B12-3
MAX13044EEBC+T* 12 UCSP-12
MAX13044EETD+T* 14 TDFN-EP**
MAX1304ꢀEEBC+T* 12 UCSP-12
MAX13045EETD+T* 14 TDFN-EP**
High Impedance
High Impedance
16.5kΩ to GND
16.5kΩ to GND
T1433-2
B12-3
T1433-2
Note: All devices operate over the -40°C to +85°C temperature
range.
*Future product—contact factory for availability.
**EP = Exposed paddle.
+Denotes a lead-free package.
______________________________________________________________________________________ 11
1.62V to 3.6V Improved High-Speed LLT
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.comꢃpac5ages.)
PACKAGE OUTLINE, 4x3 UCSP
1
21-0104
F
1
12 ______________________________________________________________________________________
1.62V to 3.6V Improved High-Speed LLT
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.comꢃpac5ages.)
______________________________________________________________________________________ 13
1.62V to 3.6V Improved High-Speed LLT
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.comꢃpac5ages.)
PACKAGE VARIATIONS
COMMON DIMENSIONS
SYMBOL
A
MIN.
0.70
MAX.
0.80
PKG. CODE
T633-2
N
6
D2
E2
e
JEDEC SPEC
MO229 / WEEA
MO229 / WEEC
MO229 / WEEC
MO229 / WEED-3
MO229 / WEED-3
- - - -
b
[(N/2)-1] x e
1.90 REF
1.95 REF
1.95 REF
1.50±0.10
1.50±0.10
1.50±0.10
1.50±0.10
1.50±0.10
1.70±0.10
1.70±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
0.95 BSC
0.65 BSC
0.65 BSC
0.50 BSC
0.50 BSC
0.40 BSC
0.40 BSC
0.40±0.05
0.30±0.05
0.30±0.05
0.25±0.05
0.25±0.05
0.20±0.05
0.20±0.05
T833-2
8
D
E
2.90
2.90
3.10
3.10
T833-3
8
A1
0.00
0.20
0.05
0.40
T1033-1
T1033-2
T1433-1
T1433-2
10
10
14
14
2.00 REF
2.00 REF
2.40 REF
2.40 REF
L
k
0.25 MIN.
0.20 REF.
- - - -
A2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
Springer
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