MAX1315ECM [MAXIM]
1075ksps, 12-Bit, Parallel-Output ADCs with ±10V, ±5V, and 0 to 5V Analog Input Ranges;
| 型号： | MAX1315ECM |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1075ksps, 12-Bit, Parallel-Output ADCs with ±10V, ±5V, and 0 to 5V Analog Input Ranges 信息通信管理 转换器 |
| 文件： | 总28页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3481; Rev 0; 10/04
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
General Description
Features
♦ ±±1 LS1ꢀI ꢁ1±ꢂꢃ01 LS1BI 1ꢄꢅ(ma
♦ 84dSc1LFBRꢁ1-86dSc1THBꢁ17±dS1LꢀIABꢁ1
=15ꢂꢂkHz1(t1-ꢂꢃ4dSFL
The MAX1307/MAX1311/MAX1315 12-bit, analog-to-digi-
tal converters (ADCs) feature a 1075ksps sampling rate, a
20MHz input bandwidth, and three analog input ranges.
The MAX1307 provides a 0 to +5V input range, with ±±V
fault-tolerant inputs. The MAX1311 provides a ±5V input
range with ±1±.5V fault-tolerant inputs. The MAX1315 pro-
vides a ±10V input range with ±1±.5V fault-tolerant inputs.
f
ꢀI
♦ Emtended1ꢀnput1R(nges
ꢂ1to1+5V1ꢄMAX±3ꢂ7a
-5V1to1+5V1ꢄMAX±3±±a
-±ꢂV1to1+±ꢂV1ꢄMAX±3±5a
The MAX1307/MAX1311/MAX1315 include an on-chip
2.5V reference. These devices also accept an external
+2V to +3V reference.
♦ F(ult-Toler(nt1ꢀnputs
±6V1ꢄMAX±3ꢂ7a
±±6ꢃ5V1ꢄMAX±3±±ꢆMAX±3±5a
All devices operate from a +4.75 to +5.25V analog sup-
ply, and a +2.7V to +5.25V digital supply. The devices
consume 3±mA total supply current when fully opera-
tional. A 0.±2µA shutdown mode is available to save
power during idle periods.
♦ F(st1ꢂꢃ72µs1Conversion1Tiꢅe
♦ ±2-Sitꢁ12ꢂMHz1P(r(llel1ꢀnterf(ce
♦ ꢀntern(l1or1Emtern(l1Clock
A 20MHz, 12-bit, parallel data bus provides the conver-
sion results. An internal 15MHz oscillator, or an externally
applied clock, drives conversions.
♦ +2ꢃ5V1ꢀntern(l1Reference1or1+2ꢃꢂV1to1+3ꢃꢂV
Emtern(l1Reference
♦ +5V1An(log1Lupplyꢁ1+3V1to1+5V1Bigit(l1Lupply
36ꢅA1An(log1Lupply1Current
±ꢃ3ꢅA1Bigit(l1Lupply1Current
Lhutdown1Mode
Each device is available in a 48-pin 7mm x 7mm
TQFP package and operates over the extended
(-40°C to +85°C) temperature range.
Applications
♦ 48-Pin1TQFP1P(ck(ge1ꢄ7ꢅꢅ1m17ꢅꢅ1Footprinta
Industrial Process Control and Automation
Vibration and Waveform Analysis
Data-Acquisition Systems
Pin Configuration
Ordering Information
TOP VIEW
PART
TEMP1RAIGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PꢀI-PACKAGE
48 TQFP
MAX±3ꢂ7ECM
MAX±3±±ECM
MAX±3±5ECM
48 TQFP
48 TQFP
AVDD
AGND
AGND
AIN
1
2
36 D10
35 D9
34 D8
33 D7
32 D6
31 D5
30 D4
29 D3
3
4
I.C.
5
MSV
I.C.
6
MAX1307
MAX1311
MAX1315
7
Selector Guide
I.C.
8
I.C.
D2
9
28
27
26
25
ꢀIPUT
RAIGE1ꢄVa
CHAIIE
COUIT
PKG
COBE
I.C.
D1
10
11
12
PART
I.C.
D0
I.C.
DVDD
MAX1307EC
MAX1311EC
MAX1315EC
0 to +5
±5
1
1
1
C48-±
C48-±
C48-±
±10
TQFP
________________________________________________________________ Maxim Integrated Products
±
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
ASLO UTE1MAXꢀMUM1RATꢀIGL
AV to AGND .........................................................-0.3V to +±V
REF , REF, MSV to AGND.....................-0.3V to (AV + 0.3V)
MS DD
DD
DV
to DGND.........................................................-0.3V to +±V
REF+, COM, REF- to AGND.....................-0.3V to (AV + 0.3V)
DD
DD
AGND to DGND.....................................................-0.3V to +0.3V
CH0, I.C. to AGND (MAX1307)..............................................±±V
CH0, I.C. to AGND (MAX1311) .............................................±1±.5V
CH0, I.C. to AGND (MAX1315) .............................................±1±.5V
D0–D11 to DGND ....................................-0.3V to (DV + 0.3V)
EOC, EOLC, RD, WR, CS to DGND.........-0.3V to (DV + 0.3V)
Maximum Current into Any Pin Except AV
,
DD
DV , AGND, DGND....................................................±50mA
DD
Continuous Power Dissipation (T = +70°C)
A
TQFP (derate 22.7mW/°C above +70°C)................1818.2mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-±5°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
DD
DD
DD
CONVST, CLK, SHDN, CHSHDN to DGND...-0.3V to (DV + 0.3V)
INTCLK/EXTCLK to AGND.......................-0.3V to (AV + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
E ECTRꢀCA 1CHARACTERꢀLTꢀCL
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
REF-
REF+-to-REF-
COM
MSV
lar devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T = T
to T
,
MAX
CLK
A
MIN
unless otherwise noted. Typical values are at T = +25°C.) (See Figures 3 and 4)
A
PARAMETER
LTATꢀC1PERFORMAICE1ꢄIote1±a
Resolution
LYMSO
COIBꢀTꢀOIL
MꢀI
TYP
MAX
UIꢀTL
N
12
Bits
LSB
LSB
Integral Nonlinearity
INL
DNL
±0.5
±0.3
±3
±3
7
±1.0
±0.ꢀ
±10
±15
Differential Nonlinearity
No missing codes
Unipolar, 0x000 to 0x001
Bipolar, 0xFFF to 0x000
Unipolar, 0x000 to 0x001
Bipolar, 0xFFF to 0x000
Offset Error
LSB
Offset-Error Temperature Drift
ppm/°C
7
Gain Error
±2
4
±1±
-80
LSB
Gain-Error Temperature Drift
ppm/°C
BYIAMꢀC1PERFORMAICE1AT1f 1=15ꢂꢂkHzꢁ1A =1-ꢂꢃ4dSFL
ꢀI
ꢀI1
Signal-to-Noise Ratio
SNR
SINAD
THD
±8
±8
71
71
dB
dB
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
AIA OG1ꢀIPUTL ꢄAꢀIa
-8±
84
dBc
dBc
SFDR
MAX1307
MAX1311
MAX1315
MAX1307
MAX1311
MAX1315
0
+5
+5
Input Voltage
V
-5
V
AIN
-10
+10
7.58
8.±±
Input Resistance
(Note 2)
R
kΩ
AIN
14.2±
0.54
V
V
V
V
V
V
= +5V
= 0V
0.72
0.3ꢀ
0.74
CH
CH
CH
CH
CH
CH
MAX1307
MAX1311
MAX1315
-0.157
-1.1±
-1.13
-0.12
0.2ꢀ
= +5V
= -5V
Input Current
(Note 2)
I
mA
AIN
-0.87
0.5±
= +10V
= -10V
-0.85
2
_______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
E ECTRꢀCA 1CHARACTERꢀLTꢀCL1ꢄcontinueda
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
REF-
REF+-to-REF-
COM
MSV
lar devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T = T
to T
,
MAX
CLK
A
MIN
unless otherwise noted. Typical values are at T = +25°C.) (See Figures 3 and 4)
A
PARAMETER
Input Capacitance
LYMSO
COIBꢀTꢀOIL
MꢀI
TYP
MAX
UIꢀTL
C
15
pF
AIN
TRACKꢆHO B
External-Clock Throughput Rate
Internal-Clock Throughput Rate
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
f
f
(Note 3)
(Note 3)
1075
ꢀ83
20
ksps
ksps
MHz
MHz
ns
TH
TH
20
t
8
AD
Aperture Jitter
t
50
ps
RMS
AJ
ꢀITERIA 1REFEREICE
REF Output Voltage
V
2.475
2.475
2.500
30
2.525
2.525
V
REF
Reference Output-Voltage
Temperature Drift
ppm/°C
REF
Output Voltage
V
2.500
3.850
2.±00
1.350
V
V
V
V
MS
REFMS
REF+ Output Voltage
COM Output Voltage
REF- Output Voltage
V
REF+
V
COM
V
REF-
V
V
-
REF+
Differential Reference Voltage
2.500
V
-
REF
EXTERIA 1REFEREICE ꢄREF1(nd1REF 1(re1emtern(lly1drivena
ML
REF Input Voltage Range
REF Input Resistance
REF Input Capacitance
V
2.0
2.0
2.5
5
3.0
3.0
V
kΩ
pF
V
REF
R
(Note 4)
(Note 5)
REF
15
REF
REF
REF
Input Voltage Range
Input Resistance
V
2.5
MS
MS
MS
REFMS
R
5
kΩ
pF
V
REFMS
Input Capacitance
15
REF+ Output Voltage
COM Output Voltage
REF- Output Voltage
V
V
V
V
= +2.5V
= +2.5V
= +2.5V
3.850
2.±00
1.350
REF+
REF
REF
REF
V
V
COM
V
V
REF-
V
V
-
REF+
Differential Reference Voltage
V
= +2.5V
2.500
V
REF
-
REF
BꢀGꢀTA 1ꢀIPUTL ꢄRDꢁ1WRꢁ1CSꢁ1C Kꢁ1LHBIꢁ1CHSHDNꢁ1COIVLTa
Input-Voltage High
Input-Voltage Low
Input Hysteresis
V
0.7 x DV
V
V
IH
DD
V
0.3 x DV
DD
IL
20
mV
_______________________________________________________________________________________
3
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
E ECTRꢀCA 1CHARACTERꢀLTꢀCL1ꢄcontinueda
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
REF-
REF+-to-REF-
COM
MSV
lar devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T = T
to T
,
MAX
CLK
A
MIN
unless otherwise noted. Typical values are at T = +25°C.) (See Figures 3 and 4)
A
PARAMETER
Input Capacitance
Input Current
C OCK-LE ECT1ꢀIPUT ꢄꢀITC KꢆEXTCLKa
LYMSO
COIBꢀTꢀOIL
MꢀI
TYP
15
MAX
UIꢀTL
pF
C
IN
I
V
= 0 or DV
DD
0.02
±1
µA
IN
IN
Input-Voltage High
Input-Voltage Low
V
0.7 x AV
V
V
IH
DD
V
0.3 x AV
DD
IL
BꢀGꢀTA 1OUTPUTL ꢄBꢂ–B±±ꢁ1EOCꢁ1EOLCa
Output-Voltage High
V
I
I
= 0.8mA, Figure 1
DV - 0.±
DD
V
V
OH
SOURCE
Output-Voltage Low
V
= 1.±mA, Figure 1
SINK
0.4
1
OL
D0–D11 Tri-State Leakage Current
RD = high or CS = high
0.0±
15
µA
D0–D11 Tri-State Output
Capacitance
RD = high or CS = high
pF
POWER1LUPP ꢀEL
Analog Supply Voltage
Digital Supply Voltage
AV
DV
4.75
2.70
5.25
5.25
3ꢀ
V
V
DD
DD
MAX1307
MAX1311
MAX1315
MAX1307
MAX1311
MAX1315
3±
34
Analog Supply Current
I
mA
mA
3±
AVDD
34
3±
1.3
1.3
1.3
0.±
0.02
50
2.±
2.±
2.±
10
Digital Supply Current
I
DVDD
(C
= 100pF) (Note ±)
LOAD
I
SHDN = DV , V
= float
AVDD
DD CH
Shutdown Current
(Note 7)
µA
dB
I
SHDN = DV , RD = WR = high
1
DVDD
DD
Power-Supply Rejection Ratio
PSRR
AV
= +4.75V to +5.25V
DD
TꢀMꢀIG1CHARACTERꢀLTꢀCL1ꢄFigure1±a
Internal clock, Figure ±
External clock, Figure 7
800
12
ꢀ00
ns
Time to Conversion Result
t
CONV
CLK
cycles
CONVST Pulse-Width Low
(Acquisition Time)
t
Figures ±, 7 (Note 8)
0.1
1000.0
µs
ACQ
CS to RD
RD to CS
t
t
Figures ±, 7
Figures ±, 7
(Note ꢀ)
(Note ꢀ)
ns
ns
CTR
RTC
Data Access Time
(RD Low to Valid Data)
t
Figures ±, 7
30
30
ns
ACC
Bus Relinquish Time (RD High)
CLK Rise to EOC Delay
t
Figures ±, 7
Figure 7
5
ns
ns
ns
ns
REQ
t
20
20
20
EOCD
CLK Rise to EOLC Fall Delay
CONVST Fall to EOLC Rise Delay
t
Figure 7
EOLCD
t
Figures ±, 7
CVEOLCD
4
_______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
E ECTRꢀCA 1CHARACTERꢀLTꢀCL1ꢄcontinueda
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
REF-
REF+-to-REF-
COM
MSV
lar devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T = T
to T
,
MAX
CLK
A
MIN
unless otherwise noted. Typical values are at T = +25°C.) (See Figures 3 and 4)
A
PARAMETER
LYMSO
COIBꢀTꢀOIL
Internal clock, Figure ±
MꢀI
TYP
MAX
UIꢀTL
50
ns
EOC Pulse Width
t
EOC
CLK
cycles
External clock, Figure 7
1
External CLK Period
t
Figure 7
0.05
20
10.00
20.0
µs
ns
CLK
External CLK High Period
External CLK Low Period
External Clock Frequency
Internal Clock Frequency
CONVST High to CLK Edge
t
Logic sensitive to rising edges, Figure 7
Logic sensitive to rising edges, Figure 7
(Note 10)
CLKH
t
20
ns
CLKL
f
0.1
MHz
MHz
ns
CLK
f
15
INT
CNTC
t
Figure 7
20
Iote1±: For the MAX1307, V = 0 to +5V. For the MAX1311, V = -5V to +5V. For the MAX1315, V = -10V to +10V.
IN
IN
IN
Iote12: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:
V
− V
BIAS
AIN
I
=
AIN
R
AIN
for AIN within the input voltage range.
Iote13: Throughput rate is a function of clock frequency (f
). The external clock throughput rate is specified with f
=
CLK
CLK
1±.±7MHz and the internal clock throughput rate is specified with f
information.
= 15MHz. See the Data Throughput section for more
CLK
Iote14: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
VREF − 2.5V
IREF
=
RREF
for V
within the input voltage range.
REF
Iote15: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
MS
MS
VREFMS − 2.5V
IREFMS
=
RREFMS
for V
within the input voltage range.
REFMS
Iote16: The analog input is driven with a -0.4dBFS 500kHz sine wave.
Iote17: Shutdown current is measured with the analog input floating. The large amplitude of the maximum shutdown-current speci-
fication is due to automated test equipment limitations.
Iote18: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.
Iote10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply.
Iote1±ꢂ: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST
and the falling edge of EOLC to a maximum of 1ms.
_______________________________________________________________________________________
5
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Typical Operating Characteristics
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
OFFSET ERROR
vs. TEMPERATURE
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
16
1.0
0.8
12
8
0.6
0.4
4
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-4
-8
-12
-16
-40
-15
10
35
60
85
4.7
4.8
4.9
5.0
AV (V)
5.1
5.2
5.3
°
TEMPERATURE ( C)
DD
GAIN ERROR
vs. TEMPERATURE
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
16
12
8
1
0
-1
4
0
-2
-3
-4
-5
-4
-8
-12
-16
-40
-15
10
35
60
85
4.7
4.8
4.9
5.0
AV (V)
5.1
5.2
5.3
°
TEMPERATURE ( C)
DD
6
_______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
SMALL-SIGNAL BANDWIDTH
vs. ANALOG INPUT FREQUENCY
LARGE-SIGNAL BANDWIDTH
vs. ANALOG INPUT FREQUENCY
2
0
2
0
A
= -20dBFS
A
= -0.5dBFS
IN
IN
-2
-2
-4
-4
-6
-6
-8
-8
-10
-12
-10
-12
0.1
1
10
100
0.1
1
10
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(2048-POINT DATA RECORD)
OUTPUT HISTOGRAM (DC INPUT)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
6000
5000
4000
3000
2000
1000
0
f
f
A
= 1.04167Msps
= 500kHz
TH
IN
5497
= -0.05dBFS
IN
SNR = 70.7dB
SINAD = 70.6dB
THD = -87.5dBc
SFDR = 87.1dBc
1611
1084
0
0
0
100
200
300
400
500
2044
2045
2046
2047
2048
FREQUENCY (kHz)
DIGITAL OUTPUT CODE
_______________________________________________________________________________________
7
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
SIGNAL-TO-NOISE RATIO
vs. CLOCK FREQUENCY
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK FREQUENCY
80
78
76
74
72
70
68
66
64
62
60
80
78
76
74
72
70
68
66
64
62
60
0
5
10
15
(MHz)
20
25
0
5
10
15
(MHz)
20
25
f
f
CLK
CLK
TOTAL HARMONIC DISTORTION
vs. CLOCK FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
-60
-65
-70
-75
-80
-85
-90
-95
-100
100
95
90
85
80
75
70
65
60
0
5
10
15
(MHz)
20
25
0
5
10
15
(MHz)
20
25
f
f
CLK
CLK
8
_______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. REFERENCE VOLTAGE
SIGNAL-TO-NOISE RATIO
vs. REFERENCE VOLTAGE
75
74
73
72
71
70
69
68
67
66
65
75
74
73
72
71
70
69
68
67
66
65
2.0
2.2
2.4
2.6
(V)
2.8
3.0
2.0
2.2
2.4
2.6
(V)
2.8
3.0
V
V
REF
REF
TOTAL HARMONIC DISTORTION
vs. REFERENCE VOLTAGE
SPURIOUS-FREE DYNAMIC RANGE
vs. REFERENCE VOLTAGE
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
100
95
90
85
80
75
70
2.0
2.2
2.4
2.6
(V)
2.8
3.0
2.0
2.2
2.4
2.6
(V)
2.8
3.0
V
REF
V
REF
_______________________________________________________________________________________
0
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
1.2
1.0
0.8
0.6
0.4
0.2
0
42
40
38
36
34
32
30
2.5
3.0
3.5
4.0
4.5
5.0
5.5
4.7
4.8
4.9
5.0
5.1
5.2
5.3
DV (V)
DD
AV (V)
DD
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
DIGITAL SHUTDOWN CURRENT
vs. DIGITAL SUPPLY VOLTAGE
700
22
680
660
640
620
600
580
560
540
520
500
20
18
16
14
12
10
4.7
4.8
4.9
5.0
AV (V)
5.1
5.2
5.3
2.5
3.0
3.5
4.0
DV (V)
4.5
5.0
5.5
DD
DD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.5004
2.5003
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
-40
-15
10
35
60
85
4.7
4.8
4.9
5.0
AV (V)
5.1
5.2
5.3
TEMPERATURE (°C)
DD
±ꢂ ______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, AGND = DGND = 0, V
= V
= +2.5V (external reference), C
= C
= 0.1µF, C
=
DD
DD
REF
REFMS
REF
REFMS
REF+
C
= 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF, C
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
REF-
REF+-to-REF-
COM
MSV
devices), f
= 1±.±7MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), f = 500kHz, A = -0.4dBFS. T = +25°C,
CLK
IN IN A
unless otherwise noted.) (Figures 3 and 4)
INTERNAL CLOCK CONVERSION TIME
INTERNAL CLOCK CONVERSION TIME
vs. TEMPERATURE
vs. ANALOG SUPPLY VOLTAGE
900
800
700
600
500
400
300
200
100
0
820
800
780
760
740
720
700
t
t
CONV
CONV
4.7
4.8
4.9
5.0
5.1
5.2
5.3
-40
-15
10
35
60
85
AV (V)
DD
TEMPERATURE (°C)
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
2.0
1.5
1.0
0.5
0
3.0
2.0
1.5
1.0
0.5
0
MAX1307
MAX1311
MAX1315
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
-20 -15 -10 -5
0
5
10 15 20
-6
-4
-2
0
2
4
6
-20 -15 -10 -5
0
5
10 15 20
V
(V)
V
(V)
CH_
V
(V)
CH_
CH_
______________________________________________________________________________________ ±±
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Pin Description
PꢀI
IAME
AV
FUICTꢀOI
is the power input for the analog section of the converter. Apply +5V to AV
pins together.1See the Layout, Grounding, and Bypassing section for additional
DD
Analog Power Input. AV
Connect all AV
information.
.
DD
DD
1, 15, 17
DD
2, 3, 14,
1±, 23
AGND Analog Ground. AGND is the power return for AV .1Connect all AGND pins together.
DD
4
A
IN
Analog Input
Midscale Voltage Bypass.1For the unipolar MAX1307, connect a 2.2µF and a 0.1µF capacitor from MSV to
AGND. For the bipolar MAX1311/MAX1315, connect MSV to AGND.
±
MSV
INTCLK/ Clock-Mode Select Input.1Connect INTCLK/EXTCLK to AV
EXTCLK INTCLK/EXTCLK to AGND to use an external clock connected to CLK.
to select the internal clock. Connect
DD
13
18
Midscale Reference Bypass/Input.1REF connects through a 5kΩ resistor to the internal +2.5V bandgap
MS
reference buffer.
For the MAX1307 unipolar devices, V
is the input to the unity-gain buffer that drives MSV.1MSV sets the
REFMS
midpoint of the input voltage range.1For internal reference operation, bypass REF with a ≥0.01µF capacitor
MS
REF
MS
to AGND.1For external reference operation, drive REF with an external voltage from +2V to +3V.
MS
For the MAX1311/MAX1315 bipolar devices, connect REF to REF.1For internal reference operation, bypass
MS
the REF /REF node with a ≥0.01µF capacitor to AGND.1For external reference operation, drive the
MS
REF /REF node with an external voltage from +2V to +3V.
MS
ADC Reference Bypass/Input. REF connects through a 5kΩ resistor to the internal +2.5V bandgap
reference buffer.
For internal reference operation, bypass REF with a ≥0.01µF capacitor.
For external reference operation with the MAX1307 unipolar devices, drive REF with an external voltage
from +2V to +3V.
1ꢀ
REF
For external reference operation with the MAX1311/MAX1315 bipolar devices, connect REF to REF and
MS
drive the REF /REF node with an external voltage from +2V to +3V.
MS
Positive Reference Bypass.1Bypass REF+ with a 0.1µF capacitor to AGND. Also bypass REF+ to REF- with
20
21
REF+
COM
a 2.2µF and a 0.1µF capacitor.1V
= V
+ V
/ 2.
REF
REF+
COM
Reference Common Bypass.1Bypass COM to AGND with a 2.2µF and a 0.1µF capacitor.
= 13 / 25 x AV
V
.
DD
COM
Negative Reference Bypass.1Bypass REF- with a 0.1µF capacitor to AGND. Also bypass REF- to REF+ with
a 2.2µF and a 0.1µF capacitor.
22
REF-
V
= V
- V
/ 2.
REF+
COM
REF
24, 3ꢀ
25, 38
DGND Digital Ground. DGND is the power return for DV .1Connect all DGND pins together.
DD
Digital Power Input. DV
powers the digital section of the converter, including the parallel interface. Apply
DD
DV
DD
+2.7V to +5.25V to DV . Bypass DV
to DGND with a 0.1µF capacitor.1Connect all DV
pins together.
DD
DD
DD
2±
27
28
2ꢀ
30
31
D0
Digital Output 0 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output 1 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output 2 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output 3 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output 4 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output 5 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
D1
D2
D3
D4
D5
±2 ______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Pin Description (continued)
PꢀI
32
33
34
35
3±
37
IAME
D±
FUICTꢀOI
Digital Output ± of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output 7 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output 8 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output ꢀ of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output 10 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
Digital Output 11 of 12-Bit Parallel Data Bus.1High impedance when RD = 1 or CS = 1.
D7
D8
Dꢀ
D10
D11
End-of-Conversion Output. EOC goes low to indicate the end of a conversion.1It returns high on the next rising
CLK edge or the falling CONVST edge.
40
41
EOC
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion.1It returns high
when CONVST goes low for the next conversion sequence.
EOLC
42
43
RD
Read Input. Pulling RD low initiates a read command of the parallel data bus.
WR
Write Input. WR is not implemented. Connect WR to RD, CS, DGND, or DV
DD.
Chip-Select Input.1Pulling CS low activates the digital interface.1Forcing CS high places D0–D11 in high-
impedance mode.
44
45
CS
Conversion Start Input. Driving CONVST high initiates the conversion process. The analog inputs are
sampled on the rising edge of CONVST.
CONVST
External Clock Input.1For external clock operation, connect INTCLK/EXTCLK to DGND and drive CLK with
an external clock signal from 100kHz to 20MHz.1For internal clock operation, connect INTCLK/EXTCLK to
4±
47
CLK
DV
and connect CLK to DGND.
DD
Shutdown Input. Driving SHDN high initiates device shutdown. Connect SHDN to DGND for normal
operation.
SHDN
48
CHSHDN CHSHDN Is Not Implemented. Connect CHSHDN to DGND.
5, 7–12
I.C.
Internally Connected. Connect I.C. to AGND.
______________________________________________________________________________________ ±3
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Detailed Description
The MAX1307/MAX1311/MAX1315 contain a 1075ksps 12-
V
DD
bit ADC with track and hold (T/H). Input scaling on the
MAX1307/MAX1311/MAX1315 allows a 0 to +5V, ±5V, or
±10V analog input signal, respectively. Additionally, the
MAX1307 features ±±V fault-tolerant inputs, while the
MAX1311/MAX1315 feature ±1±.5V fault-tolerant inputs.
The MAX1307/MAX1311/MAX1315 include an on-chip
+2.5V reference. These devices also accept an external
+2V to +3V reference.
I
OL
= 1.6mA
1.6V
DEVICE PIN
The conversion results are available in 0.72µs with a
sampling rate of 1075ksps. Internal or external clock
capabilities offer greater flexibility. A high-speed, 20MHz
parallel interface outputs the conversion results.
100pF
I
= 0.8mA
OH
Figure 1. Digital Load Test Circuit
AV
DD
MAX1307
MAX1311
MAX1315
DV
DD
D11
DATA
REGISTER
OUTPUT
DRIVERS
12-BIT
ADC
T/H
A
IN
D0
MSV
WR
*
CS
REF+
COM
REF-
RD
INTERFACE
AND
CONTROL
CONVST
SHDN
5kΩ
5kΩ
INTCLK/EXTCLK
REF
CLK
CHSHDN
REF
MS
EOC
2.500V
EOLC
DGND
AGND
*SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES
Figure 2. Functional Diagram
±4 ______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
25, 38
+5V
+2.7V TO +5.25V
DV
DD
0.1µF
0.1µF
0.1µF
1
15
17
0.1µF
AV
AV
AV
DD
DD
DD
24, 39
48
DGND
GND
CHSHDN
SHDN
CLK
47
46
45
44
43
42
41
40
6
18
19
MSV
BIPOLAR
CONFIGURATION
0.01µF
REF
REF
MS
CONVST
CS
DIGITAL
INTERFACE
AND
MAX1311
MAX1315
CONTROL
WR
0.1µF
20
REF+
REF-
RD
0.1µF
2.2µF
EOLC
EOC
22
0.1µF
2.2µF
0.1µF
37
36
35
34
33
32
31
30
29
28
27
26
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
21
COM
2, 3, 14, 16, 23
GND
AGND
12
11
10
9
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
PARALLEL
DIGITAL
OUTPUT
8
7
5
BIPOLAR
ANALOG
INPUT
4
A
IN
13
INTCLK/EXTCLK
Figure 3. Typical Bipolar Operating Circuit
______________________________________________________________________________________ ±5
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
+5V
0.1µF
25, 38
1
15
17
+2.7V TO +5.25V
DV
DD
AV
AV
AV
DD
DD
DD
0.1µF
0.1µF
0.1µF
24, 39
48
DGND
GND
2.2µF
0.1µF
CHSHDN
SHDN
CLK
6
MSV
REF
47
46
45
44
43
42
41
40
0.01µF
0.01µF
UNIPOLAR
CONFIGURATION
18
19
CONVST
CS
MS
DIGITAL
INTERFACE
AND
MAX1307
REF
CONTROL
WR
0.1µF
RD
20
REF+
REF-
EOLC
EOC
0.1µF
2.2µF
22
0.1µF
37
36
35
34
33
32
31
30
29
28
27
26
2.2µF
0.1µF
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
21
COM
2, 3, 14, 16, 23
GND
AGND
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
12
11
10
9
PARALLEL
DIGITAL
OUTPUT
8
7
5
UNIPOLAR
ANALOG
INPUTS
4
A
IN
13
INTCLK/EXTCLK
Figure 4. Typical Unipolar Operating Circuit
±6 ______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Due to the analog input resistive divider formed by R1
and R2 in Figure 5, any significant analog input source
resistance (R
) results in gain error. Further-
SOURCE
more, R
causes distortion due to nonlinear
SOURCE
analog input currents. Limit R
of 100Ω.
to a maximum
SOURCE
MAX1307
MAX1311
MAX1315
Selecting an Input Buffer
To improve the input signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance (15pF) and
settle quickly. For example, the MAX4431 or the
MAX42±5 can be used for 0 to +5V unipolar devices, or
the MAX4350 can be used for ±5V bipolar inputs.
AV
DD
C
HOLD
OVERVOLTAGE
PROTECTION
CLAMP
2.5pF
*R
SOURCE
R1
CH_
C
SAMPLE
ANALOG
SIGNAL
SOURCE
UNDERVOLTAGE
PROTECTION
CLAMP
R2
Most applications require an input buffer to achieve 12-bit
accuracy. Although slew rate and bandwidth are impor-
tant, the most critical input buffer specification is settling
time. At the beginning of the acquisition, the ADC internal
sampling capacitor array connects to the analog inputs,
causing some disturbance. Ensure the amplifier is capa-
ble of settling to at least 12-bit accuracy during the acqui-
V
BIAS
*MINIMIZE R
TO AVOID GAIN ERROR AND DISTORTION.
SOURCE
PART INPUT RANGE (V) R1 (kΩ) R2 (kΩ)
V
(V)
BIAS
sition time (t
). Use a low-noise, low-distortion,
ACQ
MAX1307
MAX1311
MAX1315
0 TO +5
3.33
6.67
5.00
2.86
2.35
0.90
2.50
2.06
wideband amplifier that settles quickly and is stable with
the ADC’s 15pF input capacitance.
5
10
13.33
Refer to the Maxim website at www.maxim-ic.com for
application notes on how to choose the optimum buffer
amplifier for your ADC application.
R1 | | R2 = 2kΩ
Input Bandwidth
The input-tracking circuitry has a 20MHz small-signal
bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Figure 5. Equivalent Analog Input T/H Circuit
Analog Input
Track and Hold (T/H)
The input T/H circuit is controlled by the CONVST input.
When CONVST is low, the T/H circuit tracks the analog
input. When CONVST is high, the T/H circuit holds the
analog input. The rising edge of CONVST is the analog
Input Range and Protection
The MAX1307 provides a 0 to +5V input voltage range
with fault protection of ±±V. The MAX1311 provides a
±5V input voltage range with fault protection of ±1±.5V.
The MAX1315 provides a ±10V input voltage range with
fault protection of ±1±.5V. Figure 5 shows the equiva-
lent analog input circuit.
input sampling instant. There is an aperture delay (t
)
AD
of 8ns and a 50ps
aperture jitter (t ).
AJ
RMS
To settle the charge on C
to 12-bit accuracy,
SAMPLE
use a minimum acquisition time (t
) of 100ns.
ACQ
Therefore, CONVST must be low for at least 100ns.
Although longer acquisition times allow the analog input
to settle to its final value more accurately, the maximum
acquisition time must be limited to 1ms. Accuracy with
conversion times longer than 1ms cannot be guaran-
teed due to capacitor droop in the input circuitry.
______________________________________________________________________________________ ±7
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Data Throughput
The data throughput (f ) of the MAX1307/MAX1311/
Starting a Conversion
To start a conversion using internal clock mode, pull
TH
MAX1315 is a function of the clock speed (f
). In
CONVST low for the acquisition time (t
). The T/H
ACQ
CLK
internal clock mode, f
= 15MHz (typ). In external
acquires the signal while CONVST is low, and conver-
sion begins on the rising edge of CONVST. The end-of-
conversion (EOC) signal and end-of-last-conversion
signal (EOLC) pulse low whenever a conversion result
is available for reading (Figure ±).
CLK
clock mode, these devices accept an f
between
CLK
100kHz and 20MHz. Figures ± and 7 calculate f
follows:
as
TH
1
f
=
TH
To start a conversion using external clock mode, pull
13
CONVST low for the acquisition time (t
). The T/H
ACQ
t
+ t
+
ACQ
QUIET
f
acquires the signal while CONVST is low. The rising
edge of CONVST is the sampling instant. Apply an
external clock to CLK to start the conversion. To avoid
T/H droop degrading the sampled analog input signals,
the first CLK pulse must occur within 10µs from the
rising edge of CONVST. Additionally, the external clock
frequency must be greater than 100kHz to avoid T/H
droop degrading accuracy. The conversion result is
available for read when EOC or ELOC goes low on the
rising edge of the 13th clock cycle (Figure 7).
CLK
where t
is the period of bus inactivity before the
QUIET
rising edge of CONVST (≥50ns). See the Starting a
Conversion section for more information.
Clock Modes
The MAX1307/MAX1311/MAX1315 perform conversions
using either an internal clock or external clock. There are
13 clock periods per conversion.
In both internal and external clock modes, hold
CONVST high until the conversion result is read. If
CONVST goes low in the middle of a conversion, the
current conversion is aborted and a new conversion is
initiated. Furthermore, there must be a period of bus
Internal Clock
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For inter-
nal clock operation, connect INTCLK/EXTCLK to AV
DD
and connect CLK to DGND. Note that INTCLK/EXTCLK
is referenced to AV , not DV
inactivity (t
) for 50ns or longer before the falling
QUIET
.
DD
DD
edge of CONVST for the specified ADC performance.
External Clock
Reading a Conversion Result
Figures ± and 7 show the interface signals to initiate a
read operation. CS can be low at all times, low during the
RD cycles, or the same as RD.
For external clock operation, connect INTCLK/EXTCLK
to AGND and connect an external clock source to CLK.
Note that INTCLK/EXTCLK is referenced to AV , not
DD
DV . The external clock frequency can be up to
DD
After initiating a conversion by bringing CONVST high,
wait for EOC or EOLC to go low. In internal clock mode,
EOC or EOLC goes low within ꢀ00ns. In external clock
mode, EOC or EOLC goes low on the rising edge of the
13th CLK cycle. To read the conversion result, drive CS
and RD low to latch data to the parallel digital output
bus. Bring RD high to release the digital bus.
20MHz. Linearity is not guaranteed with clock frequen-
cies below 100kHz due to droop in the T/H circuits.
Applications Information
Digital Interface
Conversion results are available through the 12-bit digital
interface (D0–D11). The interface includes the following
control signals: chip select (CS), read (RD), end of con-
version (EOC), end of last conversion (EOLC), conversion
start (CONVST), shutdown (SHDN), internal clock select
(INTCLK/EXTCLK), and external clock input (CLK).
Figures ± and 7 and the Timing Characteristics show the
operation of the interface. D0–D11 go high impedance
when RD = 1 or CS = 1.
±8 ______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
SAMPLE
INSTANT
NEXT SAMPLE
INSTANT
t
ACQ
HOLD
CONVST
TRACK
TRACK
t
CONV
EOC
t
EOC
t
CVEOLCD
EOLC
t
≥ 50ns
QUIET
t
RTC
CS*
t
CTR
RD
t
RDL
AIN
D0–D11
t
ACC
t
REQ
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 6. Reading a Conversion—Internal Clock
The state of the digital outputs D0–D11 is independent
of the state of SHDN. If CS and RD are low, the digital
outputs D0–D11 are active regardless of SHDN. The
digital outputs only go high impedance when CS or RD
is high. When the digital outputs are powered down,
the digital supply current drops to 20nA.
Power-Up Reset
After applying power, allow a 1ms wake-up time to
elapse and then initiate a conversion and discard the
results. After the conversion is complete, accurate con-
versions can be obtained.
Shutdown Modes
During shutdown the internal reference and analog
circuits in the device shutdown and the analog supply
current drops to 0.±µA (typ). Set SHDN high to enter
shutdown mode.
Exiting shutdown (falling edge of SHDN) starts a con-
version in the same way as the rising edge of CONVST.
After coming out of shutdown, initiate a conversion and
discard the results. Allow a 1ms wake-up time to expire
before initiating the first accurate conversion.
EOC and EOLC are high when the MAX1307/MAX1311/
MAX1315 are shut down.
______________________________________________________________________________________ ±0
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
SAMPLE
INSTANT
NEXT SAMPLE
INSTANT
t
ACQ
CONVST
CLK
HOLD
TRACK
t
TRACK
t
CLK
t
t
CLKL
CLKH
CNTC
1
2
3
8
9
10
12
13
14
15
16
1
t
t
EOCD
EOCD
EOC
t
EOC
t
t
EOLCD
CVEOLCD
EOLC
CS*
t
CONV
t
= 50ns
QUIET
t
RTC
t
CTR
RD
t
RDL
D0–D11
AIN
t
ACC
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
t
REQ
Figure 7. Reading a Conversion—External Clock
2ꢂ ______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Reference
Midscale ꢀoltage (MSꢀ)
) sets the midpoint of the ADC
The voltage at MSV (V
MSV
Internal Reference
The internal reference circuits provide for analog input
voltages of 0 to +5V for the unipolar MAX1307, ±5V for
the bipolar MAX1311, or ±10V for the bipolar MAX1315.
Install external capacitors for reference stability, as indi-
cated in Table 1 and shown in Figures 3 and 4.
transfer functions. For the 0 to +5V input range (unipolar
devices), the midpoint of the transfer function is +2.5V.
For the ±5V and ±10V input range devices, the midpoint
of the transfer function is zero.
As shown in Figure 2, there is a unity-gain buffer
between REF
and MSV in the unipolar MAX1307. This
MS
As illustrated in Figure 2, the internal reference voltage
midscale buffer sets the midpoint of the unipolar transfer
functions to either the internal +2.5V reference or an
is 2.5V (V
). This 2.5V is internally buffered to create
REF
the voltages at REF+ and REF-. Table 2 shows the volt-
ages at COM, REF+, and REF-.
externally applied voltage at REF . V
REFMS
follows
MSV
MS
V
within ±3mV.
External Reference
External reference operation is achieved by overriding
the internal reference voltage. Override the internal ref-
erence voltage by driving REF with a +2.0V to +3.0V
external reference. As shown in Figure 2, the REF input
impedance is 5kΩ. For more information about using
external references, see the Transfer Functions section.
The midscale buffer is not active for the bipolar
devices. For these devices, MSV must be connected to
AGND or externally driven. REF
must be bypassed
MS
with a 0.01µF capacitor to AGND.
See the Transfer Functions section for more information
about MSV.
T(ble1±ꢃ1Reference1Syp(ss1C(p(citors
ꢀIPUT1VO TAGE1RAIGE
OCATꢀOI
UIꢀPO AR1ꢄµFa
SꢀPO AR1ꢄµFa
N/A
MSV Bypass Capacitor to AGND
2.2 || 0.1
0.01
REF
Bypass Capacitor to AGND
0.01
MS
REF Bypass Capacitor to AGND
REF+ Bypass Capacitor to AGND
REF+ to REF- Capacitor
0.01
0.01
0.1
0.1
2.2 || 0.1
0.1
2.2 || 0.1
0.1
REF- Bypass Capacitor to AGND
COM Bypass Capacitor to AGND
2.2 || 0.1
2.2 || 0.1
N/A = Not applicable. Connect MSV directly to AGND.
T(ble12ꢃ1Reference1Volt(ges
CA CU ATEB1VA UE1ꢄVa CA CU ATEB1VA UE1ꢄVa CA CU ATEB1VA UE1ꢄVa
1=12ꢃꢂꢂꢂVꢁ 1=12ꢃ5ꢂꢂVꢁ =13ꢃꢂꢂꢂVꢁ
V
REF
V
REF
V
REF1
PARAMETER
EQUATꢀOI
(
(
)
(
)
)
AV =15ꢃꢂV
BB1
AV =15ꢃꢂV
BB1
AV =15ꢃꢂV
BB1
V
V
= 13 / 25 x AV
DD
2.±00
3.±00
1.±00
2.000
2.±00
3.850
1.350
2.500
2.±00
4.100
1.100
3.000
COM
COM
V
V
= V
= V
+ V
/ 2
REF
REF+
REF+
COM
COM
V
V
- V
/ 2
REF-
REF-
REF
V
- V
V
= V
- V
REF- REF+
REF+
REF-
REF
______________________________________________________________________________________ 2±
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
The input range is centered about V
, internally set
Transfer Functions
MSV
to +2.5V. For a custom midscale voltage, drive REF
MS
Unipolar 0 to +5V Devices
Table 3 and Figure 8 show the offset binary transfer
function for the MAX1307 with a 0 to +5V input range.
The full-scale input range (FSR) is two times the voltage
at REF. The internal +2.5V reference gives a +5V FSR,
while an external +2V to +3V reference allows an FSR
of +4V to +±V, respectively. Calculate the LSB size
using:
with an external voltage source and MSV will follow
REF . Noise present on MSV or REF directly cou-
ples into the ADC result. Use a precision, low-drift volt-
age reference with adequate bypassing to prevent
MSV from degrading ADC performance. For maximum
FSR, do not violate the absolute maximum voltage rat-
ings of the analog inputs when choosing MSV.
MS
MS
Determine the input voltage as a function of V
MSV
,
REF
V
, and the output code in decimal using:
2 x V
REF
1 LSB =
12
2
V
CH_
= LSB x CODE + V
- 2.500V
10
MSV
which equals 1.22mV when using a 2.5V reference.
T(ble13ꢃ1ꢂ1to15V1Unipol(r1Code1T(ble
BECꢀMA
ꢀIPUT1VO TAGE
EQUꢀVA EIT
BꢀGꢀTA 1OUTPUT
COBE
SꢀIARY
BꢀGꢀTA
OUTPUT1COBE
ꢄVa
2 x V
REF
V
1=1+2ꢃ5V
1=1+2ꢃ5V
REF
0xFFF
0xFFE
0xFFD
0xFFC
(
)
V
REFML
ꢄCOBE
a
±ꢂ
1111 1111 1111
= 0xFFF
40ꢀ5
40ꢀ4
204ꢀ
2048
2047
1
+4.ꢀꢀꢀ4 ± 0.5 LSB
+4.ꢀꢀ82 ± 0.5 LSB
+2.5018 ± 0.5 LSB
+2.500± ± 0.5 LSB
+2.4ꢀꢀ4 ± 0.5 LSB
+0.0018 ± 0.5 LSB
+0.000± ± 0.5 LSB
0x801
0x800
0x7FF
1111 1111 1110
= 0xFFE
1000 0000 0001
= 0x801
1000 0000 0000
= 0x800
0x0003
0x0002
0x0001
0x0000
2 x V
212
REF
1 LSB =
0111 1111 1111
= 0x7FF
0000 0000 0001
= 0x001
0
1
2
2046 2048 2050
(MSV)
4093 4095
3
INPUT VOLTAGE (LSBs)
0000 0000 0000
= 0x000
0
Figure 8. 0 to +5V Unipolar Transfer Function
22 ______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Bipolar 5V Devices
Table 4 and Figure ꢀ show the two’s complement trans-
fer function for the ±5V input range MAX1311. The FSR is
four times the voltage at REF. The internal +2.5V refer-
ence gives a +10V FSR, while an external +2V to +3V
reference allows an FSR of +8V to +12V respectively.
Calculate the LSB size using:
The input range is centered about V
. Normally, MSV
MSV
= AGND, and the input is symmetrical about zero. For a
custom midscale voltage, drive MSV with an external
voltage source. Noise present on MSV directly couples
into the ADC result. Use a precision, low-drift voltage
reference with adequate bypassing to prevent MSV
from degrading ADC performance. For maximum FSR,
do not violate the absolute maximum voltage ratings of
the analog inputs when choosing MSV.
4 x V
REF
1 LSB =
12
2
Determine the input voltage as a function of V
,
REF
V
MSV
, and the output code in decimal using:
which equals 2.44mV when using a 2.5V reference.
V
CH_
= LSB x CODE + V
10
MSV
T(ble14ꢃ1±5V1Sipol(r1Code1T(ble
BECꢀMA
TWO’s
COMP EMEIT
BꢀGꢀTA 1OUTPUT
COBE
ꢀIPUT1VO TAGE
ꢄVa
EQUꢀVA EIT
BꢀGꢀTA 1OUTPUT
COBE
4 x V
REF
V
1=1+2ꢃ5V
0x7FF
0x7FE
0x7FD
0x7FC
REF
V
(
)
1=1ꢂ
MLV
ꢄCOBE
a
±ꢂ
0111 1111 1111 =
0x7FF
+2047
+204±
+1
+4.ꢀꢀ88 ± 0.5 LSB
+4.ꢀꢀ±3 ± 0.5 LSB
+0.0037 ± 0.5 LSB
+0.0012 ± 0.5 LSB
-0.0012 ± 0.5 LSB
-4.ꢀꢀ±3 ± 0.5 LSB
-4.ꢀꢀ88 ± 0.5 LSB
0x001
0x000
0xFFF
0111 1111 1110 =
0x7FE
0000 0000 0001 =
0x001
0000 0000 0000 =
0x000
0
0x803
0x802
0x801
0x800
4 x V
212
REF
1 LSB =
1111 1111 1111 =
0xFFF
-1
1000 0000 0001 =
0x801
-2048 -2046
-1
(MSV)
INPUT VOLTAGE (V
0
+1
+2045 +2047
IN LSBs)
MSV
-2047
-2048
- V
CH_
1000 0000 0000 =
0x800
Figure 9. 5V Bipolar Transfer Function
______________________________________________________________________________________ 23
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Bipolar 10V Devices
Table 5 and Figure 10 show the two’s complement trans-
fer function for the ±10V input range MAX1315. The FSR
is eight times the voltage at REF. The internal +2.5V refer-
ence gives a +20V FSR, while an external +2V to +3V ref-
erence allows an FSR of +1±V to +24V, respectively.
Calculate the LSB size using:
The input range is centered about V
. Normally,
MSV
MSV = AGND, and the input is symmetrical about zero.
For a custom midscale voltage, drive MSV with an
external voltage source. Noise present on MSV directly
couples into the ADC result. Use a precision, low-drift
voltage reference with adequate bypassing to prevent
MSV from degrading ADC performance. For maximum
FSR, do not violate the absolute maximum voltage rat-
ings of the analog inputs when choosing MSV.
8 x V
REF
12
1 LSB =
2
Determine the input voltage as a function of V
,
REF
V
MSV
, and the output code in decimal using:
which equals 4.88mV with a +2.5V internal reference.
V
CH_
= LSB x CODE + V
10 MSV
T(ble15ꢃ1±±ꢂV1Sipol(r1Code1T(ble
BECꢀMA
TWO’s
COMP EMEIT
BꢀGꢀTA 1OUTPUT
COBE
ꢀIPUT1VO TAGE
ꢄVa
EQUꢀVA EIT
BꢀGꢀTA 1OUTPUT
COBE
8 x V
REF
0x7FF
0x7FE
0x7FD
0x7FC
V
1=1+2ꢃ5V
REF
V
(
)
1=1ꢂ
MLV
ꢄCOBE
a
±ꢂ
0111 1111 1111 =
0x7FF
+2047
+204±
+1
+ꢀ.ꢀꢀ7± ± 0.5 LSB
+ꢀ.ꢀꢀ27 ± 0.5 LSB
+0.0073 ± 0.5 LSB
0.0024 ± 0.5 LSB
-0.0024 ± 0.5 LSB
-ꢀ.ꢀꢀ27 ± 0.5 LSB
-ꢀ.ꢀꢀ7± ± 0.5 LSB
0x001
0x000
0xFFF
0111 1111 1110 =
0x7FE
0000 0000 0001 =
0x001
0000 0000 0000 =
0x000
0x803
0x802
0x801
0x800
0
8 x V
212
REF
1 LSB =
1111 1111 1111 =
0xFFF
-1
-2048 -2046
-1
(MSV)
INPUT VOLTAGE (V
0
+1
+2045 +2047
IN LSBs)
MSV
1000 0000 0001 =
0x801
-2047
-2048
- V
CH_
1000 0000 0000 =
0x800
Figure 10. 10V Bipolar Transfer Function
24 ______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Layout, Grounding, and Bypassing
For best performance use PC boards. Board layout must
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines paral-
lel to one another (especially clock lines), and do not run
digital lines underneath the ADC package.
DIGITAL
GROUND
POINT
ANALOG SUPPLY
+5V RETURN
DIGITAL SUPPLY
RETURN +3V TO +5V
Figure 11 shows the recommended system ground con-
nections. Establish an analog ground point at AGND and
a digital ground point at DGND. Connect all analog
grounds to the analog ground point. Connect all digital
grounds to the digital ground point. For lowest-noise
operation, make the power-supply ground returns as low
impedance and as short as possible. Connect the analog
ground point to the digital ground point at one location.
ANALOG
GROUND
POINT
OPTIONAL
FERRITE
BEAD
AV
DGND
DD
AGND
DV
DD
DGND
DV
DD
High-frequency noise in the power supplies degrades
the ADC’s performance. Bypass the analog power
plane to the analog ground plane with a 2.2µF capaci-
DIGITAL
CIRCUITRY
DATA
MAX1307
MAX1311
MAX1315
tor within one inch of the device. Bypass each AV
to
DD
AGND pair of pins with a 0.1µF capacitor as close to
the device as possible. AV to AGND pairs are pin 1
DD
to pin 2, pin 14 to pin 15, and pin 1± to pin 17.
Likewise, bypass the digital power plane to the digital
ground plane with a 2.2µF capacitor within one inch of
Figure 11. Power-Supply Grounding and Bypassing
the device. Bypass each DV
to DGND pair of pins
DD
with a 0.1µF capacitor as close to the device as possi-
ble. DV to DGND pairs are pin 24 to pin 25, and pin
38 to pin 3ꢀ. If a supply is very noisy use a ferrite bead
as a lowpass filter as shown in Figure 11.
DD
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Typically, the point at which
offset error is specified is either at or near the zero-
scale point of the transfer function or at or near the mid-
scale point of the transfer function.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For these devices, this
straight line is drawn between the end points of the
transfer function, once offset and gain errors have
been nullified.
For the unipolar devices (MAX1307), the ideal zero-scale
transition from 0x000 to 0x001 occurs at 1 LSB above
AGND (Figure 8, Table 3). Unipolar offset error is the
amount of deviation between the measured zero-scale
transition point and the ideal zero-scale transition point.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. For these devices, the DNL of
each digital output code is measured and the worst-
case value is reported in the Electrical Characteristics
table. A DNL error specification of less than ±1 LSB
guarantees no missing codes and a monotonic
transfer function.
For the bipolar devices (MAX1311/MAX1315), the ideal
midscale transition from 0xFFF to 0x000 occurs at MSV
(Figures ꢀ and 10, Tables 4 and 5). The bipolar offset
error is the amount of deviation between the measured
midscale transition point and the ideal midscale transi-
tion point.
______________________________________________________________________________________ 25
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. For the MAX1307/
MAX1311/MAX1315, the gain error is the difference of
the measured full-scale and zero-scale transition points
minus the difference of the ideal full-scale and zero-
scale transition points.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal
to the RMS noise plus distortion. RMS noise plus distor-
tion includes all spectral components to the Nyquist fre-
quency excluding the fundamental and the DC offset.
⎛
⎜
⎞
⎟
Signal
2
RMS
SINAD(dB) = 20 x log
⎜
⎝
2 ⎟
⎠
For the unipolar devices (MAX1307), the full-scale tran-
sition point is from 0xFFE to 0xFFF and the zero-scale
transition point is from 0x000 to 0x001.
Noise
+ Distortion
RMS
RMS
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed as:
For the bipolar devices (MAX1311/MAX1315), the full-
scale transition point is from 0x7FE to 0x7FF and the
zero-scale transition point is from 0x800 to 0x801.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
−
SINAD 1.7±
ENOB =
±.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmon-
ics to the fundamental itself. This is expressed as:
SNR
= ±.02 × N + 1.7±
dB dB
dB[max]
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2
2
2
2
2
V
+ V + V + V + V
3 5 ±
4
2
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter.
=
THD 20 x log
V
1
For these devices, SNR is computed by taking the ratio
of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
where V is the fundamental amplitude, and V through
±
order harmonics.
1
2
V
are the amplitudes of the 2nd- through ±th-
26 ______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the fundamen-
tal (maximum signal component) to the RMS value of the
next-largest spurious component, excluding DC offset.
SFDR is specified in decibels relative to the carrier (dBc).
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so that the signal’s slew rate does not limit the
ADC’s performance. The input frequency is then swept
up to the point where the amplitude of the digitized
conversion result has decreased by -3dB.
Aperture Delay
Aperture delay (t ) is the time delay from the CONVST
AD
Full-Power Bandwidth
A large, -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
rising edge to the instant when an actual sample is taken.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
aperture delay.
Jitter is a concern when considering an ADC’s dynamic
performance, e.g., SNR. To reconstruct an analog input
from the ADC digital outputs, it is critical to know the
time at which each sample was taken. Typical applica-
tions use an accurate sampling clock signal that has
low jitter from sampling edge to sampling edge. For a
system with a perfect sampling clock signal, with no
clock jitter, the SNR performance of an ADC is limited
by the ADC’s internal aperture jitter as follows:
DC Power-Supply Rejection (PSRR)
DC PSRR is defined as the change in the positive full-
scale transfer-function point caused by a ±5% variation
in the analog power-supply voltage (AV ).
DD
Chip Information
TRANSISTOR COUNT: 50,000
PROCESS: 0.±µm BiCMOS
⎛
⎞
1
=
SNR 20 x log
⎜
⎟
2 x π x f x t
⎝
⎠
IN
AJ
where f represents the analog input frequency and
IN
t
AJ
is the time of the aperture jitter.
______________________________________________________________________________________ 27
1075ksps, 12-Bit, Parallel-Output ADCs with
10ꢀ, 5ꢀ, and 0 to +5ꢀ Analog Input Ranges
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to wwwꢃꢅ(miꢅ-icꢃcoꢅꢆp(ck(ges.)
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
1
21-0054
E
2
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
2
21-0054
E
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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