MAX1338ETN-T [MAXIM]
ADC, Proprietary Method, 14-Bit, 1 Func, 4 Channel, Parallel, Word Access, BICMOS, 8 X 8 MM, 0.80 MM HEIGHT, MO-220, QFN-56;
| 型号： | MAX1338ETN-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Proprietary Method, 14-Bit, 1 Func, 4 Channel, Parallel, Word Access, BICMOS, 8 X 8 MM, 0.80 MM HEIGHT, MO-220, QFN-56 |
| 文件： | 总24页 (文件大小：704K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3151; Rev 1; 7/04
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
General Description
Features
The MAX1338 14-bit, analog-to-digital converter (ADC)
offers four simultaneously sampled, fully differential input
channels, with independent track-and-hold (T/H) circuitry
for each channel. The input channels are individually
software programmable for input ranges of ±1ꢀ0, ±ꢁ0,
±±.ꢁ0, and ±1.±ꢁ0. The input channels feature fault tol-
erance to ±1ꢂ0. The internal T/H circuits have a 1ꢃns
aperture delay and 1ꢀꢀps aperture-delay matching.
♦ 150ksps Sample Rate per Channel
♦ All Four Input Channels Simultaneously Sampled
16ns Aperture Delay
100ps Aperture-Delay Matching
♦ Channel-Independent Software-Selectable Input
Range: ±10ꢀV ±5ꢀV ±,ꢁ5ꢀV ±1ꢁ,5ꢀ
♦ ±1ꢂꢀ Fault-ꢃolerant Inputs
A 14-bit parallel bus provides the conversion result with
a maximum per-channel output rate of 1ꢁꢀksps
(ꢃꢀꢀksps for all four channels). The MAX1338 has an
on-board oscillator and ±.ꢁ0 internal reference. An
external clock and/or reference can also be used.
♦ Dynamic Performance at 10kHz Input
SNR: ꢂꢂdB
SINAD: ꢂ6dB
SFDR: 98dBc
The MAX1338 operates from a +ꢁ0 supply for analog
inputs and digital core. The device operates from a +±.ꢂ0
to +ꢁ.±ꢁ0 supply for the digital I/O lines. The MAX1338
features two power-saving modes: standby mode and
shutdown mode. Standby mode allows rapid wake-up
and reduces quiescent current to 4mA (typ), and shut-
down mode reduces sleep current to less than 1ꢀµA (typ).
ꢃHD: -83dBc
♦ DC Performance
INL: ±, LSB
DNL: ±1 LSB
Offset Error: ±± LSB
Gain Error: ±0ꢁ1ꢄ FSR
The MAX1338 is available in an 8mm x 8mm x ꢀ.8mm,
ꢁꢃ-pin, thin QFN package. The device operates over
the extended -4ꢀ°C to +8ꢁ°C temperature range.
♦ 1±-Bit Parallel Interface
♦ Internal Clock and Reference ꢀoltage
♦ +5ꢀ Analog and Digital Supplies
♦ +,ꢁꢂꢀ to +5ꢁ,5ꢀ Digital I/O Supply
♦ 56-Pin ꢃhin QFN Package (8mm x 8mm x 0ꢁ8mm)
Applications
Multiple-Channel Data Recorders
0ibration Analysis
Motor Control: 3-Phase 0oltage, Current, and
Power Measurement
Ordering Information
PARꢃ
ꢃEMP RANGE
PIN-PACKAGE
Optical Communication Equipment
MAX1338ETN
-4ꢀ°C to +8ꢁ°C
ꢁꢃ Thin QFN-EP*
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
ABSOLUꢃE MAXIMUM RAꢃINGS
A0
D0
DR0
A0
to AGND .........................................................-ꢀ.30 to +ꢃ0
to DGND.........................................................-ꢀ.30 to +ꢃ0
to DRGND....................................................-ꢀ.30 to +ꢃ0
CS, RD, WR, CON0ST, to DRGND........-ꢀ.30 to (DR0
SHDN, STANDBY, CLK, EOC,
+ ꢀ.30)
+ ꢀ.30)
DD
DD
DD
DD
EOLC to DRGND................................-ꢀ.30 to (DR0
DD
to D0 .......................................................-ꢀ.30 to +ꢀ.30
Maximum Current into Any Pin .........................................±ꢁꢀmA
DD
DD
DGND to DRGND..................................................-ꢀ.30 to +ꢀ.30
AGND to DGND.....................................................-ꢀ.30 to +ꢀ.30
AGND to DRGND ..................................................-ꢀ.30 to +ꢀ.30
AINꢀ+, AINꢀ-, AIN1+, AIN1-, AIN±+, AIN±-, AIN3+,
Continuous Power Dissipation (T = +ꢂꢀ°C)
A
ꢁꢃ-Pin Thin QFN (derate 31.3mW /°C above +ꢂꢀ°C)....±ꢁꢀꢀmW
Operating Temperature Range ...........................-4ꢀ°C to +8ꢁ°C
Storage Temperature Range.............................-ꢃꢁ°C to +1ꢁꢀ°C
Maximum Junction Temperature .....................................+1ꢁꢀ°C
Lead Temperature (soldering, 1ꢀs) .................................+3ꢀꢀ°C
AIN3- to AGND.....................................................-1ꢂ0 to +1ꢂ0
Dꢀ–D13 to DRGND................................-ꢀ.30 to (DR0
+ ꢀ.30)
DD
REFADC, REFP1, REFP±, REFN1, REFN±, COM1, COM± to
Junction to Ambient Thermal Resistance θ ..................3±°C/W
JA
AGND....................................................-ꢀ.30 to (A0
INTCLK/EXTCLK to AGND.......................-ꢀ.30 to (A0
+ ꢀ.30)
+ ꢀ.30)
Junction to Case Thermal Resistance θ .........................±°C/W
DD
DD
JC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECꢃRICAL CHARACꢃERISꢃICS
(A0
= D0
= +ꢁ.ꢀ0, DR0
= +3.ꢀ0, AGND = DGND = DRGND = ꢀ, INTCLK/EXTCLK = AGND, f
= ꢁMHz, input range =
DD
DD
DD
CLK
±1ꢀ0, REFP± = REFP1, REFN± = REFN1, COM1 = COM±, 1.ꢀnF from REFADC to AGND, 1.ꢀµF and ꢀ.1µF from COM1 to AGND,
ꢀ.1µF from REFP1 to AGND, ꢀ.1µF from REFN1 to AGND, 1.ꢀµF from REFP1 to REFN1. Typical values are at T = +±ꢁ°C. T = T
MIN
A
A
to T
, unless otherwise noted.)
MAX
PARAMEꢃER
SYMBOL
CONDIꢃIONS
MIN
ꢃYP
MAX
UNIꢃS
SꢃAꢃIC PERFORMANCE
Resolution
N
14
Bits
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
(Note 1)
1
ꢀ.±ꢁ
4
3
1
No missing codes (Note 1)
(Note 1)
1ꢃ
Offset-Error Temperature
Coefficient
ꢁ
ppm/°C
Offset-Error Matching
Gain Error
1ꢀ
ꢀ.1
±ꢀ
LSB
%FSR
LSB
Offset nulled (Notes 1, ±)
Offset nulled
ꢀ.3ꢁ
Channel Gain-Error Matching
Gain-Error Temperature
Coefficient
Offset nulled
1ꢀ
ppm/°C
DYNAMIC PERFORMANCE (at f = 10kHzV A = -0ꢁ,dBFS)
IN
IN
Sampling Rate Per Channel
Signal-to-Noise Ratio
Simultaneous on all channels
(Note 1)
1ꢁꢀ
-8ꢀ
ksps
dB
SNR
SINAD
THD
ꢂꢁ
ꢂ4
ꢂꢂ
ꢂꢃ
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Isolation
ANALOG INPUꢃS (AIN_)
(Note 1)
dB
(Note 1)
-83
dBc
dBc
dB
SFDR
Range ꢀ (Note 1)
(Note 1)
8ꢁ
8ꢀ
Range set bits = (ꢀ,ꢀ)
Range set bits = (ꢀ,1)
Range set bits = (1,ꢀ)
Range set bits = (1,1)
-1ꢀ
-ꢁ
+1ꢀ
+ꢁ
Input Differential 0oltage Range
0
-±.ꢁ
-1.±ꢁ
+±.ꢁ
+1.±ꢁ
,
_______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
ELECꢃRICAL CHARACꢃERISꢃICS (continued)
(A0
= D0
= +ꢁ.ꢀ0, DR0
= +3.ꢀ0, AGND = DGND = DRGND = ꢀ, INTCLK/EXTCLK = AGND, f
= ꢁMHz, input range =
DD
DD
DD
CLK
±1ꢀ0, REFP± = REFP1, REFN± = REFN1, COM1 = COM±, 1.ꢀnF from REFADC to AGND, 1.ꢀµF and ꢀ.1µF from COM1 to AGND,
ꢀ.1µF from REFP1 to AGND, ꢀ.1µF from REFN1 to AGND, 1.ꢀµF from REFP1 to REFN1. Typical values are at T = +±ꢁ°C. T = T
MIN
A
A
to T
, unless otherwise noted.)
MAX
PARAMEꢃER
SYMBOL
CONDIꢃIONS
Range set bits = (ꢀ,ꢀ)
MIN
-ꢁ
ꢃYP
MAX
+ꢁ
UNIꢃS
Range set bits = (ꢀ,1)
Range set bits = (1,ꢀ)
Range set bits = (1,1)
All settings
-±.ꢁ
+±.ꢁ
Input Common-Mode Range
0
-1.±ꢁ
-ꢀ.ꢃ±ꢁ
+1.±ꢁ
+ꢀ.ꢃ±ꢁ
Input Resistance
ꢃ.±ꢁ
1ꢁ
1
kΩ
pF
Input Capacitance
Small-Signal Bandwidth
Full-Power Bandwidth
INꢃERNAL REFERENCE (REFADC)
Output 0oltage
SSBW
FPBW
(Note 1)
(Note 1)
MHz
kHz
ꢂꢁ
±.4ꢂꢁ
±.ꢁ
±.ꢁ
±.ꢁ±ꢁ
0
0
REFP–
REFN
Differential Reference 0oltage
Output-0oltage Temperature
Coefficient
ꢁꢀ
ꢁ
ppm/°C
Load Regulation
0/mA
EXꢃERNAL REFERENCE
REFADC 0oltage Input Range
REFADC Input Current
REFADC Input Resistance
REFADC Input Capacitance
ꢃRACK/HOLD (ꢃ/H)
Aperture Delay
±.ꢀ
±.ꢁ
3.ꢀ
0
(Note 3)
-±ꢁꢀ
+±ꢁꢀ
µA
kΩ
pF
R
t
ꢁ
REF
1ꢁ
(Note 1)
(Note 1)
1ꢃ
1ꢀꢀ
ꢁꢀ
ns
ps
AD
Aperture-Delay Matching
Aperture Jitter
t
ps
RMS
AJ
CLOCK-SELECꢃ INPUꢃ (INꢃCLK/EXTCLK)
ꢀ.ꢂ x
Input-0oltage High
Input-0oltage Low
0
0
0
IH
A0
DD
ꢀ.3 x
0
IL
A0
DD
DIGIꢃAL INꢃERFACE AND CONꢃROL INPUꢃS (CSV RDV WRV CONꢀSꢃV SHDNV CLKV SꢃANDBY)
ꢀ.ꢂ x
DR0
Input-0oltage High
Input-0oltage Low
0
0
0
IH
DD
ꢀ.3 x
DR0
0
IL
DD
Input Hysteresis
ꢁꢀ
1ꢁ
m0
pF
Input Capacitance
C
IN
_______________________________________________________________________________________
3
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
ELECꢃRICAL CHARACꢃERISꢃICS (continued)
(A0
= D0
= +ꢁ.ꢀ0, DR0
= +3.ꢀ0, AGND = DGND = DRGND = ꢀ, INTCLK/EXTCLK = AGND, f
= ꢁMHz, input range =
DD
DD
DD
CLK
±1ꢀ0, REFP± = REFP1, REFN± = REFN1, COM1 = COM±, 1.ꢀnF from REFADC to AGND, 1.ꢀµF and ꢀ.1µF from COM1 to AGND,
ꢀ.1µF from REFP1 to AGND, ꢀ.1µF from REFN1 to AGND, 1.ꢀµF from REFP1 to REFN1. Typical values are at T = +±ꢁ°C. T = T
MIN
A
A
to T
, unless otherwise noted.)
MAX
PARAMEꢃER
SYMBOL
CONDIꢃIONS
MIN
ꢃYP
MAX
UNIꢃS
Input Current
I
0
= ꢀ or DR0
±1
µA
IN
IN
DD
DIGIꢃAL INꢃERFACE AND CONꢃROL OUꢃPUꢃS (EOCV EOLC)
DR0
- ꢀ.ꢃ
DD
Output-0oltage High
0
Sourcing ꢀ.8mA
Sinking 1.ꢃmA
0
0
OH
Output-0oltage Low
0
ꢀ.4
OL
PARALLEL DIGIꢃAL I/O (D0–Dꢂ)
DR0
-
DD
Output-0oltage High
0
Sourcing ꢀ.8mA
Sinking 1.ꢃmA
0
OH
ꢀ.ꢃ
Output-0oltage Low
Leakage Current
0
ꢀ.4
1
0
OL
µA
pF
Tristate Output Capacitance
RD = 1 or CS = 1
1ꢁ
ꢀ.ꢂ x
Input-0oltage High
Input-0oltage Low
0
0
0
IH
DR0
DD
ꢀ.3 x
0
IL
DR0
DD
Input Hysteresis
Input Capacitance
Input Current
ꢁꢀ
1ꢁ
m0
pF
µA
C
IN
I
0
= ꢀ or DR0
±1
IN
IN
DD
PARALLEL DIGIꢃAL OUꢃPUꢃS (D8–D13)
DR0
-
DD
Output-0oltage High
0
Sourcing ꢀ.8mA
Sinking 1.ꢃmA
0
OH
ꢀ.ꢃ
Output-0oltage Low
0
ꢀ.4
1
0
OL
Leakage Current
µA
pF
Tristate Output Capacitance
POWER SUPPLIES
1ꢁ
Analog Supply 0oltage
Digital Supply 0oltage
Parallel Digital I/O Supply 0oltage
A0
D0
4.ꢂꢁ
4.ꢂꢁ
±.ꢂꢀ
ꢁ
ꢁ
ꢁ.±ꢁ
ꢁ.±ꢁ
ꢁ.±ꢁ
ꢃꢀ
0
0
0
DD
DD
DR0
DD
41
Analog Supply Current
Digital Supply Current
AI
DI
SHDN = 1
ꢀ.ꢀꢀꢁ
4.±
ꢀ.1
ꢁ
mA
mA
DD
STANDBY = 1, SHDN = ꢀ
3
SHDN = 1
ꢀ.ꢀꢀ1
ꢀ.ꢀꢀ1
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
3
DD
STANDBY = 1, SHDN = ꢀ
SHDN = 1
ꢀ
ꢀ
ꢀ.ꢀꢁ
Digital Driver Supply Current
DRI
mA
dB
DD
STANDBY = 1, SHDN = ꢀ
4.ꢂꢁ0 to ꢁ.±ꢁ0 (Note 1)
ꢀ.ꢀꢁ
Analog Power-Supply Rejection
ꢂꢁ
±
_______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
ELECꢃRICAL CHARACꢃERISꢃICS (continued)
(A0
= D0
= +ꢁ.ꢀ0, DR0
= +3.ꢀ0, AGND = DGND = DRGND = ꢀ, INTCLK/EXTCLK = AGND, f
= ꢁMHz, input range =
DD
DD
DD
CLK
±1ꢀ0, REFP± = REFP1, REFN± = REFN1, COM1 = COM±, 1.ꢀnF from REFADC to AGND, 1.ꢀµF and ꢀ.1µF from COM1 to AGND,
ꢀ.1µF from REFP1 to AGND, ꢀ.1µF from REFN1 to AGND, 1.ꢀµF from REFP1 to REFN1. Typical values are at T = +±ꢁ°C. T = T
MIN
A
A
to T
, unless otherwise noted.)
MAX
PARAMEꢃER
SYMBOL
CONDIꢃIONS
MIN
ꢃYP
MAX
UNIꢃS
ꢃIMING CHARACꢃERISꢃICS (Figures 4, ꢁ, and ꢃ)
Internal clock
External clock
Internal clock
External clock
±.9
3.±
1ꢃ
ꢃꢀꢀ
3
3.ꢁ
µs
Time to First Conversion Result
t
EOC1
CLK
Cycles
ns
Time to Subsequent Conversions
CON0ST Pulse-Width Low
t
NEXT
CLK
Cycles
Internal clock
External clock
ꢀ.±
ꢀ.1
3ꢀ
3ꢀ
3ꢀ
3ꢀ
ꢀ
t
µs
CON0ST
CS Pulse Width
t
ns
ns
ns
ns
ns
ns
ns
ns
CS
RD Pulse-Width Low
RD Pulse-Width High
WR Pulse-Width Low
CS to WR Setup Time
WR to CS Hold Time
CS to RD Setup Time
RD to CS Hold Time
t
RDL
RDH
WRL
CTW
WTC
t
t
t
t
ꢀ
t
ꢀ
CTR
RTC
t
ꢀ
Data Access Time
(RD Low to 0alid Data)
t
Figure 1
Figure 1
3ꢀ
3ꢀ
ns
ns
ns
ns
ACC
Bus Relinquish Time
(RD High to D_ High-Z)
t
ꢁ
REQ
CLK Rise to End-of-Conversion
(EOC) Rise/Fall Delay
t
±ꢀ
±ꢀ
EOCD
CLK Rise to End-of-Last-
Conversion (EOLC) Fall Delay
t
EOLCD
CON0ST Rise to EOLC Fall Delay
EOC Pulse-Width Low
t
±ꢀ
ns
ns
C0EOLCD
Internal clock
External clock
18ꢀ
±ꢀꢀ
t
EOC
CLK
Cycle
1
Wake-Up Time From Standby
Wake-Up Time From Shutdown
ꢂ
ꢁ
µs
ns
All bypass capacitors discharged
_______________________________________________________________________________________
5
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
ELECꢃRICAL CHARACꢃERISꢃICS (continued)
(A0
= D0
= +ꢁ.ꢀ0, DR0
= +3.ꢀ0, AGND = DGND = DRGND = ꢀ, INTCLK/EXTCLK = AGND, f
= ꢁMHz, input range =
DD
DD
DD
CLK
±1ꢀ0, REFP± = REFP1, REFN± = REFN1, COM1 = COM±, 1.ꢀnF from REFADC to AGND, 1.ꢀµF and ꢀ.1µF from COM1 to AGND,
ꢀ.1µF from REFP1 to AGND, ꢀ.1µF from REFN1 to AGND, 1.ꢀµF from REFP1 to REFN1. Typical values are at T = +±ꢁ°C. T = T
MIN
A
A
to T
, unless otherwise noted.)
MAX
PARAMEꢃER
SYMBOL
CONDIꢃIONS
MIN
ꢀ
ꢃYP
MAX
UNIꢃS
EOC Fall to RD Fall Setup Time
EOLC Fall to RD Fall Setup Time
Input Data Setup Time
Input Data Hold Time
t
ns
ns
EOCRD
t
ꢀ
EOLCRD
t
t
1ꢀ
1ꢀ
1ꢃꢃ
ꢃꢀ
ꢃꢀ
1
ns
DTW
WTD
ns
External CLK Period
t
±ꢀꢀ
ns
CLK
External CLK High Period
External CLK Low Period
External Clock Frequency
Internal Clock Frequency
CON0ST High to CLK Edge
Quiet Time
t
Logic sensitive to rising edges
Logic sensitive to rising edges
(Note 4)
ns
CLKH
t
ns
CLKL
f
ꢃ
MHz
MHz
ns
CLK
f
ꢁ.ꢀ
3ꢀ
ꢃꢀꢀ
ꢁ.±ꢁ
ꢁ.ꢁ
INT
t
CNTC
t
ns
QUIET
Note 1: See definition for this parameter in the Definitions section.
Note ,: Differential reference voltage (REFP–REFN) error nulled.
Note 3: This is the load the MAX1338 presents to an external reference at REFADC.
Note ±: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CON0ST to
the falling edge of EOLC to a maximum of ꢀ.±ꢁms.
1.6mA
1.6V
TO OUTPUT PIN
50pF
0.8mA
Figure 1. Load Circuit for Data Access Time and Bus-
Relinquish Time
6
_______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Typical Operating Characteristics
(A0
= D0
= +ꢁ.ꢀ0, DR0
= +3.ꢀ0, AGND = DGND = DRGND = ꢀ, INTCLK/EXTCLK = AGND, f
= ꢁMHz, input range =
DD
DD
DD
CLK
±1ꢀ0, REFP± = REFP1, REFN± = REFN1, COM1 = COM±, 1.ꢀnF from REFADC to AGND, 1.ꢀµF and ꢀ.1µF from COM1 to AGND,
ꢀ.1µF from REFP1 to AGND, ꢀ.1µF from REFN1 to AGND, 1.ꢀµF from REFP1 to REFN1.)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
OFFSET ERROR
vs. SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.8
0.6
0.4
0.2
0
0
-1
-2
-3
-4
-5
-6
0.6
0.4
0.2
0
CHANNEL 0
CHANNEL 2
CHANNEL 1
-0.2
-0.4
-0.6
-0.8
-0.2
-0.4
-0.6
CHANNEL 3
4.85
-8192
-4096
0
4096
8192
4.75
4.95
5.05
5.15
5.25
-8192
-4096
0
4096
8192
OUTPUT CODE (DECIMAL)
AV (V)
DD
OUTPUT CODE (DECIMAL)
GAIN ERROR
vs. SUPPLY VOLTAGE
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
-0.13
-0.14
-0.15
-0.16
-0.17
-0.18
-0.19
-0.20
-0.21
15
10
5
0.15
0.10
0.05
0
CH1
CH2
CH3
0
-5
-0.05
-0.10
-0.15
-10
-15
CH0
REFERENCE ERROR NULLED
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT HISTOGRAM
(DC INPUT)
ANALOG INPUT BANDWIDTH
6000
0.1
OFFSET NORMALIZED
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
5000
4000
3000
2000
1000
0
4584.25
1802.75
1646.25
97.25
-2
61
-1
0
1
2
0
50
100
(kHz)
150
200
DIGITAL OUTPUT CODE
f
IN
_______________________________________________________________________________________
ꢂ
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Typical Operating Characteristics (continued)
(A0
= D0
= +ꢁ.ꢀ0, DR0
= +3.ꢀ0, AGND = DGND = DRGND = ꢀ, INTCLK/EXTCLK = AGND, f
= ꢁMHz, input range =
DD
DD
DD
CLK
±1ꢀ0, REFP± = REFP1, REFN± = REFN1, COM1 = COM±, 1.ꢀnF from REFADC to AGND, 1.ꢀµF and ꢀ.1µF from COM1 to AGND,
ꢀ.1µF from REFP1 to AGND, ꢀ.1µF from REFN1 to AGND, 1.ꢀµF from REFP1 to REFN1.)
SIGNAL-TO-NOISE RATIO
vs. CLOCK FREQUENCY
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK FREQUENCY
FFT AT f
= 150ksps, f = 10kHz
IN
SAMPLE
80
79
78
77
76
75
74
73
72
71
70
80
79
78
77
76
75
74
73
72
71
70
0
-25
-50
-75
-100
-125
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
3.0
3.0
0
15
30
45
60
75
f
(MHz)
f
(MHz)
CLK
CLK
FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION
vs. CLOCK FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. REFERENCE VOLTAGE
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
-90
-92
80
79
78
77
76
75
74
73
72
71
70
110
105
100
95
-94
-96
-98
-100
-102
-104
-106
-108
-110
90
85
80
1
2
3
4
5
6
7
8
9
10
2.0
2.2
2.4
2.6
(V)
2.8
1
2
3
4
5
6
7
8
9
10
f
(MHz)
V
REFADC
CLK
f
(MHz)
CLK
SIGNAL-TO-NOISE PLUS DISTORTION
vs. REFERENCE VOLTAGE
TOTAL HARMONIC DISTORTION
vs. REFERENCE VOLTAGE
SPURIOUS-FREE DYNAMIC RANGE
vs. REFERENCE VOLTAGE
80
79
78
77
76
75
74
73
72
71
70
-85
-87
110
105
100
95
-89
-91
-93
-95
-97
90
-99
-101
-103
-105
85
80
2.0
2.2
2.4
2.6
(V)
2.8
3.0
2.0
2.2
2.4
2.6
(V)
2.8
3.0
2.0
2.2
2.4
2.6
(V)
2.8
V
V
V
REFADC
REFADC
REFADC
8
_______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Typical Operating Characteristics (continued)
(A0
= D0
= +ꢁ.ꢀ0, DR0
= +3.ꢀ0, AGND = DGND = DRGND = ꢀ, INTCLK/EXTCLK = AGND, f
= ꢁMHz, input range =
DD
DD
DD
CLK
±1ꢀ0, REFP± = REFP1, REFN± = REFN1, COM1 = COM±, 1.ꢀnF from REFADC to AGND, 1.ꢀµF and ꢀ.1µF from COM1 to AGND,
ꢀ.1µF from REFP1 to AGND, ꢀ.1µF from REFN1 to AGND, 1.ꢀµF from REFP1 to REFN1.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DRIVER SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
44.0
43.8
43.6
43.4
43.2
43.0
42.8
42.6
42.4
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
46
45
44
43
42
41
40
EXCLUDES DRIVER CURRENT
EXCLUDES DRIVER CURRENT
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
2.75
3.25
3.75
4.25
4.75
5.25
AV (V)
DD
TEMPERATURE (°C)
DRV (V)
DD
DRIVER SUPPLY CURRENT
vs. TEMPERATURE
REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
0.98
0.97
0.96
0.95
0.94
0.93
0.92
0.91
0.90
2.4987
DRV = 3V
DD
2.4986
2.4985
2.4984
2.4983
2.4982
2.4981
2.4980
2.4979
2.4978
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
AV (V)
DD
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
REFERENCE VOLTAGE
vs. TEMPERATURE
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
70
65
60
55
50
45
40
SHDN = AV
DD
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
AV (V)
DD
TEMPERATURE (°C)
_______________________________________________________________________________________
9
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Typical Operating Characteristics (continued)
(A0
= D0
= +ꢁ.ꢀ0, DR0
= +3.ꢀ0, AGND = DGND = DRGND = ꢀ, INTCLK/EXTCLK = AGND, f
= ꢁMHz, input range =
DD
DD
DD
CLK
±1ꢀ0, REFP± = REFP1, REFN± = REFN1, COM1 = COM±, 1.ꢀnF from REFADC to AGND, 1.ꢀµF and ꢀ.1µF from COM1 to AGND,
ꢀ.1µF from REFP1 to AGND, ꢀ.1µF from REFN1 to AGND, 1.ꢀµF from REFP1 to REFN1.)
SHUTDOWN CURRENT
vs. TEMPERATURE
STANDBY CURRENT
vs. SUPPLY VOLTAGE
70
65
60
55
50
45
40
4.30
4.25
4.20
4.15
4.10
4.05
4.00
SHDN = AV
DD
STANDBY = AV
DD
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
AV (V)
DD
STANDBY CURRENT
vs. TEMPERATURE
CONVERSION TIME
vs. SUPPLY VOLTAGE
4.30
4.25
4.20
4.15
4.10
4.05
4.00
5.8
5.6
5.4
5.2
5.0
4.8
STANDBY = AV
INTERNAL CLOCK
DD
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
AV (V)
DD
CONVERSION TIME
vs. TEMPERATURE
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
4
3
5.8
5.6
5.4
5.2
5.0
4.8
INTERNAL CLOCK
2
1
0
-1
-2
-3
-4
-17.0
-8.5
0
8.5
17.0
-40
-15
10
35
60
85
INPUT VOLTAGE (V)
TEMPERATURE (°C)
10 ______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Pin Description
PIN
NAME
FUNCꢃION
Analog Power Input. A0
is the power input for the analog section of the converter. Connect a
DD
1, ꢂ, 9, 1ꢂ,
19
+4.ꢂꢁ0 to +ꢁ.±ꢁ0 power supply to A0 . Bypass each A0
to AGND with a ꢀ.1µF capacitor very
DD
DD
A0
DD
close to the device. Bypass A0 to AGND with a bulk capacitor of at least 4.ꢂµF where power enters
DD
the board. Connect all A0
pins to the same potential.
DD
±
3
4
ꢁ
AINꢀ+
AINꢀ-
AIN1+
AIN1-
Channel ꢀ Differential Analog Input
Channel ꢀ Differential Analog Input
Channel 1 Differential Analog Input
Channel 1 Differential Analog Input
ꢃ, 8, 14, 1ꢃ,
18, ±ꢀ, ±8
AGND
Analog Ground. AGND is the power return for A0 . Connect all AGNDs to the same potential.
DD
1ꢀ
11
1±
13
AIN±+
AIN±-
AIN3+
AIN3-
Channel ± Differential Analog Input
Channel ± Differential Analog Input
Channel 3 Differential Analog Input
Channel 3 Differential Analog Input
INTCLK/
EXTCLK
Clock-Select Input. Force INTCLK/EXTCLK high for internal clock mode. Force INTCLK/EXTCLK low
for external clock mode.
1ꢁ
ADC Reference Bypass or Input. REFADC is the bypass point for an internally generated reference
voltage. Bypass REFADC with a 1.ꢀnF capacitor to AGND. REFADC can be driven externally by a
precision external voltage reference. See the Reference section and the Typical Operating Circuit.
±1
REFADC
±±
±3
±4
±ꢁ
±ꢃ
±ꢂ
REFP1
REFP±
COM1
COM±
REFN1
REFN±
Positive Differential Reference Bypass Point 1. Connect REFP1 to REFP±.
Positive Differential Reference Bypass Point ±. Connect REFP± to REFP1. Bypass REFP± with a ꢀ.1µF
capacitor to AGND. Also bypass REFP± to REFN± with a ꢀ.1µF capacitor.
Common-Mode 0oltage Bypass Point 1. Connect COM1 to COM±.
Common-Mode 0oltage Bypass Point ±. Connect COM± to COM1. Connect a 1.ꢀµF capacitor from
COM± to AGND.
Negative Differential Reference Bypass Point 1. Connect REFN1 to REFN±.
Negative Differential Reference Bypass Point ±. Connect REFN± to REFN1. Bypass REFN± with a
ꢀ.1µF capacitor to AGND. Also bypass REFN± to REFP± with a ꢀ.1µF capacitor.
±9
3ꢀ
31
3±
33
34
3ꢁ
3ꢃ
3ꢂ
38
39
4ꢀ
Dꢀ
D1
D±
D3
D4
Dꢁ
Dꢃ
Dꢂ
D8
D9
D1ꢀ
D11
Data Input/Output Bit ꢀ (LSB)
Data Input/Output Bit 1
Data Input/Output Bit ±
Data Input/Output Bit 3
Data Input/Output Bit 4
Data Input/Output Bit ꢁ
Data Input/Output Bit ꢃ
Data Input/Output Bit ꢂ
Data Output Bit 8
Data Output Bit 9
Data Output Bit 1ꢀ
Data Output Bit 11
______________________________________________________________________________________ 11
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Pin Description (continued)
PIN
41
NAME
D1±
FUNCꢃION
Data Output Bit 1±
4±
D13
Data Output Bit 13 (MSB)
Digital I/O Power-Supply Input. DR0
is the power input for the digital I/O buffers and drivers.
DD
Connect a +±.ꢂ0 to +ꢁ.±ꢁ0 power supply to DR0 . Bypass DR0
DD
to DRGND with a ꢀ.1µF
43
DR0
DD
DD
capacitor very close to the device.
44
4ꢁ
DRGND
Driver Ground. DRGND is the power-supply return for DR0
.
DD
End-of-Conversion Output. EOC goes low to indicate the end of a conversion. EOC returns high after
one clock period.
EOC
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion. EOLC
returns high when CON0ST goes low for the next conversion sequence.
4ꢃ
EOLC
Read Input. Forcing RD low initiates a read command of the parallel data bus, Dꢀ–D13. Dꢀ–D13 are
high impedance while either RD or CS is high.
4ꢂ
48
49
RD
WR
CS
Write Input. Forcing WR low initiates a write command for configuring the device through Dꢀ–Dꢂ.
Chip-Select Input. Forcing CS low activates the digital interface. Dꢀ–D13 are high impedance while
either CS or RD is high.
Convert Start Input. CON0ST initiates the conversion process. The analog inputs are sampled on the
rising edge of CON0ST.
ꢁꢀ
ꢁ1
ꢁ±
ꢁ3
ꢁ4
CON0ST
CLK
External-Clock Input. CLK accepts a 1MHz to ꢃMHz external clock signal. For externally clocked
conversions, apply the clock signal to CLK and force INTCLK/EXTCLK low. For internally clocked
conversions, connect CLK to DGND and force INTCLK/EXTCLK high.
Standby-Control Input. Forcing STANDBY high partially powers down the device but leaves all the
reference-related circuitry alive. Use STANDBY instead of SHDN when quick wake-up is required.
STANDBY
SHDN
Shutdown-Control Input. Force SHDN high to place the device into full shutdown. When in full
shutdown, all circuitry within the device is powered down and all reference capacitors are allowed to
discharge. Allow 1ms for wake-up from full shutdown before starting a conversion.
Digital Power-Supply Input. D0 is the power input for the digital circuitry. Connect a +4.ꢂꢁ0 to +ꢁ.±ꢁ0
DD
D0
DD
power supply to D0 . Bypass D0 to DGND with a ꢀ.1µF capacitor very close to the device.
DD
DD
ꢁꢁ, ꢁꢃ
—
DGND
EP
Digital Ground. Power return for D0
.
DD
Exposed Pad. Connect to AGND.
external reference. All channels offer input protection to
±1ꢂ0, independent of the selected input range.
Detailed Description
The MAX1338 simultaneously samples four differential
analog inputs with internal T/H circuits, and sequentially
converts them to a digital code with a 14-bit ADC.
Output data is provided by a 14-bit parallel interface. At
power-up, all channels default to a ±1ꢀ0 input range.
Program different input ranges (±1ꢀ0, ±ꢁ0, ±±.ꢁ0, or
±1.±ꢁ0) using the configuration register. Different input
ranges between ±1±0 and ±1.ꢀ0 are realized using an
The internal clock operates the ADC at ꢁMHz, or uses
an external conversion clock from 1MHz to ꢃMHz. EOC
goes low when the result of each conversion is avail-
able, and EOLC goes low when the last conversion
result is available. Standby and shutdown modes,
selectable through logic-control inputs, save power
between conversions. Figure ± shows a block diagram
of the MAX1338.
1, ______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
DV
DD
DRV
DD
AV
DD
MAX1338
D13
AIN0+
AIN0-
S/H
S/H
4 x 1
MUX
14-BIT
ADC
D8
D7
4 x 14
SRAM
OUTPUT
DRIVERS
AIN3+
AIN3-
D0
REFP2
REFP1
COM2
COM1
CONFIGURATION
REGISTER
WR
CS
INTERFACE
AND
CONTROL
REFN2
REFN1
RD
CONVST
SHDN
CLK
5kΩ
REFADC
STANDBY
EOC
2.500V
EOLC
INTCLK/EXTCLK
AGND
DRGND
DGND
Figure 2. Functional Diagram
parallel I/O. See the Configuration Register section for
Power-Supply Inputs
Three separate power supplies power the MAX1338. A
programming details.
+ꢁ0 analog supply, A0 , powers the analog input and
DD
Input Protection
Protection at the analog inputs provides ±1ꢂ0 fault
immunity for the MAX1338. This protection circuit limits
the current at the analog inputs to less than ±±mA.
Input fault protection is active in standby, in shutdown,
during normal operation, and over all input ranges.
converter sections. A +ꢁ0 digital supply, D0 , powers
DD
the internal logic circuitry, and a +±.ꢂ0 to +ꢁ0 digital
supply (DR0 ), powers the parallel I/O and the control
DD
I/O (see the Typical Operating Circuit). Bypass the
power supplies as indicated in the Layout, Grounding,
and Bypassing section. Power-supply sequencing is
not required for the MAX1338.
Track and Hold (T/H)
To preserve relative phase information between input
channels, each input channel has a dedicated T/H
amplifier. The rising edge of CON0ST represents the
sampling instant for all channels. All samples are taken
within an aperture delay (t ) of 1ꢃns. The aperture
AD
delay of all channels is matched to within 1ꢀꢀps.
Analog Inputs
Software-Selectable Input Range
The MAX1338 provides four independent, software-
selectable, analog input voltage ranges for each chan-
nel. The selectable input ranges are ±0
x 4 (the
REF
x ±, ±0
power-up default condition), ±0
, and
REF
REF
±0
x ꢀ.ꢁ. Using the ±.ꢁ0 internal reference, the
REF
selectable input ranges are ±1ꢀ0 (power-up default),
±ꢁ0, ±±.ꢁ0, and ±1.±ꢁ0. Program the analog input
ranges with the configuration register through the
______________________________________________________________________________________ 13
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Figure 3 shows the equivalent analog input T/H circuit
for one analog input.
As conversion begins, the T/H circuits hold the analog
R1 || R2 = 6.25kΩ
MAX1338
signals. After the 1±th clock cycle (or ±.4µs in internal
clock mode) into the conversion process, the last ana-
log input sample begins shifting through the converter,
and the T/H circuits begin to track the analog inputs
again in preparation for the next CON0ST rising edge.
R1
C
AIN_
HOLD
R2
Due to the resistive load presented by the analog
inputs, any significant analog input source resistance,
R
, increases gain error. Limit R
to a
SOURCE
1.9V
SOURCE
maximum of ±ꢀΩ to limit the effect to less than ꢀ.1%.
Drive the input with a wideband buffer (>1MHz) that
can drive the ADC’s input impedance.
Figure 3. Simplified Typical Input Circuit
Selecting an Input Buffer
Most applications require an input buffer to achieve 14-
bit accuracy. Although slew rate and bandwidth are
important, the most critical specification is output imped-
ance. Use a low-noise, low-distortion amplifier with low
output impedance, for best gain-accuracy performance.
CONVST
CONFIGURATION
REGISTER ACTIVATES
Input Bandwidth
The input-tracking circuitry has a 1MHz small-signal
bandwidth. To avoid high-frequency signals being
aliased into the frequency band of interest, anti-alias fil-
tering is recommended.
RD
t
CS
CS
Data Throughput
t
t
t
CTW
WRL
WTC
The data throughput (f ) of the MAX1338 is a function
TH
WR
of the clock speed (f
). The MAX1338 operates from
CLK
a ꢁMHz internal clock or an external clock between
1MHz and ꢃMHz. For fastest throughput, read the con-
version result during conversion (Figure ꢁ), and calcu-
late data throughput using:
t
DTW
DATA
IN
D0–D7
1
f
=
t
WTD
TH
±ꢃ
t
+
QUIET
f
CLK
Figure 4. Write Timing
where t
is the period of bus inactivity before the
QUIET
Internal Clock
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For inter-
rising edge of CON0ST.
Clock Modes
The MAX1338 provides an internal clock of ꢁMHz.
Alternatively, use an external clock of 1MHz to ꢃMHz.
nal-clock operation, connect INTCLK/EXTCLK to A0
DD
and CLK to DRGND. Note that INTCLK/EXTCLK is ref-
erenced to the analog power supply, A0 . Total con-
DD
version time for all four channels using the internal
clock is ꢃµs (typ).
1± ______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
External Clock
For external clock operation, force INTCLK/EXTCLK low
ꢃable 1ꢁ Configuration Register
and connect an external clock source to CLK. Use an
external clock frequency from 1MHz to ꢃMHz with a
duty cycle between 4ꢀ% and ꢃꢀ%. Choose a minimum
clock frequency of 1MHz to prevent linearity errors
caused by excessive droop in the T/H circuits.
REGISꢃER
NAME
I/O LINE
FUNCꢃION
Dꢀ
D1
D±
D3
D4
Dꢁ
Dꢃ
Dꢂ
CHꢀRꢀ
CHꢀR1
CH1Rꢀ
CH1R1
CH±Rꢀ
CH±R1
CH3Rꢀ
CH3R1
Channel ꢀ input range setting bit ꢀ
Channel ꢀ input range setting bit 1
Channel 1 input range setting bit ꢀ
Channel 1 input range setting bit 1
Channel ± input range setting bit ꢀ
Channel ± input range setting bit 1
Channel 3 input range setting bit ꢀ
Channel 3 input range setting bit 1
Applications Sections
Power-On Reset
At power-up, all channels default to a ±1ꢀ0 input range.
After applying power, allow a 1ms wake-up time to
elapse and perform one dummy conversion before
initiating first conversion.
Power Saving
ꢃable ,ꢁ Input-Range Register Settings
Full Shutdown
During shutdown, the analog and digital circuits in the
MAX1338 power down and the device draws less than
REGISꢃER
SEꢃꢃING
ALLOWABLE
COMMON-MODE
RANGE
SELECꢃED INPUꢃ
RANGE
ꢀ.ꢀꢃmA from A0 , and less than 1ꢀµA from D0
.
DD
DD
CH_R0
CH_R1
Select shutdown mode using the SHDN input. Force
SHDN high to enter shutdown mode. When coming out of
shutdown, allow the 1ms wake-up and then perform one
dummy conversion before making the first conversion.
ꢀ
ꢀ
-1ꢀ0 to +1ꢀ0
-ꢁ0 to +ꢁ0
±ꢁ0
ꢀ
1
1
1
ꢀ
1
±±.ꢁ0
-±.ꢁ0 to +±.ꢁ0
-1.±ꢁ0 to +1.±ꢁ0
±1.±ꢁ0
±ꢀ.ꢃ±ꢁ0
Standby
Standby is similar to shutdown but the reference cir-
cuits remain powered up, allowing faster wake-up.
Enter standby by forcing STANDBY high. After coming
out of standby, perform a dummy conversion before
making the first conversion.
Configuration Register
The MAX1338 uses an 8-bit configuration word to set the
input range for each channel. Table 1 and Table ± describe
the configuration word and the input-range settings.
Write to the configuration register by forcing CS and WR
low, loading bits Dꢀ–Dꢂ onto the parallel bus, and then
forcing WR high. The configuration bits are latched on
the rising edge of WR (Figure 4). It is possible to write to
the configuration register at any point during the conver-
sion sequence. However, it will not be active until the
next convert-start signal. At power-up, the configuration
register contains all zeros, making all channels default to
the maximum input range, -1ꢀ0 to +1ꢀ0. Shutdown and
standby do not change the configuration register, but
the configuration register can be programmed while the
MAX1338 is in shutdown or standby modes.
Digital Interface
The digital interface consists of two sections: a control
I/O section and a parallel I/O section. The control I/O
section includes the following control signals: chip
select (CS), read (RD), write (WR), end of conversion
(EOC), end of last conversion (EOLC), convert start
(CON0ST), power-down (SHDN), standby (STANDBY),
and external-clock input (CLK).
The bidirectional parallel I/O section sets the 8-bit input
range configuration register using Dꢀ–Dꢂ (see the
Configuration Register section) and outputs the 14-bit
conversion result using Dꢀ–D13. The I/O operations are
controlled by the control I/O signals RD, WR, and CS. All
parallel I/O bits are high impedance when either RD = 1
or CS = 1. Figures 4, ꢁ, and ꢃ and the Timing Character-
istics section detail the operation of the digital interface.
______________________________________________________________________________________ 15
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
SAMPLE
t
CONVST
CONVST
29
25
26
27
24
23
17
18
t
19
20
21
22
CLK
EOC
t
EOC1
NEXT
t
EOC
EOLC
RD
t
QUIET
t
ACC
t
RDL
D0–D13
CH0
CH1
CH2
CH3
t
REQ
Figure 5. Reading During a Conversion—Internal or External Clock
Starting a Conversion
Reading a Conversion Result
Internal Clock
For internal clock operation, force INTCLK/EXTCLK
high. To start a conversion using internal clock mode,
Reading During a Conversion
Figure ꢁ shows the interface signals to initiate a read
operation during a conversion cycle. CS can be held
low permanently, low during the RD cycles, or it can be
the same as RD. After initiating a conversion by bring-
ing CON0ST high, wait for EOC to go low (about 3.4µs
in internal clock mode) or 1ꢂ clock cycles (external
clock mode) before reading the first conversion result.
Read the conversion result by bringing RD low, which
latches the data to the parallel digital output bus. Bring
RD high to release the digital bus. Wait for the next
falling edge of EOC (about ꢃꢀꢀns in internal clock
mode or three clock cycles in external clock mode)
before reading the next result. When the last result is
available, EOLC goes low, along with EOC. Wait three
pull CON0ST low for at least t
. The T/H acquires
CON0ST
the signal while CON0ST is low. An EOC signal pulses
low when the first result becomes available, and for
each subsequent result until the end of the conversion
cycle. The EOLC signal goes low when the last conver-
sion result becomes available (Figure ꢃ).
External Clock
For external clock operation, force INTCLK/EXTCLK
low. To start a conversion using external clock mode,
pull CON0ST low for at least t
. The T/H circuits
CON0ST
track the input signal while CON0ST is low. Conversion
begins on the rising edge of CON0ST. Apply an exter-
nal clock to CLK. To avoid T/H droop degrading the
sampled analog input signals, the first CLK pulse must
occur within 1ꢀµs after the rising edge of CON0ST and
have a minimum 1MHz clock frequency. The first con-
version result is available for read on the rising edge of
the 1ꢂth clock cycle, and subsequent conversions on
every 3rd clock cycle thereafter, as indicated by EOC
and EOLC.
clock cycles, t
sion cycle.
, before starting the next conver-
QUIET
Reading After a Conversion
Figure ꢃ shows the interface signals for a read operation
after a conversion using an external clock. At the falling
of EOLC, on the ±ꢃth clock pulse after the initiation of a
conversion, driving CS and RD low places the first con-
version result onto the parallel I/O bus. Read the conver-
sion result on the rising edge of RD. Successive low
pulses of RD place the successive conversion results
16 ______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
SAMPLE
t
CONVST
CONVST
t
CLKH
27
t
CNTC
28
29
30
31
2
26
1
CLK
EOC
t
CLK
t
CLKL
ONLY LAST PULSE SHOWN
t
EOC
EOLC
CS
t
RTC
t
t
t
t
CTR
QUIET
RDH
RDL
RD
t
EOCRD
t
EOLCRD
D0–D13
CH0
CH2
CH3
CH1
t
t
ACC
REQ
Figure 6. Reading After a Conversion—External Clock
onto the bus. After reading all four channels, bring CS
ꢃable 3ꢁ Reference Bypass Capacitors
high to release the parallel I/O. After waiting t
pulse CON0ST low to initiate the next conversion.
,
QUIET
BYPASS
LOCAꢃION
CAPACIꢃORS
Reference
Bypass the reference inputs as indicated in Table 3.
REFADC bypass capacitor to AGND
REFP1 bypass capacitor to AGND
REFN1 bypass capacitor to AGND
REFP1 to REFN1 capacitor
1nF
ꢀ.1µF
Internal Reference
The internal reference supports all input ranges for the
MAX1338.
ꢀ.1µF
1.ꢀµF
COM1 bypass capacitor to AGND
1.ꢀµF || ꢀ.1µF
External Reference
Implement external-reference operation by overdriving
the internal reference voltage. Override the internal ref-
erence voltage by connecting a ±.ꢀ0 to 3.ꢀ0 external
reference at REF. The REF input impedance is typically
ꢁkΩ. For more information about using an external ref-
erence, see the Transfer Functions section.
Transfer Functions
Digital Correction
Factory trim procedures digitally shift the transfer func-
tion to reduce bipolar zero-code offset to less than
±4 LSBs (typ). Depending on initial conditions, the
transfer function is shifted up or down, as required. The
maximum shift that any transfer function experiences is
ꢃ4 codes, which can have a small effect at the
extremes of the transfer function, as shown in Figure ꢂ.
______________________________________________________________________________________ 1ꢂ
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
8 x V
REFADC
0x1FFF
0x1FFF
0x1FFE
0x1FFD
0x1FFC
INITIAL
TRANSFER
FUNCTION
ADJUSTED
TRANSFER
FUNCTION
0x0001
0x0000
0x3FFF
0x0000
MAXIMUM
64 CODES
0x2003
0x2002
0x2001
0x2000
8 x V
214
REF
1 LSB =
0x2000
-8192 -8190
-1 0 +1
INPUT VOLTAGE (V - V
+8189 +8191
IN LSBs)
AIN_-
+8191
-8192
0
INPUT VOLTAGE (LSBs)
AIN_+
Figure 7. Example of Digitally Adjusted Transfer Function—
Shifted Down to Minimize Zero-Code Offset
Figure 8. 10ꢀ Transfer Function
Input Range Settings
Table 4 shows the two’s complement output for a selec-
tion of inputs.
Applications Information
Layout, Grounding, and Bypassing
For best performance, the board layout must follow
some simple guidelines. Separate the control I/O and
parallel I/O signals from the analog signals, and run the
clock signals separate from everything. Do not run ana-
log and digital (especially clock) lines parallel to one
another, or digital lines underneath the ADC package.
Run the parallel I/O signals together as a bundle.
The full-scale input range (FSR) depends on the select-
ed range, and the voltage at REF, as shown in Table ꢁ.
Also shown in Table ꢁ are the allowable common-mode
ranges for the differential inputs.
Calculate the LSB size using:
A × 0
REFADC
14
The MAX1338 has an exposed underside pad for a
low-inductance ground connection and low thermal
resistance. Connect the exposed pad to the circuit
board ground plane. Figure 1± shows the recommend-
ed system ground connections. Establish an analog
ground point at AGND and a digital ground point at
DGND. Connect all analog grounds to the analog
ground point. Connect all digital grounds to the digital
ground point. For lowest noise operation, make the
power-supply ground returns as low impedance and as
short as possible. Connect the analog ground point to
the digital ground point at one location.
1 LSB=
±
where A = gain multiplier for the selected input range,
from Table ꢃ.
Determine the input voltage as a function of 0
the output code using:
, and
REF
CODE
0
− 0
= 0
× A ×
AIN_+
AIN_−
REFADC
14
±
where A = gain multiplier for the selected input range,
from Table ꢃ.
High-frequency noise in the power supplies degrades
the ADC’s performance. Bypass A0
to AGND with a
DD
Figures 8, 9, 1ꢀ, and 11 show the transfer functions for
the four selectable input ranges.
parallel combination of ꢀ.1µF and ±.±µF capacitors,
bypass D0 to DGND with a parallel combination of
DD
ꢀ.1µF and ±.±µF capacitors, and bypass DR0
to
DD
DRGND with a parallel combination of ꢀ.1µF and ±.±µF
capacitors. If the supply is very noisy use a ferrite bead
as a lowpass filter, as shown in Figure 1±.
18 ______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
ꢃable ±ꢁ Code ꢃable with ꢀ
= ,ꢁ500ꢀ
REF
INPUꢃ ꢀOLꢃAGE (ꢀ)
DECIMAL
EQUIꢀALENꢃ
OUꢃPUꢃ
ꢃWO’S COMPLEMENꢃ
BINARY OUꢃPUꢃ CODE
±10ꢀ INPUꢃ
RANGE
±5ꢀ INPUꢃ
RANGE
±,ꢁ5ꢀ INPUꢃ
RANGE
±1ꢁ,5ꢀ INPUꢃ
RANGE
SELECꢃED
(CODE
)
10
SELECꢃED
SELECꢃED
SELECꢃED
9.9988
9.99ꢂꢃ
ꢀ.ꢀꢀ1±
ꢀ
4.9994
4.9988
ꢀ.ꢀꢀꢀꢃ
ꢀ
±.4998
±.499ꢂ
ꢀ.ꢀꢀꢀ±
ꢀ
1.±499
1.±498
ꢀ.ꢀꢀꢀ1
ꢀ
8191
819ꢀ
1
ꢀ1 1111 1111 1111 → ꢀx1FFF
ꢀ1 1111 1111 111ꢀ → ꢀx1FFE
ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀ1 → ꢀxꢀꢀꢀ1
ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ → ꢀxꢀꢀꢀꢀ
11 1111 1111 1111 → ꢀx3FFF
1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀ1 → ꢀx±ꢀꢀ1
1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ → ꢀx±ꢀꢀꢀ
ꢀ
-ꢀ.ꢀꢀ1±
-9.9988
-1ꢀ.ꢀꢀꢀꢀ
-ꢀ.ꢀꢀꢀꢃ
-4.9994
-ꢁ.ꢀꢀꢀꢀ
-ꢀ.ꢀꢀꢀ±
-±.4998
-±.ꢁꢀꢀꢀ
-ꢀ.ꢀꢀꢀ1
-1.±499
-1.±ꢁꢀꢀ
-1
-8191
-819±
Definitions
ꢃable 5ꢁ Input Ranges
Integral Nonlinearity (INL)
SELECꢃED
INPUꢃ
RANGE (ꢀ)
FULL-SCALE
INPUꢃ RANGE COMMON-MODE
ALLOWABLE
ꢀ
REFADC
(ꢀ)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For these
devices, this straight line is a line drawn between the
endpoints of the transfer function, once offset and gain
errors have been nulled.
(ꢀ)
RANGE (ꢀ)
±.ꢀ
±.ꢁ
3.ꢀ
±.ꢀ
±.ꢁ
3.ꢀ
±.ꢀ
±.ꢁ
3.ꢀ
±.ꢀ
±.ꢁ
3.ꢀ
±8
±1ꢀ
±1±
±4
±ꢁ
±ꢁ
±1ꢀ
±ꢁ
±ꢁ
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specifica-
tion of less than ±1 LSB guarantees no missing codes
and a monotonic transfer function.
±±.ꢁ
±ꢁ
±±.ꢁ
±ꢃ
±±.ꢁ
±±
±1.±ꢁ
±1.±ꢁ
±1.±ꢁ
±ꢀ.ꢃ±ꢁ
±ꢀ.ꢃ±ꢁ
±ꢀ.ꢃ±ꢁ
±±.ꢁ
±1.±ꢁ
±±.ꢁ
±3
±1
Offset Error
Offset error indicates how well the actual transfer func-
tion matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified
is at or near the zero scale of the transfer function or at
or near the midscale of the transfer function.
±1.±ꢁ
±1.ꢁ
ꢃable 6ꢁ LSB Size with ꢀ
= ,ꢁ500ꢀ
REF
SELECꢃED
INPUꢃ RANGE
(ꢀ)
For the MAX1338, the ideal zero-scale digital output
transition from ꢀx3FFF to ꢀxꢀꢀꢀꢀ occurs with an analog
input voltage of zero. Offset error is the amount of ana-
log input-voltage deviation between the measured input
voltage and the calculated input voltage at the zero-
scale transition.
GAIN MULꢃIPLIER
(A)
LSB SIZE (mꢀ)
±1ꢀ
±ꢁ
8
4
±
1
1.±±ꢀꢂ
ꢀ.ꢃ1ꢀ4
ꢀ.1ꢁ±ꢃ
ꢀ.ꢀꢂ3ꢃ
±±.ꢁ
±1.±ꢁ
______________________________________________________________________________________ 19
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
4 x V
2 x V
REFADC
REFADC
0x1FFF
0x1FFE
0x1FFD
0x1FFC
0x1FFF
0x1FFE
0x1FFD
0x1FFC
0x0001
0x0000
0x3FFF
0x0001
0x0000
0x3FFF
0x2003
0x2002
0x2001
0x2000
0x2003
0x2002
0x2001
0x2000
4 x V
214
2 x V
214
REF
REF
1 LSB =
1 LSB =
-8192 -8190
-1 0 +1
+8189 +8191
IN LSBs)
-8192 -8190
-1 0 +1
INPUT VOLTAGE (V - V
+8189 +8191
IN LSBs)
AIN_-
INPUT VOLTAGE (V
- V
AIN_-
AIN_+
AIN_+
Figure 9. 5ꢀ Transfer Function
Figure 10. 2.5ꢀ Transfer Function
V
REFADC
ANALOG
POWER SUPPLY
0x1FFF
0x1FFE
0x1FFD
0x1FFC
DIGITAL POWER SUPPLIES
+3V
+5V
GND
+5V
AGND
FERRITE
BEAD
0x0001
0x0000
0x3FFF
0x2003
0x2002
0x2001
0x2000
AV
DV
DD
AGND
+5V
GND
V
214
DD
DGND
DRV
DRGND
DD
REF
1 LSB =
DIGITAL
CIRCUITS
MAX1338
-8192 -8190
-1 0 +1
INPUT VOLTAGE (V - V
+8189 +8191
IN LSBs)
AIN_-
AIN_+
Figure 11. 1.25ꢀ Transfer Function
Figure 12. Power-Supply Grounding and Bypassing
Gain Error
Signal-to-Noise Ratio (SNR)
Gain error indicates how well the slope of the actual
transfer function matches the slope of the ideal transfer
function. For the MAX1338, the gain error is the differ-
ence between the measured positive full-scale and
negative full-scale transition points minus the difference
between the ideal positive full-scale and negative full-
scale bipolar transition points.
SNR is a measure of the converter’s noise characteris-
tics. For a waveform perfectly reconstructed from digi-
tal samples, SNR is the ratio of the full-scale analog
input (RMS value) to the RMS quantization error (resid-
ual error). The ideal, theoretical minimum analog-to-dig-
ital noise is caused by quantization noise error only and
results directly from the ADC’s resolution (N bits):
,0 ______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
SNR = (ꢃ.ꢀ± x N + 1.ꢂꢃ)dB
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the funda-
mental (maximum signal component) to the RMS value
of the next largest spurious component, excluding DC
offset. SFDR is specified in decibels relative to the car-
rier (dBc).
where N = 14 bits. In reality, there are other noise
sources such as thermal noise, reference noise, and
clock jitter. SNR is computed by taking the ratio of the
RMS signal to the RMS noise. RMS noise includes all
spectral components to the Nyquist frequency exclud-
ing the fundamental, the first five harmonics, and the
DC offset.
Aperture Delay
Aperture delay (t ) is the time delay from the sampling
AD
clock edge to the instant when an actual sample is taken.
Signal-to-Noise Plus Distortion (SINAD)
SINAD indicates the converter’s noise and distortion
performance.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.
aperture delay.
Channel-to-Channel Isolation
Channel-to-channel isolation indicates how well each
analog input is isolated from the others. The channel-to-
channel isolation for the MAX1338 is measured by
applying a DC -ꢀ.ꢁdBFS sine wave to the ON channel
while a high frequency 1ꢀkHz -ꢀ.ꢁdBFS sine wave is
applied to all OFF channels. An FFT is taken for the ON
channel. From the FFT data, channel-to-channel
crosstalk is expressed in dB as the power ratio of the
DC signal applied to the ON channel and the high-fre-
quency crosstalk signal from the OFF channels.
SIGNAL
RMS
SINAD(dB) = ±ꢀ × log
(NOISE + DISTORTION)
RMS
Effective Number of Bits (ENOB)
ENOB specifies the global accuracy of an ADC at a spe-
cific input frequency and sampling rate. An ideal ADC’s
error consists of quantization noise only. ENOB for a full-
scale sinusoidal input waveform is computed from:
Power-Supply Rejection (PSRR)
PSRR is defined as the shift in gain error when the ana-
log power supply is changed from 4.ꢂꢁ0 to ꢁ.±ꢁ0.
SINAD − 1.ꢂꢃ
ENOB =
Small-Signal Bandwidth
A -±ꢀdBFS sine wave is applied to the MAX1338 input.
The frequency is increased until the amplitude of the
digitized conversion result decreases 3dB.
ꢃ.ꢀ±
Total Harmonic Distortion (THD)
THD is a dynamic indication of how much harmonic
distortion the converter adds to the signal.
Full-Power Bandwidth
A -ꢀ.ꢁdBFS sine wave is applied to the MAX1338 input.
The frequency is increased until the amplitude of the
digitized conversion result decreases 3dB.
THD is the ratio of the RMS sum of the first five harmon-
ics of the fundamental signal to the fundamental itself.
This is expressed as:
±
±
±
±
±
0
+ 0 + 0 + 0 + 0
ꢃ
±
3
4
ꢁ
THD = ±ꢀ × log
0
1
where 0 is the fundamental amplitude and 0 –0 are
1
±
ꢃ
the amplitudes of the ±nd- through ꢃth-order harmonics.
______________________________________________________________________________________ ,1
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Typical Operating Circuit
54
15
+5V
0.1µF
DV
INTCLK/EXTCLK
DD
+5V
1
7
MAX1338
AV
DD
55, 56
GND
DGND
0.1µF
0.1µF
AV
DD
53
51
50
49
48
47
46
45
52
SHDN
CLK
9
17
19
21
AV
AV
DD
DD
0.1µF
0.1µF
0.1µF
CONVST
CS
CONTROL I/O
AV
WR
DD
RD
REFADC
EOLC
EOC
0.001µF
22
23
REFP1
REFP2
0.1µF
STANDBY
1.0µF
43
44
DRV
DD
+3V TO +5V
27
26
REFN2
REFN1
0.1µF
0.1µF
1.0µF
0.1µF
GND
DRGND
24
25
COM1
COM2
42
41
40
39
38
37
36
35
34
33
D13
D12
D11
D10
D9
6, 8, 14, 16, 18, 20, 28
GND
AGND
DIGITAL
OUTPUT
2
AIN0+
AIN0-
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
3
4
D8
D7
PARALLEL I/O
D6
5
ANALOG
INPUTS
D5
10
11
12
13
D4
DIGITAL
I/O
32
31
30
29
D3
D2
D1
D0
,, ______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Pin Configuration
Chip Information
TRANSISTOR COUNT: ±ꢂ,ꢀꢀꢀ
TOP VIEW
PROCESS: BiCMOS
EXPOSED PAD: Connect to AGND
D13
41 D12
40
1
42
AV
DD
2
AIN0+
AIN0-
AIN1+
AIN1-
AGND
3
D11
4
39 D10
38 D9
5
6
37
36 D7
D6
D8
7
AV
DD
MAX1338
AGND
8
35
AV
DD
9
34 D5
33 D4
AIN2+
AIN2-
AIN3+
AIN3-
AGND
10
11
12
13
14
D3
31 D2
32
30
29
D1
D0
ꢃHIN QFN
______________________________________________________________________________________ ,3
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to wwwꢁmaxim-icꢁcom/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
,± ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© ±ꢀꢀ4 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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