MAX1359BCTL [MAXIM]
Analog Circuit, 1 Func, BICMOS, 6 X 6 MM, 0.80 MM HEIGHT, MO-220WJJD-2, TQFN-40;
| 型号： | MAX1359BCTL |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, BICMOS, 6 X 6 MM, 0.80 MM HEIGHT, MO-220WJJD-2, TQFN-40 信息通信管理 |
| 文件： | 总74页 (文件大小：1204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3710; Rev 1; 8/05
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
General Description
Features
♦ +1.8V to +3.6V Single-Supply Operation
The MAX1358/MAX1359/MAX1360 smart data-acquisition
systems (DAS) are each based on a 16-bit, sigma-delta
analog-to-digital converter (ADC) and system-support
functionality for a microprocessor (µP)-based system.
These devices integrate an ADC, DACs, operational
amplifiers, internal 1.25V/2.048V/2.5V selectable refer-
ence, temperature sensors, analog switches, a 32kHz
oscillator, a real-time clock (RTC) with alarm, a high-fre-
quency-locked loop (FLL) clock, four user-programma-
ble I/Os, an interrupt generator, and 1.8V and 2.7V
voltage monitors in a single chip.
♦ Multichannel 16-Bit Sigma-Delta ADC
10sps to 512sps Programmable Conversion Rate
Self and System Offset and Gain Calibration
PGA with Gains of 1, 2, 4, or 8
Unipolar and Bipolar Modes
10-Input Differential Multiplexer
♦ 10-Bit Force-Sense DACs
♦ Uncommitted Op Amps
♦ Dual SPDT Analog Switches
♦ 1.25V, 2.048V, or 2.5V Selectable Voltage
The MAX1358/MAX1359/MAX1360 have dual 10:1 dif-
ferential input multiplexers (muxes) that accept signal
levels from 0 to AV . An on-chip 1x to 8x programma-
DD
Reference
♦ Internal Charge Pump
ble-gain amplifier (PGA) measures low-level signals
and reduces external circuitry required.
♦ System Support
Real Time Clock and Alarm Register
Internal/External Temperature Sensor
Internal Oscillator with Clock Output
User-Programmable I/O and Interrupt Generator
The MAX1358/MAX1359/MAX1360 operate from a sin-
gle +1.8V to +3.6V supply and consume only 1.4mA in
normal mode and only 6.1µA in sleep mode.
V
Monitors
DD
The MAX1358 has two DACs with one uncommitted op
amp; the MAX1359 has one DAC with two uncommit-
ted op amps; and the MAX1360 has three uncommit-
ted op amps.
♦ SPI/QSPI/MICROWIRE, 4-Wire Serial Interface
♦ Space-Saving (6mm x 6mm x 0.8mm) 40-Pin TQFN
Package
Ordering Information
The serial interface is compatible with either SPI™/QSPI™
or MICROWIRE™, and is used to power up, configure,
and check the status of all functional blocks.
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
The MAX1358/MAX1359/MAX1360 are available in a
space-saving 40-pin TQFN package and are specified
over the commercial (0°C to +70°C) and the extended
(-40°C to +85°C) temperature ranges.
MAX1358AETL* -40°C to +85°C 40 TQFN-EP** T4066-4
MAX1358BETL
MAX1358ACTL*
MAX1358BCTL*
-40°C to +85°C 40 TQFN-EP** T4066-4
0°C to +70°C 40 TQFN-EP** T4066-4
0°C to +70°C 40 TQFN-EP** T4066-4
Applications
MAX1359AETL* -40°C to +85°C 40 TQFN-EP** T4066-4
Battery-Powered and Portable Devices
Electrochemical and Optical Sensors
Medical Instruments
MAX1359BETL
MAX1359ACTL*
MAX1359BCTL
-40°C to +85°C 40 TQFN-EP** T4066-4
0°C to +70°C 40 TQFN-EP** T4066-4
0°C to +70°C 40 TQFN-EP** T4066-4
MAX1360AETL* -40°C to +85°C 40 TQFN-EP** T4066-4
MAX1360BETL* -40°C to +85°C 40 TQFN-EP** T4066-4
Industrial Control
Data-Acquisition Systems
MAX1360ACTL*
MAX1360BCTL*
0°C to +70°C 40 TQFN-EP** T4066-4
0°C to +70°C 40 TQFN-EP** T4066-4
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
*Future product—contact factory for availability.
**EP = Exposed pad.
Pin Configurations appear at end of data sheet.
Selector Guide
SPDT/SPST
SWITCHES
EXTERNAL ADC
PART
DACs
OP AMPs
UPIOs
INPUTS
MAX1358
MAX1359
MAX1360
2
1
0
1
2
3
2/2
2/1
2/0
2
2
2
4
4
4
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ABSOLUTE MAXIMUM RATINGS
AV
to AGND .........................................................-0.3V to +4V
Continuous Current Into Any Pin.........................................50mA
DD
DV to DGND.........................................................-0.3V to +4V
Continuous Power Dissipation (T = +70°C)
DD
A
AV
to DV
............................................................-4V to +4V
40-Pin TQFN (derate 25.6mW/°C above +70°C) ....2051.3mW
DD
DD
AGND to DGND.....................................................-0.3V to +0.3V
CLK32K to DGND....................................-0.3V to (DV + 0.3V)
Operating Temperature Range
MAX13_ _ CTL ....................................................0°C to +70°C
MAX13_ _ ETL .................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
UPIO_ to DGND........................................................-0.3V to +4V
Digital Inputs to DGND ............................................-0.3V to +4V
Analog Inputs to AGND ...........................-0.3V to (AV
Digital Output to DGND…........................-0.3V to (DV
Analog Outputs to AGND.........................-0.3V to (AV
+ 0.3V)
+ 0.3V)
+ 0.3V)
DD
DD
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DC ACCURACY
Data rate = 10sps, PGA gain = 2;
data rate = 10sps to 60sps, PGA gain = 1;
no missing codes, Table 1 (Note 2)
Noise-Free Resolution
16
10
Bits
sps
Conversion Rate
Output Noise
No missing codes, Table 1
No missing codes
512
Table 1
µV
RMS
Unipolar mode, AV
= 3V, data
DD
A grade
B grade
0.003
Integral Nonlinearity
INL
%FSR
%FSR
rate = 40sps, PGA gain = 1,
= +25°C
0.004
1.0
T
A
Uncalibrated
Unipolar Offset Error or Bipolar
Zero Error (Note 3)
Data rate = 10sps, PGA gain = 1, calibrated
0.003
Unipolar Offset-Error or Bipolar
Zero-Error Temperature Drift
(Note 4)
Bipolar
2.0
10
µV/°C
Unipolar
Uncalibrated
0.6
Gain Error (Notes 3, 5)
% FSR
Data rate = 10sps, PGA = 1, calibrated
0.003
Gain-Error Temperature
Coefficient
(Notes 4, 6)
1.0
73
ppm/ °C
DC Positive Power-Supply
Rejection Ratio
PGA gain = 1, unipolar mode, measured by
full-scale error with AV
PSRR
dB
= 1.8V to 3.6V
DD
ADC ANALOG INPUTS (AIN1, AIN2)
DC Input Common-Mode
Rejection Ratio
CMRR
PGA gain = 1, unipolar mode
85
dB
2
_______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Normal-Mode 60Hz Rejection
Ratio
Data rate = 10sps or 60sps, PGA gain = 1,
unipolar mode (Note 2)
100
dB
Normal-Mode 50Hz Rejection
Ratio
Data rate = 10sps or 50sps, PGA gain = 1,
unipolar mode (Note 2)
100
dB
V
Absolute Input Range
AGND
AV
DD
-0.05 /
Gain
V
Gain
/
REF
Unipolar mode
Differential Input Range
V
-V
REF
/
V
Gain
/
REF
Bipolar mode
Gain
ADC not in measurement mode, mux
1
5
enabled, T ≤ +55°C, inputs = +0.1V to
A
DC Input Current (Note 7)
nA
(AV
- 0.1V)
DD
T
A
= +85°C
Input Sampling Capacitance
Input Sampling Rate
C
5
pF
IN
f
21.84
kHz
SAMPLE
External Source Impedance at
Input
See Table 3
Table 3
kΩ
FORCE-SENSE DAC (MAX1358/MAX1359 only, R = 10kΩ and C = 200pF, FBA = OUTA and FBB = OUTB, unless otherwise
L
L
noted)
Resolution
Guaranteed monotonic
Code 3D hex to 3FF hex
10
Bits
Differential Nonlinearity
DNL
INL
1
2
LSB
A grade
B grade
Code 3D hex to 3FF
hex
Integral Nonlinearity
LSB
4
Offset Error
Reference to code 52 hex
20
mV
µV/°C
LSB
Offset-Error Tempco
Gain Error
4.4
1
Excludes offset and voltage reference error
Excludes offset and reference drift
SWA/B switches open (Notes 7, 8)
5
Gain-Error Tempco
Input Leakage Current at SWA/B
ppm/°C
nA
1
T
T
T
= -40°C to +85°C
= 0°C to +70°C
= 0°C to +50°C
1
nA
A
A
A
V
(AV
(Note 7)
= +0.3V to
- 0.3V)
FBA/B
Input Leakage Current at FBA/B
600
400
DD
pA
nA
V
DAC Output Buffer Leakage
Current
DAC buffer disabled (Note 7)
At FBA and FBB
75
AV
-
DD
0.35
Input Common-Mode Voltage
0
Line Regulation
AV
= +1.8V to +3.6V
40
175
0.5
µV/V
µV/µA
V
DD
Load Regulation
I
= 2mA, C = 1000pF (Note 2)
OUT L
Output Voltage Range
AGND
AV
DD
_______________________________________________________________________________________
3
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
Output Slew Rate
SYMBOL
CONDITIONS
52 hex to 3FF hex code swing rising or
falling, R = 10kΩ, C = 100pF
MIN
TYP
40
MAX
UNITS
V/ms
µs
L
L
Output-Voltage Settling Time
10% to 90% rising or falling to 0.5 LSB
65
f = 0.1Hz to
10Hz
80
Referred to FBA/B,
excludes reference noise
Input Voltage Noise
µV
P-P
f = 10Hz to
10kHz
200
OUTA/B shorted to AGND
20
15
Output Short-Circuit Current
mA
OUTA/B shorted to AV
DD
Input-Output SWA/SWB Switch
Resistance
Between SWA and OUTA, or SWB and
OUTB, HFCK enabled
150
Ω
SWA/SWB Switch Turn-On/Off
Time
HFCK enabled
100
18
ns
µs
Power-On Time
Excluding reference
EXTERNAL REFERENCE (REF)
Input Voltage Range
Input Resistance
AGND
AV
V
DD
DAC on, internal REF and ADC off
2.5
MΩ
nA
DC Input Leakage Current
Internal REF, DAC, and ADC off (Note 7)
100
INTERNAL VOLTAGE REFERENCE (C
= 4.7µF)
REF
A grade
B grade
A grade
B grade
A grade
B grade
1.237
1.213
2.027
1.987
2.475
2.425
1.25
1.25
2.048
2.048
2.5
1.263
1.288
2.068
2.109
2.525
2.575
50
AV
AV
AV
≥ +1.8V, T = +25°C
A
DD
DD
DD
Reference Output Voltage
V
≥ +2.2V, T = +25°C
V
REF
A
≥ +2.7V, T = +25°C
A
2.5
V
= 1.25V
15
REF
A grade
Output-Voltage Temperature
Coefficient (Note 7)
V
=
REF
ppm/oC
65
TC
2.048V, 2.5V
B grade
15
18
90
REF shorted to AGND
mA
µA
Output Short-Circuit Current
Line Regulation
I
RSC
REF shorted to AV
DD
A grade
B grade
100
1.2
T
T
= +25°C
µV/V
A
A
25
I
= 0
SOURCE
to 500µA
= 0 to
Load Regulation
= +25°C, V
= 1.25V
µV/µA
REF
I
SINK
1.7
50µA
4
_______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
Long-Term Stability
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ppm/
1000hrs
(Note 9)
f = 0.1Hz to 10Hz, AV
35
= 3V
= 3V
50
DD
Output Noise Voltage
µV
P-P
f = 10Hz to 10kHz, AV
400
100
DD
Turn-On Settling Time
Buffer only, settle to 0.1% of final value
µs
TEMPERATURE SENSOR
Temperature Measurement
Resolution
ADC resolution is 16-bit, 10sps
0.11
°C/LSB
°C
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
= 0°C to +70°C
= -40oC to +85°C
= 0°C to +70°C
= -40°C to +85°C
= +25°C
0.5
1
A grade
B grade
Internal Temperature-Sensor
Measurement Error
0.5
1
0.50
A grade
B grade
= 0°C to +70°C
= -40°C to +85°C
= +32°C to +43°C
= +10°C to +50°C
= 0°C to +70°C
= -40°C to +85°C
1
2
External Temperature-Sensor
Measurement Error (Note 10)
0.50
0.5
0.5
1
°C
Temperature Measurement Noise
0.18
°C
RMS
Temperature Measurement
Power-Supply Rejection Ratio
0.2
°C/V
OP AMP (R = 10kΩ connected to AV / 2)
L
DD
Input Offset Voltage
Offset-Error Tempco
V
V
= 0.5V
CM
15
mV
µV/oC
nA
OS
3
0.006
4
T
T
T
T
T
T
= -40°C to +85°C
= 0°C to +70°C
= 0°C to +50°C
= -40°C to +85°C
= 0°C to +70°C
= 0°C to +50°C
1
A
A
A
A
A
A
IN1+, IN2+, IN3+
IN1-, IN2-, IN3-
300
200
1
pA
nA
pA
nA
V
2
Input Bias Current (Note 7)
Input Offset Current
I
BIAS
0.025
20
600
400
1
I
V
,
= +0.3V to (AV - 0.3V) (Note 7)
OS
IN1_ IN2_ DD
Input Common-Mode Voltage
Range
AV
-
DD
0.35
CMVR
CMRR
0
0 ≤ V
≤ 75mV
60
75
CM
Common-Mode Rejection Ratio
dB
75mV < V
≤ AV
- 0.35V
60
CM
DD
_______________________________________________________________________________________
5
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
= +1.8V to +3.6V
MIN
76.5
90
TYP
100
116
MAX
UNITS
dB
Power-Supply Rejection Ratio
Large-Signal Voltage Gain
PSRR
AV
DD
A
100mV ≤ V
≤ AV - 100mV (Note 11)
DD
dB
VOL
OUT_
I
I
I
I
I
I
I
I
I
I
= 10µA
= 50µA
= 100µA
= 500µA
= 2mA
0.005
0.025
0.05
0.25
0.5
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
Sourcing
Maximum Current Drive
∆V
V
OUT
= 10µA
0.005
0.025
0.05
0.25
0.5
SINK
SINK
SINK
SINK
SINK
= 50µA
Sinking
= 100µA
= 500µA
= 2mA
Gain Bandwidth Product
Phase Margin
GBW
SR
Unity-gain configuration, C = 1nF
80
60
kHz
L
Unity-gain configuration, C = 1nF (Note 11)
Degrees
V/µs
L
Output Slew Rate
C = 200pF
L
0.04
80
f = 0.1Hz to 10Hz
f = 10Hz to 10kHz
Unity-gain
configuration
Input Voltage Noise
µV
P-P
200
20
V
V
shorted to AGND
OUT_
OUT_
Output Short-Circuit Current
Power-On Time
mA
shorted to AV
15
DD
15
µs
SPDT SWITCHES (SNO_, SNC_, SCM_, HFCK enabled)
V
V
V
= 0V
T
T
= 0°C to +50°C
= 0°C to +50°C
45
50
SCM_
SCM_
SCM_
A
On-Resistance
R
Ω
= 0.5V
ON
A
= 0.5V to AV
150
1
DD
T
A
= -40°C to +85°C
nA
pA
SNO_, SNC_ = +0.5V,
+1.5V; SCM_ = +1.5V, T = 0°C to +70°C
+0.5V
SNO_, SNC_ Off-Leakage
Current (Note 7)
I
I
SNO_(OFF)
SNC_(OFF)
600
400
2
A
T
= 0°C to +50°C
A
A
T
= -40°C to +85°C
SNO_, SNC_ = +0.5V,
+1.5V; SCM_ = +1.5V, T = 0°C to +70°C
+0.5V
SCM_ Off-Leakage Current
(Note 7)
I
nA
nA
1.2
0.8
2
SCM_(OFF)
A
T
A
T
A
T
A
T
A
= 0°C to +50°C
= -40°C to +85°C
= 0°C to +70°C
= 0°C to +50°C
SNO_, SNC_ = +0.5V,
+1.5V, or floating;
SCM_ = +1.5V, +0.5V
SCM_ On-Leakage Current
(Note 7)
I
1.2
0.8
SCM_(ON)
Input Voltage Range
Turn-On/Off Time
AGND
AV
V
DD
t
/t
Break-before-make
100
ns
ON OFF
6
_______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
SNO_, SNC_, or SCM_ = AV
MIN
TYP
MAX
UNITS
or AGND;
DD
Input Capacitance
5
pF
switch connected to enabled mux input
CHARGE PUMP (10µF at REG and 10µF external capacitor between CF+ and CF-)
Maximum Output Current
Output Voltage
I
10
3.2
3.0
mA
V
OUT
No load
= 10mA
3.3
3.6
50
I
OUT
10µF external capacitor between CPOUT
and DGND, I = 10mA, excluding ESR of
Output Voltage Ripple
mV
OUT
external capacitor
I
= 10mA, excluding ESR of external
OUT
Load Regulation
15
20
mV/mA
capacitor
REG Input Voltage Range
REG Input Current
Internal linear regulator disabled
Linear regulator off, charge pump off
Charge pump disabled
1.6
1.8
1.8
V
3
2
nA
V
CPOUT Input Voltage Range
CPOUT Input Leakage Current
SIGNAL-DETECT COMPARATOR
3.6
Charge pump disabled
nA
TSEL[2:0] = 0 hex
TSEL[2:0] = 4 hex
TSEL[2:0] = 5 hex
TSEL[2:0] = 6 hex
TSEL[2:0] = 7 hex
0
50
Differential Input-Detection
Threshold Voltage
100
150
200
mV
mV
Differential Input-Detection
Threshold Error
10
Common-Mode Input Voltage
Range
AGND
1.0
AV
V
DD
Turn-On Time
50
µs
VOLTAGE MONITORS
DV Monitor Supply Voltage
DD
Range
For valid reset
3.6
V
V
A grade
B grade
1.80
1.80
1.85
1.85
1.90
1.95
Trip Threshold (DV
Falling)
DD
DV
Period
Monitor Timeout Reset
DD
1.5
s
HYSE bit set to logic 1
HYSE bit set to logic 0
200
35
DV
Monitor Hysteresis
mV
DD
_______________________________________________________________________________________
7
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DV
Monitor Turn-On Time
5
ms
DD
CPOUT Monitor Supply Voltage
Range
1.0
2.7
3.6
2.9
V
CPOUT Monitor Trip Threshold
CPOUT Monitor Hysteresis
CPOUT Monitor Turn-On Time
Internal Power-On Reset Voltage
32kHz Oscillator (32KIN, 32KOUT)
Clock Frequency
2.8
35
5
V
mV
ms
V
1.7
DV
= 2.7V
32.768
25
kHz
ppm
ms
DD
DD
Stability
DV
= 1.8V to 3.6V, excluding crystal
Oscillator Startup Time
1500
6
Crystal Load Capacitance
pF
LOW-FREQUENCY CLOCK INPUT/OUTPUT (CLK32K)
Output Clock Frequency
32.768
kHz
ns
Absolute Input to Output Clock
Jitter
Cycle to cycle
10% to 90%, 30pF load
5
5
Input to Output Rise/Fall Time
Input/Output Duty Cycle
HIGH-FREQUENCY CLOCK OUTPUT (CLK)
ns
%
40
60
f
f
f
f
= f
4.8660 4.9152 4.9644
OUT
OUT
OUT
OUT
FLL
FLL
FLL
FLL
= f
= f
= f
/ 2, power-up default
2.4330 2.4576 2.4822
MHz
FLL Output Clock Frequency
/ 4
/ 8
1.2165 1.2288 1.2411
608.25 614.4 620.54
kHz
ns
Cycle to cycle, FLL off
Cycle to cycle, FLL on
10% to 90%, 30pF load
0.15
1
Absolute Clock Jitter
Rise and Fall Time
Duty Cycle
t /t
R F
10
ns
f
= 4.9152MHz
40
45
60
55
OUT
OUT
%
f
= 2.4576MHz, 1.2288MHz, 614.4kHz
Uncalibrated CLK Frequency
Error
FLL calibration not performed
35
%
DIGITAL INPUTS (SCLK, DIN, CS, UPIO_, CLK32K)
0.7 x
Input High Voltage
Input Low Voltage
V
V
V
IH
DV
DD
0.3 x
V
IL
DV
DD
8
_______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
supply voltage
MIN
TYP
MAX
UNITS
0.7 x
DV
DD
DV
DD
UPIO_ Input High Voltage
V
V
0.7 x
CPOUT
CPOUT supply voltage
0.3 x
DV
supply voltage
DD
DV
DD
UPIO_ Input Low Voltage
0.3 x
CPOUT
CPOUT supply voltage
DV = 3.0V
Input Hysteresis
Input Current
V
200
0.01
10
mV
nA
pF
HYS
DD
I
V
V
V
= DGND or DV
= DGND or DV
(Note 7)
100
IN
IN
IN
IN
DD
DD
Input Capacitance
= DV
or CPOUT, pullup enabled
0.01
1
1
DD
UPIO_ Input Current
UPIO_ Pullup Current
µA
µA
V
= DV
or CPOUT or 0V,
IN
DD
pullup disabled
V
= 0V, pullup enabled, floating UPIO
IN
inputs are pulled up to DV
with pullup enabled
or CPOUT
0.5
2
5
DD
DIGITAL OUTPUTS (DOUT, RESET, UPIO_, CLK32K, INT, CLK)
Output Low Voltage
V
I
= 1mA
0.4
V
V
OL
SINK
= 500µA
SOURCE
0.8 x
Output High Voltage
V
I
OH
DV
DD
DOUT Tri-State Leakage Current
I
0.01
15
1
µA
pF
L
DOUT Tri-State Output
Capacitance
C
OUT
RESET Output Low Voltage
V
I
= 1mA
0.4
0.1
0.4
0.4
V
OL
SINK
RESET Output Leakage Current
Open-drain output, RESET deasserted
µA
I
I
I
= 1mA, UPIO_ referenced to DV
DD
SINK
SINK
UPIO_ Output Low Voltage
UPIO_ Output High Voltage
V
V
V
OL
= 4mA, UPIO_ referenced to CPOUT
= 500µA, UPIO_ referenced to
0.8 x
DV
SOURCE
DV
DD
DD
V
OH
I
= 4mA, UPIO_ referenced to
V
SOURCE
CPOUT
- 0.4
CPOUT
POWER REQUIREMENT
Analog Supply Voltage Range
Digital Supply Voltage Range
AV
DV
1.8
1.8
3.6
3.6
V
V
DD
DD
_______________________________________________________________________________________
9
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Everything on,
charge pump
unloaded, max
internal temp-sensor
current, clock output
buffers unloaded,
ADC at 512sps
AV
AV
= DV
= DV
= 3.6V
= 3.3V
1.36
2.0
DD
DD
DD
I
MAX
Total Supply Current
mA
1.15
1.17
1.7
1.3
DD
All on except charge pump and temp
sensor, ADC at 512sps, CLK output buffer
enabled, clock output buffers unloaded
I
NORMAL
AV
AV
AV
AV
= DV
= DV
= DV
= DV
= 3.0V
= 3.6V
= 3.0V
= 3.6V
5.18
6.15
4.42
5.56
6.5
9
DD
DD
DD
DD
DD
DD
DD
DD
T
= -45°C to +85°C
= +25°C
A
A
Sleep-Mode Supply Current
Shutdown Supply Current
I
µA
µA
SLEEP
5.19
8.3
4
T
T
A
A
= -40°C to +85°C
= +25°C
I
All off
SHDN
T
1.6
Note 1: Devices are production tested at T = +25°C and T = +85°C. Specifications to T = -40°C are guaranteed by design.
A
A
A
Note 2: Guaranteed by design or characterization.
Note 3: The offset and gain errors are corrected by self-calibration. The calibration process requires measurement to be made at
the selected data rate. The calibration error is therefore in the order of peak-to-peak noise for the selected rate.
Note 4: Eliminate drift errors by recalibration at the new temperature.
Note 5: The gain error excludes reference error, offset error (unipolar), and zero error (bipolar).
Note 6: Gain-error drift does not include unipolar offset drift or bipolar zero-error drift. It is effectively the drift of the part if zero-
scale error is removed.
Note 7: These specs are obtained from characterization during design or from initial product evaluation. Not production tested or
guaranteed.
Note 8: OUTA/B = +0.5V or +1.5V, SWA/B = +1.5V or +0.5V, T = 0°C to +50°C.
A
Note 9: Long-term stability is characterized using five to six parts. The bandgaps are turned on for 1000hrs at room temperature
with the parts running continuously. Daily measurements are taken and any obvious outlying data points are discarded.
Note 10: All of the stated temperature accuracies assume that 1) the external diode characteristic is precisely known (i.e., ideal)
and 2) the ADC reference voltage is exactly equal to 1.25V. Any variations to this known reference characteristic and volt-
age caused by temperature, loading, or power supply results in errors in the temperature measurement. The actual tem-
perature calculation is performed externally by the microcontroller (µC).
Note 11: Values based on simulation results and are not production tested or guaranteed.
10 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Table 1. Output Noise (Notes 12, 13, and 14)
OUTPUT NOISE (µV
)
RMS
RATE (sps)
GAIN = 1
1.820
GAIN = 2
GAIN = 4
1.345
GAIN = 8
0.660
10
40
3.286
3.257
3.845
1.928
0.630
50
3.065
2.317
1.631
0.625
60
2.873
2.662
1.519
0.728
200
240
400
512
4.525
2.910
1.397
0.519
6.502
2.954
1.596
0.629
5.300
80.068
282.959
1.686
0.436
119.078
281.056
28.470
Note 12: V
= 1.25V, bipolar mode, V = 1.24912, PGA gain = 1, T = +85°C.
IN A
REF
Note 13: C = 5pF, op-amp noise is considered to be the same as the switching noise. The increase of the op amp’s noise contri-
IN
bution is due to large input swing (0 to 3.6V).
Note 14: Assume 3 sigma peak-to-peak variation; noise-free resolution means no code flicker at given bits’ LSB.
Table 2. Peak-to-Peak Resolution
PEAK-TO-PEAK RESOLUTION (Bits)
RATE (sps)
GAIN = 1
16.7
GAIN = 2
14.8
14.8
15.3
15.1
15.0
15.0
10.2
8.4
GAIN = 4
15.1
14.6
14.8
14.9
15.0
14.9
14.8
7.4
GAIN = 8
15.1
15.2
15.2
15.0
15.5
15.2
15.7
9.7
10
40
15.6
50
15.9
60
16.0
200
240
400
512
15.4
14.8
15.1
10.6
Table 3. Maximum External Source Impedance Without 16-Bit Gain Error
EXTERNAL CAPACITANCE (pF)
PARAMETER
0 (Note 15)
350
50
60
100
30
500
10
1000
4
5000
Resistance (kΩ)
1
Note 15: 2pF parasitic capacitance is assumed, which represents pad and any other parasitic capacitance.
______________________________________________________________________________________ 11
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
TIMING CHARACTERISTICS (Figures 1 and 21)
(AV
= DV
= +1.8V to +3.6V, external V
= +1.25V, CLK32K = 32.768kHz (external clock), C = 10µF, C
= 10µF,
DD
DD
REF
REG
CPOUT
10µF between CF+ and CF-, T = T
A
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
MIN
PARAMETER
SCLK Operating Frequency
SCLK Cycle Time
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
MHz
ns
f
10
SCLK
t
100
40
40
30
0
CYC
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
t
ns
CH
t
t
ns
CL
DS
DH
DO
ns
DIN to SCLK Hold
t
ns
SCLK Fall to DOUT Valid
CS Fall to Output Enable
CS Rise to DOUT Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
t
C = 50pF, Figure 2
40
48
48
ns
L
t
C = 50pF, Figure 2
ns
DV
L
t
C = 50pF, Figure 2
L
ns
TR
t
20
0
ns
CSS
CSH
t
ns
t
DV
Monitor Timeout Period
(Note 16)
1.5
1
s
DD
DSLP
Minimum pulse width required to detect a
wake-up event
t
Wake-Up (WU) Pulse Width
Shutdown Delay
µs
µs
ms
µs
WU
The delay for SHDN to go high after a valid
wake-up event
t
1
DPU
The turn-on time for the high-frequency
clock and FLL (FLLE = 1) (Note 17)
10
10
t
HFCK Turn-On Time
DFON
If FLLE = 0, the turn-on time for the high-
frequency clock (Note 18)
The delay for CRDY to go low after the
HFCK clock output has been enabled
(Note 19)
t
CRDY to INT Delay
7.82
ms
DFI
The delay after a shutdown command has
asserted and before HFCK is disabled
(Note 20)
t
HFCK Disable Delay
1.95
2.93
ms
ms
DFOF
t
SHDN Assertion Delay
(Note 21)
DPD
Note 16: The delay for the sleep voltage monitor output, RESET, to go high after V
rises above the reset threshold. This is largely
DD
driven by the startup of the 32kHz oscillator.
Note 17: It is gated by an AND function with three inputs—the external RESET signal, the internal DV
monitor output, and the
DD
external SHDN signal. The time delay is timed from the internal LOV
going high or the external RESET going high,
DD
whichever happens later. HFCK always starts in the low state.
Note 18: If FLLE = 0, the internal signal CRDY is not generated by the FLL block and INT or INT are deasserted.
Note 19: CRDY is used as an interrupt signal to inform the µC that the high-frequency clock has started. Only valid if FLLE = 1.
t
t
Note 20:
Note 21:
gives the µC time to clean up and go into sleep-override mode properly.
is greater than the HFCK delay for the MAX1358/MAX1359/MAX1360 chip to clean up before losing power.
DFOF
DPD
12 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
CS
t
t
t
t
CSH
CSH
CYC
CH
t
CSS
t
CL
SCLK
DIN
t
t
DH
DS
t
t
t
TR
DV
DO
DOUT
Figure 1. Detailed Serial-Interface Timing
DV
DD
6kΩ
DOUT
DOUT
6kΩ
C
= 50pF
C
= 50pF
LOAD
LOAD
a) FOR ENABLE, HIGH IMPEDANCE
TO V AND V TO V
b) FOR ENABLE, HIGH IMPEDANCE
TO V AND V TO V
OH
OL
OH
OL
OH
OL
FOR DISABLE, V TO HIGH IMPEDANCE
FOR DISABLE, V TO HIGH IMPEDANCE
OH
OL
Figure 2. DOUT Enable and Disable Time Load Circuits
Typical Operating Characteristics
(DV
= AV = 1.8V, REF = +1.25V C
DD
= 10µF, T = +25°C, unless otherwise noted.)
A
CPOUT
DD
DV SUPPLY CURRENT
DD
DV SUPPLY CURRENT
DD
DV SUPPLY CURRENT
DD
vs. DV SUPPLY VOLTAGE
vs. DV SUPPLY VOLTAGE
vs. DV SUPPLY VOLTAGE
DD
DD
DD
1.0
0.8
0.6
0.4
0.2
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
700
SLEEP MODE,
ALL FUNCTIONS DISABLED
SLEEP MODE, CLK BUFFER DISABLED
NORMAL MODE
CLK BUFFER DISABLED
32kHz OSC, RTC, DV MONITOR ENABLED
DD
600
500
400
300
200
1.8
2.1
2.4
2.7
DV (V)
3.0
3.3
3.6
1.8
2.1
2.4
2.7
DV (V)
3.0
3.3
3.6
1.8
2.1
2.4
2.7
DV (V)
3.0
3.3
3.6
DD
DD
DD
______________________________________________________________________________________ 13
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, REF = +1.25V C
= 10µF, T = +25°C, unless otherwise noted.)
A
CPOUT
DD
DD
DV SUPPLY CURRENT
DD
vs. TEMPERATURE
DV SUPPLY CURRENT
DD
vs. TEMPERATURE
DV SUPPLY CURRENT
DD
vs. TEMPERATURE
700
600
500
400
300
200
1.0
0.8
0.6
0.4
0.2
0
3.0
2.5
2.0
1.5
1.0
0.5
0
SLEEP MODE, CLK BUFFER DISABLED
NORMAL MODE
CLK BUFFER DISABLED
SLEEP MODE, ALL
FUNCTIONS DISABLED
32kHz OSC, RTC, DV MONITOR ENABLED
DD
DV = 3.0V
DD
DV = 3.0V
DD
DV = 3.0V
DD
DV = 1.8V
DD
DV = 1.8V
DD
DV = 1.8V
DD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
3.6
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
AV SUPPLY CURRENT
DD
AV SUPPLY CURRENT
DD
vs. AV SUPPLY VOLTAGE
AV SUPPLY CURRENT
DD
vs. AV SUPPLY VOLTAGE
vs. AV SUPPLY VOLTAGE
DD
DD
DD
450
425
400
375
350
325
300
275
250
4.0
3.5
3.0
2.5
2.0
1.5
2.0
1.8
1.6
1.4
1.2
1.0
NORMAL MODE
SLEEP MODE,
32kHz OSC, RTC, DV MONITOR ENABLED
SLEEP MODE,
ALL FUNCTIONS DISABLED
DD
1.8
2.1
2.4
2.7
AV (V)
3.0
3.3
3.6
1.8
2.1
2.4
2.7
AV (V)
3.0
3.3
1.8
2.1
2.4
2.7
AV (V)
3.0
3.3
3.6
DD
DD
DD
AV SUPPLY CURRENT
DD
vs. TEMPERATURE
AV SUPPLY CURRENT
DD
vs. TEMPERATURE
AV SUPPLY CURRENT
DD
vs. TEMPERATURE
2.0
1.8
1.6
1.4
1.2
1.0
400
375
350
325
300
275
250
225
200
4.0
3.5
3.0
2.5
2.0
1.5
1.0
SLEEP MODE, ALL
FUNCTIONS DISABLED
NORMAL MODE
SLEEP MODE,
32kHz OSC, RTC, DV MONITOR ENABLED
DD
AV = 3.0V
DD
AV = 3.0V
DD
AV = 3.0V
DD
AV = 1.8V
DD
AV = 1.8V
DD
AV = 1.8V
DD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
14 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, REF = +1.25V C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
CPOUT
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
REFERENCE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.60
3.0
2.5
2.0
1.5
1.0
A: V = 1.25V
REF
B: V = 2.048V
2.55
REF
FLL DISABLED
C: V = 2.5V
REF
C
2.50
2.45
C
FLL ENABLED
2.40
B
B
2.35
2.30
A
A
2.25
CLK = 2.4576MHz
CLK = 2.4576MHz
2.20
-40
-15
10
TEMPERATURE (°C)
A: FLL DISABLED; AV , DV = 1.8V
35
60
85
1.8
2.1
2.4
2.7
3.0
3.3
3.6
1.8
2.1
2.4
2.7
AV (V)
3.0
3.3
3.6
AV , DV (V)
DD
DD
DD
DD
DD
B: FLL ENABLED
C: FLL DISABLED; AV , DV = 3.0V
DD
DD
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
2.5050
2.5048
2.5046
2.5044
2.5042
2.5040
2.5038
2.5036
2.5034
2.5032
2.5030
2.0486
2.0484
2.0482
2.0480
2.0478
2.0476
2.0474
2.0472
1.2510
1.2505
1.2500
1.2495
1.2490
AV = 2.5V
DD
AV = 3.0V
DD
AV = 1.8V
DD
V
= 2.048V
V
= 2.5V
REF
V
= 1.25V
REF
REF
-50
50
150
250
350
450
-50
50
150
250
350
450
-50
50
150
250
350
450
OUTPUT CURRENT (µA)
OUTPUT CURRENT (µA)
OUTPUT CURRENT (µA)
NORMALIZED REFERENCE OUTPUT
VOLTAGE vs. TEMPERATURE
NORMALIZED REFERENCE OUTPUT
VOLTAGE vs. TEMPERATURE
NORMALIZED REFERENCE OUTPUT
VOLTAGE vs. TEMPERATURE
1.0010
1.0005
1.0000
0.9995
0.9990
0.9985
0.9980
0.9975
0.9970
1.0010
1.0005
1.0000
0.9995
0.9990
0.9985
0.9980
0.9975
0.9970
1.0010
1.0005
1.0000
0.9995
0.9990
0.9985
0.9980
0.9975
0.9970
V
= 1.25V
-15
V
= 2.048V
-15
V
REF
= 2.5V
-15
REF
REF
-40
10
35
60
85
-40
10
35
60
85
-40
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________________________________ 15
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, REF = +1.25V C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
CPOUT
REFERENCE VOLTAGE OUTPUT NOISE
REFERENCE VOLTAGE OUTPUT
NOISE vs. FREQUENCY
10,000
REFERENCE VOLTAGE OUTPUT
NOISE vs. FREQUENCY
(0.1Hz TO 10Hz)
MAX1358/59/60 toc22
10,000
1000
100
V
= 1.25V
V
= 2.048V
REF
REF
1000
50µV/div
V
= +1.25V
REF
AV = +1.8V
DD
100
1
10
100
1k
10k
1
10
100
1k
10k
1s/div
FREQUENCY (Hz)
FREQUENCY (Hz)
REFERENCE VOLTAGE OUTPUT
NOISE vs. FREQUENCY
ADC MUX INPUT DC CURRENT
vs. TEMPERATURE
DAC INL vs. OUTPUT CODE
10,000
1000
100
2
0.25
0.15
V
= 2.5V
REF
AV = 1.8V
AV = 1.8V
DD
DD
V
= 1.25V
V
= 0.5V
REF
AIN
0
-2
0.05
-4
-6
-0.05
-0.15
-0.25
-8
-10
-12
1
10
100
1k
10k
-40
-15
10
35
60
85
0
200
400
600
800
1000
FREQUENCY (Hz)
TEMPERATURE (°C)
OUTPUT CODE
DAC INL vs. OUTPUT CODE
DAC INL vs. OUTPUT CODE
DAC DNL vs. OUTPUT CODE
0.20
0.15
0.10
0.05
0
0.25
0.15
0.25
0.15
AV = 2.5V
AV = 3.0V
DD
DD
V
= 2.048V
V
= 2.5V
REF
REF
0.05
0.05
-0.05
-0.15
-0.25
-0.05
-0.15
-0.25
-0.05
-0.10
-0.15
-0.20
AV = 1.8V
DD
V
= 1.25V
REF
0
200
400
600
800
1000
0
200
400
600
800
1000
0
200
400
600
800
1000
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
16 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, REF = +1.25V C
DD
= 10µF, T = +25°C, unless otherwise noted.)
DD
A
CPOUT
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
DAC DNL vs. OUTPUT CODE
DAC DNL vs. OUTPUT CODE
1.248
1.246
1.244
1.242
1.240
0.20
0.20
0.15
0.10
0.05
0
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.05
-0.10
AV = 2.5V
DD
AV = 3.0V
CODE = 3FF hex
AV = 1.8V, 3.0V
DD
DD
-0.15
V
= 2.048V
V
= 2.5V
REF
REF
-0.20
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
SOURCE CURRENT (mA)
0
200
400
600
800
1000
0
200
400
600
800
1000
OUTPUT CODE
OUTPUT CODE
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
DAC OUTPUT VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
DAC OUTPUT VOLTAGE
vs. TEMPERATURE
0.30
0.25
0.20
0.15
0.10
0.05
0
650
640
630
620
610
630
628
626
624
622
620
AV = 1.8V
DD
AV = 1.8V
DD
AV = 3.0V
DD
AV = 3.0V
DD
V
= 1.25V
REF
CODE = 200 hex
3.0 3.3 3.6
CODE = 020 hex
CODE = 200 hex
600
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
SOURCE CURRENT (mA)
1.8
2.1
2.4
2.7
-40
-15
10
35
60
85
AV (V)
DD
TEMPERATURE (°C)
DAC OUTPUT NOISE
(0.1Hz TO 10Hz)
DAC OUTPUT
NOISE vs. FREQUENCY
DAC FBA/B INPUT BIAS CURRENT
vs. TEMPERATURE
MAX1358/59/60 toc38
10,000
1000
100
2
1
DAC CODE = 3FF hex
= 2.5V
AV = 1.8V
DD
V
REF
V
= 0.5V
AIN
0
-1
-2
-3
-4
-5
50µV/div
AV = +1.8V
DD
V
= +1.25V
REF
DAC CODE = 3FF hex
1
10
100
FREQUENCY (Hz)
1k
10k
1s/div
-40
-15
10
35
60
85
TEMPERATURE (°C)
______________________________________________________________________________________ 17
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, REF = +1.25V C
= 10µF, T = +25°C, unless otherwise noted.)
A
CPOUT
DD
DD
DAC LARGE-SIGNAL OUTPUT
STEP RESPONSE
OP-AMP INPUT OFFSET VOLTAGE
vs. TEMPERATURE
MAX1358/59/60 toc40
7.5
7.2
6.9
6.6
6.3
6.0
V
= 0.5V
CM
CS
2V/div
AV = 3.0V
DD
AV = 1.8V
DD
OUT_
1V/div
V
= +1.25V
DD
REF
AV = +3.0V
40µs/div
-40
-15
10
35
60
85
TEMPERATURE (°C)
OP-AMP INPUT BIAS CURRENT
vs. TEMPERATURE
OP-AMP INPUT BIAS CURRENT
vs. TEMPERATURE
14
12
10
8
12
10
8
AV = 1.8V
DD
AV = 3.0V
DD
V
= 0.5V
V
= 0.5V
CM
CM
6
6
4
4
2
2
0
0
-2
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
OP-AMP OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
OP-AMP OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
250
200
150
100
50
3.00
2.96
2.92
2.88
2.84
2.80
AV = 3.0V
DD
AV = 1.8V
DD
AV = 3.0V
DD
UNITY GAIN, V + = AV
UNITY GAIN, V + = 0V
IN_
IN_
DD
0
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
SINK CURRENT (mA)
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
SOURCE CURRENT (mA)
18 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, REF = +1.25V C
= 10µF, T = +25°C, unless otherwise noted.)
A
CPOUT
DD
DD
OP-AMP OUTPUT VOLTAGE
vs. TEMPERATURE
OP-AMP OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
501.0
500.8
500.6
500.4
500.2
500.0
1.80
1.75
1.70
1.65
1.60
UNITY GAIN, V + = 0.5V
IN_
R = 10kΩ
L
AV = 3.0V
DD
AV = 1.8V
DD
UNITY GAIN, V + = AV
IN_
DD
AV = 1.8V
DD
-40
-15
10
35
60
85
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
SOURCE CURRENT (mA)
TEMPERATURE (°C)
OP-AMP OUTPUT NOISE
vs. FREQUENCY
OP-AMP OUTPUT VOLTAGE
vs. AV SUPPLY VOLTAGE
DD
10,000
1000
100
501.0
500.8
500.6
500.4
500.2
500.0
UNITY GAIN, V + = 0.5V
IN_
UNITY GAIN, V + = 0.5V
IN_
R = 10kΩ
L
1
10
100
1k
10k
1.8
2.1
2.4
2.7
AV (V)
3.0
3.3
3.6
FREQUENCY (Hz)
DD
SPDT ON-RESISTANCE
vs. V VOLTAGE
SPST ON-RESISTANCE
vs. V VOLTAGE
COM
COM
75
65
55
45
35
25
150
130
110
90
AV = 3.0V
DD
AV = 3.0V
DD
AV = 1.8V
DD
70
AV = 1.8V
DD
50
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
V
(V)
COM
COM
______________________________________________________________________________________ 19
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, REF = +1.25V C
= 10µF, T = +25°C, unless otherwise noted.)
A
CPOUT
DD
DD
SPDT ON-RESISTANCE
vs. TEMPERATURE
SPST ON-RESISTANCE
vs. TEMPERATURE
45
42
39
36
33
30
100
97
94
91
88
85
82
AV = 1.8V, 3.0V
I
= 1mA
DD
COM
COM
I
= 1mA
AV = 3.0V
DD
AV = 1.8V
DD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
SPDT/SPST SWITCHING TIME
SPDT/SPST ON/OFF-LEAKAGE
CURRENT vs. TEMPERATURE
vs. AV SUPPLY VOLTAGE
DD
45
40
35
30
25
20
15
100
AV = 1.8V
DD
V
= 0V
CM
ON-LEAKAGE
10
1
t
ON
OFF-LEAKAGE
t
OFF
0.1
1.8
2.1
2.4
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
AV (V)
DD
TEMPERATURE (°C)
SPDT/SPST SWITCHING TIME
vs. TEMPERATURE
SPDT/SPST SWITCHING TIME
vs. TEMPERATURE
50
35
31
27
23
19
15
AV = 1.8V
DD
AV = 3.0V
DD
t
46
42
38
34
30
ON
t
ON
t
OFF
t
OFF
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
20 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, REF = +1.25V C
= 10µF, T = +25°C, unless otherwise noted.)
A
CPOUT
DD
DD
CHARGE-PUMP OUTPUT VOLTAGE
vs. OUTPUT CURRENT
VOLTAGE SUPERVISOR THRESHOLD
vs. TEMPERATURE
3.6
3.5
3.4
3.3
3.2
3.1
3.0
0.10
0.05
0
DV SUPERVISOR
DD
-0.05
-0.10
-0.15
-0.20
CPOUT SUPERVISOR
DV = 1.8V
DD
0
2
4
6
8
10
-40
-40
0
-15
10
35
60
85
85
10
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
CHARGE-PUMP OUTPUT RESISTANCE
vs. CAPACITANCE
CHARGE-PUMP OUTPUT VOLTAGE
vs. TEMPERATURE
100
80
60
40
20
0
3.30
3.26
3.22
3.18
3.14
3.10
DV = 3.0V
DD
DV = 1.8V
DD
DV = 1.8V
DD
I
= 10mA
I
= 10mA
-15
OUT
OUT
0
4
8
12
16
20
10
35
60
C (µF)
TEMPERATURE (°C)
F
CHARGE-PUMP OUTPUT
VOLTAGE RIPPLE
CHARGE-PUMP OUTPUT VOLTAGE
RIPPLE vs. OUTPUT CURRENT
MAX1358/59/60 toc63
50
40
30
20
10
0
DV = 1.8V
DD
CPOUT
20mV/div
AC-COUPLED
DV = +1.8V
DD
I
= 10mA
LOAD
20µs/div
2
4
6
8
OUTPUT CURRENT (mA)
______________________________________________________________________________________ 21
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Pin Description
PIN
NAME
CLK
FUNCTION
MAX1358 MAX1359 MAX1360
1
1
1
Clock Output. Default is 2.457MHz output clock for µC.
User-Programmable Input/Output 2. See the UPIO2_CTRL Register section for
functionality.
2
2
2
UPIO2
User-Programmable Input/Output 3. See the UPIO3_CTRL Register section for
functionality.
3
4
3
4
3
4
UPIO3
UPIO4
User-Programmable Input/Output 4. See the UPIO4_CTRL Register section for
functionality.
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance
when CS is high, when UPIO/SPI passthrough mode is enabled, DOUT mirrors the
state of UPIO1.
5
5
5
DOUT
6
7
6
7
6
7
SCLK
DIN
Serial-Clock Input. Clocks data in and out of the serial interface.
Serial-Data Input. Data is clocked in on SCLK’s rising edge.
Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When
CS is high, DOUT is high impedance. High impedance when CS is high, when
UPIO/SPI passthrough mode is enabled, DOUT mirrors the state of UPIO1.
8
9
8
9
8
9
CS
Programmable Active-High/Low Interrupt Output. ADC, UPIO wake-up, alarm, and
voltage-monitor events.
INT
32kHz Clock Input/Output. Outputs 32kHz clock for µC. Can be programmed as
an input by enabling the IO32E bit to accept an external 32kHz input clock. The
RTC, PWM, and watchdog timer always use the internal 32kHz clock derived from
the 32kHz crystal.
10
11
10
11
10
11
CLK32K
Active-Low Open-Drain Reset Output. Remains low while DV
is below the 1.8V
DD
voltage threshold and stays low for a timeout period (t
) after DV
rises above
DSLP
DD
RESET
the 1.8V threshold. RESET also pulses low when the watchdog timer times out and
holds low during POR until the 32kHz oscillator stabilizes.
32kHz Crystal Output. Connect external 32kHz watch crystal between 32KIN and
32KOUT.
12
13
12
13
12
13
32KOUT
32KIN
32kHz Crystal Input. Connect external 32kHz watch crystal between 32KIN and
32KOUT.
14
15
16
17
18
19
20
21
22
23
24
14
15
16
17
18
19
20
21
22
23
24
14
15
16
17
18
19
20
21
22
—
—
SNO1
SCM1
SNC1
SNO2
SCM2
SNC2
OUT1
IN1-
Analog Switch 1 Normally Open Terminal. Analog input to mux.
Analog Switch 1 Common Terminal. Analog input to mux.
Analog Switch 1 Normally Closed Terminal. Analog input to mux (open on POR).
Analog Switch 2 Normally Open Terminal. Analog input to mux.
Analog Switch 2 Common Terminal. Analog input to mux (open on POR).
Analog Switch 2 Normally Closed Terminal. Analog input to mux.
Amplifier 1 Output. Analog input to mux.
Amplifier 1 Inverting Input. Analog input to mux.
IN1+
SWA
Amplifier 1 Noninverting Input
DACA SPST Shunt Switch Input. Connects to OUTA through a SPST switch.
DACA Force-Sense Feedback Input. Analog input to mux.
FBA
22 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1358 MAX1359 MAX1360
25
26
25
26
—
OUTA
AGND
DACA Force-Sense Output. Analog input to mux.
Analog Ground
26
Analog Supply Voltage. Also ADC reference voltage during AV
measurement.
DD
Bypass to AGND with 10µF and 0.1µF capacitors in parallel as close to the pin as
possible.
27
27
27
AV
DD
28
29
30
—
—
—
—
—
—
SWB
FBB
DACB SPST Shunt Switch Input. Connects to OUTB through an SPST switch.
DACB Force-Sense Feedback Input. Analog input to mux.
Force-Sense DACB Ouput. Analog input to mux.
OUTB
Analog Input 2. Analog input to mux. Inputs have internal programmable current
source for external temperature measurement.
31
32
31
32
31
32
AIN2
AIN1
Analog Input 1. Analog input to mux. Inputs have internal programmable current
source for external temperature measurement.
Reference Input/Output. Output of the reference buffer amplifier or external
reference input. Disabled at power-up to allow external reference. Reference
voltage for ADC and DACs.
33
33
33
REF
Linear Voltage-Regulator Output. Charge-pump-doubler input voltage. Bypass
REG with a 10µF capacitor to DGND for charge-pump regulation.
34
34
34
REG
35
36
35
36
35
36
CF-
Charge-Pump Flying Capacitor Terminals. Connect an external 10µF (typ)
capacitor between CF+ and CF-.
CF+
Charge-Pump Output. Connect an external 10µF (typ) reservoir capacitor between
CPOUT and DGND. There is a low threshold diode between DV and CPOUT. When
DD
37
37
37
CPOUT
the charge pump is disabled, CPOUT is pulled up within 300mV (typ) of DV
.
DD
Digital Supply Voltage. Bypass to DGND with 10µF and 0.1µF capacitors in parallel
as close to the pin as possible.
38
39
38
39
38
39
DV
DD
Digital Ground. Also ground for cascaded linear voltage regulator and charge-
pump doubler.
DGND
40
—
—
—
—
—
—
—
40
—
—
—
28
29
30
—
40
23
24
25
28
29
30
—
UPIO1
IN3+
IN3-
User-Programmable Input/Output 1. See the UPIO1_CTRL Register for functionality.
Amplifier 3 Noninverting Input
Amplifier 3 Inverting Input. Analog input to mux.
Amplifier 3 Output. Analog input to mux.
OUT3
IN2+
IN2-
Amplifier 2 Noninverting Input
Amplifier 2 Inverting Input. Analog input to mux.
Amplifier 2 Output. Analog input to mux.
OUT2
EP
Exposed Pad. Leave unconnected or connect to AGND.
______________________________________________________________________________________ 23
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
The DAS directly interfaces to various sensor outputs
Detailed Description
and, once configured, provides the stimulus, signal
The MAX1358/MAX1359/MAX1360 DAS feature a multi-
conditioning, and data conversion, as well as µP sup-
plexed differential 16-bit ADC, 10-bit force-sense
port. See the Applications section for sample
DACs, an RTC with an alarm, a selectable bandgap
MAX1358/MAX1359/MAX1360 applications.
voltage reference, a signal-detect comparator, 1.8V
The 16-bit ADC features programmable continuous con-
version rates as shown in Table 4, and gains of 1, 2, 4,
and 8 (Table 5) to suit applications with different power
and 2.7V voltage monitors, and wake-up control
circuitry, all controlled by a 4-wire serial interface. (See
Figures 3, 4, and 5 for the functional diagrams).
INT
CLK32K
32KOUT
CLK
AV
DD
32KIN
DV
DD
4.9152MHz HF
OSCILLATOR
AND FLL
CLK32K
INPUT/OUTPUT
CONTROL
M32K
CS
SCLK
DIN
32.768kHz
UPIO1
INTERRUPT
16
OSCILLATOR
UPIO2
UPIO3
UPIO4
SERIAL
INTERFACE
UPIO
HFCLK
4
4
32K
UPR<4:1>
CRDY
CONTROL
LOGIC
PWM
UPF<4:1>
DOUT
STATUS
RTC AND
ALARM
ALD
SDC
ADD
ADOU
WATCHDOG
TIMER
DV (1.8V)
DD
VOLTAGE
MONITOR
RESET
LDVD
LCPD
WDTO
AIN1
AIN2
TEMP
PROG
CURRENT
SOURCE
CPOUT (2.7V)
VOLTAGE
MONITOR
CPOUT
CF+
CF-
TEMP+
TEMP-
CHARGE-
PUMP
DOUBLER
DV
M32K
DD
SENSOR
MAX1358
LINEAR 1.65V
VOLTAGE
REGULATOR
REG
AIN1
SNO1
FBA
SCM1
FBB
SNC1
AIN1
AIN2
M32K
PROG. Vos
PGA
1.25V BANDGAP
REF
10:1
MUX
POS
CMP
Av = 1, 1.6384, 2 V/V
INM1
TEMP+
REF
SNO1
SNC1
SCM1
REF
REF
10-BIT DAC
AGND
IN+
OUTA
SWA
FBA
BUF
HFCLK
16-BIT ADC
IN-
PGA
Av = 1, 2, 4, 8 V/V
TEMP-
SNO2
OUTA
SCM2
OUTB
SNC2
OUT1
AIN2
SPDT1
POLARITY
FLIPPER
REF
SNO2
SNC2
SCM2
10:1
MUX
NEG
10-BIT DAC
OUTB
BUF
OP1
SWB
FBB
REF
SPDT2
AGND
IN1+
IN1-
OUT1
DGND
AGND
Figure 3. MAX1358 Functional Diagram
24 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
and dynamic range constraints. The force-sense DACs
provide 10-bit resolution for precise sensor applica-
tions. The ADCs and DACs both utilize a low-drift 1.25V
internal bandgap reference for conversions and full-
scale range setting. The RTC has a 138-year range and
provides an alarm function that can be used to wake up
the system or cause an interrupt at a predefined time.
RESET. The MAX1358/MAX1359/MAX1360 use a 4-wire
serial interface to communicate directly between SPI,
QSPI, or MICROWIRE devices for system configuration
and readback functions.
Analog-to-Digital Converter (ADC)
The MAX1358/MAX1359/MAX1360 include a sigma-
delta ADC with programmable conversion rate, a PGA,
and a dual 10:1 input mux. When performing continu-
The power-supply voltage monitor detects when DV
DD
falls below a trip threshold voltage of +1.8V, asserting
INT
CLK32K
32KOUT
CLK
AV
DD
32KIN
DV
DD
4.9152MHz HF
OSCILLATOR
AND FLL
CLK32K
INPUT/OUTPUT
CONTROL
M32K
32.768kHz
OSCILLATOR
CS
SCLK
DIN
UPIO1
INTERRUPT
16
UPIO2
UPIO3
UPIO4
SERIAL
INTERFACE
UPIO
HFCLK
4
4
UPR<4:1>
32K
CONTROL
LOGIC
CRDY
PWM
UPF<4:1>
DOUT
STATUS
RTC AND
ALARM
ALD
SDC
ADD
ADOU
WATCHDOG
TIMER
DV (1.8V)
DD
VOLTAGE
MONITOR
RESET
LDVD
LCPD
WDTO
AIN1
AIN2
TEMP
PROG
CURRENT
SOURCE
CPOUT (2.7V)
VOLTAGE
MONITOR
CPOUT
CF+
CF-
TEMP+
TEMP-
CHARGE-
PUMP
DOUBLER
DV
M32K
DD
SENSOR
MAX1359
LINEAR 1.65V
VOLTAGE
REGULATOR
REG
AIN1
SNO1
FBA
SCM1
IN2-
SNC1
AIN1
AIN2
M32K
PROG. Vos
PGA
1.25V BANDGAP
REF
10:1
MUX
POS
CMP
Av = 1, 1.6384, 2 V/V
INM1
TEMP+
REF
SNO1
SNC1
SCM1
REF
REF
10-BIT DAC
AGND
IN+
OUTA
SWA
FBA
BUF
HFCLK
16-BIT ADC
IN-
PGA
Av = 1, 2, 4, 8 V/V
TEMP-
SNO2
OUTA
SCM2
OUT2
SNC2
OUT1
AIN2
SPDT1
POLARITY
FLIPPER
SNO2
SNC2
SCM2
10:1
MUX
NEG
OUT2
OP2
OP1
SPDT2
REF
AGND
IN2+
IN2-
IN1+
IN1-
OUT1
AGND
DGND
Figure 4. MAX1359 Functional Diagram
______________________________________________________________________________________ 25
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ous conversions at 10sps or single conversions at the
40sps setting (effectively 10sps due to four sample
sigma-delta settling), the ADC has 16-bit noise-free res-
olution. The noise-free resolution drops to 10 bits at the
maximum sampling rate of 512sps. Differential inputs
ADOU bit in the status register indicates if the ADC has
over-ranged or under-ranged.
Zero-scale and full-scale calibrations remove offset and
gain errors. Direct access to gain and zero-scale cali-
bration registers allows system-level offset and gain cal-
ibration. The zero-scale adjustment register allows
intentional positive offset skewing to preserve unipolar-
mode resolution for signals that have a slight negative
support unipolar (between 0 and V
) and bipolar
REF
(between
V
) modes of operation. Note: Avoid
REF
combinations of input signal and PGA gains that
exceed the reference range at the ADC input. The
INT
CLK32K
32KOUT
CLK
AV
DD
32KIN
DV
DD
4.9152MHz HF
OSCILLATOR
AND FLL
CLK32K
INPUT/OUTPUT
CONTROL
M32K
32.768kHz
OSCILLATOR
CS
SCLK
DIN
UPIO1
INTERRUPT
16
UPIO2
UPIO3
UPIO4
SERIAL
INTERFACE
UPIO
HFCLK
4
4
UPR<4:1>
CRDY
32K
CONTROL
LOGIC
PWM
UPF<4:1>
DOUT
STATUS
RTC AND
ALARM
ALD
SDC
ADD
ADOU
WATCHDOG
TIMER
DV (1.8V)
DD
VOLTAGE
MONITOR
RESET
LDVD
LCPD
WDTO
AIN1
AIN2
TEMP
PROG
CURRENT
SOURCE
CPOUT (2.7V)
VOLTAGE
MONITOR
CPOUT
CF+
CF-
TEMP+
TEMP-
CHARGE-
PUMP
DOUBLER
DV
M32K
DD
SENSOR
MAX1360
LINEAR 1.65V
VOLTAGE
REGULATOR
REG
AIN1
SNO1
IN3-
SCM1
IN2-
SNC1
AIN1
AIN2
M32K
PROG. Vos
PGA
1.25V BANDGAP
REF
10:1
MUX
POS
CMP
Av = 1, 1.6384, 2 V/V
INM1
TEMP+
REF
SNO1
SNC1
SCM1
IN3+
REF
AGND
IN+
HFCLK
16-BIT ADC
IN-
PGA
Av = 1, 2, 4, 8 V/V
OUT3
IN3-
OP3
TEMP-
SNO2
OUT3
SCM2
OUT2
SNC2
OUT1
AIN2
SPDT1
POLARITY
FLIPPER
SNO2
SNC2
SCM2
10:1
MUX
NEG
OUT2
OP2
OP1
SPDT2
REF
AGND
IN2+
IN2-
IN1+
IN1-
OUT1
AGND
DGND
Figure 5. MAX1360 Functional Diagram
26 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
offset (i.e., unipolar clipping near zero can be removed).
Perform ADC calibration whenever the ADC configura-
Figures 3, 4, and 5 illustrate which signals are present at
the inputs of each mux for the MAX1358/MAX1359/
MAX1360. The MUXP[3:0] and MUXN[3:0] bits of the mux
register select the input to the ADC and the signal-detect
comparator (Tables 8 and 9). See the mux register
description in the Register Definitions section for multi-
plexer functionality. The POL bit of the ADC register
swaps the polarity of mux output signals to the ADC.
tion, temperature, or AV
changes. The ADC-done sta-
DD
tus can be programmed to provide an interrupt on INT
or on any UPIO_.
PGA Gain
An integrated PGA provides four selectable gains: +1V/V,
+2V/V, +4V/V, and +8V/V to maximize the dynamic range
of the ADC. Bits GAIN1 and GAIN0 set the gain (see the
ADC Register for more information). The PGA gain is
implemented in the digital filter of the ADC.
Digital Filtering
The MAX1358/MAX1359/MAX1360 contain an on-chip
digital lowpass filter that processes the data stream
from the modulator using a SINC4 (sinx/x)4 response.
The SINC4 filter has a settling time of four output data
periods (4 x 200ms).
ADC Modulator
The MAX1358/MAX1359/MAX1360 perform analog-to-
digital conversions using a single-bit, 3rd-order,
switched-capacitor sigma-delta modulator. The sigma-
delta modulation converts the input signal into a digital
pulse train whose average duty cycle represents the dig-
itized signal information. The pulse train is then
processed by a digital decimation filter. The modulator
provides 2nd-order frequency shaping of the quantiza-
tion noise resulting from the single-bit quantizer. The
modulator is fully differential for maximum signal-to-noise
ratio and minimum susceptibility to power-supply noise.
The MAX1358/MAX1359/MAX1360 have 25% overrange
capability built into the modulator and digital filter:
4
f
SIN Nπ
f
1
N
m
H(f) =
f
SIN π
f
m
Figure 6 shows the filter frequency response. The
SINC4 characteristic -3dB cutoff frequency is 0.228
times the first notch frequency.
Signal-Detect Comparator
INT asserts (and remains asserted) within 30µs when
the differential voltage on the selected analog inputs
exceeds the signal-detect comparator trip threshold.
The signal-detect comparator’s differential input trip
threshold (i.e., offset) is user selectable and can be pro-
grammed to the following values: 0mV, 50mV, 100mV,
150mV, or 200mV.
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. The notches of the SINC4 filter are
repeated at multiples of the first notch frequency. The
SINC4 filter provides an attenuation of better than
100dB at these notches. For example, 50Hz is equal to
five times the first notch frequency and 60Hz is equal to
six times the first notch frequency.
Analog Inputs
The ADC provides two external analog inputs: AIN1
and AIN2. The rail-to-rail inputs accept differential or
single-ended voltages, or external temperature-sensing
diodes. The unused op amps, switches, or DAC inputs
and output pins can also be used as rail-to-rail analog
inputs if the associated function is disabled.
0
-40
Analog Input Protection
-80
Internal protection diodes clamp the analog inputs to
AV
and AGND, and allow the channel input to swing
DD
-120
-160
-200
from (AGND - 0.3V) to (AV
+ 0.3V). For accurate
DD
conversions near full scale, the inputs must not exceed
AV by more than 50mV or be lower than AGND by
50mV. If the inputs exceed (AGND - 0.3V) to (AV
0.3V), limit the current to 50mA.
DD
+
DD
0
20
40
60
80
100
120
Analog Mux
The MAX1358/MAX1359/MAX1360 include a dual 10:1
mux for the positive and negative inputs of the ADC.
FREQUENCY (Hz)
Figure 6. Filter Frequency Response
______________________________________________________________________________________ 27
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
DV
DD
LDOE
CPE
CPOUT
1.22V
NONOVERLAP
CLOCK GENERATOR
OP
M32K
1.65V
CF+
CF-
REG
REG
LDOE
CHARGE-PUMP DOUBLER
LINEAR 1.65V VOLTAGE REGULATOR
Figure 8. Charge-Pump Block Diagram
Figure 7. Linear-Regulator Block Diagram
from DV . See Figures 7 and 8 for block diagrams of
DD
the charge pump and linear regulator. The charge
pump is disabled at power-on reset.
Force-Sense DAC (MAX1358/MAX1359)
The MAX1358 incorporates two 10-bit force-sense
DACs and the MAX1359 has one. The DACs’ reference
voltage sets the full-scale range. Program the
DACA_OP and DACB_OP registers using the serial
interface to set the output voltages of the DACs at
OUTA and OUTB. Shorting FBA/B and OUTA/B config-
ures the DAC in a unity-gain setting. Connecting resis-
tors in a voltage-divider configuration between
OUTA/B, FBA/B, and GND sets a different closed-loop
gain for the output amplifier (see the Applications
Information section).
An internal clock drives the charge-pump clock and
ADC clock. The charge pump delivers a maximum
10mA of current to external devices. The droop and the
ripple depend on the clock frequency (f
=
CLK
= 5Ω),
32.768kHz / 2), switch resistances (R
SWITCH
and the external capacitors (10µF) along with their
respective ESRs, as shown below.
V
= I
R
DROOP
OUT OUT
The DAC output amplifier typically settles to 0.5 LSB
from a full-scale transition within 50µs (unity gain and
loaded with 10kΩ in parallel with 200pF). Loads of less
than 1kΩ may degrade performance. See the Typical
Operating Characteristics for the source-and-sink
capability of the DAC output.
1
R
=
+ 2R
+ 4ESR
+ ESR
C
F CPOUT
OUT
SWITCH
C
f
C
F
CLK
I
OUT
V
=
+ 2I
ESR
OUT C
CPOUT
RIPPLE
f
C
CLK CPOUT
The MAX1358/MAX1359 feature a software-program-
mable shutdown mode for the DACs. Power down
DACA or DACB independently or simultaneously by
clearing the DAE and DBE bits (see the DACA_OP
Registers and DACB_OP Registers sections). DAC out-
puts OUTA and OUTB go high impedance when pow-
ered down. The DACs are normally powered down at
power-on reset.
Voltage Supervisors
The MAX1358/MAX1359/MAX1360 provide voltage
supervisors to monitor DV
supervisor monitors the DV
and CPOUT. The first
supply voltage. RESET
DD
DD
asserts and sets the corresponding LDVD status bit
when DV
falls below the 1.8V threshold voltage. When
supply voltage rises above the threshold dur-
DD
the DV
DD
ing power-up, RESET deasserts after a nominal 1.5s
timeout period to give the crystal oscillator time to stabi-
lize. Set the threshold hysteresis using the HYSE bit of
the PS_VMONS register. See the PS_VMONS Register
section for configuring hysteresis. There is no separate
Charge Pump
The charge pump provides >3V at CPOUT with a maxi-
mum 10mA load. Enable the charge pump through the
PS_VMONS register. The charge pump is powered
voltage monitor for AV , but the analog supply is cov-
DD
28 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
WDTO
DV
DD
HYSE
POR
RSTE
RESET
LSDE
CMP
1.8VTH
2.0VTH
ANALOG
2:1 MUX
CONTROL
LOGIC
1.25V
LDVD
LSDE
DV (1.8V) VOLTAGE MONITOR
DD
Figure 9. DV
Voltage-Supervisor Block Diagram
DD
to monitor AV
See Figure 10 for a block diagram of
DD.
the CPOUT voltage supervisor.
CPOUT
Interrupt Generator (INT)
CPDE
The interrupt generator provides an interrupt to an
external µC. The source of the interrupt is generated by
the status register and can be masked and unmasked
through the IMSK register. CRDY is unmasked by
default and INT is active-high at power-on reset. INT is
programmable as active-high and active-low. Possible
sources include a rising or falling edge of UPIO_, an
RTC alarm, an ADC conversion completion, or the volt-
age-supervisor outputs. The interrupt causes INT to
assert when configured as an interrupt output.
2.7VTH
LCPD
CMP
1.25V
CPDE
CPOUT (2.7V) VOLTAGE MONITOR
Crystal Oscillator
The on-chip oscillator requires an external crystal (or
resonator) connected between 32KIN and 32KOUT
with a 32.768kHz operating frequency. This oscillator is
used for the RTC, alarm, PWM, watchdog, charge
pump, and FLL. In any crystal-based oscillator circuit,
the oscillator frequency is sensitive to the capacitive
Figure 10. CPOUT Voltage-Supervisor Block Diagram
ered by the DV
monitor in many applications where
are externally connected together.
DD
DV
and AV
DD
DD
Multiple supply applications where AV
and DV
are
DD
DD
not connected together require a separate external volt-
age monitor for AV . See Figure 9 for a block diagram
DD
load (C ). C is the capacitance that the crystal needs
L
L
of the DV voltage supervisor.
DD
from the oscillator circuit and not the capacitance of the
crystal. The input capacitance across the 32KIN and
32KOUT is 6pF. Choose a crystal with a 32.768kHz
oscillation frequency and a 6pF capacitive load such
as the C-002RX32-E from Epson Crystal. Using a crys-
The second voltage monitor tracks the charge-pump
output voltage, CPOUT. If CPOUT falls below the 2.7V
threshold, a corresponding register status bit (LCPD) is
set to flag the condition. The CPOUT monitor output
can also be mapped to the interrupt generator and out-
put on INT. The CPOUT monitor can be used as a 3V
tal with a C that is larger than the load capacitance of
L
the oscillator circuit causes the oscillator to run faster
than the specified nominal frequency of the crystal or to
not start up. See Figures 11 and 12 for block diagrams
of the crystal oscillator and the CLK32K I/O.
AV
monitor in applications where the charge pump is
DD
disabled and CPOUT is connected to AV . AV
DD
DD
must be greater or equal to DV
when CPOUT is used
DD
______________________________________________________________________________________ 29
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
OSCE
32K
OSCE
CK32E
IO32E
IO32E
0
32KOUT
32KIN
32kHz
OSCILLATOR
32K
IO32E
2:1
MUX
M32K
CLK32K
1
32.768kHz OSCILLATOR
CLK32K I/O CONTROL
Figure 11. 32kHz Crystal-Oscillator Block Diagram
Figure 12. CLK32K I/O Block Diagram
POR PULSES HIGH DURING POWER-UP.
WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE.
WDTO
D
Q
D
Q
4Hz
CK
32K
DIVIDE-
BY-8192
Q
CK
Q
WDE
R
R
POR
WDW
WATCHDOG TIMER
Figure 13. Watchdog Timer Block Diagram
rent time with a 1s resolution. The alarm status bit, ALD,
asserts when the 20 bits of the AL_DAY register match-
es the 20 LSBs of the 32-bit second counter. The ADE
bit automatically clears when the time-of-day alarm
trips. The time-of-day alarm causes the device to exit
sleep mode.
Real-Time Clock (RTC)
The integrated RTC provides the current time information
from a 32-bit counter and subsecond counts from an 8-
bit ripple counter. An internally generated reference
clock of 256Hz (derived from the 32.768kHz crystal) dri-
ves the 8-bit subsecond counter. An overflow of the 8-bit
subsecond counter inputs a 1Hz clock to increment the
32-bit second counter. The RTC 32-bit second counter is
translatable to calendar format with firmware. All 40 bits
(32-bit second counter and 8-bit subsecond counter)
must be clocked in or out for valid data. The RTC and
the 32.768kHz crystal oscillator consume less than 1µA
when the rest of the IC is powered down.
Watchdog
Enable the watchdog timer by writing a 1 to the WDE bit
in the CLK_CTRL register. After enabling the watchdog
timer, the device asserts RESET for 250ms, if the
watchdog address register is not written every 500ms.
Due to the asynchronous nature of the watchdog timer,
the watchdog timeout period varies between 500ms
and 750ms. Write a 0 to the WDE bit to disable the
watchdog timer. See Figure 13 for a block diagram of
the watchdog timer.
Time-of-Day Alarm
Program the AL_DAY register with a 20-bit value, which
corresponds to a time 1s to 12 days later than the cur-
30 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
32.768kHz
CKSEL2
CKSEL<1:0>
CLKE
HFCE
0
FLLE
2:1
MUX
1, 2, 4, 8
DIVIDER
CLK
FREQ
ERROR
M32K
TUNE<8:0> DIGITALLY
CONTROLLED
FREQUENCY
COMPARE
FREQUENCY
INTEGRATOR
1
OSCILLATOR
4.9152MHz
HFCLK
CRDY
4.9152MHz HF OSCILLATOR AND FLL
Figure 14. High-Frequency Clock and FLL Block Diagram
High-Frequency Clock
An internal oscillator and a frequency-locked loop (FLL)
are used to generate a 4.9152MHz 1% high-frequen-
cy clock. This clock and derivatives are used internally
by the ADC, analog switches, and PWM. This clock sig-
nal outputs to CLK. When the FLL is enabled, the high-
frequency clock is locked to the 32.768kHz reference. If
the FLL is disabled, the high-frequency clock is free-
running. At power-up, the CLK pin defaults to a
2.4576MHz clock output, which is compatible with most
µCs. See Figure 14 for a block diagram of the high-fre-
quency clock.
PROGRAMMABLE CURRENT SOURCE
CURRENT
IVAL<1:0>
SOURCE
1:3
DEMUX
IMUX<1:0>
AIN1
AIN1
AIN2
AIN2
User-Programmable I/Os
The MAX1358/MAX1359/MAX1360 provide four digital
programmable I/Os (UPIO1–UPIO4). Configure UPIOs
as logic inputs or outputs using the UPIO control regis-
ter. Configure the internal pullups using the UPIO setup
register, if required. At power-up, the UPIO’s are inter-
TEMP+
TEMP-
nally pulled up to DV . UPIO_ outputs can be refer-
DD
enced to DV
or CPOUT. See the UPIO__CTRL
Register and UPIO_SPI Register sections for more
DD
details on configuring the UPIO_ pins.
Program each UPIO1–UPIO4 as one of the following:
• General-purpose input
• Power-mode control
TEMP SENSOR
• Analog switch (SPST) and SPDT control input
• ADC data-ready output
• General-purpose output
• PWM output
Figure 15. Temperature-Sensor Measurement Block Diagram
• Alarm output
• SPI passthrough
______________________________________________________________________________________ 31
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
CS
SCLK
DIN
X
1
0
A5
A4
A3
A2
A1
A0
D
D
D
D
D
D
D
0
X
N
N -1
N-2
N-3
2
1
DOUT
X = DON’T CARE.
Figure 16. Serial-Interface Register Write with 8-Bit Control Word, Followed by a Variable Length Data Write
CS
SCLK
DIN
X
1
1
A5
A4
A3
A2
A1
A0
X
X
X
X
X
X
X
X
D
D
D
D
D
D
D
0
N
N-1
N-2
N-3
2
1
DOUT
X = DON’T CARE.
Figure 17. Serial-Interface Register Read with 8-Bit Control Word Followed by a Variable Length Data Read
CS
SCLK
DIN
1
0
A4 A3 A2 A1 A0 X D7 D6 D5 D4 D3 D2 D1 D0
1
1 A4 A3 A2 A1 A0 X
ADC
CONV
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CHANGES
DOUT
DRDY
X = DON’T CARE.
Figure 18. Performing an ADC Conversion (DRDY Function can be Accessed at UPIO Pins)
measure the temperature. For either method, two to
Temperature Sensor
The internal temperature sensor measures die tempera-
ture and the external temperature sensor measures
remote temperatures. Use the internal temperature sen-
sor or external temperature sensor (remote transistor/
diode) with the ADC and internal current sources to
four currents are passed through a p-n junction and
sense resistor, and its temperature is calculated by a
µC using the diode equation and the forward-biased
junction voltage drops measured by the ADC. The tem-
perature offset between the internal p-n junction and
32 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ambient is negligible. For the four and eight measure-
ment methods, the ratio of currents used in the diode
calculations is precisely known since the ADC mea-
sures the resulting voltage across the same sense
resistor. See Figure 15 for a block diagram of the tem-
perature sensor.
1) Current I is driven through the diode and the series
1
resistor R, and the voltage is measured across the
diode using the ADC as NVBE1.
2) For the same current, the voltage across the diode and
the series resistor is measured by the ADC as NV1.
3) Repeat steps 1 and 2 with I , I , and I .
2
3
4
Two-Current Method
The measured temperature is defined as follows:
For the two-current method, currents I and I are
1
2
passed through a p-n junction. This requires two V
q N
(
−N
−q N
−N
)
(
)
×
BE
V
REF
VBE3
VBE1
VBE4 VBE2
T
=
MEAS
measurements. Temperature measurements can be
performed using I and I .
16
M
2
1
nkIn
1
2
M
2
q V
− V
BE1
(
)
BE2
T
=
MEAS
where V
is the reference voltage used and:
REF
I
1
nk ln
M
N
N
V1
−N
−N
N
N
−N
−N
I
1
V3
VBE3
VBE1
V2
VBE2
VBE4
2
=
M
2
V4
where k is Boltzman’s constant. A four-measurement
procedure is adopted to improve accuracy by precisely
External Temperature Sensor
measuring the ratio of I and I :
1
2
For an external temperature sensor, either the two-cur-
rent or four-current method can be used. Connect an
external diode (such as 2N3904 or 2N3906) between
pins AIN1 and AGND (or AIN2 and AGND). Connect a
sense resistor R between AIN1 and AIN2. Maximize R
1) Current I is driven through the diode and the series
1
resistor R, and the voltage across the diode is mea-
sured as V
.
BE1
2) For the same current, the voltage across the diode
and R is measured as V .
so the IR drop plus V
of the p-n junction [(R x
BE
1
60µA)+V ] is the smaller of the ADC reference voltage
BE
3) Repeat steps 1 and 2 with I . I is typically 4µA and
2
1
or (AV
- 400mV). The same procedure as the internal
DD
I is typically 60µA (see Table 22).
2
temperature sensor can be used for the external tem-
perature sensor, by routing the currents to AIN1 (or
AIN2) (see Table 21).
Since only four integer numbers are accessible from the
ADC conversions at a certain voltage reference, the previ-
ous equation can be represented in the following manner:
For the two-current method, if the external diode’s
series resistance (R ) is known, then the temperature
S
q(N
−N
)
V
REF
VBE2
VBE1
T
=
×
measurement can be corrected as shown below:
MEAS
16
N
−N
−N
2
V1
VBE1
VBE2
nk ln
N
V2
9(N −N
V2 VBE2
)− 9(N −N
)
V
R
S
R
V1 VBE1
REF
T
= T
MEAS
−
×
×
16
ACTUAL
N
−N
−N
2
V2
VBE1
where N , N , N
, and N
are the measure-
VBE2
V1
V2
VBE1
nkIn
N
V1
VBE1
ment results in integer format and V
is the reference
REF
voltage used in the ADC measurements.
Temperature-Sensor Calibration
Four-Current Method
The four-current method is used to account for the
diode series resistance and trace resistance. The four
currents are defined as follows; I , I , M I , and M I . If
To account for various error sources during the temper-
ature measurement, the internal temperature sensor is
calibrated at the factory. The calibrated temperature
equation is shown below:
1
2
1 1
2 2
the currents are selected so (M - 1)I = (M - 1)I , the
1
1
2
2
T = g x T
A
+ b
MEAS
effect of the series resistance is eliminated from the
temperature measurements. For the currents I = 4µA
where g and b are the gain and offset calibration val-
ues, respectively. These calibration values are avail-
able for reading from the TEMP_CAL register.
1
and I = 60µA, the factors are selected as M = 16 and
2
1
M = 2. This results in the currents I = M I = 64µA
2
3
1 1
and I = M I = 120µA (typ). As in the case of the two-
4
2 2
Voltage Reference and Buffer
An internal 1.25V bandgap reference has a buffer with
a selectable 1.0V/V, 1.638V/V, or 2.0V/V gain, resulting
current method, two measurements per current are
used to improve accuracy by precisely measuring the
values of the currents.
______________________________________________________________________________________ 33
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
in a respective 1.25V, 2.048V, or 2.5V reference voltage
at REF. The ADC and DACs use this reference voltage.
The state of the internal voltage reference output buffer at
POR is disabled so it can be driven, at REF, with an exter-
cy-divided versions of each. Although most µCs have
built-in PWM functions, the MAX1358/MAX1359/
MAX1360 PWM is more flexible by allowing the UPIO
outputs to be driven to DV
or regulated CPOUT
DD
nal reference between AGND and AV . The A-grade
DD
logic-high voltage levels. For duty-cycled power-control
schemes, use the 32kHz-derived input clock. The PWM
output is available independent of µC power state. The
FLL is typically disabled in sleep-override mode.
reference has an initial tolerance of 1%. The B-grade
reference has an initial tolerance of 3%. Program the
reference buffer through the serial interface. Bypass REF
with a 4.7µF capacitor to AGND.
Serial Interface
The MAX1358/MAX1359/MAX1360 feature a 4-wire serial
interface consisting of a chip select (CS), serial clock
(SCLK), data in (DIN), and data out (DOUT). CS must be
low to allow data to be clocked into or out of the device.
DOUT is high impedance while CS is high. The data is
clocked in at DIN on the rising edge of SCLK. Data is
clocked out at DOUT on the falling edge of SCLK. The
serial interface is compatible with SPI modes CPOL = 0,
CPHA = 0 and CPOL = 1, CPHA = 1. A write operation to
the MAX1358/MAX1359/MAX1360 takes effect on the last
rising edge of SCLK. If CS goes high before the complete
transfer, the write is ignored. Every data transfer is initiat-
ed by the command byte. The command byte consists of
a start bit (MSB), R/W bit, and 6 address bits. The start bit
must be 1 to perform data transfers to the device. Zeros
clocked in are ignored. For SPI passthrough mode, see
the UPIO_SPI register. An address byte identifies each
register. Table 4 shows the complete register address
map for this family of DAS. Figures 16, 17, and 18 provide
timing diagrams for read and write commands.
Operational Amplifiers (Op Amps)
The MAX1358 includes one uncommitted op amp; the
MAX1359 includes two op amps; and the MAX1360
includes three op amps. These op amps feature rail-to-rail
outputs, near rail-to-rail inputs, and have an 80kHz (1nF
load) input bandwidth. The DACA_OP (DACB_OP) regis-
ter controls the power state of the op amps. When pow-
ered down, the outputs of the op amps are high
impedance.
Single-Pole/Double-Throw (SPDT) Switches
The MAX1358/MAX1359/MAX1360 provide two uncom-
mitted SPDT switches. Each switch has a typical on-resis-
tance of 35Ω. Control the switches through the SW_CTRL
register, the PWM output, and/or a UPIO port configured
to control the switches (UPIO1–UPIO4_CTRL register).
Pulse-Width Modulator (PWM)
A single 8-bit PWM is available for various system tasks
such as LCD bias control, sensor bias voltage trim,
buzzer drive, and duty-cycled sleep-mode power-con-
trol schemes. PWM input clock sources include the
4.9512MHz FLL output, the 32kHz clock, and frequen-
34 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Register Definitions
Table 4. Register Address Map
REGISTER
NAME
CTL
(R/W)
ADR<5:0>
(ADDRESS)
D<39:0>, D<23:0>, D<15:0> OR D<7:0>
(DATA)
START
ADCE STRT
RATE<2:0>
BIP
POL CONT ADCREF GAIN<1:0>
MODE<2:0>
MUXN<3:0>
ADC<15:0>
OFFSET<23:0>
GAIN<23:0>
ADC
1
R/W
0
0
0
0
0
X
X
X
MUX
DATA
OFFSET CAL
GAIN CAL
RESERVED
1
1
1
1
1
R/W
R
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
S
X
X
X
X
MUXP<3:0>
Reserved. Do not use.
DAE/
OP3E OP2E
DBE/
OP1E
X
X
X
X
DACA<9:8>
DACB<9:8>
DACA_OP
DACB_OP
1
1
R/W
R/W
0
0
0
0
1
1
1
1
0
1
X
X
DACA<7:0>
DAE/ DBE/
OP1E
X
X
OP3E OP2E
REFV<1:0>
DACB<7:0>
REF_SDC
AL_DAY
1
1
1
1
R/W
R/W
R/W
R/W
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
X
X
X
X
AOFF AON SDCE
ASEC<19:4>
TSEL<2:0>
ASEC<3:0>
X
X
X
X
RESERVED
CLK_CTRL
Reserved. Do not use.
AWE
ADE
X
RWE RTCE
IO32E CK32E
SEC<31:0>
SUB<7:0>
SWAH
OSCE
CLKE
FLLE HFCE
INTP WDE
CKSEL<2:0>
RTC
1
1
1
R/W
R/W
R/W
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
X
X
X
PWME
FSEL<2:0>
SWAL SWBH SWBL
PWM_CTRL
PWM_THTP
SPD1 SPD2
X
X
X
X
X
X
PWMTH<7:0>
PWMTP<7:0>
WATCHDOG
NORM_MD
SLEEP
1
1
1
1
1
1
1
1
1
1
1
1
W
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
W
W
SLEEP_CFG
UPIO4_CTRL
UPIO3_CTRL
UPIO2_CTRL
UPIO1_CTRL
UPIO_SPI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
SLP SOSCE SCK32E SPWME SHDN
X
X
X
X
X
X
X
X
X
X
UP4MD<3:0>
UP3MD<3:0>
PUP4
PUP3
PUP2
PUP1
X
SV4
SV3
SV2
SV1
X
ALH4 LL4
ALH3 LL3
ALH2 LL2
ALH1 LL1
X
X
X
X
UP2MD<3:0>
UP1MD<3:0>
UP4S UP3S UP2S UP1S
X
X
X
X
X
SW_CTRL
SWA
IMUX<1:0>
TGAIN<7:0>
SWB SPDT1<1:0>
SPDT2<1:0>
TEMP_CTRL
TEMP_CAL
IVAL<1:0>
X
X
TOFFS<5:0>
MLDVD MLCPD MADO MSDC MCRDY MADD MALD
MUPR<4:1> MUPF<4:1>
Reserved. Do not use.
IMSK
1
R/W
1
1
0
1
1
X
RESERVED
PS_VMONS
RESERVED
1
1
1
R/W
R/W
R/W
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
X
X
X
LDOE
CPE LSDE CPDE HYSE
RSTE
X
X
X
Reserved. Do not use.
LDVD LCPD ADOU SDC CRDY
UPR<4:1>
ADD
ALD
STATUS
1
R
1
1
1
1
1
X
UPF<4:1>
X = Don’t care.
______________________________________________________________________________________ 35
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Register Bit Descriptions
ADC Register (Power-On State: 0000 0000 0000 00XX)
MSB
LSB
ADCE
STRT
BIP
POL
CONT
ADCREF
GAIN<1:0>
RATE<2:0>
MODE<2:0>
X
X
The ADC register configures the ADC and starts
a conversion.
CONT: Continuous conversion bit. CONT = 1 enables
continuous conversions following completion of the first
conversion or calibration(s) initiated by the STRT or S
bit. Set CONT = 0 while asserting the STRT bit, or prior
to asserting the S bit to perform a single conversion or to
prevent conversions following a calibration. Set CONT =
0 to abort continuous conversions already in progress.
When the ADC is stopped in this way, the last complete
conversion result remains in the DATA register and the
internal ADC state information is lost. Asserting the
CONT bit does not restart the ADC, but results in contin-
uous conversions once the ADC is restarted with the
STRT or S bit.
ADCE: ADC power-enable bit. ADCE = 1 powers up
the ADC, and ADCE = 0 powers down the ADC.
STRT: ADC start bit. STRT = 1 resets the registers
inside the ADC filter and initiates a conversion or cali-
bration. The conversion begins immediately after the
16th ADC control bit is clocked by the rising edge of
SCLK. The initial conversion requires four conversion
cycles for valid output data. If CONT = 0 when STRT is
asserted, the ADC stops after a single conversion and
holds the result in the DATA register. If CONT = 1 when
STRT is asserted, the ADC performs continuous conver-
sions at the rate specified by the RATE<2:0> bits until
CONT is deasserted or ADCE is deasserted, powering
down the ADC. The STRT bit is automatically deasserted
after the initial conversion is complete (four conversion
cycles, the ADC status bit ADD in the STATUS register
asserts.) The current ADC configurations are not affect-
ed if the ADC register is written with STRT = 0. This
allows the ADC and mux configurations to be updated
simultaneously with the S bit in the MUX register.
ADCREF: ADC reference source bit. Set ADCREF = 0
to select REF as the ADC reference. Set ADCREF = 1
to select AV
as the ADC reference. To measure the
DD
AV
voltage without having to attenuate the supply
DD
voltage, select REF and AGND as the differential inputs
to the ADC, with POL = 0 and while ADCREF = 1.
GAIN<1:0>: ADC gain-setting bits. These two bits
select the gain of the ADC as shown in Table 5.
BIP: Unipolar/bipolar bit. Set BIP = 0 for unipolar mode
and BIP = 1 for bipolar mode. Unipolar-mode data is
unsigned binary format and bipolar is two’s complement.
See the ADC Transfer Functions section for more details.
Table 5. Setting the Gain of the ADC
GAIN SETTING (V/V)
GAIN1
GAIN0
POL: Polarity flipper bit. POL = 1 flips the polarity of the
differential signal to the ADC and the input to the signal-
detect comparator (SDC). POL = 0 sets the positive mux
output to the positive ADC and SDC inputs, and the neg-
ative mux output to the negative ADC and SDC inputs.
POL = 1 sets the positive mux output to the negative
ADC and SDC inputs, and the negative mux output to
the positive ADC and SDC inputs.
1
2
4
8
0
0
1
1
0
1
0
1
36 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
RATE<2:0>: ADC conversion-rate-setting bits. These
Table 6. Setting the ADC Conversion Rate*
three bits set the conversion rate of the ADC as shown
CONTINUOUS
SINGLE
in Table 6. The initial conversion requires four conver-
sion cycles for valid data and subsequent conversions
require only one cycle (if CONT = 1). A full-scale input
change can require up to five cycles for valid data if
the digital filter is not reset with the STRT or S bit.
CONVERSION CONVERSION
RATE2 RATE1 RATE0
RATE (sps)
RATE (sps)
10
40
2.5
10
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MODE<2:0>: Conversion-mode bits. These three bits
determine the type of conversion for the ADC as shown
in Table 7. When the ADC finishes an offset calibration
and/or gain calibration, the MODE<2:0> bits clear to 0
hex, the ADD bit in the STATUS register asserts, and
an interrupt asserts on INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked. Perform a gain calibra-
tion after achieving the desired offset (calibrated or
not). If an offset and gain calibration are performed
together (MODE<2:0> = 7 hex), the offset calibration is
performed first followed by the gain calibration, and the
µC is interrupted by INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked only upon completion of
both offset and gain calibration. After power-on or cali-
bration, the ADC does not begin conversions until initi-
ated by the user (see the ADCE and STRT bit
descriptions in this section and see the S bit descrip-
tions in the MUX Register section). See the GAIN CAL
Register and OFFSET CAL Register sections for details
on system calibration.
50
12.5
15
60
200
240
400
512
50
60
100
128
The actual rates are:
NOMINAL
CONTINUOUS
CONVERSION
RATE (sps)
ACTUAL
DECIMATION
CONTINUOUS
CONVERSION
RATE (sps)
RATIO
10
40
1096
274
220
183
55
10.01042142
40.04168568
49.87009943
59.953125
50
60
200
240
400
512
199.4803977
238.5091712
406.3489583
477.0183424
46
27
Table 7. Setting the ADC Conversion Mode
23
CONVERSION MODE
Normal
MODE2 MODE1 MODE0
*Calculate the ADC sampling rate using the following
equation:
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
System Offset Calibration
System Gain Calibration
Normal
f
HFCLK
f =
S
448×decimation ratio
= 4.9152MHz nominally.
Normal
where f
HFCLK
Self Offset Calibration
Self Gain Calibration
Self Offset and Gain
Calibration
1
1
1
______________________________________________________________________________________ 37
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MUX Register (Power-On State: 0000 0000)
MSB
LSB
S (ADR0)
MUXP3
MUXP2
MUXP1
MUXP0
MUXN3
MUXN2
MUXN1
MUXN0
The MUX register configures the positive and negative
mux inputs and can start an ADC conversion.
ified by the RATE<2:0> bits until CONT deasserts or
ADCE deasserts, powering down the ADC. When a
conversion initiates using the S bit, the STRT bit asserts
and deasserts automatically after the initial conversion
completes. Writing to the MUX register with S = 0 caus-
es the MUX settings to change immediately and the
ADC continues in its prior state with its settings unaf-
fected. When the ADC is powered down, MUX inputs
are open.
S (ADR0): Conversion start bit. The S bit is the LSB of
the MUX register address byte. S = 1 resets the regis-
ters inside the ADC filter and initiates a conversion or
calibration. The conversion begins immediately after
the eighth MUX register data bit, when S = 1 and when
writing to the MUX register. This allows the new MUX
and ADC register settings to take effect simultaneously
for a new conversion, if STRT = 0 during the last write
to the ADC register. If the S bit is asserted and the
command is a read from the MUX register, the conver-
sion starts immediately after the S bit (ADR0) is clocked
in by the rising edge of SCLK.
MUXP<3:0>: MUX positive input bits. These four bits
select one of ten inputs from the positive MUX to go to the
positive output of the MUX as shown in Table 8. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
Read the MUX register with S = 1 for the fastest method
of initiating a conversion because only 8 bits are
required. The subsequent MUX register read is valid,
but can be aborted by raising CS with no harmful side
effects. The initial conversion requires four conversion
cycles for valid output data. If CONT = 0 and S = 1, the
ADC stops after a single conversion and holds the
result in the DATA register. If CONT = 1 and S = 1, the
ADC performs continuous conversions at the rate spec-
MUXN<3:0> MUX negative input bits. These four bits
select one of ten inputs from the negative MUX to go to
the negative output of the MUX as shown in Table 9. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
The DATA register contains the data from the most
recently completed conversion.
Table 8. Selecting the Positive MUX Inputs
POSITIVE MUX INPUT
MUXP3
MUXP2
MUXP1
MUXP0
MAX1358
AIN1
MAX1359
AIN1
MAX1360
AIN1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
X
0
1
0
1
0
1
0
1
0
1
X
X
SNO1
FBA
SNO1
FBA
SNO1
IN3-
SCM1
FBB
SCM1
IN2-
SCM1
IN2-
SNC1
IN1-
SNC1
IN1-
SNC1
IN1-
TEMP+
REF
TEMP+
REF
TEMP+
REF
AGND
AGND
AGND
Open
Open
Open
X = Don’t care.
38 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Table 9. Selecting the Negative MUX Inputs
NEGATIVE MUX INPUT
MUXN3
MUXN2
MUXN1
MUXN0
MAX1358
TEMP-
SNO2
OUTA
SCM2
OUTB
SNC2
OUT1
AIN2
MAX1359
TEMP-
SNO2
OUTA
SCM2
OUT2
SNC2
OUT1
AIN2
MAX1360
TEMP-
SNO2
OUT3
SCM2
OUT2
SNC2
OUT1
AIN2
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
X
0
1
0
1
0
1
0
1
0
1
X
X
REF
REF
REF
AGND
AGND
AGND
Open
Open
Open
X = Don’t care.
DATA Register (Power-On State: 0000 0000 0000 0000)
MSB
ADC15
ADC14
ADC13
ADC12
ADC11
ADC10
ADC9
LSB
ADC8
ADC0
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC<15:0> Analog-to-digital conversion data bits.
These 16 bits are the results from the most recently
completed conversion. The data format is unsigned,
binary for unipolar mode, and two’s complement for
bipolar mode.
______________________________________________________________________________________ 39
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
OFFSET CAL Register (Power-On State: 0000 0000 0000 0000 0000 0000)
MSB
OFFSET23
OFFSET15
OFFSET7
OFFSET22
OFFSET14
OFFSET6
OFFSET21
OFFSET13
OFFSET5
OFFSET20
OFFSET12
OFFSET4
OFFSET19
OFFSET11
OFFSET3
OFFSET18
OFFSET10
OFFSET2
OFFSET17
OFFSET9
OFFSET1
OFFSET16
OFFSET8
LSB
OFFSET0
The OFFSET CAL register contains the 24-bit data of
the most recently completed offset calibration.
offset calibration or self offset calibration. Self-calibra-
tion performs a calibration for the entire signal path.
See the ADC Calibration section for more details.
OFFSET<23:0>: Offset-calibration bits. The data format
is two’s complement and is subtracted from the ADC
output before being written to the DATA register. The
offset calibration allows input offset errors between
The ADC input voltage range specifications must
always be obeyed and the OFFSET CAL register effec-
tively offsets the ADC digital scale to a “zero” value
determined by the calibration.
V
50% to be corrected in unipolar or bipolar mode.
REF
The MAX1358/MAX1359/MAX1360 can perform system
GAIN CAL Register (Power-On State: 1000 0000 0000 0000 0000 0000)
MSB
GAIN23
GAIN15
GAIN7
GAIN22
GAIN14
GAIN6
GAIN21
GAIN13
GAIN5
GAIN20
GAIN12
GAIN4
GAIN19
GAIN11
GAIN3
GAIN18
GAIN10
GAIN2
GAIN17
GAIN9
GAIN1
GAIN16
GAIN8
LSB
GAIN0
GAIN<23:0>: Gain-calibration bits. The data format is
unsigned binary with 23 bits to the right of the decimal
point and scales the ADC output before being written to
the DATA register. The gain calibration allows full-scale
system calibration performs a calibration for the entire
signal path. See the ADC Calibration section for more
details.
The ADC input voltage range specifications must always
be obeyed and the GAIN CAL register effectively scales
the ADC digital output to a full-scale value determined
by the calibration. The usable gain-calibration range is
limited to less than the full GAIN CAL register digital-
scaling range by the internal noise of the ADC.
errors between -V
/ 2 and +V
/ 2 to be corrected
REF
REF
in unipolar mode, and full-scale errors between (+50%
x V ) and (+200% x V ) in unipolar or bipolar
REF
REF
mode. The MAX1358/MAX1359/MAX1360 can perform
system gain calibration or self gain calibration. Self-cali-
bration performs a calibration for offsets in the ADC and
40 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
DACA_OP Registers
where
is the reference voltage for the DAC.
Writing to the DACA_OP output register updates DACA
on the rising SCLK edge of the LSB data bit. The output
voltage can be calculated as follows:
V
REF
N is the integer value of DACA<9:0> output register.
The output buffer is in unity gain.
V
OUTA
= V
x N / 210
REF
The DACA data is 10 bits long and right justified.
MAX1358 (Power-On State: 000X XX00 0000 0000)
MSB
DAE
DBE
OP1E
X
X
X
DACA9
DACA1
DACA8
LSB
DACA7
DACA6
DACA5
DACA4
DACA3
DACA2
DACA0
MAX1359 (Power-On State: 000X XX00 0000 0000)
MSB
DAE
OP2E
OP1E
X
X
X
DACA9
DACA1
DACA8
LSB
DACA7
DACA6
DACA5
DACA4
DACA3
DACA2
DACA0
MAX1360 (Power-On State: 000X XXXX XXXX XXXX)
MSB
OP3E
X
OP2E
X
OP1E
X
X
X
X
X
X
X
X
X
X
LSB
X
DAE: DACA enable bit. Set DAE = 1 to power up the
DACA and the DACA output buffer in the MAX1358/
MAX1359. This bit is mirrored in the DACB_OP register.
OP2E: OP2 power-enable bit. Set OP2E = 1 to power
up OP2 in the MAX1359/MAX1360. This bit is mirrored
in the DACB_OP register.
DBE: DACB enable bit. Set DBE = 1 to power up
DACB and the DACB output buffer in the MAX1358.
This bit is mirrored in the DACB_OP register.
OP3E: OP3 power-enable bit. Set OP3E = 1 to power
up OP3 in the MAX1360. This bit is mirrored in the
DACB_OP register.
OP1E: OP1 power-enable bit. Set OP1E = 1 to power
up OP1 in the MAX1358/MAX1359/MAX1360. This bit is
mirrored in the DACB_OP register.
DACA<9:0>: DACA data bits.
______________________________________________________________________________________ 41
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
DACB_OP Registers
where
V is the reference voltage for the DAC.
REF
Writing to the DACB_OP output register updates DACB
on the rising SCLK edge of the LSB. The output voltage
can be calculated as follows:
N is the integer value of DACB<9:0> output register.
The output buffer is in unity gain.
V
OUTB
= V
x N / 210
REF
The DACB data is 10 bits long and right justified.
MAX1358 (Power-On State: 000X XX00 0000 0000)
MSB
DAE
DBE
OP1E
X
X
X
DACB9
DACB1
DACB8
LSB
DACB7
DACB6
DACB5
DACB4
DACB3
DACB2
DACBD
MAX1359 (Power-On State: 000X XXXX XXXX XXXX)
MSB
DAE
X
OP2E
X
OP1E
X
X
X
X
X
X
X
X
X
X
LSB
X
MAX1360 (Power-On State: 000X XXXX XXXX XXXX)
MSB
OP3E
X
OP2E
X
OP1E
X
X
X
X
X
X
X
X
X
X
LSB
X
DAE: DACA enable bit. Set DAE = 1 to power up
DACA and the DACA output buffer in the
MAX1358/MAX1359. This bit is mirrored in the
DACA_OP register.
OP3E: OP3 power-enable bit. Set OP3E = 1 to power
up OP3 in the MAX1360. This bit is mirrored in the
DACA_OP register.
DACB<9:0>: DACB data bits.
DBE: DACB enable bit. Set DBE = 1 to power up
DACB and the DACB output buffer in the MAX1358.
This bit is mirrored in the DACA_OP register.
OP1E: OP1 power-enable bit. Set OP1E = 1 to power
up OP1 in the MAX1358/MAX1359/MAX1360. This bit is
mirrored in the DACA_OP register.
OP2E: OP2 power-enable bit. Set OP2E = 1 to power
up OP2 in the MAX1359/MAX1360. This bit is mirrored
in the DACA_OP register.
42 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
REF_SDC Register (Power-On State: 0000 0000)
MSB
LSB
REFV1
REFV0
AOFF
AON
SDCE
TSEL2
TSEL1
TSEL0
The REF_SDC register contains bits to control the refer-
ence voltage and signal-detect comparator.
AON: ADC and DAC/op-amp power-on bit. This bit
provides a method of turning on several analog func-
tions with a single write. Setting AON = 1 asserts the
ADCE bit in the ADC register and DAE/OP3E,
DBE/OP2E, and OP1E bits in the DACA_OP and
DACB_OP registers, powering up these blocks. Setting
AON = 0 has no effect. The AON bit has priority when
both AON and AOFF bits are asserted.
REFV<1:0>: Reference buffer voltage gain and enable
bits. Enables the output buffer, sets the gain and the
voltage at the REF pin as shown in Table 10. Power-on
state is off to enable an external reference to drive the
REF pin without contention.
AOFF: ADC and DAC/op-amp power-off bit. This bit pro-
vides a method for turning off several analog functions
with a single write. Setting AOFF = 1 deasserts the
ADCE in the ADC register and DAE/OP3E, DBE/OP2E,
and OP1E bits in the DACA_OP and DACB_OP regis-
ters, powering down these analog blocks. Setting AOFF
= 0 has no effect. The AON bit has priority when both
AON and AOFF bits are asserted.
Most of the analog functions can be enabled with a sin-
gle write to the REF_SDC register using AON,
REFV<1:0>, and SDCE.
SDCE: Signal-detect comparator power-enable bit. Set
SDCE = 1 to power up the signal-detect comparator
and set SDCE = 0 to power down the signal-detect
comparator. The ADCE bit in the ADC register must be
set to 1 to use the signal-detect comparator.
Most of the analog functions can be disabled with a
single write to the REF_SDC register by using AOFF,
REFV<1:0>, and SDCE.
TSEL<2:0>: Threshold-select bits. These bits select the
threshold for the signal-detect comparator as shown in
Table 11.
Table 10. Setting the Reference Output
Voltage
Table 11. Setting the Signal-Detect
Comparator Threshold
NOMINAL
REFERENCE
REF OUTPUT
VOLTAGE (V)
REFV1 REFV0
TSEL2
TSEL1
TSEL0
BUFFER GAIN (V/V)
THRESHOLD (mV)
0
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Off (High
Impedance at REF)
Disabled
0
0
50
1.0
1.638
2.0
1.25
2.048
2.5
0
1
1
1
0
1
100
150
200
X = Don’t care.
______________________________________________________________________________________ 43
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
AL_DAY Register (Power-On State: 0000 0000 0000 0000 0000 XXXX)
MSB
ASEC19
ASEC11
ASEC3
ASEC18
ASEC10
ASEC2
ASEC17
ASEC9
ASEC1
ASEC16
ASEC8
ASEC0
ASEC15
ASEC7
X
ASEC14
ASEC6
X
ASEC13
ASEC5
X
ASEC12
ASEC4
LSB
X
The AL_DAY register stores the second information of
the time-of-day alarm.
second counter match the contents of this register, the
alarm triggers and asserts ALD in the STATUS register. It
also asserts an interrupt on the INT pin unless masked by
the MALD bit in the IMSK register. The part enters normal
mode if an alarm triggers while in sleep mode. The time-
of-day alarm is intended to trigger single events.
Therefore, once it triggers, in the CLK_CTRL register, the
ADE bit is automatically cleared, disabling the time-of-
day alarm. Implement a recurring alarm with repeated
software writes over the serial interface each time the
time-of-day alarm triggers. The time-of-day alarm can
also be programmed to output at the UPIO pins.
ASEC<19:0>: Alarm-second bits. These 20 bits store
the time-of-day alarm, which corresponds to the lower
20 bits of the RTC second counter or SEC<19:0>.
Program the time-of-day alarm trigger between 1s to
just over 12 days beyond the current RTC second
counter value in increments of 1s.
Assert the AWE bit in the CLK_CTRL register (see the
CLK_CTRL Register section) to enable writing to the
AL_DAY register. Enabling the time-of-day alarm requires
two writes to the CLK_CTRL register. Write the 20 alarm-
second bits in 3 bytes, MSB first. If CS is raised before
the LSB is written, the alarm write is aborted, and the
existing value remains. When the lower 20 bits in the RTC
When configured this way the MALD bit does not mask
the UPIO alarm output.
44 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
CLK_CTRL Register (Power-On State: 00X0 1111 0010 1110)
MSB
AWE
ADE
X
RWE
RTCE
OSCE
CLKE
FLLE
INTP
HFCE
LSB
CKSEL2
CKSEL1
CKSEL0
IO32E
CK32E
WDE
The CLK_CTR register contains the control bits for the
RTC alarms and clocks.
therefore, a second write to this register is required to
change the value of the RTCE bit. The power-on default
state is 0.
AWE: Alarm write-enable bit. Set AWE = 1 to write data
to the AL_DAY register as well as the ADE bit in this
register. When AWE = 0, all writes are prevented to the
AL_DAY register and the ADE bit in this register. A sec-
ond write to this register is required to change the value
of the ADE bit. The power-on default state is 0.
RTCE: Real-time-clock enable bit. Set RTCE = 1 to
enable the RTC, and set RTCE = 0 to disable the RTC.
The RTC has a 32-bit second and an 8-bit subsecond
counter. The power-on default state is 1.
OSCE: 32kHz crystal-oscillator enable bit. Set OSCE =
1 to power up the 32kHz oscillator and set OSCE = 0 to
power down the oscillator. The power-on default state
is 1.
ADE: Alarm (time-of-day) enable bit. Set ADE = 1 to
enable the time-of-day alarm and set ADE = 0 to dis-
able the time-of-day alarm. When enabled, the ALD bit
in the STATUS register asserts when the RTC second
counter time matches AL_DAY register. The device
wakes up from sleep to normal mode if not already
awake. The ADE bit can only be written if the AWE = 1
from a previous write. The power-on default state is 0.
FLLE: Frequency-locked-loop enable bit. Set FLLE = 1
to enable the FLL, and set FLLE = 0 to disable the FLL.
If HFCE = 1 and FLLE = 0, the internal high-frequency
oscillator is enabled but it is not frequency-locked to
the 32kHz clock. When FLLE is asserted, it typically
takes 3.5ms for the high-frequency clock to settle to
within 1% of the 32kHz reference clock frequency.
Switching the FLL on or off with this bit does not cause
high-frequency clock glitching. The power-on default
state is 1.
RWE: RTC write-enable bit. Set RWE = 1 prior to writing
to the RTC register and the RTCE bit in this register. If
RWE = 0, all writes are prevented to the RTC register
as well as the RTCE bit in this register. The RWE signal
takes effect after the rising edge of the 16th clock;
______________________________________________________________________________________ 45
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
HFCE: High-frequency-clock enable bit. Set HFCE = 1
Table 12. Setting the CLK Frequency
to enable the internal high-frequency clock source, and
CLOCK FREQUENCY
(kHz)
set HFCE = 0 to disable the high-frequency clock
source.
CKSEL2
CKSEL1
CKSEL0
4915.2
2457.6
1228.8
614.4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
If HFCE = 1 and CLKE = 1, the internal high-frequency
oscillator is enabled and is present at CLK. The power-
on default state is 1.
CKSEL<2:0>: Clock selection bits. These bits select
the FLL-based output clock frequency at the high-fre-
quency CLK pin as shown in Table 12. The power-on
default state is 001.
32.768
16.384
8.192
IO32E: Input/output 32kHz clock select bit. Set IO32E
= 0 to configure the CLK32K pin as an output and set
IO32E = 1 to configure the CLK32K pin as an input,
regardless of the signal on the 32KIN pin as shown in
Table 13.
4.096
internally but is not needed externally. If HFCE = 0, or if
CLKE = 0, CLK remains low. The power-on default
state is 1.
External clock frequencies applied to CLK32K are
clock sources to the FLL, charge pump, and the signal-
detect comparator. The default power-on state is 0.
INTP: Interrupt pin polarity bit. Set INTP = 1 to make
INT an active-high output when asserted and set INTP
= 0 to make INT an active-low output when asserted.
The power-on default state is 1.
CK32E: CLK32K output-buffer enable bit. Set CK32E =
1 to enable the CLK32K output buffer as long as OSCE
= 1 and IO32E = 0, otherwise the CK32E bit will not be
asserted. Set CK32E = 0 to disable the CLK32K output
buffer. The power-on default state is 1.
WDE: Watchdog-enable bit. Set WDE = 1 to enable the
watchdog timer, which asserts RESET low within 500ms
if the WATCHDOG register is not written. Set WDE = 0
to disable the watchdog timer. The power-on default
state is 0.
CLKE: CLK output-buffer enable bit. Set CLKE = 1 to
enable the CLK output buffer. Set CLKE = 0 to disable
the buffer. Disabling the buffer is useful for saving
power in cases where the high-frequency clock is used
Table 13. Configuring the CLK32K as an Input or Output
RTC, PWM, WDT
CLOCK SOURCE
FLL, C/P, SDC INPUT
CLK32K CLK32K
IO32E
32KIN, 32KOUT
ADC CLOCK SOURCE
SOURCE
Output
Input
1
0
0
1
XTAL attached
XTAL attached
XTAL
XTAL
XTAL
FLL/HFCLK
FLL/HFCLK
CLK32K
46 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
RTC Register (Power-On State: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000)
MSB
SEC31
SEC23
SEC15
SEC7
SEC30
SEC22
SEC14
SEC6
SEC29
SEC21
SEC13
SEC5
SEC28
SEC20
SEC12
SEC4
SEC27
SEC19
SEC11
SEC3
SEC26
SEC18
SEC10
SEC2
SEC25
SEC17
SEC9
SEC1
SUB1
SEC24
SEC16
SEC8
SEC0
LSB
SUB7
SUB6
SUB5
SUB4
SUB3
SUB2
SUB0
The RTC register stores the 40-bit second and subsec-
ond count of the respective time-of-day and system
clocks.
of the RTC register in less than 1ms. The power-on
default state is 0000 0000 hex.
SUB<7:0>: The subsecond bits store the system clock.
This 8-bit binary counter has 3.9ms resolution (1/256Hz)
and a span of 1s. The subsecond counter increments in
single counts from 00 hex to FF hex before rolling over
again to 00 hex, at which time, the RTC second counter
(SEC<31:0>) increments. The RTC runs continuously
(as long as RTCE = 1) and does not stop for reads or
writes. A 256Hz clock, derived from the 32kHz crystal,
increments this counter. Set the RWE = 1 bit to enable
writing to the RTC register. After writing to RWE, perform
another write, setting RTCE = 1, to enable the RTC. A
40-bit burst write operation, starting with SEC31 and fin-
ishing with SUB0, is required to set the RTC second and
subsecond bits. If CS is brought high before the 40th
rising SCLK edge, the write is aborted and the RTC con-
tents are unchanged. The RTC register is loaded on the
rising SCLK edge of the 40th bit (SUB0). A 40-bit burst
read operation, starting with SEC31 and finishing with
SUB0, is required to retrieve the current RTC second
and subsecond counts. The read command can be
aborted prior to receiving the 40th bit (SUB0) by raising
CS and any RTC data read to that point is valid. When
the read command is received, a snapshot of a valid
RTC second count is latched to avoid reading an erro-
neous, transitioning RTC value. Due to the asynchro-
nous nature of RTC reads, it is possible to have a
maximum 1s error between the actual and reported
times from the time-of-day clock. To prevent the data
from changing during a read operation, complete reads
of the RTC registers occur in less than 1ms. The power-
on default state is 00 hex.
SEC<31:0>: The second bits store the time-of-day
clock settings. It is a 32-bit binary counter with 1s reso-
lution that can keep time for a span of over 136 years.
Firmware in the µC can translate this time count to units
that are meaningful to the system (i.e., translate to cal-
endar time or as an elapsed time from some predefined
time = 0, such as January 1, 2000). The RTC runs con-
tinuously as long as RTCE = 1 (see the CLK_CNTL
Register section) and does not stop for reads or writes.
The counter increments when the subsecond counter
overflows. Set RWE = 1 to enable writing to the RTC
register. After writing to RWE, perform another write
and set RTCE = 1 to enable the RTC. A 40-bit burst
write operation, starting with SEC31 and finishing with
SUB0 is required to set the RTC second and subsec-
ond bits. If CS is brought high before the 40th rising
SCLK edge, the write is aborted and the RTC contents
are unchanged. The RTC register is loaded on the ris-
ing SCLK edge of the 40th bit (SUB0). A 40-bit burst
read operation, starting with SEC31 and finishing with
SUB0, is required to retrieve the current RTC second
and subsecond counts. The read command can be
aborted prior to receiving the 40th bit (SUB0) by raising
CS and any RTC data read to that point is valid. When
the read command is received, a snapshot of a valid
RTC second count is latched to avoid reading an erro-
neous, transitioning RTC value. Due to the asynchro-
nous nature of RTC reads, it is possible to have a
maximum 1s error between the actual and reported
times from the time-of-day clock. To prevent the data
from changing during a read operation, complete reads
______________________________________________________________________________________ 47
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
PWM_CTRL Register (Power-On State: 0000 0000 00XX XXXX)
MSB
PWME
FSEL2
FSEL1
FSEL0
SWAH
SWAL
X
SWBH
X
SWBL
LSB
X
SPD1
SPD2
X
X
X
The PWM_CTRL register contains control bits for the 8-
bit PWM.
PWM low output refers to the end of the period when
the output is logic-low. See Table 17 for more details.
The power-on default is 0.
PWME: PWM-enable bit. Set PWME = 1 to enable the
internal PWM and set PWME = 0 to disable the internal
PWM. Enable the high frequency clock before enabling
the PWM when using input clock frequencies above
32.768kHz. The power-on default state is 0.
SWBH: SWB-switch PWM-high control bit. Set SWBH =
1 to enable the PWM output to directly control the SWB
switch. When SWBH = SWBL, the PWM output is dis-
abled from controlling the SWB switch. When SWBH =
1, a PWM high output closes the SWB switch and a
PWM low output opens the SWB switch. The PWM high
output refers to the beginning of the period when the
output is logic-high. See Table 18 for more details. The
power-on default is 0.
FSEL<2:0>: Frequency selection bits. Selects the PWM
input clock frequency as shown in Table 14. The
power-on default is 000.
SWAH: SWA-switch PWM-high control bit. Set SWAH =
1 to enable the PWM output to directly control the SWA
switch. When SWAH = SWAL, the PWM output is dis-
abled from controlling the SWA switch. When SWAH =
1, a PWM high output closes the SWA switch and a
PWM low output opens the SWA switch. The PWM high
output refers to the beginning of the period when the
output is logic-high. See Table 17 for more details. The
power-on default is 0.
SWBL: SWB-switch PWM-low control bit. Set SWBL = 1
to enable the inverted PWM output to directly control
the SWB switch. When SWBH = SWBL the PWM output
is disabled from controlling the SWB switch. When
SWBL = 1, a PWM low output closes the SWB switch
and a PWM high output opens the SWB switch. The
PWM low output refers to the end of the period when
the output is logic-low. See Table 18 for more details.
The power-on default is 0.
SWAL: SWA-switch PWM-low control bit. Set SWAL = 1
to enable the inverted PWM output to directly control
the SWA switch. When SWAH = SWAL, the PWM output
is disabled from controlling the SWA switch. When
SWAL = 1, a PWM low output closes the SWA switch
and a PWM high output opens the SWA switch. The
SPD1: SPDT1-switch PWM drive control bit. Set SPD1
= 1 to enable the PWM output to directly control the
SPDT1 switch and set SPD1 = 0 to disable the PWM
output controlling the SPDT1 switch. The SPDT1<1:0>
bits, the UPIO pins (if programmed), and the PWM out-
put (if enabled), determine the SPDT1-switch state. See
Table 19 for more details. The power-on default is 0.
Table 14. Setting the PWM Frequency
PWM INPUT FREQUENCY*
SPD2: SPDT2-switch PWM drive control bit. Set SPD2
= 1 to enable the PWM output to directly control the
SPDT2 switch and set SPD2 = 0 to disable the PWM
output controlling the SPDT2 switch. The SPDT2<1:0>
bits, the UPIO pins (if programmed), and the PWM out-
put (if enabled), determine the SPDT2-switch state. See
Table 20 for more details. The power-on default is 0.
FSEL2
FSEL1
FSEL0
(kHz)
4915.2**
2457.6**
1228.8**
32.768
8.192
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.024
0.256
0.032
*The lower PWM frequencies are useful for power-supply duty
cycling to conserve battery life and enable a single battery cell-
powered system. The higher frequencies allow reasonably small,
external components for RC filtering when used as a DAC for bias
adjustments.
**When the part is in sleep mode, the HFCK is shut down. In this
case, PWM frequencies above 32kHz are not available (see
SPWME in the SLEEP_CFG Register section).
48 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
PWM_THTP Register (Power-On State: 0000 0000 0000 0000)
MSB
PWMTH7
PWMTH6
PWMTH5
PWMTH4
PWMTH3
PWMTH2
PWMTP2
PWMTH1
PWMTP1
PWMTH0
LSB
PWMTP7
PWMTP6
PWMTP5
PWMTP4
PWMTP3
PWMTP0
The PWM_THTP register contains the bits that set the
PWM on-time and period.
WATCHDOG Register (Power-On State: N/A)
Writing to the WATCHDOG register address sets the
watchdog timer to 0ms. If the watchdog is enabled
(WDE = 1) and the WATCHDOG register is not written
to before the 750ms expiration, RESET asserts low for
250ms and the watchdog timer restarts at 0ms when
the watchdog timer is enabled. There are no data bits
for this register and the watchdog timer is reset on the
rising edge of SCLK during the ADR0 bit in the
WATCHDOG register address control byte. Figure 19
shows an example of watchdog timing.
PWMTH<7:0>: PWM time high bits. These bits define
the PWM on (or high) time and when combined with the
PWMTP<7:0> bits, they determine the duty cycle and
period. The on-time duty cycle is defined as:
(PWMTH<7:0> + 1) / (PWMTP<7:0> + 1)
To get 50% duty cycle, set PWMTH<7:0> to 127 deci-
mal and PWMTP<7:0> to 255 decimal. A 100% duty
cycle (i.e., always on) is possible with a value of
PWMTH<7:0> ≥ PWMTP<7:0> > 0. A 0% duty cycle is
possible by setting PWMTH<7:0> = 0 or PWME = 0 in
the PWM_CTRL register. If the PWM is selected to drive
the UPIO_ pin(s), the ALH_ bit(s) (UPIO_CTRL register)
determine the on-time polarity at the beginning of the
PWM cycle. If ALH_= 1, the on-time at the start of the
NORM_MD Register (Power-On State: N/A)
Exit sleep mode and enter normal mode by writing to
the NORM_MD register. The specific normal-mode
state of all circuit blocks is set by the user, who must
configure the individual power-enable bits before enter-
ing sleep mode (Table 15). There are no data bits for
this register and normal mode begins on the rising
edge of SCLK during the ADR0 bit in the NORM_MD
register address control byte.
PWM period causes a logic-high level (DV
or
DD
CPOUT) at the UPIO_ pin and when ALH_= 0, it causes
a logic-low level (DGND) during the on-time. When the
PWM output drives the SWA/B switches, the SWA(B)H
or SWA(B)L bits in the PWM_CTRL register, determine
which PWM phase closes these switches. The SPDT1
and SPDT2 switches do not have PWM polarity inver-
sion bits (see the SPDT1<1:0> and SPDT2<1:0> bit
descriptions in the SW_CTRL Register section) but their
effective polarity is set by how the switches are con-
nected externally. The power-on default is 00 hex.
SLEEP Register (Power-On State: N/A)
Enter sleep mode by writing to the SLEEP register. This
low-power state overrides most of the normal power-
control bits. Table 15 shows which functions are off,
which functions are unaffected (ADE, RTCE, LSDE, and
HYSE), and which functions are controlled by special
sleep-mode bits (SOSCE, SCK32E, and SPWME) while
in sleep mode. There are no data bits for this register
and sleep mode begins on the rising edge of SCLK
during the ADR0 bit in the SLEEP register address con-
trol byte.
PWMTP<7:0>: PWM time period bits. These bits con-
trol the PWM output period defined. The PWM output
period is defined as:
(PWMTP<7:0> + 1) / (PWM input frequency)
Set the PWM input frequency by selecting the
FSEL<2:0> bits as described in Table 14. The power-
on default is 00 hex.
______________________________________________________________________________________ 49
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Table 15. Normal-Mode and Sleep-Register Summary
REGISTER
NAME
CIRCUIT BLOCK
DESCRIPTION
POR DEFAULT
NORMAL MODE
SLEEP
ADC
ADC
DACA/OP3
DACB/OP2
OP1
ADCE = 0
DAE/OP3E = 0
DBE/OP2E = 0
OP1E = 0
ADCE
DAE/OP3E
DBE/OP2E
OP1E
OFF
OFF
OFF
OFF
DACA_OP,
DACB_OP
Reference Buffer Gain and
Enable
REFV<1:0> = 00
REFV<1:0>
OFF
REF_SDC
Signal-Detect Comparator
Time-of-Day Alarm Enable
SDCE = 0
ADE = 0
SDCE
ADE
OFF
ADE
RTC
RTCE = 1
OSCE = 1
RTCE
OSCE
RTCE
CK32 Xtal Oscillator
SOSCE
CLK_CTRL
CK32 Output Buffer
CK32E = 1
CK32E
SCK32E
High-Frequency Clock
HFCE = 1
CLKE = 1
HFCE
CLKE
OFF
OFF
High-Frequency Clock Output
Buffer
FLL Enable
FLLE = 1
WDE = 0
FLLE
WDE
OFF
OFF
Watchdog Timer
PWM_CTRL
PS_VMONS
PWM
PWME = 0
PWME
SPWME
Linear Regulator
LDOE = 0
CPE = 0
LDOE
CPE
OFF
OFF
Charge-Pump Doubler
CPOUT Voltage Monitor
CPDE = 0
CPDE
OFF
1.8V DV
Monitor
LSDE = 1
LSDE
LSDE
HYSE
OFF
DD
1.8V Monitor Hysteresis
Temperature Sense Source
UPIO_ Function
HYSE = 0
HYSE
TEMP_CTRL
UPIO_CTRL
IMUX<1:0> = 00
UP_MD<3:0> = 0 hex
PUP_ = 1
IMUX<1:0>
UP_MD<3:0>
PUP_
UP_MD<3:0>
PUP_
UPIO_ Pullup
UPIO_ Supply Voltage
UPIO_ Assertion Level
SV_ = 0
SV_
SV_
ALH_ = 0
ALH_
ALH_
50 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
SLEEP_CFG Register (Power-On State: 1100 XXXX)
MSB
LSB
SLP (ADR0)
SOSCE
SCK32E
SPWME
SHDN
X
X
X
X
The SLEEP_CFG register allows users to program spe-
cific behavior for the 32kHz oscillator, buffer, and PWM
in sleep mode. It also contains a sleep-control bit (SLP)
to enable sleep mode.
SPWME: Sleep mode PWM enable bit. SPWME = 1
enables the internal PWM in sleep mode and SPWME =
0 disables it in sleep mode, regardless of the state of the
PWME bit.
SLP (ADR0): Sleep bit. The SLP bit is the LSB in the
SLEEP_CFG address control byte. Set SLP = 1 to
assert the SHDN bit and enter sleep mode. Writing the
register with SLP = 0 or reading with SLP = 0 or SLP =
1 has no effect on the SHDN bit.
Input frequencies are limited to 32.768kHz or lower
since the high-frequency clock is disabled in sleep
mode. SOSCE must be asserted to have 32kHz avail-
able as an input to the PWM. The power-on default is 0.
SHDN: Shutdown bit. This bit is read only. SHDN is
asserted by writing to the SLEEP register address or by
writing to the SLEEP_CFG register with SLP = 1. When
SHDN is asserted, the device is in sleep mode even if
the SLEEP or SLEEP function on the UPIO is deassert-
ed. The SHDN bit is deasserted by writing to the
NORM_MD register or by other defined events. Events
that cause SHDN to be deasserted are a day alarm or
an edge on the UPIO wake-up pin causing wake-up to
be asserted. The power-on default is 0.
SOSCE: Sleep mode 32kHz crystal oscillator enable
bit. SOSCE = 1 enables the 32kHz oscillator in sleep
mode and SOSCE = 0 disables it in sleep mode,
regardless of the state of the OSCE bit. The power-on
default is 1.
SCK32E: Sleep-mode CK32K-pin output-buffer enable
bit. SCK32E = 1 enables the 32kHz output buffer in
sleep mode and SCK32E = 0 disables it in sleep mode,
regardless of the state of the CK32E bit. The power-on
default is 1.
RESET
Q
D
D
Q
4Hz
CK
32K
Q
DIVIDE-
BY-8192
Q
CK
WDE
R
R
POR
WDW
WATCHDOG TIMER
750ms
1
4Hz CLOCK
2-BIT COUNTER
X
0
1
2
0
1
0
2
3
0
1
2
0
SPI WRITES
RESET
WATCHDOG
ADDRESS
WATCHDOG
ADDRESS
WDE = 1
WATCHDOG
ADDRESS
250ms
Figure 19. Watchdog Timer Architecture
______________________________________________________________________________________ 51
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
UPIO4_CTRL Register (Power-On State: 0000 1000)
MSB
LSB
UP4MD3
UP4MD2
UP4MD1
UP4MD0
PUP4
SV4
ALH4
LL4
UPIO4_CTRL register. This register configures the
UPIO4 pin functionality.
ALH4: Active logic-level assertion high UPIO4 bit. Set
ALH4 = 0 to define the input or output assertion level
for UPIO4 as low except when in GPI and GPO modes.
Set ALH4 = 1 to define the input or output assertion
level as high. For example, asserting ALH4 defines the
UPIO4 output signal as ALARM, while deasserting
ALH4 defines it as ALARM. Similarly, asserting ALH4
defines the UPIO4 input signal as WU, while deassert-
ing ALH4 defines it as WU. The power-on default is 0.
UP4MD<3:0>: UPIO4-mode selection bits. These bits
configure the mode for the UPIO4 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
PUP4: Pullup UPIO4 control bit. Set PUP4 = 1 to enable
a weak pullup resistor on the UPIO4 pin and set PUP4 =
0 to disable it. The pullup resistor is connected to either
DV
or CPOUT as programmed by the SV4 bit. The
DD
LL4: Logic-level UPIO4 bit. When UPIO4 is configured
as GPO, LL4 = 0 sets the output to a logic-low and LL4
= 1 sets the output to a logic-high. A read of LL4
returns the voltage level at the UPIO4 pin at the time of
the read regardless of how it is programmed. The
power-on default is 0.
pullup is enabled only when UPIO4 is configured as an
input. Open-drain behavior can be simulated at UPIO4
by setting the mode to GPO with LL4 = 0 and by chang-
ing the mode to GPI with PUP4 = 0, allowing external
high pullup. The power-on default is 1.
SV4: Supply-voltage UPIO4 selection bit. Set SV4 = 0
to select DV
as the supply voltage for the UPIO4 pin
DD
and set SV4 = 1 to select CPOUT as the supply volt-
age. The selected supply voltage applies to all modes
for the UPIO4 pin. The power-on default is 0.
UPIO3_CTRL Register (Power-On State: 0000 1000)
MSB
LSB
UP3MD3
UP3MD2
UP3MD1
UP3MD0
PUP3
SV3
ALH3
LL3
UPIO3_CTRL register. This register configures the
UPIO3 pin functionality.
ALH3: Active logic-level assertion high UPIO3 bit. Set
ALH3 = 0 to define the input or output assertion level
for UPIO3 as low except when in GPI and GPO modes
and set ALH3 = 1 to define the input or output assertion
level as high. For example, asserting ALH3 defines the
UPIO3 output signal as ALARM, while deasserting
ALH3 defines it as ALARM. Similarly, asserting ALH3
defines the UPIO3 input signal as WU, while deassert-
ing ALH3 defines it as WU. The power-on default is 0.
UP3MD<3:0>: UPIO3-mode selection bits. These bits
configure the mode for the UPIO3 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
PUP3: Pullup UPIO3 control bit. Set PUP3 = 1 to enable
a weak pullup resistor on the UPIO3 pin and set PUP3
= 0 to disable it. The pullup resistor is connected to
either DV
or CPOUT as programmed by the SV3 bit.
DD
LL3: Logic-level UPIO3 bit. When UPIO3 is configured
as GPO, LL3 = 0 sets the output to a logic-low and LL3
= 1 sets the output to a logic-high. A read of LL3
returns the voltage level at the UPIO3 pin at the time of
the read regardless of how it is programmed. The
power-on default is 0.
The pullup is enabled only when UPIO3 is configured
as an input. Open-drain behavior can be simulated at
UPIO3 by setting the mode to GPO with LL3 = 0 and by
changing the mode to GPI with PUP3 = 0, allowing
external high pullup. The power-on default is 1.
SV3: Supply-voltage UPIO3 selection bit. Set SV3 = 0
to select DV
as the supply voltage for the UPIO3 pin
DD
and set SV3 = 1 to select CPOUT as the supply volt-
age. The selected supply voltage applies to all modes
for the UPIO3 pin. The power-on default is 0.
52 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
UPIO2_CTRL Register (Power-On State: 0000 1000)
MSB
LSB
UP2MD3
UP2MD2
UP2MD1
UP2MD0
PUP2
SV2
ALH2
LL2
UPIO2_CTRL register. This register configures the
UPIO2 pin functionality.
ALH2: Active logic-level assertion high UPIO2 bit. Set
ALH2 = 0 to define the input or output assertion level
for UPIO2 as low except when in GPI and GPO modes
and set ALH2 = 1 to define the input or output assertion
level as high. For example, asserting ALH2 defines the
UPIO2 output signal as ALARM, while deasserting
ALH2 defines it as ALARM. Similarly, asserting ALH2
defines the UPIO2 input signal as WU, while deassert-
ing ALH2 defines it as WU. The power-on default is 0.
UP2MD<3:0>: UPIO2-mode selection bits. These bits
configure the mode for the UPIO2 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
PUP2: Pullup UPIO2 control bit. Set PUP2 = 1 to
enable a weak pullup resistor on the UPIO2 pin and set
PUP2 = 0 to disable it. The pullup resistor is connected
to either DV
or CPOUT as programmed by the SV2
DD
LL2: Logic-level UPIO2 bit. When UPIO2 is configured
as GPO, LL2 = 0 sets the output to a logic-low and LL2
= 1 sets the output to a logic-high. A read of LL2
returns the voltage level at the UPIO2 pin at the time of
the read regardless of how it is programmed. The
power-on default is 0.
bit. The pullup is enabled only when UPIO2 is config-
ured as an input. Open-drain behavior can be simulated
at UPIO2 by setting the mode to GPO with LL2 = 0 and
by changing the mode to GPI with PUP2 = 0, allowing
external high pullup. The power-on default is 1.
SV2: Supply-voltage UPIO2 selection bit. Set SV2 = 0
to select DV
as the supply voltage for the UPIO2 pin
DD
and set SV2 = 1 to select CPOUT as the supply volt-
age. The selected supply voltage applies to all modes
for the UPIO2 pin. The power-on default is 0.
UPIO1_CTRL Register (Power-On State: 0000 1000)
MSB
LSB
UP1MD3
UP1MD2
UP1MD1
UP1MD0
PUP1
SV1
ALH1
LL1
UPIO1_CTRL register. This register configures the
UPIO1 pin functionality.
ALH1: Active logic-level assertion high UPIO1 bit. Set
ALH1 = 0 to define the input or output assertion level
for UPIO1 as low except when in GPI and GPO modes
and set ALH1 = 1 to define the input or output assertion
level as high. For example, asserting ALH1 defines the
UPIO1 output signal as ALARM, while deasserting
ALH1 defines it as ALARM. Similarly, asserting ALH1
defines the UPIO1 input signal as WU, while deassert-
ing ALH1 defines it as WU. The power-on default is 0.
UP1MD<3:0>: UPIO1-mode selection bits. These bits
configure the mode for the UPIO1 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
PUP1: Pullup UPIO1 control bit. Set PUP1 = 1 to
enable a weak pullup resistor on the UPIO1 pin and set
PUP1 = 0 to disable it. The pullup resistor is connected
to either DV
or CPOUT as programmed by the SV1
DD
LL1: Logic-level UPIO1 bit. When UPIO1 is configured
as GPO, LL1 = 0 sets the output to a logic-low and LL1
= 1 sets the output to a logic-high. A read of LL1
returns the voltage level at the UPIO1 pin at the time of
the read regardless of how it is programmed. The
power-on default is 0.
bit. The pullup is enabled only when UPIO1 is config-
ured as an input. Open-drain behavior can be simulated
at UPIO1 by setting the mode to GPO with LL1 = 0 and
by changing the mode to GPI with PUP1 = 0, allowing
external high pullup. The power-on default is 1.
SV1: Supply-voltage UPIO1 selection bit. Set SV1 = 0
to select DV
as the supply voltage for the UPIO1 pin
DD
and set SV1 = 1 to select CPOUT as the supply volt-
age. The selected supply voltage applies to all modes
for the UPIO1 pin. The power-on default is 0.
______________________________________________________________________________________ 53
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Table 16. UPIO Mode Configuration
MODE
UP4MD<3:0>, UP3MD<3:0>,
UP2MD<3:0>, UP1MD<3:0>
DESCRIPTION
MAX1358
MAX1359
MAX1360
General-purpose digital input. Active edges detected
by UPR_ or UPF_ status register bits. ALH_ has no
effect with this setting.
0
0
0
0
GPI
GPI
GPI
General-purpose digital output. Logic level set by LL_
bit. ALH_ has no effect with this setting.
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
GPO
GPO
GPO
X
Digital input. DAC A buffer switch control. See the SWA
bit description in the SW_CTRL Register section.
SWA or SWA SWA or SWA
Digital input. DAC B buffer switch control. See the SWB
bit description in the SW_CTRL Register section.
SWB or SWB
X
X
SPDT1 or
SPDT1
SPDT1 or
SPDT1
SPDT1 or
SPDT1
Digital input. SPDT1 switch control. See the SPDT1<1:0>
bit description in the SW_CTRL Register section.
SPDT2 or
SPDT2
SPDT2 or
SPDT2
SPDT2 or
SPDT2
Digital input. SPDT2 switch control. See the SPDT2<1:0>
bit description in the SW_CTRL Register section.
Sleep-mode digital input. Overrides power-control
register and puts the part into sleep mode when
asserted. When deasserted, power mode is determined
by the SHDN bit.
SLEEP or
SLEEP
SLEEP or
SLEEP
SLEEP or
SLEEP
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
WU or WU
WU or WU
WU or WU Wake-up digital input. Asserted edge clears SHDN bit.
Reserved
Reserved
Reserved Reserved. Do not use these settings.
PWM digital output. Signal defined by the PWM_CTRL
register. PWM on (or high or “1”); assertion level defined
by the ALH_ bit. When PWM is disabled (PWME = 0),
PWM or
PWM
PWM or
PWM
PWM or
PWM
1
1
0
1
1
0
1
0
the UPIO pin idles high (DV
or CPOUT) if ALH = 1,
DD
and low (DGND) if ALH = 0.
Power-supply shutdown digital output. Equivalent to
SHDN bit. Power-on default of GPI with pullup ensures
initial power-supply turn-on when UPIO is connected to
a power supply with a SHDN input.
SHDN or
SHDN
SHDN or
SHDN
SHDN or
SHDN
AL_DAY or
AL_DAY
AL_DAY or
AL_DAY
AL_DAY or RTC alarm digital output. Asserts for time-of-day alarm
AL_DAY events; equivalent to ALD in STATUS register.
Reserved Reserved. Do not use these settings.
1
1
1
1
0
1
1
0
Reserved
Reserved
ADC data-ready digital output. Asserts when analog-to-
digital conversion or calibration completes. Not masked
by MADD bit.
DRDY or
DRDY
DRDY or
DRDY
DRDY or
DRDY
1
1
1
1
Note: When multiple UPIO inputs are configured for the same input function, the inputs are OR’ed together.
54 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
UPIO_SPI Register (Power-On State: 0000 XXXX)
MSB
LSB
UP4S
UP3S
UP2S
UP1S
X
X
X
X
UPIO SPI pass-through control register. These bits map
the serial interface signals to the UPIO pins, allowing
the DAS (MAX1358/MAX1359/MAX1360) to drive other
UP4S: UPIO4 SPI pass-through-mode enable bit. A
logic 1 maps the inverted CS signal to the UPIO4 pin.
Therefore, UPIO4 is low (near DGND) when SPI pass-
devices at CPOUT or DV
voltage levels, depending
through mode is active, and is high (near DV
or
DD
DD
on the SV_ bit setting found in the UPIO_CTRL register.
Individual bits are provided to set only the desired
UPIO inputs to the SPI pass-through mode. This mode
becomes active when CS is driven high to complete the
write to this register, and remains active as long as CS
stays high (i.e., multiple pass-through writes are possi-
ble). The SPI pass-through mode is deactivated imme-
diately when CS is pulled low for the next DAS
(MAX1358/MAX1359/MAX1360) write.
CPOUT) when the mode is inactive. A logic 0 disables
the UPIO4 SPI pass-through mode. The power-on
default is 0.
UP3S: UPIO3 SPI pass-through-mode enable bit. A
logic 1 maps the SCLK signal to UPIO3 (directly with no
inversion), while a logic 0 disables the UPIO3 SPI pass-
through mode. The power-on default is 0.
UP2S: UPIO2 SPI pass-through-mode enable bit. A
logic 1 maps the DIN signal to UPIO2 (directly with no
inversion), while a logic 0 disables the UPIO2 SPI pass-
through mode. The power-on default is 0.
The UPIO_ state (both before and after the SPI pass-
through mode) is set by the UP_MD<3:0> and LL_ bits.
When a UPIO is configured for SPI pass-through mode
and the CS is high, UPR_, UPF_, and LL_ continue to
detect UPIO_ edges, which can still generate interrupts.
See Figure 20 for an SPI pass-through timing diagram.
UP1S: UPIO1 SPI pass-through-mode enable bit. A
logic 1 maps the UPIO1 input signal to DOUT (directly
with no inversion), while a logic 0 disables the UPIO1
SPI pass-through mode. The power-on default is 0.
WRITE TO DAS TO ENABLE SPI MODE
NORMAL WRITE TO DAS
WRITE THROUGH DAS TO UPIO DEVICE
CS
SCLK
DIN
D
D
D
D
D
D
D
D
E
E
E
E
X
X
X
E
X
D
D
D
D
D
D
D
D
0
N
N-1
N-2
N-3
3
2
1
0
N
N-1
N-2
N-3
7
6
5
4
3
2
1
E
E
E
0
DOUT
3
2
1
SET BY UPIO4_CTRL REGISTER
SET BY UPIO3_CTRL REGISTER
SET BY UPIO2_CTRL REGISTER
SET BY UPIO1_CTRL REGISTER
UPIO4
UPIO3
UPIO2
UPIO1
SET BY UPIO4_CTRL REGISTER
SET BY UPIO3_CTRL REGISTER
SET BY UPIO2_CTRL REGISTER
SET BY UPIO1_CTRL REGISTER
E
E
E
E
N-3
X
X
X
E
X
N
N-1
N-2
E
E
E
0
3
2
1
Figure 20. SPI Pass-Through Timing Diagram
______________________________________________________________________________________ 55
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
SW_CTRL Register (Power-On State: 0000 00XX)
MSB
LSB
SWA
SWB
SPDT11
SPDT10
SPDT21
SPDT20
X
X
The switch-control register controls the two SPDT
switches (SPDT1 and SPDT2) and the two DACA and
DACB output buffer SPST switches (SWA and SWB).
Control these switches by the serial bits in this register,
by any of the UPIO pins that are enabled for that func-
tion, or by the PWM.
Table 18. SWB States (MAX1358 Only)
SWB BIT*
UPIO_*
PWM*
SWB SWITCH STATE
0
0
X
1
X
0
1
X
X
Switch open
X
Switch closed
X
Switch closed
SWA: (MAX1358/MAX1359) DACA output buffer SPST-
switch A control bit. The SWA bit, the UPIO inputs (if
configured), and the PWM (if configured) control the
state of the SWA switch as shown in Table 17. The
UPIO_ states of 0 and 1 in the table below correspond
to respective deasserted and asserted logic states as
defined by the ALH_ bit of the UPIO_CTRL register. If a
UPIO is not configured for this mode, its value applied
to the table below is 0. The PWM states of 0 and 1 in the
table below correspond to the respective PWM off (or
low) and on (or high) states defined by the SWAH and
SWAL bits (see the PWM_CTRL Register section). If the
PWM is not configured for this mode, its value applied
to the table below is 0. The power-on default is 0.
1
Switch closed
X = Don’t care.
*Switch SWB control is effectively an OR of the SWB bit, UPIO
pins, and PWM.
SPDT1<1:0>: Single-pole double-throw switch 1 con-
trol bits. The SPDT1<1:0> bits, the UPIO pins (if config-
ured), and the PWM (if configured) control the state of
the switch as shown in Table 19. The UPIO_ states of 0
and 1 in the table below correspond to respective
deasserted and asserted logic states as defined by the
ALH_ bit of the UPIO_CTRL register. If a UPIO is not
configured for this mode, its value applied to Table 19
is 0. The PWM states of 0 and 1 in Table 19 below cor-
respond to the respective PWM off (low) and on (high)
states defined by the SPD1 bit in the PWM_CTRL regis-
ter. If the PWM is not configured for this mode, its value
applied to Table 19 is 0. The power-on default is 00.
Table 17. SWA States
SWA BIT*
UPIO_*
PWM*
SWA SWITCH STATE
Switch open
0
X
X
1
0
X
1
X
0
1
X
X
Switch closed
Table 19. SPDT Switch 1 States
SPDT1<1:0> UPIO_* PWM* SPDT1 SWITCH STATE
Switch closed
Switch closed
0
0
0
0
1
1
1
1
0
X
X
1
0
X
X
1
0
X
1
X
0
X
1
X
0
1
X
X
0
1
X
X
SNO1 open, SNC1 open
SNO1 closed, SNC1 closed
SNO1 closed, SNC1 closed
SNO1 closed, SNC1 closed
SNC1 closed, SNO1 open
SNC1 open, SNO1 closed
SNC1 open, SNO1 closed
SNC1 open, SNO1 closed
X = Don’t care.
*Switch SWA control is effectively an OR of the SWA bit, UPIO
pins, and PWM.
SWB: (MAX1358 only) DACB output buffer SPST-switch
B control bit. The SWB bit, the UPIO inputs (if config-
ured), and the PWM (if configured) control the state of
the SWB switch as shown in Table 18. The UPIO_ states
of 0 and 1 in the table correspond to respective
deasserted and asserted logic states as defined by the
ALH_ bit (see the UPIO_CTRL Register section). If a
UPIO is not configured for this mode, its value applied
to the table is 0. The PWM states of 0 and 1 in the table
correspond to the respective PWM off (or low) and on
(or high) states defined by the SWBH and SWBL bits
(see the PWM_CTRL Register section). If the PWM is
not configured for this mode, its value applied to the
table is 0. The power-on default is 0.
X = Don’t care.
*Switch SPDT1 control is effectively an OR of the SPDT10 bit, the
UPIO pins, and the PWM output. The SPDT11 bit determines if
the switches open and close together or if they toggle.
56 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
SPDT2<1:0>: Single-pole double-throw switch 2 control
Table 20. SPDT Switch 2 States
SPDT2<1:0> UPIO_* PWM* SPDT2 SWITCH STATE
bits. The SPDT2<1:0> bits, the UPIO pins (if config-
ured), and the PWM (if configured) control the state of
0
0
0
0
1
1
1
1
0
X
X
1
0
X
X
1
0
X
1
X
0
X
1
X
0
1
X
X
0
1
X
X
SNO2 open, SNC2 open
SNO2 closed, SNC2 closed
SNO2 closed, SNC2 closed
SNO2 closed, SNC2 closed
SNC2 closed, SNO2 open
SNC2 open, SNO2 closed
SNC2 open, SNO2 closed
SNC2 open, SNO2 closed
the switch as shown in Table 20. The UPIO_ states of 0
and 1 in the table correspond to respective deasserted
and asserted logic states as defined by the ALH_ bit in
the UPIO_CTRL register. If a UPIO is not configured for
this mode, its value applied to Table 20 is 0. The PWM
states of 0 and 1 in Table 20 correspond to the respec-
tive PWM off (low) and on (high) states defined by the
SPD2 bit in the PWM_CTRL register. If the PWM is not
configured for this mode, its value applied to Table 20 is
0. The power-on default is 00.
X = Don’t care.
*Switch SPDT2 control is effectively an OR of the SPDT20 bit, the
UPIO pins, and the PWM output. The SPDT21 bit determines if
the switches open and close together or if they toggle.
TEMP_CTRL Register (Power-On State: 0000 XXXX)
MSB
LSB
IMUX1
IMUX0
IVAL1
IVAL0
X
X
X
X
The temperature-sensor control register controls the
internal and external temperature measurement.
IVAL<1:0>: Internal current-source value bits. Selects
the value of internal current source as shown in Table
22. The power-on default is 00.
IMUX<1:0>: Internal current-source MUX bits. Selects
the pin to be driven by the internal current sources as
shown in Table 21. The power-on default is 00.
Table 21. Selecting Internal Current Source
Table 22. Setting the Current Level
CURRENT SOURCE
IMUX1
IMUX0
CURRENT
TYPICAL CURRENT (µA)
IVAL1
IVAL0
Disabled
Internal temperature sensor
0
0
1
1
0
1
0
1
I
1
I
2
I
3
I
4
4
0
0
1
1
0
1
0
1
60
AIN1
AIN2
64
120
TEMP_CAL Register (Power-On State: Varies By Factory Calibration)
MSB
TGAIN7
TGAIN6
TGAIN5
TGAIN4
TGAIN3
TGAIN2
TOFFS0
TGAIN1
X
TGAIN0
LSB
TOFFS5
TOFFS4
TOFFS3
TOFFS2
TOFFS1
X
This register is the internal temperature sensor calibra-
tion register.
TOFFS<5:0>: Factory-preset temperature offset cor-
rection coefficient bits. This is the linear offset factor
used to derive absolute temperature values from tem-
perature values measured with the internal temperature
TGAIN<7:0>: Factory-preset temperature gain correc-
tion coefficient bits. This is the linear scaling factor used
to derive absolute temperature values from temperature
values measured with the internal temperature sensor
sensor (T
= T
x T
+ T
). This
OFFS
ACTUAL
MEAS
GAIN
method does not correct for delta V absolute voltage
BE
measurement errors, and assumes the measurement
was taken with a reference voltage that is either exactly
1.250V, or an exact value known by the user. The errors
being corrected by this factor are variables in the inter-
nal temperature-sensing diode. This factor is based on
characterization data. The power-on default varies.
(T
= T
x T
+ T
). This method does
ACTUAL
MEAS
GAIN
OFFS
not correct for delta V absolute voltage measurement
BE
errors, and assumes the measurement is taken with a
reference voltage that is either exactly 1.250V, or an
exact value known by the user. The errors being correct-
ed by this factor are variables in the internal tempera-
ture-sensing diode. This factor is programmed to typical
values. The power-on default varies.
______________________________________________________________________________________ 57
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
IMSK Register (Power-On State: 1111 011X 1111 1111)
MSB
MLDVD
MLCPD
MADO
MSDC
MCRDY
MUPF4
MADD
MALD
X
LSB
MUPR4
MUPR3
MUPR2
MUPR1
MUPF3
MUPF2
MUPF1
The IMSK register determines which bits of the STATUS
register generate an interrupt on INT. The bits in this
register do not mask output signals routed to UPIO
since the output signals are masked by disabling that
UPIO function.
MCRDY = 1 to mask the CRDY status bit interrupt. The
power-on default value is 0.
MADD: ADD status bit mask. Set MADD = 0 to enable
the ADD status bit interrupt to INT and set MADD = 1 to
mask the ADD status bit interrupt. The power-on default
value is 1.
MLDVD: LDVD status bit mask. Set MLDVD = 0 to
enable the LDVD status bit interrupt to INT and set
MLDVD = 1 to mask the LDVD status bit interrupt. The
power-on default value is 1.
MALD: ALD status bit mask. Set MALD = 0 to enable
the ALD status bit interrupt to INT and set MALD = 1 to
mask the ALD status bit interrupt. The power-on default
value is 1.
MLCPD: LCP status bit mask. Set MLCP = 0 to enable
the LCP status bit interrupt to INT and set MLCP = 1 to
mask the LCP status bit interrupt. The power-on default
value is 1.
MUPR<4:1>: UPR<4:1> status bits mask. Set MUPR_ =
0 to enable the UPR_ status bit interrupt to INT and set
MUPR_ = 1 to mask the UPR_ status bit interrupt. (_ =
1, 2, 3, or 4 and corresponds to the UPIO1, UPIO2,
UPIO3, or UPIO4 pins, respectively.) The power-on
default value is F hex.
MADO: ADO status bit mask. Set MADO = 0 to enable
the ADO status bit interrupt to INT and set MADO = 1 to
mask the ADO status bit interrupt. The power-on default
value is 1.
MUPF<4:1>: UPF<4:1> status bits mask. Set MUPF_ =
0 to enable the UPF_ status bit interrupt to INT and set
MUPF_ = 1 to mask the UPF_ status bit interrupt. (_ = 1,
2, 3, or 4 and corresponds to the UPIO1, UPIO2,
UPIO3, or UPIO4 pins, respectively.) The power-on
default value is F hex.
MSDC: SDC status bit mask. Set MSDC = 0 to enable
the SDC status bit interrupt to INT and set MSDC = 1 to
mask the SDC status bit interrupt. The power-on default
value is 1.
MCRDY: CRD status bit mask. Set MCRDY = 0 to
enable the CRDY status bit interrupt to INT and set
PS_VMONS Register (Power-On State: 0010 01XX)
MSB
LSB
LDOE
CPE
LSDE
CPDE
HYSE
RSTE
X
X
This register is the power-supply and voltage monitors
control register.
able the DV
low-supply-voltage detector. The power-
DD
on default value is 1.
LDOE: Low-dropout linear-regulator enable bit. Set
LDOE = 1 to enable the low-dropout linear regulator to
provide the internal source voltage for the charge
pump. Set LDOE = 0 to disable the LDO, allowing an
external drive to the charge pump input through REG.
The power-on default value is 0.
CPDE: CPOUT low-supply voltage-detector power-
enable bit. Set CPDE = 1 to enable the +2.7V CPOUT
low-supply voltage-detector comparator and set CPDE =
0 to disable the CPOUT low-supply voltage-detector
comparator. The power-on default value is 0.
HYSE: DV
low-supply voltage-detector hysteresis-
DD
CPE: Charge-pump enable bit. Set CPE = 1 to enable
the charge-pump doubler and set CPE = 0 to disable the
charge-pump doubler. The power-on default value is 0.
enable bit. Set HYSE = 1 to set the hysteresis for the
+1.8V (DV ) low-supply-voltage detector to +200mV and
DD
set HYSE = 0 to set the hysteresis to +20mV. On initial
power-up, the hysteresis is +20mV and can be pro-
grammed to 200mV once RESET goes high. Once pro-
LSDE: DV
low-supply voltage-detector power-
DD
enable bit. Set LSDE = 1 to enable the +1.8V (DV
)
DD
grammed to +200mV, the DV
falling threshold is +1.8V
DD
low-supply-voltage detector and set LSDE = 0 to dis-
58 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
nominally and the rising threshold is +2.0V nominally. The
hysteresis helps eliminate chatter when running directly off
RSTE: RESET output enable bit. Set RSTE = 1 to
enable RESET to be controlled by the +1.8V DV low-
supply-voltage detector and set RSTE = 0 to disable
this control. The power-on default is 1.
DD
unregulated batteries. If DV
falls below +1.3V (typ), the
DD
power-on reset circuitry is enabled and the HYSE bit is
deasserted setting the hysteresis back to +20mV. The
power-on default is 0.
STATUS Register (Power-On State: 0000 000X 0000 0000)
MSB
LDVD
LCPD
ADOU
SDC
CRDY
UPF4
ADD
ALD
X
LSB
UPF1
UPR4
UPR3
UPR2
UPR1
UPF3
UPF2
The STATUS register contains the status bits of events in
various system blocks. Any status bits not masked in the
IMSK register cause an interrupt on INT. Some of the
status bit setting events (GPI, WAKEUP, ALARM, DRDY)
can be directed to UPIO_ to provide multiple µC inter-
rupt inputs. There are no specific mask bits for the UPIO
interrupt signals since the bits are effectively masked by
selecting a different function for UPIO. The STATUS bits
always record the triggering event(s), even for masked
bits, which do not generate an interrupt on INT. It is pos-
sible to set multiple STATUS bits during a single INT
interrupt event. Clear all status bits except for ADD and
ADOU by reading the STATUS register. During a STA-
TUS register read, INT deasserts when the first STATUS
data bit (LDVD) reads out (9th rising SCLK) and remains
deasserted until shortly after the last STATUS data bit
(~15ns). At this point, INT reasserts if any status bit is set
during the STATUS register read. If the STATUS register
is partially read (i.e., the read is aborted midway), none
of the status bits are cleared. New events occurring dur-
ing a STATUS register read, or events that persist after
reading the STATUS bits result in another interrupt
immediately after the STATUS register read finishes. This
is a read-only register.
ADOU: ADC overflow/underflow status bit. ADOU = 1
indicates an ADC underflow or overflow condition in the
current ADC result. New conversions that are valid
clear the ADOU bit. ADOU = 0 when the ADC data is
valid or the ADC is disabled (ADCE = 0). An underflow
condition occurs when the ADC data is theoretically
less than 0000 hex in unipolar mode and less than
8000 hex in bipolar mode. An overflow condition occurs
when the ADC data is theoretically greater than FFFF
hex in unipolar mode and greater than 7FFF hex in
bipolar mode. Use this bit to determine the validity of
an ADC result at the maximum or minimum code values
(i.e., 0000 hex or FFFF hex for unipolar mode and 8000
hex and 7FFF hex for bipolar mode). The power-on
default is 0. Reading the STATUS register does not
clear the ADOU bit.
SDC: Signal-detect comparator status bit. When SDC =
1, the positive input to the signal-detect comparator
exceeds the negative input plus the programmed thresh-
old voltage. The SDC bit clears during the STATUS regis-
ter read unless the condition remains true. The SDC bit
also deasserts when the signal-detect comparator pow-
ers down (SDCE = 0). The power-on default is 0.
CRDY: High-frequency-clock ready status bit. CRDY =
1 indicates a locked high-frequency clock to the 32kHz
reference frequency by the FLL. The CRDY bit clears
during the STATUS register read. This bit only asserts
after power-up or after enabling the FLL using the FLLE
bit. The power-on default is 0.
LDVD: Low DV
voltage-detector status bit. LDVD = 1
DD
indicates DV
is below the +1.8V threshold, otherwise
DD
LDVD = 0. LDVD clears during the STATUS register
read as long as the condition does not persist.
Otherwise, the LDVD bit reasserts immediately. If the
DV
low voltage detector is disabled, LDVD = 0. The
DD
ADD: ADC-done status bit. ADD = 1 indicates a com-
pleted ADC conversion or calibration. Clear the ADD bit
by reading the appropriate ADC data, offset, or gain-cali-
bration registers. The ADC status bit also clears when a
new ADC result updates to the data or calibration regis-
ters (i.e., it follows the assertion level of the UPIO =
DRDY signal). Reading the STATUS register does not
clear this bit. This bit is equivalent to the DRDY signal
available through UPIO_. The power-on default is 0.
power-on default is 0.
LCPD: Low CPOUT voltage-detector status bit. LCPD =
1 indicates CPOUT is below the +2.7V threshold, other-
wise LCPD = 0. LCPD clears during the STATUS regis-
ter read as long as the condition does not persist.
Otherwise the LCPD bit reasserts immediately. LCPD =
0 when the CPOUT low voltage detector is disabled.
The power-on default is 0.
______________________________________________________________________________________ 59
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ALD: Alarm (day) status bit. ALD = 1 when the value
programmed in ASEC<19:0> in the AL_DAY register
matches SEC<19:0> in the RTC register. Clear the ALD
bit by reading the STATUS register or by disabling the
day alarm (ADE = 0). The power-on default is 0.
When placing passive components in front of the
MAX1358/MAX1359/MAX1360, ensure a low enough
source impedance to prevent introducing gain errors to
the system. This configuration significantly limits the
amount of passive anti-aliasing filtering that can be
applied in front of the MAX1358/MAX1359/MAX1360.
See Table 3 for acceptable source impedances.
UPR<4:1>: User-programmable I/O rising-edge status
bits. UPR_ = 1 indicates a rising edge on the respec-
tive UPIO_ pin has occurred. Clear UPR_ by reading
the STATUS register. Rising edges are detected inde-
pendent of UPIO_ configuration, providing the ability to
capture and record rising input (e.g., WU) or output
(e.g., PWM) edge events on the UPIO_. Set the appro-
priate mask to determine if the edge will generate an
interrupt on INT. If the UPIO_ is configured as an out-
put, INT provides confirmation that an intended rising
edge output occurred and has reached the desired
Power-On Reset or Power-Up
After a power-on reset, the DV
voltage supervisor is
DD
enabled and all UPIOs are configured as inputs with
pullups enabled. The internal oscillators are enabled
and are output at CLK and CLK32K once the DV
DD
voltage supervisor is cleared and the subsequent time-
out period has expired. All interrupts are masked
except CRDY. Figure 21 illustrates the timing of various
signals during initial power-up, sleep mode, and wake-
up events. The ADC, charge pump, internal reference,
op amp(s), DAC(s), and switches are disabled after
power-up.
DV
or CPOUT level (i.e., was not loaded down exter-
DD
nally). The power-on default is 0.
UPF<4:1>: User-programmable I/O falling-edge status
bit. UPF_= 1 indicates a falling edge on the respective
UPIO_ has occurred. Clear UPF_ by reading the
STATUS register. Falling edges are detected indepen-
dent of UPIO_ configuration, providing the ability to cap-
ture and record falling input (e.g., WU) or output (e.g.,
PWM) edge events on the UPIO_. Set the appropriate
mask to determine if that edge should generate an inter-
rupt on the INT pin. If the UPIO is configured as an out-
put, the INT provides confirmation that an intended
falling edge output occurred at the pin and it reached
the desired DGND level. The power-on default is 0.
Power Modes
Two power modes are available for the MAX1358/
MAX1359/MAX1360; sleep and normal mode. In sleep
mode, all functional blocks are powered down except
the serial interface, data registers, internal bandgap,
wake-up circuitry (if enabled), DV
voltage supervisor
DD
(if enabled), and the 32kHz oscillator (if enabled),
which remain active. See Table 15 for details of the
sleep-mode and normal-mode power states of the vari-
ous internal blocks.
Each analog block can be shut down individually
through its respective control register with the excep-
tion of the bandgap reference.
Applications Information
Analog Filtering
The internal digital filter does not provide rejection
close to the harmonics of the modulator sample fre-
quency. However, due to high oversampling ratios in
the MAX1358/MAX1359/MAX1360, these bands typical-
ly occupy a small fraction of the spectrum and most
broadband noise is filtered. Therefore, the analog filter-
ing requirements in front of the MAX1358/MAX1359/
MAX1360 are considerably reduced compared to a
conventional converter with no on-chip filtering. In addi-
tion, because the device’s common-mode rejection
(60dB) extends out to several kHz, the common-mode
noise susceptibility in this frequency range is substan-
tially reduced.
Sleep Mode
Sleep mode is entered one of three ways:
• Writing to the SLEEP register address. The result is
the SHDN bit is set to 1.
• Asserting the SLEEP or SLEEP function on a UPIO
(SLEEP takes precedence over software writes or
wake-up events). The SHDN bit is unaffected.
• Asserting the SHDN bit by writing SLP = 1 in the
SLEEP_CFG register.
Entering sleep mode is an OR function of the UPIO or
SHDN bit. Before entering sleep mode, configure the
normal mode conditions.
Depending on the application, provide filtering prior to the
MAX1358/MAX1359/MAX1360 to eliminate unwanted fre-
quencies the digital filter does not reject. Providing addi-
tional filtering in some applications ensures that
differential noise signals outside the frequency band of
interest do not saturate the analog modulator.
Exit sleep mode and enter normal mode by one of the
following methods:
60 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
INITIAL POWER, WAKE-UP, AND SLEEP
2
1
XTAL B/W 32KIN AND 32KOUT PIN
1.8V
AV
DV
DD
DD
0v
2
1.8V
1
0v
HI
POR
LO
OSCE = 1
SOSCE = 1
OSCE = 1
CK32E = 1
HI
XIN, XOUT
(32kHz)
LO
CK32E = 1
SCK32E = 0
BUFFER DISABLED
HI
CK32K
(32kHz)
LO
HI
LO
HI
RESET
(OPEN-DRAIN)
INTERNAL
EXTERNAL
OUTPUT DISABLED,
BUT
PULLED LOW
INTERNAL
LOW DV DETECTOR
OUTPUT ENABLED
DD
LO
HI
UPIO(WU)
(INT. PULLUP)
t
WU
LO
t
DPU
HI
UPIO(SHDN)
INTERNAL
LO
t
DPD
HI
CLK
INTERNAL
LO
t
t
t
DFON
DFON
DFOF
INTERNAL
CRDY
HFCE = 1, FLLE = 1
HI
IF FLLE = 0, CRDY WILL
STAY LOW, DFON = 0 )
LO
t
t
DFI
DFI
HI
INT
LO
PWME = 0
PWME = 0
POWER SUPPLY OFF
SPWME = 1
UPIO(PWM)
TIED TO POWER
SUPPLY SHDN PIN
HI
LO
HI
POWER SUPPLY OFF
INTERNAL
DRDY
LO
HI
DOUT
TRI-STATED
LO
HI
SLEEP
WRITE
CS
LO
HI
SCLK,
DIN
LO
Figure 21. Initial Power-Up, Sleep Mode, and Wake-Up Timing Diagram with AV
> 1.8V
DD
______________________________________________________________________________________ 61
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
V /GAIN
REF
V
REF
/GAIN
V
REF
/GAIN
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
FULL-SCALE TRANSITION
V
REF
V
REF
1 LSB =
1 LSB =
x 2
(GAIN x 65,536)
(GAIN x 65,536)
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
0
65,533 65,535
1
2
3
-32,768
-1
0
+1
+32,765 +32,767
-32,766
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 22. ADC Unipolar Transfer Function
Figure 23. ADC Bipolar Transfer Function
• With the SHDN bit = 0, deassert the SLEEP or
SLEEP function on UPIO, only if SLEEP or SLEEP
function is used for entering sleep mode.
Driving UPIO Outputs to AV
Levels
DD
UPIO outputs can be driven to AV
levels in systems
DD
with separate AV
and DV
supplies. Disable the
DD
DD
charge-pump doubler by setting CPE = 0 in the
PS_VMONS register, and connect the system’s analog
• With the SLEEP or SLEEP function deasserted on
UPIO, clear the SHDN bit by writing to the normal-
mode register address control byte.
supply to AV
and CPOUT. Setting UPIO outputs to
DD
drive to CPOUT results in AV -referenced logic levels.
DD
• With the SLEEP or SLEEP function deasserted,
assert WU or WU (wake-up) function on UPIO.
Supply Voltage Measurement
supply voltage can be measured with the
The AV
DD
• With the SLEEP or SLEEP function deasserted, the
ADC by reversing the normal input and reference sig-
nals. The REF voltage is applied to one multiplexer
input and AGND is selected in the other. The AV
day alarm triggers.
Wake-Up
A wake-up event, such as an assertion of a UPIO con-
figured as WU or a time-of-day alarm causes the
MAX1358/MAX1359/MAX1360 to exit sleep mode, if in
sleep mode. A wake-up event in normal mode results
only in a wake-up event being recorded in the
STATUS register.
sig-
DD
FBA
FBB
MAX1358
MAX1359
RESET
OUTA
OUTB
DAC A
The RESET output pulls low for any one of the following
cases: power-on reset, DV
monitor trips and RSTE =
DD
REF
0, watchdog timer expires, crystal oscillator is attached,
and 32kHz clock not ready.
DAC B
The RESET output can be turned off through the RSTE
bit in the PS_VMONS register, causing DV
low sup-
DD
ply voltage events to issue an interrupt or poll through
the LDVD status bit. This allows brownout detection
µCs that operate with DV
< 1.8V.
DD
THE MAX1359 HAS ONE DAC.
Figure 24. DAC Unipolar Output Circuit
62 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
V
REF
R
R
2
1
10kΩ
FBA
MAX1358
MAX1359
+3.3V
FB_
10kΩ
V
OUT
OUTA
OUTB
DAC_
DAC A
DAC B
OUT_
-3.3V
10kΩ
REF
FBB
R = R
2
1
MAX1358
MAX1359
V
= 1.25V
REF
10kΩ
Figure 26. DAC Bipolar Output Circuit
ceramic capacitor. For improved performance, place the
bypass capacitors as close to the device as possible.
THE MAX1359 HAS ONE DAC.
= 1.25V
ADC Transfer Functions
Figures 22 and 23 provide the ADC transfer functions
for unipolar and bipolar mode. The digital output code
format is binary for unipolar mode and two’s comple-
ment for bipolar mode. Calculate 1 LSB using the fol-
lowing equations:
V
REF
Figure 25. DAC Unipolar Rail-to-Rail Output Circuit
nal is then switched in as the ADC reference voltage
and a conversion is performed. The AV
then be calculated directly as:
value can
DD
1 LSB (Unipolar Mode) = V
/ (Gain x 65,536)
/ (Gain x 65,536)
REF
V
= (V
x Gain x 65536) / N
REF
1 LSB (Bipolar Mode) = 2V
AVDD
REF
where V
is the reference voltage for the ADC, Gain
where V
equals the reference voltage at REF and
REF
REF
is the PGA gain before the ADC, and N is the ADC
result. Note the AV voltage must be greater than the
Gain equals the PGA gain.
DD
In unipolar mode, the output code ranges from 0 to
65,535 for inputs from zero to full-scale. In bipolar
mode, the output code ranges from -32,768 to +32,767
for inputs from negative full-scale to positive full-scale.
gained-up REF voltage (AV
measurement must be done in unipolar mode.
> V
x GAIN). This
REF
DD
Power Supplies
AV
and DV
provide power to the MAX1358/
DD
DD
DAC Unipolar Output
For a unipolar output, the output voltages and the refer-
ence have the same polarity. Figure 24 shows the
MAX1358/MAX1359’s unipolar output circuit, which is
also the typical operating circuit for the DACs. Table 23
lists some unipolar input codes and their correspond-
ing output voltages.
MAX1359/MAX1360. The AV
powers up the analog
DD
section, while the DV
powers up the digital section.
DD
The power supply for both AV
and DV
ranges from
DD
and DV
DD
+1.8V to +3.6V. Both AV
must be greater
and DV
DD
DD
DD
than +1.8V for device operation. AV
can
DD
DD
connect to the same power supply. Bypass AV
to
AGND with a 10µF electrolytic capacitor in parallel with a
For larger output swing, see Figure 25. This circuit
shows the output amplifiers configured with a closed-
0.1µF ceramic capacitor and bypass DV
to DGND
DD
with a 10µF electrolytic capacitor in parallel with a 0.1µF
Table 23. Unipolar Code Table
Table 24. Bipolar Code Table
DAC CONTENTS
ANALOG OUTPUT
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
MSB
LSB
1111 1111 11
1000 0000 01
1000 0000 00
0111 1111 11
0000 0000 01
0000 0000 00
+V
+V
(1023/1024)
(513/1024)
1111 1111 11
1000 0000 01
1000 0000 00
0111 1111 11
0000 0000 01
0000 0000 00
+V
+V
(511/512)
REF
REF
(1/512)
REF
REF
+V
(512/1024) = +V
/ 2
0
REF
REF
(511/1024)
+V
+V
-V
-V
(1/512)
REF
REF
(1/1024)
0
(511/512)
REF
REF
-V
(512/512) = -V
REF
REF
______________________________________________________________________________________ 63
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
loop gain of +2V/V to provide 0 to 2.5V full-scale range
with the 1.25V reference.
can differentially measure directly across the external
transimpedance resistor, RF, eliminating any errors due
to voltages drifting over time, temperature, or supply
voltage. Figure 29 shows a traditional electrochemical
meter application.
DAC Bipolar Output
The MAX1358/MAX1359 DAC outputs can be config-
ured for bipolar operation using the application circuit
in Figure 26:
Temperature Measurement with
Two Remote Sensors
2N
1024
Use two diode-connected 2N3904 transistors for exter-
nal temperature sensing in Figure 30. Select AIN1 and
AIN2 through the positive and negative mux, respec-
tively. For internal temperature sensor measurements,
set MUXP<3:0> to 0111, and set MUXN<3:0> to 0000.
The analog input signals feed through a PGA to the
ADC for conversion.
V
= V
− 1
OUT
REF
where N is the decimal value of the DAC’s binary input
code.
Table 24 shows digital codes (offset binary) and corre-
sponding output voltages for Figure 26 assuming
R1 = R2.
Strain-Gauge Measurement with
Remote Temperature Sensor
Optical Reflectometry Application with
Dual LED and Single Photodiode
Figure 31 shows the MAX1360 in a strain-gauge mea-
surement application with a remote diode-connected
2N3904 transistor temperature sensor. Rs is the sense
resistor used for making temperature measurements.
See the Temperature with two Remote Sensors section
for more details.
Figure 27 illustrates the MAX1359 in a complete optical
reflectometry application with two transmitting LEDs
and one receiving photodiode. The LEDs transmit light
at a specific wavelength onto the sample strip and the
photodiode receives the reflections from the strip. Set
the DAC to provide appropriate bias currents for the
LEDs. Always keep the photodiodes reverse-biased or
zero-biased. SPDT1 and SPDT2 switch between the
two LEDs.
Programmable-Gain Instrumentation
Amplifier
Use two op amps and two SPDT switches to implement
a programmable-gain instrumentation amplifier as
shown in Figure 32.
Electrochemical Sensor Operation
The MAX1358/MAX1359/MAX1360 family interface with
electrochemical sensors. The 10-bit DACs with the
force-sense buffers have the flexibility to connect to
many different types of sensors. Figure 28 shows how
to interface the MAX1360 in a self-biased electrochemi-
cal meter application. An external precision resistor
completes the transimpedance amplifier configuration
to convert the current generated by the sensor to a
voltage measurement using the ADC. The induced
error from this source is negligible due to FBA’s
extremely low input bias current. Internally, the ADC
PWM Applications
The MAX1358/MAX1359/MAX1360 integrated PWM is
available for LCD bias control, sensor-bias voltage trim-
ming, buzzer drive, and duty-cycled sleep-mode
power-control schemes. Figure 33 shows the
MAX1358/MAX1359/MAX1360 performing LCD bias
control. A sensor-bias voltage trimming application is
shown in Figure 34. Figures 36 and 37 show the PWM
circuitry being used in a single-ended and differential
piezoelectric buzzer-driving application.
64 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
V
CP
TXD
RXD
SERIAL-PORT INTERFACE
V
SS
V
SS
µC
V
BAT
EEPROM
V
SS
MOSI
V
CC
SI
SO
MISO
SCK
CS1
SCK
CS
GND
V
SS
V
CP
MAX1359
LCD MODULE
BDIN
BDOUT
BSCLK
BCS2
UPIO1
UPIO2
UPIO3
UPIO4
DIN
DOUT
SCLK
CS
V
SS
CS2
CS2
IN2-
MEM
UP
RESET
INT
RESET
INPUT
X2IN
INPUT
INPUT
INPUT
IN2+
OUT2
HIGH-FREQUENCY MICRO CLOCK
32kHz MICRO CLOCK
DOWN
CLK
IN1-
32KIN
CLK32K
V
SS
AV
DD
IN1+
V
BAT
OUT1
DV
DD
V
SS
V
SS
V
DD
2 AAA OR
1 LITHIUM
COIN CELL
1nF
SNO2
SCM2
ADC
TEST
STRIP
V
AGND
DGND
SS
V
SS
SNC2
V
SS
PWM
DACA
AIN1
AIN2
AMBIENT LIGHT
LED SOURCES
V
CP
OUTA
32KIN
LED
SWA
FBA
V
CP
32.768kHz
SNO1
LED
SCM1
SNC1
32KOUT
DV
DD
LINEAR
REG
REG
CF+
REF
CHARGE-
V
SS
PUMP
DOUBLER
BG
CF-
CPOUT
V
CP
V
SS
V
SS
V
SS
Figure 27. Optical Reflectometry Application with Dual LED and Single Photodiode
______________________________________________________________________________________ 65
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
µC
V
CP
LCD GLA SS
COM<3:0>
SEG<23:0>
LCDBIAS
V
CP
SS
TXD
RXD
SERIAL-PORT INTERFACE
LCD
DRIVERS
V
SS
V
V
BAT
EEPROM
V
SS
MOSI
V
CC
SI
SO
MISO
SCK
CS1
SCK
CS
V
SS
GND
V
SS
MAX1360
CPOUT
UPIO2
DIN
PWM
LCDBIAS
PWRON
DOUT
SCLK
UPIO1
UPIO3
CPOUT
V
V
SS
SS
V
SS
FREQOUT
CS2
PIEZO
ALARM
CS2
STRIP INSERTED
CS
UPIO4
MEM
UP
RESET
INT
SNO1
SCM1
SNC1
SNO2
SCM2
SNC2
OUT1
RESET
INPUT
X2IN
INPUT
INPUT
INPUT
HIGH-FREQUENCY MICRO CLOCK
32kHz MICRO CLOCK
DOWN
CLK
32KIN
CLK32K
V
SS
AV
DD
V
BAT
TEST
STRIP
DV
DD
V
DD
2 AAA OR
1 LITHIUM
COIN CELL
IN1-
IN1+
OUT2
IN2-
V
SS
V
AGND
DGND
SS
V
SS
ADC
32KIN
IN2+
OUT3
IN3-
32.768kHz
32KOUT
IN3+
REF
DV
DD
LINEAR
BG
REG
REG
V
CF+
SS
CHARGE-
PUMP
DOUBLER
AIN1
AIN2
V
SS
REMOTE TEMPERATURE-
MEASUREMENT DIODE
CF-
CPOUT
V
CP
V
SS
V
SS
Figure 28. MAX1360 Self-Biased Electrochemical Meter Application Circuit
66 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
µC
V
CP
LCD GLA SS
COM<3:0>
SEG<23:0>
LCDBIAS
RX_WAKEUP
SERIAL-PORT INTERFACE
RXD
V
SS
LCD
DRIVERS
V
SS
BUZ_HI
BUZ_LO
PIEZO
ALARM
V
BAT
EEPROM
MOSI
V
CC
SI
V
SS
SO
MISO
SCK
CS1
SCK
CS
GND
V
SS
MAX1358
CPOUT
UPIO2
DIN
TXD
CS2
DOUT
UPIO1
UPIO3
RX_WAKEUP
CPOUT
PWM
LCDBIAS
SCLK
CS
CS2
STRIP INSERTED
UPIO4
V
SS
MEM
UP
RESET
INT
OUTA
SWA
FBA
RESET
INPUT
X2IN
INPUT
TEST
STRIP
INPUT
INPUT
HIGH-FREQUENCY MICRO CLOCK
32kHz MICRO CLOCK
DOWN
CLK
32KIN
CLK32K
V
SS
AV
DD
V
BAT
V
SS
DV
DACA
DD
V
DD
OUTB
SWB
FBB
2 AAA OR
1 LITHIUM
COIN CELL
ADC
V
AGND
DGND
SS
V
SS
DACB
SNO1
SCM1
SNC1
32KIN
OUT1
IN1-
IN1+
REF
32.768kHz
32KOUT
DV
DD
LINEAR
REG
BG
REG
CF+
SNO2
SCM2
SNC2
CHARGE-
PUMP
DOUBLER
V
SS
CF-
CPOUT
V
CP
V
AIN1
AIN2
SS
V
SS
REMOTE TEMPERATURE-
MEASUREMENT DIODE
V
SS
Figure 29. MAX1358 Electrochemical Meter Application Circuit (Traditional and Counter Configuration)
______________________________________________________________________________________ 67
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ADC Calibration
Internal to the MAX1358/MAX1359/MAX1360, the ADC
is 24 bits and is always in bipolar mode. The OFFSET
CAL and GAIN CAL data are also 24 bits. The conver-
sion to unipolar and the gain are performed digitally.
The default values for the OFFSET CAL and GAIN CAL
registers in the MAX1358/MAX1359/MAX1360 are
00 0000h and 80 0000h, respectively.
Grounding and Layout
For best performance, use PC boards with separate
analog and digital ground planes.
Design the PC board so that the analog and digital sec-
tions are separated and confined to different areas of
the board. Join the digital and analog ground planes at
one point. If the DAS (MAX1358/MAX1359/MAX1360) is
the only device requiring an AGND-to-DGND connec-
tion, connect planes to the AGND pin of the DAS. In
systems where multiple devices require AGND-to-
DGND connections, the connection should still be
made at only one point. Make the star ground as close
to the MAX1358/MAX1359/MAX1360 as possible.
The calibration works as follows:
ADC = (RAW - OFFSET) x Gain x PGA
where ADC is the conversion result in the DATA regis-
ter, RAW is the output of the decimation filter internal to
the MAX1358/MAX1359/MAX1360, OFFSET is the value
stored in the OFFSET CAL register, Gain is the value
stored in the GAIN CAL register, and PGA is the select-
ed PGA gain found in the ADC register as GAIN<1:0>.
In unipolar mode, all negative values return a zero
result and an additional gain of 2 is added.
Avoid running digital lines under the device because
these may couple noise onto the device. Run the ana-
log ground plane under the MAX1358/MAX1359/
MAX1360 to minimize coupling of digital noise. Make
the power-supply lines to the MAX1358/MAX1359/
MAX1360 as wide as possible to provide low-imped-
ance paths and reduce the effects of glitches on the
power-supply line.
For self-calibration, the offset value is the RAW result
when the inputs are shorted internally and the gain value
is 1 / (RAW - OFFSET) with the reference connected to
the input. This is done automatically when these modes
are selected. The self offset and gain calibration corrects
for errors internal to the ADC and the results are stored
and used automatically in the OFFSET CAL and GAIN
CAL registers. For best results, use the ADC in the same
configuration as the calibration. This pertains to conver-
sion rate only because the PGA gain and unipolar/bipo-
lar modes are performed digitally.
Shield fast-switching signals such as clocks with digital
ground to avoid radiating noise to other sections of the
board. Avoid running clock signals near the analog
inputs. Avoid crossover of digital and analog signals.
Good decoupling is important when using high-resolu-
tion ADCs. Decouple all analog supplies with 10µF
capacitors in parallel with 0.1µF HF ceramic capacitors
to AGND. Place these components as close to the
device as possible to achieve the best decoupling.
For system calibration, the offset and gain values cor-
rect for errors in the whole signal path including the
internal ADC and any external circuits in the signal
path. For the system calibration, a user-provided zero-
input condition is required for the offset calibration and
a user-provided full-scale input is required for the gain
calibration. These values are automatically written to
the OFFSET CAL and GAIN CAL registers. The order of
the calibrations should be offset followed by gain.
Crystal Layout
Follow basic layout guidelines when placing a crystal
on a PC board with a DAS to avoid coupled noise.
1) Place the crystal as close as possible to 32KIN and
32KOUT. Keeping the trace lengths between the
crystal and inputs as short as possible reduces the
probability of noise coupling by reducing the length
of the “antennae”. Keep the 32KIN and 32KOUT
lines close to each other to minimize the loop area
of the clock lines. Keeping the trace lengths short
also decreases the amount of stray capacitance.
The offset correction value is in two’s complement. The
default value is 000000h, 00...00b, or 0 decimal.
The gain correction value is an unsigned binary num-
ber with 23 bits to the right of the decimal point. The
largest number is therefore 1.1111...1b = 2 - 2-23 and
the smallest is 0.000...0b = 0, although it does not
make sense to use a number smaller than 0.1000...0b
= 0.5. The default value is 800000h, 1.000...0b or 1
decimal.
2) Keep the crystal solder pads and trace width to
32KIN and 32KOUT as small as possible. The larg-
er these bond pads and traces are, the more likely
it is that noise will couple from adjacent signals.
3) Place a guard ring (connect to ground) around the
crystal to isolate the crystal from noise coupled
from adjacent signals.
Changing the offset or gain calibration values does not
affect the value in the DATA register until a new conver-
sion has completed. This applies to all the mode bits
for PGA gain, unipolar/bipolar, etc.
4) Ensure that no signals on other PC board layers run
directly below the crystal or below the traces to
68 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
AIN1
PGA
16-BIT ADC
MUX
REF
AGND
AIN2
A
= 1, 2, 4, 8
V
2N3904
2N3904
MAX1358
MAX1359
MAX1360
MUX
AGND
A
= 1, 1.638, 2
V
C
REF
REF
TEMP
SENSOR
1.25V
REF
Figure 30. Temperature Measurement with Two Remote Sensors
AIN1
IN1+
IN1-
MAX1360
V
IN+
OUT1
SNO1
SNC1
OUT2
V
OUT
AIN2
A
= 1, 1.638, 2
V
R
R
3
2
C
R
REF
REF
1.25V
REF
AGND
IN1+
2N3904
SCM1
OUT1
R
IN1-
IN3+
R
R
1
1
IN2+
IN2-
V
IN-
OUT3
IN3-
SNO2
SNC2
AV
DD
R
R
SCM2
R
R
R
R
A
B
2
3
IN2+
OUT2
IN2-
R
R
C
D
MAX1359
MAX1360
Figure 32. Programmable-Gain Instrumentation Amplifier
Figure 31. Strain-Gauge Measurement with Remote
Temperature Sensor
32KIN and 32KOUT. The more the crystal is isolat-
ed from other signals on the board, the less likely it
is that noise will be coupled into the crystal.
Maintain a minimum distance of 5mm between any
digital signal and any trace connected to 32KIN or
32KOUT.
5) Place a local ground plane on the PC board layer
immediately below the crystal guard ring. This
helps to isolate the crystal from noise coupling from
signals on other PC board layers.
Note: The ground plane must be in the vicinity of the
crystal only and not on the entire board.
______________________________________________________________________________________ 69
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
DV CPOUT
DD
CPOUT
UPIO_
MAX1358
MAX1359
MAX1360
MUX
SV_
100kΩ
200kΩ
(1.8V
TO
µC
PWM
0.01µF
100kΩ
2.6V)
EN_
SEG
n
ALH_
LCD
DRIVERS
100kΩ
100kΩ
LCD
COM
m
Figure 33. LCD Contrast-Adjustment Application
Parameter Definitions
~1.25V
INL
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line is either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nulled. INL for
the MAX1358/MAX1359/MAX1360 is measured using
the endpoint method.
REF
~19kHz
MAX1360
VOLTAGE
RIPPLE <1mV
240kΩ
SNO1
350kΩ
SCM1
SNC1
PWM
~0.3V
60kΩ
SPDT1
0.1µF
AGND
DNL
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of greater than -1 LSB guarantees no
missing codes and a monotonic transfer function.
IN1+
IN1-
OUT1
I
T
TRANSDUCER
Gain Error
Gain error is the amount of deviation between the mea-
sured full-scale transition point and the ideal full-scale
transition point.
0.300V ( 1mV)
Figure 34. Sensor-Bias Voltage Trim Application
70 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
V
DD
AV
DV
DD
DD
MAX1358
MAX1359
MAX1360
DV
<10µA
CPOUT
DD
V
VOUT
DD
V
IN
MUX
SV_
V
µC
BATT
100µF
POWER SUPPLY
10MΩ
UPIO_
EN_
SHDN
PWM
PSCTL
ON-TIME <100ms TYP
10s PERIOD TYP
PSCTL
+3.3V
V
ALH_
DD
+2.3V
Figure 35. Power-Supply Sleep-Mode Duty-Cycle Control
Common-Mode Rejection
Common-mode rejection (CMR) is the ability of a
device to reject a signal that is common to both input
terminals. The common-mode signal can be either an
AC or a DC signal or a combination of the two. CMR is
often expressed in decibels.
DV
CPOUT
DD
MAX1358
MAX1359
MAX1360
MUX
SV_
CPOUT(+3.2V)
0V
1 TO 8kHz TYP
~10,000pF
1kΩ
Power-Supply Rejection Ratio (PSRR)
Power-supply rejection ratio (PSRR) is the ratio of the
input supply change (in volts) to the change in the
converter output (in volts). It is typically measured in
decibels.
UPIO_
PWM
Chip Information
ALH_
PROCESS: BiCMOS
Figure 36. Single-Ended Piezoelectric Buzzer Drive
______________________________________________________________________________________ 71
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
DV CPOUT
DD
MAX1358
MAX1359
MAX1360
CPOUT(+3.2V)
0V
MUX
SV_
1 TO 8kHz TYP
1kΩ
UPIO_
PWM
CPOUT
+
6.4V DIFF
-
~10,000pF
ALH_
-CPOUT
DV CPOUT
DD
MUX
SV_
1kΩ
UPIO_
CPOUT(~+3.2V)
0V
1 TO 8kHz TYP
ALH_
Figure 37. Differential Piezoelectric Buzzer Drive
72 ______________________________________________________________________________________
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Pin Configurations
30 29 28 27 26 25 24 23 22 21
30 29 28 27 26 25 24 23 22 21
31
32
33
34
35
36
37
38
39
40
20 OUT1
19 SNC2
18 SCM2
17 SNO2
16 SNC1
15 SCM1
AIN2
AIN1
REF
31
32
33
34
35
36
37
38
39
20 OUT1
19 SNC2
18 SCM2
17 SNO2
16 SNC1
15 SCM1
14 SNO1
13 32KIN
12 32KOUT
AIN2
AIN1
REF
REG
REG
CF-
CF-
MAX1359
CF+
MAX1358
CF+
14
13
12
11
SNO1
CPOUT
CPOUT
DV
DD
32KIN
32KOUT
RESET
DV
DD
DGND
UPIO1
DGND
11
RESET
UPIO1 40
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
TQFN
TQFN
30 29 28 27 26 25 24 23 22 21
31
32
33
34
35
36
37
38
39
40
20
OUT1
SNC2
SCM2
SNO2
SNC1
SCM1
SNO1
32KIN
AIN2
19
18
17
16
15
14
13
12
11
AIN1
REF
REG
CF-
MAX1360
CF+
CPOUT
DV
DD
32KOUT
RESET
DGND
UPIO1
1
2
3
4
5
6
7
8
9
10
TQFN
______________________________________________________________________________________ 73
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
1
E
21-0141
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
2
E
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
74 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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