MAX1385BETM+T [MAXIM]
Telecom Circuit, 1-Func, 7 X 7 MM, ROHS COMPLIANT, TQFN-48;
| 型号： | MAX1385BETM+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Telecom Circuit, 1-Func, 7 X 7 MM, ROHS COMPLIANT, TQFN-48 控制器 |
| 文件： | 总52页 (文件大小：502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4456; Rev 0; 2/09
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
General Description
Features
The MAX1385/MAX1386 set and control bias conditions
for dual RF LDMOS power devices found in cellular
base stations. Each device includes a high-side cur-
rent-sense amplifier with programmable gains of 2, 10,
and 25 to monitor LDMOS drain current over the 20mA
to 5A range. Two external diode-connected transistors
monitor LDMOS temperatures while an internal temper-
ature sensor measures the local die temperature of the
MAX1385/MAX1386. A 12-bit ADC converts the pro-
grammable-gain amplifier (PGA) outputs, external/inter-
nal temperature readings, and two auxiliary inputs.
♦ Integrated High-Side Drain Current-Sense PGA
with Gain of 2, 10, or 25
♦
0.5ꢀ Accuracy for Sense ꢁoltage ꢂetween ꢃ5mꢁ
and 250mꢁ
♦ Full-Scale Sense ꢁoltage of 100mꢁ with Gain of 25
♦ Full-Scale Sense ꢁoltage of 250mꢁ with Gain of 10
♦ Common-Mode Range of 5ꢁ to 30ꢁ Drain ꢁoltage
for LDMOS
♦ Adjustable Low Noise 0 to 5ꢁ, 0 to 10ꢁ Output
The two gate-drive channels, each consisting of 8-bit
coarse and 10-bit fine DACs and a gate-drive amplifier,
generate a positive gate voltage to bias the LDMOS
devices. The MAX1385 includes a gate-drive amplifier
with a gain of 2 and the MAX1386 gate-drive amplifier
provides a gain of 4. The 8-bit coarse and 10-bit fine
DACs allow up to 18 bits of resolution. The MAX1385/
MAX1386 include autocalibration features to minimize
error over time, temperature, and supply voltage.
Gate-ꢂias ꢁoltage Ranges with 10mA Gate Drive
♦ Fast Clamp to 0ꢁ for LDMOS Protection
♦ 8-ꢂit DAC Control of Gate-ꢂias ꢁoltage
♦ 10-ꢂit DAC Control of Gate-ꢂias Offset with
Temperature
♦ Internal Die Temperature Measurement
The MAX1385/MAX1386 feature an I2C/SPI™-compatible
serial interface. Both devices operate from a 4.75V to
5.25V analog supply (3.2mA supply current), a 2.7V to
5.25V digital supply (3.1mA supply current), and a 4.75V
to 11.0V gate-drive supply (4.5mA supply current). The
MAX1385/MAX1386 are available in a 48-pin thin QFN
package.
♦ External Temperature Measurement by Diode-
Connected Transistor (2N3904)
♦ Internal 12-ꢂit ADC Measurement of Temperature,
Current, and ꢁoltages
♦ Selectable I2C-/SPI-Compatible Serial Interface
400kHz/1.ꢃMHz/3.4MHz I2C-Compatible Control
for Settings and Data Measurement
16MHz SPI-Compatible Control for Settings
and Data Measurement
Applications
RF LDMOS Bias Control in Cellular Base Stations
♦ Internal 2.5ꢁ Reference
Industrial Process Control
♦ Three Address Inputs to Control Eight Devices in
I2C Mode
Ordering Information/Selector Guide
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
48 Thin QFN-EP*
48 Thin QFN-EP*
48 Thin QFN-EP*
48 Thin QFN-EP*
TEMP ERROR (°C)
ꢁ
(ꢁ)
GATE
5
MAX1385AETM+**
MAX1385BETM+
MAX1386AETM+**
MAX1386BETM+**
*EP = Exposed pad.
1
2
1
2
5
10
10
**Future product—contact factory for availability.
+Denotes a lead(Pb)-free/RoHS-compliant package.
2
Pin Configuration and Typical Operating Circuit (I C Mode)
appear at end of data sheet.
SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
AꢂSOLUTE MAXIMUM RATINGS
AV
DV
to AGND .........................................................-0.3V to +6V
to DGND.........................................................-0.3V to +6V
Digital Inputs
to DGND............-0.3V to the lower of +6V and (DV
DD
DD
+ 0.3V)
DD
AGND to DGND.....................................................-0.3V to +0.3V
CS1+, CS1-, CS2+, CS2- to GATEGND.................-0.3V to +32V
CS1- to CS1+, CS2- to CS2+ ...................................-6V to +0.3V
SDA/DIN, SCL to DGND...........................................-0.3V to +6V
Digital Outputs to DGND .........................-0.3V to (DV + 0.3V)
Maximum Continuous Current into Any Pin ........................50mA
DD
GATEV
to GATEGND .........................................-0.3V to +12V
Continuous Power Dissipation (T = +70°C)
48-Pin, 7mm x 7mm, Thin QFN (derate 27.8 mW/°C
DD
A
GATE1, GATE2 to GATEGND...........-0.3V to (GATEV
+ 0.3V)
DD
SAFE1, SAFE2 to GATEGND....................................-0.3V to +6V
GATEGND to AGND..............................................-0.3V to +0.3V
All Other Analog Inputs
above +70°C).............................................................2222mW
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
to AGND ............-0.3V to the lower of +6V and (AV
+ 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(GATEV = +5.5V for the MAX1385, GATEV = +11V for the MAX1386, AV = DV = +5V, external V
= +2.5V, external V
REF-
5/MAX1386
DD
DD
DD
DD
REFADC
= +2.5V, C
= 0.1µF, unless otherwise noted. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
DAC
REF
A
A
PARAMETER
SYMꢂOL
CONDITIONS
MIN
TYP
MAX
UNITS
HIGH-SIDE CURRENT SENSE WITH PGA
Common-Mode Input Voltage
Range
V
, V
CS+ CS-
5
30
V
Common-Mode Rejection Ratio
CMRR
11V < V
< 30V
90
dB
CS+
V
< 100mV over the common-mode
SENSE
I
120
195
CS+
range
Input-Bias Current
µA
mV
mV
mV
I
0.002
2
100
250
1250
100
250
1250
100
250
1250
0.5
CS-
PGA gain = 25
PGA gain = 10
PGA gain = 2
PGA gain = 25
PGA gain = 10
PGA gain = 2
PGA gain = 25
PGA gain = 10
PGA gain = 2
0
V
=
SENSE
VCS_+ -
VCS_-
Full-Scale Sense Voltage Range
Sense Voltage Range for
0
0
75
75
75
20
20
20
Accuracy of 0.5ꢀ V
SENSE
Sense Voltage Range for
Accuracy of 2ꢀ V
SENSE
Total PGAOUT Voltage Error
PGAOUT Capacitive Load
V
= 75mV
0.1
ꢀ
SENSE
C
100
pF
PGAOUT
Settles to within 0.5ꢀ of final value, R =
S
PGAOUT Settling Time
t
< 25
< 45
µs
µs
HSCS
50Ω, C
= 15pF
GATE
Settles to within 0.5ꢀ accuracy; from
= 3 x full scale
Saturation Recovery Time
V
SENSE
Av
Av
Av
= 2
0.5
2
PGA
PGA
PGA
Sense-Amplifier Slew Rate
V/µs
= 10
= 25
2
2
_______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
ELECTRICAL CHARACTERISTICS (continued)
(GATEV = +5.5V for the MAX1385, GATEV = +11V for the MAX1386, AV = DV = +5V, external V
= +2.5V, external V
REF-
DD
DD
DD
DD
REFADC
= +2.5V, C
= 0.1µF, unless otherwise noted. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
DAC
REF
A
A
PARAMETER
SYMꢂOL
CONDITIONS
MIN
TYP
900
720
290
MAX
UNITS
Av
= 2
PGA
PGA
PGA
Sense-Amplifier Bandwidth
kHz
Av
Av
= 10
= 25
LDMOS GATE DRIꢁER (GAIN = 2 and 4)
GATEV
- 0.75
DD
I
I
=
1mA
0.75
1
GATE
Output Gate-Drive Voltage Range
V
V
GATE
GATEV
- 1
DD
=
10mA
GATE
Output Impedance
R
Measured at DC
0.1
10
Ω
GATE
GATE
Settles to within 0.5ꢀ of final value;
V
Settling Time
t
ms
GATE
R
= 50Ω, C
= 15µF
SERIES
GATE
No series resistance, R
= 0Ω
0
0
10
SERIES
Output Capacitive Load (Note 1)
Noise
C
nF
GATE
R
= 50Ω
25,000
SERIES
V
RMS noise; 1kHz - 1MHz
250
100
25
nV/√Hz
mV
GATE
Maximum Power-On Transient
Output Short-Circuit Current Limit
I
1s, sinking or sourcing
mA
SC
Total Unadjusted Error
No Autocalibration and Offset
Removal (Note 2)
MAX1385, LOCODE = 128, HICODE = 180
6
12
1
20
40
8
TUE
TUE
mV
mV
MAX1386, LOCODE = 128, HICODE = 180
MAX1385, LOCODE = 128, HICODE = 180
MAX1386, LOCODE = 128, HICODE = 180
Total Adjusted Error
With Autocalibration and Offset
Removal
2
16
MAX1385, V
MAX1386, V
> 1V
> 1V
15
30
1
GATE
Drift
µV/°C
µs
GATE
Clamp to Zero Delay
Output Safe Switch On-
Resistance
R
OPSW
GATE_ clamped to AGND (Note 3)
500
Ω
MAX1385
MAX1386
300
150
Amplifier Bandwidth
kHz
Amplifier Slew Rate
MONITOR ADC DC ACCURACY
Resolution
0.375
V/µs
N
12
Bits
LSB
ADC
Differential Nonlinearity
Integral Nonlinearity
Offset Error
DNL
0.5
0.6
2
2
2
4
4
ADC
ADC
INL
(Note 4)
(Note 5)
LSB
LSB
Gain Error
2
LSB
Gain Temperature Coefficient
Offset Temperature Coefficient
0.4
0.4
ppm/°C
ppm/°C
_______________________________________________________________________________________
3
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(GATEV = +5.5V for the MAX1385, GATEV = +11V for the MAX1386, AV = DV = +5V, external V
= +2.5V, external V
REF-
DD
DD
DD
DD
REFADC
= +2.5V, C
= 0.1µF, unless otherwise noted. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
DAC
REF
A
A
PARAMETER
SYMꢂOL
CONDITIONS
MIN
TYP
MAX
UNITS
Channel-to-Channel Offset
Matching
0.1
LSB
LSB
Channel-to-Channel Gain
Matching
0.1
MONITOR ADC DYNAMIC ACCURACY (1kHz sine-wave input, 2.5ꢁ , up to 94.4ksps)
P-P
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
SINAD
THD
70
-82
86
dB
dB
Up to the 5th harmonic
SFDR
IMD
dB
f
= 0.99kHz, f
= 1.02kHz
IN2
76
dB
IN1
-3dB point
10
MHz
kHz
Full-Linear Bandwidth
S/(N + D) > 68dB
100
5/MAX1386
MONITOR ADC CONꢁERSION RATE
External reference
Internal reference
Internally clocked
0.8
70
Power-Up Time
t
µs
µs
PU
Conversion Time
t
7.5
10
CONV
MONITOR ADC ANALOG INPUT (ADCIN1, ADCIN2)
Input Range
V
Relative to AGND (Note 6)
= 0V and V = AV
0
V
V
ADCIN
REF
1
Input Leakage Current
Input Capacitance
V
0.01
34
µA
pF
IN
IN
DD
C
ADCIN
TEMPERATURE MEASUREMENTS
MAX1385A/MAX1386A, T = +25°C
0.25
0.25
0.25
0.35
0.4
A
MAX1385A/MAX1386A, T = T
to T
-1.0
-2.0
-3
+1.0
+2.0
+3
Internal Sensor Measurement
Error (Note 1)
A
MIN
MAX
°C
°C
MAX1385B/MAX1386B, T = +25°C
A
MAX1385B/MAX1386B, T = T
to T
A
MIN
MAX
T
= +25°C
A
A
External Sensor Measurement
Error (Notes 1, 7)
T
= T
to T
0.75
1/8
MIN
MAX
Temperature Resolution
External Diode Drive
Drive Current Ratio
°C/LSB
µA
2.8
85
(Note 8)
16.5
INTERNAL REFERENCE
V
V
T
T
= +25°C
2.494
2.494
2.500
2.500
2.506
2.506
REFADC
REFDAC
A
REFADC/REFDAC Output Voltage
V
= +25°C
A
REFADC/REFDAC Output
Temperature Coefficient
TC
TC
,
REFADC
14
ppm/°C
kΩ
REFDAC
REFADC/REFDAC Output
Impedance
6.5
4
_______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
ELECTRICAL CHARACTERISTICS (continued)
(GATEV = +5.5V for the MAX1385, GATEV = +11V for the MAX1386, AV = DV = +5V, external V
= +2.5V, external V
REF-
DD
DD
DD
DD
REFADC
= +2.5V, C
= 0.1µF, unless otherwise noted. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
DAC
REF
A
A
PARAMETER
SYMꢂOL
CONDITIONS
MIN
TYP
MAX
UNITS
Capacitive Bypass at REF
Power-Supply Rejection Ratio
EXTERNAL REFERENCE
REFADC Input Voltage Range
270
nF
PSRR
AV
= +5V 5ꢀ
70
dB
DD
V
Limited code test
= 2.5V, f
1.0
0.5
8
AV
V
REFADC
DD
V
= 174ksps
SAMPLE
60
80
REF
REFADC Input Current
I
µA
REFADC
Acquisition/between conversions
(Note 9)
0.01
1
REFDAC Input Voltage Range
REFDAC Input Current
V
2.5
V
REFDAC
Static current when no DAC calibration
0.1
µA
GATE-DRIꢁER COARSE-DAC DC ACCURACY
Resolution
N
Bits
LSB
LSB
CDAC
Integral Nonlinearity
Differential Nonlinearity
INL
Measured at GATE; fine DAC set at full scale
Guaranteed monotonic
0.15
0.05
1
CDAC
DNL
0.5
CDAC
GATE-DRIꢁER FINE-DAC DC ACCURACY
Resolution
N
10
Bits
LSB
LSB
FDAC
Measured at GATE; coarse DAC set at full
scale
Integral Nonlinearity
INL
0.25
0.1
4
1
FDAC
Differential Nonlinearity
DNL
Guaranteed monotonic
FDAC
POWER SUPPLIES (Note 10)
Analog Supply Voltage
AV
DV
4.75
2.7
5.25
V
V
DD
AV
DD
Digital Supply Voltage
DD
+ 0.3
Gate-Drive Supply Voltage
Analog Supply Current
Digital Supply Current
V
4.75
11.00
V
GATEVDD
I
AV
DV
= 5V
3.2
3.1
4.5
0.1
0.1
0.1
4
4.3
7
mA
mA
mA
AVDD
DVDD
DD
I
= 2.7V to 5.25V
DD
GATEV
Supply Current
I
3
DD
GATEVDD
I
I
I
2
AVDD
Shutdown Current (Note 11)
I
2
µA
PD
DVDD
2
VDDGATE
_______________________________________________________________________________________
5
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(GATEV = +5.5V for the MAX1385, GATEV = +11V for the MAX1386, AV = DV = +5V, external V
= +2.5V, external V
REF-
DD
DD
DD
DD
REFADC
= +2.5V, C
= 0.1µF, unless otherwise noted. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
DAC
REF
A
A
PARAMETER
SYMꢂOL
2
CONDITIONS
MIN
TYP
MAX
UNITS
ꢁ
IH
AND ꢁ FOR SDA/DIN AND SCL IN I C OPERATION ONLY
IL
0.7 x
Input High Voltage
Input Low Voltage
Input Hysteresis
V
V
V
V
IH
DV
DD
0.3 x
V
IL
DV
DD
0.1 x
DV
V
HYS
DD
ꢁ
IH
AND ꢁ FOR OPSAFE1 AND OPSAFE2
IL
Input High Voltage
Input Low Voltage
V
2.4
V
V
IH
V
0.4
IL
ꢁ
IH
AND ꢁ FOR ALL OTHER DIGITAL INPUTS
IL
5/MAX1386
Input High Voltage
Input Low Voltage
V
2.2
V
V
IH
V
0.7
0.4
IL
ꢁ
OH
AND ꢁ FOR A1/DOUT (SPI), SDA/DIN, ALARM
OL
Output Low Voltage
V
I
= 3mA
V
V
OL
SINK
DV
DD
Output High Voltage
V
I
= 2mA
OH
SOURCE
- 0.5
ꢁ
OH
AND ꢁ FOR SAFE1, SAFE2, ꢂUSY
OL
Output Low Voltage
V
I
I
= 0.5mA
0.4
V
V
OL
SINK
DV
- 0.5
DD
Output High Voltage
V
= 0.5mA
OH
SOURCE
6
_______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
2
I C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Note 12, see Figure 1)
(GATEV
= +5.5V for MAX1385, GATEV
= +11V for MAX1386, AV
= +5V, DV
= 2.7V to 5.25V, external V
= +2.5V,
DD
DD
DD
DD
REFADC
external V
= +2.5V, C = 0.1µF, T = -40°C to +85°C, unless otherwise noted).
REF A
REFDAC
PARAMETER
Serial-Clock Frequency
SYMꢂOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
0
400
kHz
SCL
Bus Free Time Between STOP
and START Condition
t
1.3
0.6
µs
µs
BUF
Hold Time Repeated START
Condition
After this period, the first clock pulse is
generated
t
t
HD;STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time Repeated START
Condition
0.6
µs
SU;STA
Data Hold Time
Data Setup Time
t
(Note 13)
0
0.9
µs
ns
HD;DAT
t
100
SU;DAT
Rise Time of Both SDA and SCL
Signals, Receiving
t
(Note 14)
0
300
300
250
ns
ns
R
Fall Time of Both SDA and SCL
Signals, Receiving
t
t
(Note 14)
0
F
Fall Time of SDA Signal,
Transmitting
20 +
0.1C
(Notes 14, 15)
ns
µs
pF
F
b
Setup Time for STOP Condition
t
SU;STO
0.6
Capacitive Load for Each Bus
Line
C
400
50
b
Pulse Width of Spikes
Suppressed by the Input Filter
t
SP
(Note 16)
0
ns
_______________________________________________________________________________________
ꢃ
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
2
I C HIGH-SPEED-MODE TIMING CHARACTERISTICS (Note 12, see Figure 2)
(GATEV
= +5.5V for MAX1385, GATEV
= +11V for MAX1386, AV
= +5V, DV
= 2.7V to 5.25V, external V
= +2.5V,
DD
DD
DD
DD
REFADC
external V
= +2.5V, C = 0.1µF, T = -40°C to +85°C, unless otherwise noted).
REF A
REFDAC
PARAMETER
Serial-Clock Frequency
SYMꢂOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
0
3.4
MHz
SCL
Setup Time Repeated START
Condition
t
160
160
ns
ns
SU;STA
Hold Time Repeated START
Condition
t
HD;STA
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
t
160
60
10
0
ns
ns
ns
ns
LOW
t
HIGH
t
SU;DAT
HD;DAT
Data Hold Time
t
(Note 17)
70
40
Rise Time of SCL Signal,
Receiving
t
10
ns
RCL
5/MAX1386
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit,
Receiving
t
10
80
ns
RCL1
Fall Time of SCL Signal,
Receiving
t
10
10
40
80
80
ns
ns
FCL
Rise Time of SDA Signal,
Receiving
t
RDA
Fall Time of SDA Signal,
Transmitting
t
10
ns
ns
pF
FDA
Setup Time for STOP Condition
t
160
SU;STO
Capacitive Load for Each Bus
Line
C
(Note 18)
100
10
b
Pulse Width of Spikes That are
Suppressed by the Input Filter
t
0
ns
SP
8
_______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
SPI TIMING CHARACTERISTICS (Note 12, See Figure 3)
(GATEV
= +5.5V for the MAX1385, GATEV
= +11V for the MAX1386, AV
= +5V, DV
= 2.7V to 5.25V, external V
=
DD
DD
DD
DD
REFADC
+2.5V, external V
= +2.5V, C = 0.1µF, T = -40°C to +85°C, unless otherwise noted.)
REF A
REFDAC
PARAMETER
SCL Clock Period
SYMꢂOL
CONDITIONS
MIN
62.5
25
TYP
MAX
UNITS
ns
t
CP
CH
SCL High Time
SCL Low Time
DIN Setup Time
DIN Hold Time
t
ns
t
t
25
ns
CL
DS
DH
DO
10
ns
t
0
ns
SCL Fall to DOUT Transition
CSB Fall to DOUT Enable
CSB Rise to DOUT Disable
CSB Rise or Fall to SCL Rise
CSB Pulse-Width High
t
C
C
C
= 30pF
= 30pF
20
40
ns
LOAD
LOAD
LOAD
t
ns
DV
t
= 30pF (Note 12)
100
ns
TR
t
25
100
50
ns
CSS
t
ns
CSW
Last Clock Rise to CSB Rise
t
ns
CSH
Note 1: Guaranteed by design.
Note 2: Total unadjusted errors are for the entire gain drive channel including the 8- and 10-bit DACs and the gate driver. They are
all measured at the GATE1 and GATE2 outputs. Offset removal refers to presetting the drain current after a room tempera-
ture calibration by the user. This effectively removes the channel offset.
Note 3: During power-on reset, the output safe switch is closed. The output safe switch opens once both AV
and DV
supply
DD
DD
voltages are established.
Note 4: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset errors
have been removed.
Note 5: Offset nulled.
Note 6: Absolute range for analog inputs is from 0 to AV
.
DD
Note ꢃ: The MAX1385/MAX1386 and external sensor are at the same temperature. External sensor measurement error is tested with
a diode-connected 2N3904.
Note 8: The drive current ratio is defined as the large drive current divided by the small drive current in a temperature measure-
ment. See the Temperature Measurements section for further details.
Note 9: Guaranteed monotonicity. Accuracy might be degraded at lower V
.
REFDAC
Note 10: Supply current limits are valid only when digital inputs are at DV
or DGND. Timing specifications are only guaranteed
DD
when inputs are driven rail-to-rail.
Note 11: Shutdown supply currents are typically 0.1µA. Maximum specification is limited by automated test equipment.
Note 12: All timing specifications referred to V or V levels.
IH
IL
Note 13: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of SCL) to bridge the unde-
IL
fined region of SCL’s falling edge.
Note 14: C = total capacitance of one bus line in pF; t and t are measured between 0.3 x DV
and 0.7 x DV
.
b
R
F
DD
DD
Note 15: For a device operating in an I2C-compatible system.
Note 16: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 1ꢃ: A device must provide a data hold time to bridge the undefined part between V and V of the falling edge of the SCL signal.
IH
IL
An input circuit with a threshold as low as possible for the falling edge of the SCL signal minimizes this hold time.
Note 18: Cb = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be
linearly interpolated.
_______________________________________________________________________________________
9
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
SDA
t
SU;DAT
t
F
t
t
t
F
LOW
t
r
t
R
t
SP
t
BUF
HD;STA
SCL
t
SU;STO
t
t
SU;STA
HD;STA
t
t
HIGH
HD;DAT
S
r
S
P
S
Figure 1. I2C Slow-/Fast-Mode Timing Diagram
Sr
Sr
P
t
RDA
t
5/MAX1386
FDA
SDA
SCL
t
SU;STA
t
HD;DAT
t
SU;STO
t
HD;STA
t
SU;DAT
t
t
t
FCL
RCL1
RCL
t
RCL1
t
LOW
t
t
t
LOW
HIGH
HIGH
Figure 2. I2C High-Speed-Mode Timing Diagram
t
CSW
CSB
t
t
t
CSS
t
t
CSS
t
CH
CSH
CP
CL
SCL
DIN
t
DH
t
DS
D23
D22
D0
D1
t
t
TR
DO
t
DV
DOUT
D1
D0
Figure 3. SPI Timing Diagram
10 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Typical Operating Characteristics
(GATEV
= +5.5V for the MAX1385, GATEV
= +11V for the MAX1386, AV
= DV
= +5V, external V
= +2.5V, external
DD
DD
DD
DD
REFADC
V
= +2.5V, C = 0.1µF, T = +25°C, unless otherwise noted.)
REF A
REFDAC
GATEV SUPPLY CURRENT
DD
AV SUPPLY CURRENT
DD
vs. GATEV VOLTAGE
vs. AV VOLTAGE
DV SUPPLY CURRENT vs. DV VOLTAGE
DD
DD
DD
DD
4.0
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
Av
= 2
Av
= 2
PGA
PGA
Av
= 2
T
= +85°C
PGA
A
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
CMV = 12V
= 100mV
CMV = 12V
V = 100mV
SENSE
CMV = 12V
= 100mV
T
= +25°C
= -40°C
A
V
T
A
= +85°C
SENSE
V
SENSE
T
A
T
A
= +25°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
T
A
= -40°C
4
5
6
7
8
9
10 11 12
2.7
3.2
3.7
4.2
DV (V)
4.7
5.2
4.7
4.8
4.9
5.0
5.1
5.2
5.3
GATEV (V)
AV (V)
DD
DD
DD
TOTAL PGAOUT_ ERROR
vs. TEMPERATURE
TOTAL PGAOUT_ ERROR vs. V
TOTAL PGAOUT_ ERROR vs. V
SENSE
SENSE
0.150
0.125
0.100
0.075
0.050
0.025
0
0.5
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
Av = 25
PGA
CMV = 12V
Av
PGA
= 2
Av
= 2
PGA
CMV = 12V
CMV = 12V
= 100mV
V
SENSE
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
ACQUISITION
TRACKING
-0.025
-0.050
-0.075
-0.100
-0.125
-0.150
-40 -25 -10
5
20 35 50 65 80
0
20
40
V
60
80
100
0
250
500
V
750
1000
1250
TEMPERATURE (°C)
(mV)
(mV)
SENSE
SENSE
TOTAL PGAOUT_ ERROR
vs. COMMON-MODE VOLTAGE
PGAOUT_ OFFSET VOLTAGE
vs. TEMPERATURE
V TRANSIENT RESPONSE
SENSE
MAX1385/86 toc09
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
200
150
100
50
Av
= 2
= 100mV
Av
= 2
PGA
PGA
ACQUISITION
V
CMV = 12V
= 100mV
SENSE
V
SENSE
100mV/div
0
V
SENSE
TRACKING
-50
-100
-150
-200
-250
-300
-350
-400
PGAOUT_
1V/div
5
10
15
20
25
30
-40 -25 -10
5
20 35 50 65 80
10μs/div
COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
Typical Operating Characteristics (continued)
(GATEV
= +5.5V for the MAX1385, GATEV
= +11V for the MAX1386, AV
= DV
= +5V, external V
= +2.5V, external
DD
DD
DD
DD
REFADC
V
= +2.5V, C = 0.1µF, T = +25°C, unless otherwise noted.)
REF A
REFDAC
PGAOUT_ 0mV TO 250mV
PGAOUT_ PEDESTAL ERROR
DURING CALIBRATION
GATE_ OFFSET COMPENSATED
ERROR vs. TEMPERATURE
V
TRANSIENT RESPONSE
SENSE
MAX1385/86 toc10
MAX1385/86 toc11
0
-1
-2
-3
-4
-5
-6
-7
-8
100mV/div
H_ERROR, AUTOCALIBRATION
2V/div
BUSY
V
SENSE
L_ERROR, AUTOCALIBRATION
PGAOUT_
1V/div
H_ERROR, NO AUTOCALIBRATION
PGAOUT_
10mV/div
L_ERROR, NO AUTOCALIBRATION
10µs/div
20µs/div
-40 -25 -10
5
20 35 50 65 80
5/MAX1386
TEMPERATURE (°C)
GATE_ SETTLING TIME
vs. LOAD CAPACITANCE
CHARGE CURRENT vs. V
V
GATE
vs. POWER-ON TIME
GATE
MAX1385/86 toc15
MAX1385/86 toc13
16
14
12
10
8
R
= 50Ω
SERIES
V
GATE_
50mV/div
2V/div
V
GATE_
6
20mA/div
4
I
GATE_
2
0
400µs/div
1ms/div
0.1
1
10
100
LOAD CAPACITANCE (µF)
GATE_ VOLTAGE SWING
vs. LOAD RESISTANCE
GLITCH ENERGY
MAX1385/86 toc17
10
9
8
7
6
5
4
3
2
1
0
10mV/div
10
100
1000
10,000
100,000
1µs/div
LOAD RESISTANCE (Ω)
12 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Typical Operating Characteristics (continued)
(GATEV
= +5.5V for the MAX1385, GATEV
= +11V for the MAX1386, AV
= DV
= +5V, external V
= +2.5V, external
DD
DD
DD
DD
REFADC
V
= +2.5V, C = 0.1µF, T = +25°C, unless otherwise noted.)
REF A
REFDAC
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (8-BIT COARSE DAC)
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (10-BIT FINE DAC)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT DAC)
1.0
0.8
1.0
0.8
1.0
0.8
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
50
100
150
200
250
0
50
100
DIGITAL INPUT CODE
150
200
250
0
200
400
600
800
1000
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT FINE DAC)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (ADC)
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
200
400
600
800
1000
0
1000
2000
3000
4000
DIGITAL INPUT CODE
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (ADC)
FFT PLOT
1.0
0.8
0
-20
-40
-60
-80
f
f
= 303Hz
IN
SAMPLE
= 49.15kHz
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-100
-120
-140
-160
0
1000
2000
3000
4000
0
5
10
15
20
25
DIGITAL OUTPUT CODE
FREQUENCY (kHz)
______________________________________________________________________________________ 13
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
Typical Operating Characteristics (continued)
(GATEV
= +5.5V for the MAX1385, GATEV
= +11V for the MAX1386, AV
= DV
= +5V, external V
= +2.5V, external
DD
DD
DD
DD
REFADC
V
= +2.5V, C = 0.1µF, T = +25°C, unless otherwise noted.)
REF A
REFDAC
INTERNAL REFERENCE
vs. TEMPERATURE
ADC OFFSET ERROR vs. TEMPERATURE
0.100
0.075
0.050
0.025
0
2.509
2.504
2.499
2.494
2.489
2.484
AV = 5V
DD
AV = 5V
DD
-0.025
-0.050
-0.075
-0.100
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
5/MAX1386
TEMPERATURE (°C)
TEMPERATURE (°C)
ADC OFFSET ERROR vs. AV VOLTAGE
ADC GAIN ERROR vs. TEMPERATURE
DD
0.05
0.04
0.03
0.02
0.01
0
0.100
0.075
0.050
0.025
0
AV = 5V
DD
-0.01
-0.02
-0.03
-0.04
-0.05
-0.025
-0.050
-0.075
-0.100
4.75
4.85
4.95
5.05
5.15
5.25
-40 -25 -10
5
20 35 50 65 80
AV (V)
DD
TEMPERATURE (°C)
INTERNAL TEMPERATURE SENSOR
ERROR vs. TEMPERATURE
EXTERNAL TEMPERATURE SENSOR
ERROR vs. TEMPERATURE
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
14 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Pin Description
PIN
NAME
FUNCTION
1
DGND
Digital Ground
Safe Status Channel 1 Output. Programmable active-high or active-low. SAFE1 asserts when
programmed channel 1 temperature threshold or current threshold has been reached.
2
3
SAFE1
2
I C-Compatible Address 0/ SPI-Compatible Chip Select. See the Digital Serial Interface section. In
A0/CSB
SPI mode, drive A0/CSB low to select the device.
Active-Low Conversion-Start Input. Drive CNVST low to start a conversion (clock modes 01 and 11).
4
5
CNVST
Connect CNVST to DV
when initiating conversions through the serial interface (clock mode 00).
DD
2
SEL
Mode Select. Connect SEL to DGND to select I C mode. Connect SEL to DV
to select SPI mode.
DD
Alarm Output. Program ALARM for comparator or interrupt output modes (see the Alarm Modes
section). Program ALARM to assert on any combination of channel temperature or current
thresholds.
6
ALARM
Safe Status Channel 2 Output. Programmable active-high or active-low. SAFE2 asserts when
programmed channel 2 temperature threshold or current threshold has been reached.
7
SAFE2
N.C.
8, 19, 25, 28,
35–39, 42, 46
No Connection. Not internally connected.
9
REFDAC
REFADC
DAC Reference Input/Output
ADC Reference Input/Output
10
Diode Positive Input 1. Connect to anode of temperature diode or the base and collector of an npn
transistor.
11
12
13
DXP1
DXN1
DXP2
Diode Negative Input 1. Connect to cathode of temperature diode or the emitter of an npn transistor.
Diode Positive Input 2. Connect to anode of temperature diode or the base and collector of an npn
transistor.
14
DXN2
Diode Negative Input 2. Connect to cathode of temperature diode or the emitter of an npn transistor.
15
16
ADCIN1
ADCIN2
ADC Input 1
ADC Input 2
17
PGAOUT2 Programmable-Gain Amplifier Output 2
18
AV
Analog Power-Supply Input
Analog Ground
DD
20, 21, 22
AGND
______________________________________________________________________________________ 15
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
Pin Description (continued)
PIN
23
NAME
FUNCTION
GATEGND Gate-Drive Amplifier Ground
24
GATEV
Gate-Drive Amplifier Supply Input
DD
26
OPSAFE2 Operating Safe Channel 2 Input. Drive OPSAFE2 high to clamp GATE2 to AGND.
Current-Sense Positive Input 2. CS2+ is the external sense resistor connection to the LDMOS 2
supply.
27
29
CS2+
Current-Sense Negative Input 2. CS2- is the external sense resistor connection to the LDMOS 2
drain.
CS2-
30
31
GATE2
GATE1
Channel 2 Gate-Drive Amplifier Output
Channel 1 Gate-Drive Amplifier Output
Current-Sense Negative Input 1. CS1- is the external sense resistor connection to the LDMOS 1
drain.
32
33
CS1-
Current-Sense Positive Input 1. CS1+ is the external sense resistor connection to the LDMOS 1
supply.
CS1+
5/MAX1386
34
40
OPSAFE1 Operating Safe Channel 1 Input. Drive OPSAFE1 high to clamp GATE1 to AGND.
PGAOUT1 Programmable-Gain Amplifier Output 1
2
I C-Compatible Address 2. See the Digital Serial Interface section.
41
43
44
A2/N.C.
No Connection. Leave unconnected in SPI mode.
SCL
Digital Serial Clock Input
2
I C-Compatible Serial Data Input/Output
SDA/DIN
SPI-Compatible Serial Data Input
2
I C-Compatible Address 1. See the Digital Serial Interface section.
45
A1/DOUT
BUSY
SPI-Compatible Serial Data Output
47
48
—
Device Busy Output. See the BUSY Output section
Digital Supply Input
DV
DD
EP
Exposed Pad. Connect to AGND. Internally connected to analog ground.
16 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Functional Diagram
SAFE2
AV
DD
ALARM
SAFE1
DIGITAL
PGAOUT1
CS1+
CURRENT AND
TEMPERATURE
COMPARATORS
DV
DD
PGA1
PGA2
DGND
CS1-
PGA REGISTERS
CS2-
SCL
SDA/DIN
A0/CSB
CS2+
REGISTER
SECTION
PGAOUT2
SERIAL
INTERFACE
A1/DOUT
A2/N.C.
V
REFDAC
OPSAFE1
GATE1
CHANNEL 1 DAC
REGISTERS
8-BIT HIGH CODE
8-BIT LOW CODE
DRV
10-BIT FINE
ADJUST CODE
GATEV
DD
10-BIT DAC
GATEGND
OPSAFE2
V
REFDAC
CHANNEL 1 DAC
REGISTERS
8-BIT HIGH CODE
8-BIT LOW CODE
GATE2
AGND
DRV
10-BIT FINE
ADJUST CODE
10-BIT DAC
MAX1385
MAX1386
TEMP
SENSOR
PGAOUT1
PGAOUT2
FIFO
MEMORY
12-BIT ADC
WITH T/H
ADCIN0
ADCIN1
MUX
DXP1
DXN1
DXP2
DXN2
EXTERNAL
TEMP
PROCESSING
V
V
REFADC
REFDAC
2.5V
REF
CONVERSION AND
SCAN OSCILLATOR
AND CONTROL
REFDAC REFADC
CNVST
______________________________________________________________________________________ 1ꢃ
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
The internal ADC block converts the results of the die
temperature, remote diode temperature readings,
PGAOUT1, PGAOUT2, ADCIN1, or ADCIN2 voltages
according to which bits are set in the ADC Conversion
register (see the ADCCON (Write) section). The results
of the conversions are written to FIFO memory. The
FIFO holds up to 15 words (each word is 16 bits) with
channel tags to indicate which channel the 12-bit data
comes from. The FIFO indicates an overflow condition
and an underflow condition (read of an empty FIFO) by
the Flag register (see the RDFLAG (Read) section) and
channel tags. The FIFO always stores the most recent
conversion results and allows the oldest data to be
overwritten. Read the latest result stored in the FIFO by
sending the appropriate read command byte (see the
FIFO (Read) section).
Detailed Description
The MAX1385/MAX1386 set and control bias conditions
for dual RF LDMOS power devices found in cellular
base stations. Each device includes a high-side cur-
rent-sense amplifier with programmable gains of 2, 10,
and 25 to monitor the LDMOS drain current over the
20mA to 5A range. Two external diode-connected tran-
sistors monitor the LDMOS temperatures while an inter-
nal temperature sensor measures the local die
temperature of the MAX1385/MAX1386. A 12-bit ADC
converts the programmable-gain amplifier (PGA) out-
puts, external/internal temperature readings, and two
auxiliary inputs.
The two gate-drive channels, each consisting of 8-bit
coarse and 10-bit fine DACs and a gate-drive amplifier,
generate a positive gate voltage to bias the LDMOS
devices. The MAX1385 includes a gate-drive amplifier
with a gain of 2 and the MAX1386 gate-drive amplifier
provides a gain of 4. The 8-bit coarse and 10-bit fine
DACs allow up to 18 bits of resolution. The MAX1385/
MAX1386 include autocalibration modes to minimize
error over time, temperature, and supply voltage.
The MAX1385/MAX1386 feature an I2C-/SPI-compatible
serial interface. Both devices operate from a 4.75V to
5.25V analog supply (3.2mA supply current), a 2.7V to
5.25V digital supply (3.1mA supply current), and a 4.75V
to 11.0V gate-drive supply (4.5mA supply current).
Read the data stored in the FIFO through the FIFO
Read register. The FIFO (Read) section details which
channel is being read and whether the FIFO has over-
flowed.
5/MAX1386
Analog-to-Digital Conversion Scheduling
The MAX1385/MAX1386 ADC multiplexer scans select-
ed inputs in the order shown in Table 1. The ADC multi-
plexer skips over the items that are not selected in the
Analog-to-Digital Conversion register. When writing a
conversion command before a conversion is complete,
the pending conversion may be canceled. In addition,
using the serial interface while the ADC is converting
may degrade the performance of the ADC.
Power-On Reset
On power-up, the MAX1385/MAX1386 are in full power-
down mode (see the SSHUT (Write) section). To change
to normal power mode, write two commands to the
Software Shutdown register. The first command sets
FULLPD to 0 (other bits in the Software Shutdown register
are ignored). A second command is needed to activate
any internal blocks. The recommended sequence of com-
mands to ensure reliable startup following the application
of power, is given in the Appendix: Recommended
Power-Up Code Sequence section.
ADC Clock Modes
The MAX1385/MAX1386 offer three different conver-
sion/acquisition modes (known as clock modes) selec-
table through the Device Configuration register (see the
DCFIG (Read/Write) section). Clock Mode 10 is
reserved and cannot be used. For conversion/acquisi-
tion examples and timing diagrams, see the
Applications Information section.
If the analog-to-digital conversion requires the internal
reference (temperature measurement or voltage mea-
surement with internal reference selected) and the ref-
erence has not been previously forced on, the device
inserts a worst-case delay of 81µs, for the reference to
settle, before commencing the analog-to-digital conver-
sion. The reference remains powered up while there are
pending conversions. If the reference is not forced on,
it automatically powers down at the end of a scan or
when CONCONV in the Analog-to-Digital Conversion
register is set back to 0.
ADC Description
The MAX1385/MAX1386 ADC uses a fully differential
successive approximation register (SAR) conversion
technique and on-chip track-and-hold (T/H) circuitry to
convert temperature and voltage signals into 12-bit dig-
ital results. The analog inputs accept single-ended
input signals. Single-ended signals are converted using
a unipolar transfer function. See the ADC transfer func-
tion of Figure 25 for more information.
18 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Clock Mode 00
In clock mode 00, power-up, acquisition, conversion,
and power-down are all initiated by writing to the Analog-
to-Digital Conversion register and performed automati-
cally using the internal oscillator. This is the default clock
mode. The ADC sets the BUSY output high, powers up,
scans all requested channels, stores the results in the
FIFO, and then powers down. After the scan is complete,
BUSY is pulled low and the results for all the command-
ed channels are available in the FIFO.
For a temperature conversion, set CNVST low for at
least 40ns. The BUSY output goes high and the temper-
ature conversion results are available after an addition-
al 94µs (when BUSY goes low again). Thus, the
worst-case conversion time of the initial temperature
sensor scan (allowing the internal reference to settle) is
175µs. Subsequent temperature scans only take 85µs
worst case as the internal reference and temperature
sensor circuits are already powered.
For a voltage conversion while using an internal or
external reference, set CNVST low for at least 2µs but
less than 6.7µs. The BUSY output goes high and the
conversion results are available after an additional
7.5µs (typ) when BUSY goes low again.
Clock Mode 01
In clock mode 01, power-up, acquisition, conversion,
and power-down are all initiated by setting CNVST low
for at least 40ns. Conversions are performed automati-
cally using the internal oscillator. The ADC sets the
BUSY output high, powers up, scans all requested
channels, stores the results in the FIFO, and then pow-
ers down. After the scan is complete, BUSY is pulled
low and the results for all the commanded channels are
available in the FIFO.
Continuous conversion is not supported in this clock
mode (see the ADCCON (Write) section).
Changing Clock Modes During ADC Conversions
If a change is made to the clock mode in the Device
Configuration register while the ADC is already per-
forming a conversion (or series of conversions), the fol-
lowing descriptions show how the MAX1385/MAX1386
respond:
Clock Mode 11
In clock mode 11, conversions are initiated one at a
time through CNVST in the order shown in Table 1 and
performed using the internal oscillator. In this mode, the
acquisition time is controlled by the time CNVST is
brought low. CNVST is resynchronized by the internal
oscillator, which means there is a one-clock-cycle
uncertainty (typically 320ns) in the exact sampling
instant. Different timing parameters apply depending
whether the conversion is temperature, voltage, using
the external reference, or using the internal reference.
• CKSEL = 00 and is then changed to another value
The ADC completes the already triggered series of
conversions and then goes idle. The BUSY output
remains high until the conversions are completed.
The MAX1385/MAX1386 then respond in accor-
dance with the new CKSEL mode.
• CKSEL = 01 and is then changed to another value
If waiting for the initial external trigger, the
MAX1385/MAX1386 immediately exit clock mode
01, power down the ADC, and go idle. The BUSY
output stays low and waits for the external trigger. If
a conversion sequence has started, the ADC com-
pletes the requested conversions and then goes
idle. The BUSY output remains high until the conver-
sions are completed. The MAX1385/MAX1386 then
respond in accordance with the new CKSEL mode.
Table 1. Order of ADC Conversion Scan
ORDER OF SCAN
DESCRIPTION OF CONꢁERSION
Internal device temperature
External diode 1 temperature
PGAOUT1 for current sense
ADCIN1
1
2
3
4
5
6
7
• CKSEL = 11 and is then changed to another value
External diode 2 temperature
PGAOUT2 for current sense
ADCIN2
If waiting for an external trigger, the MAX1385/
MAX1386 immediately exit clock mode 11, power
down the ADC, and go idle. The BUSY output stays
low and waits for the external trigger.
______________________________________________________________________________________ 19
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
CAPACITIVE DAC
ADCIN_
CONTROL LOGIC
TRACK MODE
AGND
CAPACITIVE DAC
5/MAX1386
ADCIN_
CONTROL LOGIC
AGND
HOLD/CONVERSION MODE
Figure 4. Equivalent ADC Input Circuit
Analog Input Track and Hold
ance source can be accommodated either by lengthen-
ing t or by placing a 1µF capacitor between the
positive input and AGND. The combination of the ana-
log input source impedance and the capacitance at the
analog input creates an RC filter that limits the analog-
input bandwidth.
The equivalent circuit (Figure 4) shows the
MAX1385/MAX1386 ADC input architecture. In track
mode, a positive input capacitor is connected to
ADCIN_ and a negative input capacitor is connected to
AGND. After the T/H enters hold mode, the difference
between the sampled positive and negative input volt-
ages is converted. The input capacitance charging rate
determines the time required for the T/H to acquire an
input signal. If the input signal’s source impedance is
high, the required acquisition time lengthens.
ACQ
Analog-Input ꢂandwidth
The ADC’s input-tracking circuitry has a 10MHz band-
width to digitize high-speed transient events. Anti-alias
prefiltering of the input signals is necessary to avoid
high-frequency signals aliasing into the frequency band
of interest.
Any source impedance below 300Ω does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
20 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Analog-Input Protection
commands. The output of a coarse DAC is not updated
until the appropriate DAC output register(s) have been
set. See Figure 5 for the relationship between DAC
input registers, DAC output registers, and wipers.
Internal ESD protection diodes clamp all analog inputs
to AV
and AGND, allowing the inputs to swing from
DD
AGND - 0.3V to AV
+ 0.3V without damage. If an
DD
analog input voltage exceeds the supplies, limit the
input current to 2mA.
DAC output registers are not directly accessible to the
user. Choose which input register to write to based on
whether automatic low or high calibration is desired, or
if updates to the output of the DAC need to be initiated
immediately. In the case of automatic low or high cali-
bration, a correction code is added to or subtracted
from the 10-bit fine-DAC input register. Transfers from
the DAC input registers to DAC output registers can
occur immediately after a write to the appropriate DAC
input register or on a software command through the
Software LDAC register. See the Register Descriptions
section for bit-level descriptions of these registers.
DAC Description
The MAX1385/MAX1386 include two 8-bit and 10-bit
DAC blocks to independently control the voltage on
each LDMOS gate. Both 10-bit and 8-bit DACs can be
automatically calibrated to minimize output error over
time, temperature, and supply voltage. The 8-bit and
10-bit DACs have unipolar transfer functions and have
a relationship to the output voltage by the following
equation:
V
V
FINECODE
REF
REF
V
=
×LOCODE+
×[HICODE−LOCODE]×
8
DACOUT
8
10
10-ꢂit Fine-DAC Adjustment
Each DAC control block contains a 10-bit fine DAC that
operates between the high and low wiper positions
from the 8-bit coarse DAC. The 10-bit fine DAC also
has an optional automatic calibration mode and can be
updated immediately or on a software-issued command
in the Software LDAC register. Writing to the appropri-
ate fine-DAC input register determines whether auto-
matic calibration is used and/or when the DAC is
updated. See Figure 6 for the relationship between
DAC input registers, DAC output registers, and the
Software LDAC register.
2
2
2
where LOCODE, HICODE, and FINECODE are the low
wiper (8 bits), high wiper (8 bits), and fine DAC (10 bits)
values written to the DAC by the user. LOCODE,
HICODE, and FINECODE represent the values in the
DAC input registers and may or may not be the actual
values in the DAC output registers depending whether
autocalibration is used or not (see the 8-Bit Coarse-
DAC Adjustment section). To find the actual voltage at
GATE_, multiply the V
result by 2 (MAX1385) or
DACOUT
4 (MAX1386). Due to the buffer amplifiers, the voltage
at GATE_ cannot be set below 100mV above AGND. It
is recommended that the LOCODE for DAC1 and DAC2
are set so that the minimum possible output at GATE_
is 200mV (MAX1385) and 400mV (MAX1386).
The fine-DAC output registers are not directly accessi-
ble. Choose which DAC input register to write to based
on whether automatic fine calibration is desired, or
whether updates to the output of the DAC need to be ini-
tiated immediately. In the case of automatic fine calibra-
tion, a correction code is added to or subtracted from
the input register code and transferred to the appropriate
fine-DAC output register. Transfers from a fine-DAC input
register to a fine-DAC output register can occur immedi-
ately after a write to the appropriate DAC input register or
on a software command through the Software LDAC reg-
ister. See the Register Descriptions section for bit-level
detail of these registers.
The DACs can be operated to produce an 18-bit
monotonic DAC with 12-bit (typ) INL. Write to either
HICODE or LOCODE in a leapfrog fashion, without
commanding autocalibration, to configure the 18-bit
monotonic DAC. When LOCODE > HICODE, invert the
value of FINECODE.
8-ꢂit Coarse-DAC Adjustment
Each DAC control block contains a resistor string with
wipers that serve as an 8-bit coarse DAC. Wipers are
set by writing to the appropriate DAC input registers
and/or using the Load DAC Control register (LDAC)
______________________________________________________________________________________ 21
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
HIGH-CAL
COARSE DAC_ HIGH WIPER OUTPUT REGISTER
HCAL
HIWIPE_ REGISTER
V
DACREF
THRUHI_ REGISTER
TO 10-BIT FINE DAC
THRULO_ REGISTER
LOWIPE_ REGISTER
COARSE DAC_ LOW WIPER OUTPUT REGISTER
LCAL
5/MAX1386
LOW-CAL
LOAD DAC CONTROL REGISTER (LDAC)
Figure 5. Coarse-DAC Register Diagram
FROM 8-BIT COARSE DAC
LOAD DAC CONTROL REGISTER (LDAC)
FINE_ REGISTER
FINECAL_ REGISTER
FINECALTHRU_ REGISTER
FINETHRU_ REGISTER
TO GATE-DRIVE BLOCK
10-BIT FINE
DAC
FINE DAC_ OUTPUT REGISTER
FINE-CAL
FROM 8-BIT COARSE DAC
Figure 6. Fine-DAC Register Diagram
22 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
The external temperature-sensor drive current ratio has
been optimized for a 2N3904 npn transistor with an ide-
ality factor of 1.0065. The nonideality offset is removed
internally by a preset digital coefficient. Use of a tran-
sistor with a different ideality factor produces a propor-
tionate difference in the absolute measured
temperature. More details on this topic and others relat-
ed to using an external temperature sensor can be
found in Maxim Application Note 1057: Compensating
for Ideality and Series Resistance Differences Between
Thermal Sense Diodes and Application Note 1944:
Temperature Monitoring Using the MAX1253/MAX1254
and MAX1153/MAX1154.
ADC/DAC References
The MAX1385/MAX1386 provide an internal low-noise
2.5V reference for the ADCs, DACs, and temperature
sensor. See the Device Configuration Register section
for information on configuring the device for external or
internal reference. Connect a voltage source to
REFADC in the 1V to AV
range when using an exter-
DD
nal ADC reference. Connect a voltage source to REF-
DAC in the 0.5V to 2.5V range when using an external
DAC reference. When using an external voltage refer-
ence, bypass the reference pin with a 0.1µF capacitor
to AGND.
The internal reference has a lowpass filter to reduce
noise. The device allows 60µs (typ) and 81µs (typ) worst
case for the reference to settle before permitting an ana-
log-to-digital conversion. If reference mode 11 is select-
ed, the required settling time is longer. In this case, the
user should set at least one of DAC1PD, DAC2PD, or
FBGON in the Software Shutdown register, any of which
forces the reference to be permanently powered up.
High-Side Current-Sense PGAs
The MAX1385/MAX1386 provide two high-side current-
sense amplifiers with programmable gain. The current-
sense amplifiers are unidirectional and provide a 5V to
30V input common-mode range. Both CS1+ and CS2+
must be within the specified common-mode range for
proper operation of each amplifier.
The sense amplifiers measure the load current, I
,
Temperature Measurements
The MAX1385/MAX1386 measure the internal die tem-
perature and two external remote-diode temperature
sensors. Set up a temperature conversion by writing
to the Analog-to-Digital Conversion register (see the
ADCCON (Write) section). Optionally program SAFE1
and SAFE2 outputs to depend on programmed temper-
ature thresholds.
LOAD
, between
through an external sense resistor, R
SENSE_
the CS_+ and CS_- inputs. The full-scale sense voltage
range (V
= V
+ - V
-) depends on the pro-
CS_
SENSE_
grammed gain, Av
CS_
(see the DCFIG (Read/Write)
PGA_
section). The sense amplifiers provide a voltage output
at PGAOUT_ according to the following equation:
V
= Av
×(V
+ −V
−)
PGAOUT_
PGA _
CS_
CS_
The MAX1385/MAX1386 can perform temperature mea-
surements with an internal diode-connected transistor.
The diode bias current changes from 66µA to 4µA to
produce a temperature-dependent bias voltage differ-
ence. The second conversion result at 4µA is subtract-
ed from the first at 66µA to calculate a digital value that
is proportional to the absolute temperature. The stored
data result is the aforementioned digital code minus an
offset to adjust from Kelvin to Celsius.
These outputs are also routed to the internal 12-bit ADC
so that a digital representation of the amplified voltages
can be read through the FIFO.
The PGA scales the sensed voltages to fit the input
range of the ADC. Program the PGA with gains of 2, 10,
and 25 by setting the PGSET_ bits (see the DCFIG
(Read/Write) section). The input stages have nominal
input offset voltages of 0mV that can be adjusted by a
trim DAC (not shown in the Functional Diagram) over the
-3mV to +3mV range in 25µV steps. Autocalibration can
be used to control the trim DAC to minimize the effective
channel input offset voltage (see the PGACAL (Write)
section). The PGA feedback network is referenced to
AGND.
The reference voltage for the temperature measure-
ments is always derived from the internal reference
source. Temperature results are in degrees Celsius
(two’s-complement form).
The temperature-sensing circuits power up for the first
temperature measurement in an analog-to-digital con-
version scan. The temperature-sensing circuits remain
powered until the end of the scan to avoid a possible
67µs delay of internal reference power-up time for each
individual temperature channel. If the continuous con-
vert bit CONCONV is set high and the current ADC
channel selection includes a temperature channel, the
temperature-sensor circuits remain powered up until
the CONCONV bit is set low.
ALARM Output
The state of ALARM is logically equivalent to the inclu-
sive OR of SAFE1 and SAFE2. The exception to this
statement is when ALARM is configured for output inter-
rupt mode (see the Alarm Modes section). When in out-
put-interrupt mode, ALARM stays in its asserted state
until its associated flag is cleared by reading from the
______________________________________________________________________________________ 23
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
HIGHEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
ALARM OUTPUT DEASSERTED
WHEN MEASURED VALUE FALLS
BELOW THIS LEVEL*
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
RISES ABOVE THIS LEVEL
HIGH THRESHOLD
BUILT-IN 8 TO 64 LSBs
OF HYSTERESIS
RANGE OF VALUES THAT DO NOT CAUSE AN ALARM
BUILT-IN 8 TO 64 LSBs
OF HYSTERESIS
LOW THRESHOLD
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
FALLS BELOW THIS LEVEL
ALARM OUTPUT DEASSERTED
WHEN MEASURED VALUE RISES
ABOVE THIS LEVEL*
LOWEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
5/MAX1386
*ONLY WHEN ALARM IS CONFIGURED FOR OUTPUT-COMARATOR MODE.
WHEN IN OUTPUT-INTERRUPT MODE, FLAG REGISTER MUST BE READ
FOR ALARM TO BE DEASSERTED.
Figure 7. Window-Threshold-Mode Diagram
Flag register. Configure ALARM for open-drain/push-
pull and active-high/active-low by setting the respective
bits in the Hardware Alarm Configuration register.
BUSY Output
The BUSY output is forced high to show that the
MAX1385/MAX1386 are busy for a variety of reasons:
• The ADC is in the middle of a user-commanded con-
version cycle (but not in continuous convert mode)
SAFE1/SAFE2 Outputs
Set up the SAFE1 and SAFE2 outputs to allow Wired-
OR/AND-type logic functions or to create additional
interrupt-type signals to replace or supplement the
existing ALARM output. SAFE1 and SAFE2 do not have
any internal pullup/pulldown devices.
• The ADC is in the middle of an internally triggered
conversion cycle (for a self-calibration measurement)
• The device is in the middle of DAC calibra-
tion calculations
The SAFE1 and SAFE2 output buffers are CMOS-com-
patible, noninverting, output buffers capable of driving
to within 0.5V of either digital rail. The SAFE1 and
SAFE2 outputs power up as active-high CMOS outputs
with standard logic levels. Configure the SAFE1 and
SAFE2 outputs for open-drain or push-pull by setting
the appropriate bits in the Hardware Alarm
Configuration register. When configuring SAFE1 and
SAFE2 as open-drain outputs, an external pullup resis-
tor is required.
• The device is in the middle of power-up initialization
• One of the PGA channels is undergoing self-calibration
The serial interface remains active regardless of the
state of the BUSY output. Wait until BUSY goes low to
read the current conversion data from the FIFO. When
BUSY is high as a result of an ADC conversion, do not
enter a second conversion command until BUSY has
gone low to indicate the previous conversion is com-
plete. The rising edge of BUSY occurs on the next inter-
nal oscillator clock after the start of a new conversion
(either by CNVST or an interface command).
24 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
MEASUREMENT VALUE
(TEMPERATURE OR CURRENT)
HIGH THRESHOLD
BUILT-IN HYSTERESIS
BUILT-IN HYSTERESIS
LOW THRESHOLD
TIME
ALARM OUTPUT
OUTPUT-
COMPARATOR MODE
(ACTIVE LOW)
OUTPUT-
INTERRUPT MODE
(ACTIVE LOW)
FLAG REGISTER FLAG REGISTER
READ READ
FLAG REGISTER
READ
TIME
Figure 8. Window-Threshold-Mode Timing Diagram
In single-conversion mode (CKSEL = 11), the BUSY
signal remains high until the ADC has completed the
current conversion (not the entire scan, just the current
conversion), the data has been moved into the FIFO,
and the alarm limits for the channel have been checked
(if enabled). In multiple-conversion mode (CKSEL = 01
or CKSEL = 00), the BUSY signal remains high until all
channels have been scanned and the data from the
final channel has been moved into the FIFO and
checked for alarm limits (if enabled). In continuous-con-
version mode (CONCONV = 1), the BUSY signal does
not go high as a result of ADC conversions; however,
BUSY does go high when CONCONV is removed and
remains high until the current scan is complete and the
ADC sequence halts.
current is too high, and then to deassert when the tem-
perature/current falls back to an appropriate level.
ALARM asserts when SAFE1 and/or SAFE2 asserts.
Program ALARM for output-comparator mode to stay
asserted after an alarm condition until temperature/cur-
rent levels are back below programmed thresholds.
Program ALARM for output-interrupt mode to stay
asserted after an alarm condition until the Flag register
is read.
Window-Threshold Mode
In window-threshold mode, ADC readings of
current/temperature are compared to the configured
current/temperature low/high thresholds that are pro-
grammed to cause an alarm condition. If an ADC read-
ing falls out of the configured window and ALARM is
configured for output-comparator mode, ALARM
asserts until the current/temperature reading falls back
into the window (past the built-in hysteresis). If an ADC
reading falls out of the configured window and ALARM
is configured for output-interrupt mode, ALARM asserts
until the Flag register is read. Set the amount of built-in
hysteresis from 8 LSBs to 64 LSBs (see the ALMSCFG
(Read/Write) section). See Figures 7 and 8.
After commanding any of the DAC autocalibration compo-
nents, wait for BUSY to go low before setting OSCPD to 1.
Alarm Modes
The MAX1385/MAX1386 contain several programmable
modes for configuring outputs ALARM, SAFE1, and
SAFE2 behavior. Window-threshold mode allows SAFE_
to assert when the temperature/current is too high or
too low (outside the window). Hysteresis-threshold
mode allows SAFE_ to assert when the temperature/
______________________________________________________________________________________ 25
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
HIGHEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
RISES ABOVE THIS LEVEL
HIGH THRESHOLD
LOW THRESHOLD
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
FALLS BELOW THIS LEVEL
RANGE OF VALUES THAT DO NOT CAUSE AN ALARM
LOWEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR LOW
THRESHOLD REGISTER)
*ONLY WHEN ALARM IS CONFIGURED FOR OUTPUT-COMARATOR MODE.
WHEN IN OUTPUT-INTERRUPT MODE, FLAG REGISTER MUST BE READ
FOR ALARM TO BE DEASSERTED.
5/MAX1386
Figure 9. Hysteresis-Threshold-Mode Diagram
Hysteresis-Threshold Mode
In hysteresis-threshold mode, ADC readings of
current/temperature are compared to the configured
current/temperature low/high thresholds that are pro-
grammed to cause an alarm condition. If an ADC read-
ing exceeds its respective configured threshold and
ALARM is configured for output-comparator mode,
ALARM asserts until the current/temperature reading
falls back below its respective threshold. If an ADC
reading exceeds its respective configured threshold
and ALARM is configured for output-interrupt mode,
ALARM asserts until the Flag register is read. See
Figures 9 and 10.
TH1 and TH2 (Read/Write)
Write to Channel 1 and Channel 2 High Temperature
Threshold registers by sending the appropriate write
command byte followed by data bits D15–D0 (see Table
3). Bits D15–D12 are don’t care. Read channel 1 and
channel 2 high-temperature thresholds by sending the
appropriate read command byte. Channel 1 and
Channel 2 Temperature Threshold registers are com-
pared to temperature readings from the remote diode
connected transistors. Temperature data is in two’s-com-
plement format and the LSB corresponds to 1/8°C (see
Figure 26 for the Temperature Transfer Function).
TL1 and TL2 (Read/Write)
Write to Channel 1 and Channel 2 Low-Temperature-
Threshold registers by sending the appropriate write
command byte followed by data bits D15–D0 (see Table
4). Bits D15–D12 are don’t care. Read channel 1 and
channel 2 low-temperature thresholds by sending the
appropriate read command. Channel 1 and Channel 2
Temperature Threshold registers are compared to tem-
perature readings from the remote diode connected tran-
sistors. Temperature data is in two’s-complement format
and the LSB corresponds to 1/8°C (see Figure 26 for the
Temperature Transfer Function).
Register Descriptions
Communicate with the MAX1385/MAX1386 through the
I2C/SPI-compatible serial interface. Complete read and
write operations consist of slave address bytes, com-
mand bytes, and data bytes. The following register
descriptions cover the contents of command bytes and
data bytes. See the Digital Serial Interface section for a
detailed description of how to construct full read and
write operations. All registers are volatile and are reset
to default states upon removal of power. These default
states are referred to as power-on reset (POR) states.
All accessible MAX1385/MAX1386 registers are shown
in Table 2.
26 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 2. Register Listing (See Appendix: Recommended Power-Up Code Sequence section)
HEX COMMAND
REGISTER DESCRIPTION
Analog-to-Digital Conversion
MNEMONIC
WRITE
62
24
20
26
22
2C
28
2E
2A
34
36
74
76
3A
3C
7A
7C
30
—
READ
—
ADCCON
IH1
Channel 1 High-Current Threshold
Channel 1 High-Temperature Threshold
Channel 1 Low-Current Threshold
Channel 1 Low-Temperature Threshold
Channel 2 High-Current Threshold
Channel 2 High-Temperature Threshold
Channel 2 Low-Current Threshold
Channel 2 Low-Temperature Threshold
Coarse DAC1 High Wiper Input
Coarse DAC1 Low Wiper Input
A4
A0
A6
A2
AC
A8
AE
AA
B4
B6
B4
B6
BA
BC
BA
BC
B0
80
B8
—
TH1
IL1
TL1
IH2
TH2
IL2
TL2
HIWIPE1
LOWIPE1
THRUHI1
THRULO1
HIWIPE2
LOWIPE2
THRUHI2
THRULO2
DCFIG
Coarse DAC1 Write-Through High Wiper Input
Coarse DAC1 Write-Through Low Wiper Input
Coarse DAC2 High Wiper Input
Coarse DAC2 Low Wiper Input
Coarse DAC2 Write-Through High Wiper Input
Coarse DAC2 Write-Through Low Wiper Input
Device Configuration
FIFO Memory
FIFO
Fine DAC1 Input Read
RDFINE1
FINECAL1
FINE1
—
Fine DAC1 Input Register with Autocalibration
Fine DAC1 Input Without Autocalibration
Fine DAC1 Write-Through Input with Autocalibration
Fine DAC1 Write-Through Input Without Autocalibration
Fine DAC2 Input Read
38
50
78
52
—
—
FINECALTHRU1
FINETHRU1
RDFINE2
FINECAL2
FINE2
—
—
BE
—
Fine DAC2 Input Register with Autocalibration
Fine DAC2 Input Without Autocalibration
Fine DAC2 Write-Through Input with Autocalibration
Fine DAC2 Write-Through Input Without Autocalibration
Flag
3E
54
7E
56
—
—
FINECALTHRU2
FINETHRU2
RDFLAG
ALMHCFG
PGACAL
SCLR
—
—
EA
E0
—
Hardware Alarm Configuration
60
4E
68
66
64
32
PGA Calibration Control
Software Clear
—
Software LDAC
LDAC
—
Software Shutdown
SSHUT
—
Software Alarm Configuration
ALMSCFG
B2
______________________________________________________________________________________ 2ꢃ
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
MEASUREMENT VALUE
(TEMPERATURE OR CURRENT)
HIGH THRESHOLD
LOW THRESHOLD
TIME
ALARM OUTPUT
OUTPUT-
COMPARATOR MODE
(ACTIVE LOW)
OUTPUT-
INTERRUPT MODE
(ACTIVE LOW)
5/MAX1386
FLAG REGISTER
READ
TIME
FLAG REGISTER
READ
Figure 10. Hysteresis-Threshold-Mode Timing Diagram
Table 3. TH1 and TH2 (Read/Write)
D11
(MSꢂ)
D0
(LSꢂ)
D15 D14 D13 D12
D10
D9
D8
Dꢃ
D6
D5
D4
D3
D2
D1
POR
X
X
X
X
X
X
X
X
0
1
1
1
1
1
1
1
1
1
1
1
Bit Value
(°C)
-256
+128 +64
+32
+16
+8
+4
+2
+1
+0.5 +0.25 +0.125
X = Don’t care.
IH1 and IH2 (Read/Write)
where I
SENSE
is the current threshold in amperes,
DRAIN
Write to Channel 1 and Channel 2 High-Current-
Threshold registers by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 5). Bits D15–D12 are don’t care. Read channel 1
and channel 2 high-current thresholds by sending the
appropriate read command byte. Channel 1 and
Channel 2 Current-Threshold registers are compared to
ADC readings at PGAOUT1 and PGAOUT2. Use the
following equation to find the required threshold code
for a specified threshold current:
R
is the sense resistor, Av
is the voltage gain
PGA
of the PGA, V
is the ADC reference voltage, and
REFADC
I
is the resulting threshold register value
THRESH
in decimal.
IL1 and IL2 (Read/Write)
Write to Channel 1 and Channel 2 Low-Current-
Threshold registers by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 6). Bits D15–D12 are don’t care. Read channel 1
and channel 2 low-current thresholds by sending the
appropriate read command byte. Channel 1 and
Channel 2 Low-Current Threshold registers are com-
pared to ADC readings at PGAOUT1 and PGAOUT2.
4096
I
=I
×R
× Av
×
THRESH DRAIN
SENSE
PGA
V
REFADC
28 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 4. TL1 and TL2 (Read/Write)
D11
(MSꢂ)
D0
(LSꢂ)
D15 D14 D13 D12
D10
D9
D8
Dꢃ
D6
D5
D4
D3
D2
D1
POR
X
X
X
X
X
X
X
X
1
0
0
0
0
0
0
0
0
0
0
0
Bit Value
(°C)
-256
+128 +64
+32
+16
+8
+4
+2
+1
+0.5 +0.25 +0.125
X = Don’t care.
Table 5. IH1 and IH2 (Read/Write)
D11
D15 D14 D13 D12
(MSꢂ)
D0
(LSꢂ)
D10
D9
D8
Dꢃ
D6
D5
D4
D3
D2
D1
POR
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
Bit Value
—
—
—
—
—
—
—
—
—
—
—
—
X = Don’t care.
Table 6. IL1 and IL2 (Read/Write)
D11
(MSꢂ)
D0
(LSꢂ)
D15 D14 D13 D12
D10
D9
D8
Dꢃ
D6
D5
D4
D3
D2
D1
POR
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
Bit Value
—
—
—
—
—
—
—
—
—
—
—
—
X = Don’t care.
Use the following equation to find the required thresh-
old code for a specified threshold current:
of each clock mode. Set REFADC1 and REFADC0 to
select external/internal reference for the ADC (see
Table 7c). Set REFDAC1 and REFDAC0 to select exter-
nal/internal reference for both DACs (see Table 7d).
4096
I
=I
×R
× Av
×
THRESH DRAIN
SENSE
PGA
V
REFADC
When mode 11 is selected, the external capacitor that
is connected to the REFADC is charged by a resistor
with a typical value of 400kΩ. This time constant needs
to be allowed for powering up the reference. Avoid
leakage paths to REFADC.
where I
SENSE
is the current threshold in amperes,
DRAIN
is the sense resistor, Av
R
is the voltage gain
PGA
of the PGA, V
is the ADC reference voltage, and
REFADC
I
is the resulting threshold register value
THRESH
ALMSCFG (Read/Write)
The Software Alarm Configuration register controls the
behavior of outputs SAFE1, SAFE2, and ALARM. Write
to the Software Alarm Configuration register by sending
the appropriate write command byte followed by data
bits D15–D0 (see Table 8). Bits D15–D12 are don’t
care. Read the Software Alarm Configuration register
by sending the appropriate command byte.
in decimal.
DCFIG (Read/Write)
Select PGA gain settings, clock modes, and DAC and
ADC reference modes by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 7). Bits D15–D10 are don’t care. Read the Device
Configuration register by sending the appropriate read
command byte. Program PG2SET1 and PG2SET0 to set
channel 2’s current-sense amplifier gain (see Table 7a).
Program PG1SET1 and PG1SET0 to set channel 1’s
current-sense amplifier gain (see Table 7a). Set
CKSEL1 and CKSEL0 to determine the conversion and
acquisition timing clock modes (see Table 7b). See the
ADC Clock Modes section for a functional description
Set ALMSCLR to 1 to immediately set all temperature/
current threshold registers to their POR state. In addi-
tion, temperature-/current-related bits of the Flag regis-
ter are also reset to their POR state. The ALMSCLR
resets to 0 immediately after a write. Set ALARMCMP to
1 to enable output-comparator mode for ALARM and to
0 to enable output-interrupt mode for ALARM (see the
______________________________________________________________________________________ 29
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
Table ꢃ. DCFIG (Read/Write)
Table ꢃa. Gain-Setting Modes
ꢂIT NAME DATA ꢂIT POR
FUNCTION
Don’t care
PG_SET1
PG_SET0
FUNCTION
PGA_ gain of 2
X
D15–D10
D9
X
0
0
0
0
0
0
1
0
1
X
PG2SET1
PG2SET0
PG1SET1
PG1SET0
PGA 2 gain-setting
PGA 2 gain-setting
PGA 1 gain-setting
PGA 1 gain-setting
PGA_ gain of 10
PGA_ gain of 25
D8
D7
X = Don’t care.
D6
Table ꢃb. Clock Modes
Clock mode and CNVST
configuration
CKSEL1
CKSEL0
D5
D4
0
0
CONꢁERSION
CKSEL1 CKSEL0
CLOCK
ACQUISITION/
SAMPLING
Clock mode and CNVST
configuration
Internally timed
acquisitions and
conversions.
Conversions started by
a write to the Analog-
to-Digital Conversion
register or setting the
CONCONV bit.
REFADC1
REFADC0
REFDAC1
REFDAC0
D3
D2
D1
D0
0
0
0
0
ADC reference select
ADC reference select
DAC reference select
DAC reference select
0
0
Internal
Internal
5/MAX1386
Alarm Modes section). Setting ALARMCMP does not
affect SAFE1 and SAFE2 outputs. Program
ALARMHYST1 and ALARMHYST0 to set the amount of
built-in hysteresis used in window-threshold mode.
Internally timed
acquisitions and
conversions.
Conversions begin with
a high-to-low transition
at CNVST.
0
1
See the ALARM Output and SAFE1/SAFE2 Outputs
sections for a description of the relationship between
ALARM and SAFE1 and SAFE2. Set TALARM2 to 1 to
allow channel 2 temperature measurements to control
the state of SAFE2 and ALARM based on channel 2
temperature thresholds. Set TWIN2 to 0 to enable hys-
teresis-threshold mode and to 1 to enable window-
1
1
0
1
—
Reserved. Do not use.
Externally timed
acquisitions by
CNVST. Conversions
internally timed.
Internal
threshold mode for channel
2
temperature
measurements (see the Alarm Modes section). Set
IALARM2 to 1 to allow channel 2 current measurements
to control the state of SAFE2 and ALARM based on
channel 2 current thresholds. Set IWIN2 to 0 to enable
hysteresis-threshold mode and to 1 to enable window-
threshold mode for channel 2 current measurements.
Table ꢃc. ADC Reference Selection
REFADC1 REFADC0
DESCRIPTION
External. Bypass REFADC with a
0.1µF capacitor to AGND.
0
1
X
0
Set TALARM1 to 1 to allow channel 1 temperature mea-
surements to control the state of SAFE1 and ALARM
based on channel 1 temperature thresholds. Set TWIN1
to 0 to enable hysteresis-threshold mode and to 1 to
enable window-threshold mode for channel 1 tempera-
ture measurements (see the Alarm Modes section). Set
IALARM1 to 1 to allow channel 1 current measurements
to control the state of SAFE1 and ALARM based on
channel 1 current thresholds. Set IWIN1 to 0 to enable
hysteresis-threshold mode and to 1 to enable window-
threshold mode for channel 1 current measurements.
Internal. Leave REFADC
unconnected.
Internal. Connect a 0.1µF capacitor
to REFADC for better noise
performance.
1
1
X = Don’t care.
followed by data bits D15–D0 (see Table 9). Bits
D14–D8 are don’t care. Read the Coarse DAC1/DAC2
High Wiper Input register by sending the appropriate
read command byte. The DAC output is not updated
until an LDAC command is issued, at which point the
HIWIPE1 and HIWIPE2 (Read/Write)
Write to the Coarse DAC1/DAC2 High Wiper Input reg-
ister by sending the appropriate write command byte
30 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 12). Bits D15–D8 are reserved and must be set to
0. Bits D7–D3 are don’t care. Set FIRSTB to 1 to enable
tracking-calibration mode, and to 0 to enable acquisi-
tion-calibration mode.
Table ꢃd. DAC Reference Selection
REFDAC1 REFDAC0
DESCRIPTION
External. Bypass REFDAC with a
0.1µF capacitor to AGND.
0
1
X
0
During an offset calibration trial, for either mode, the
corresponding PGAOUT_ is put into hold, which pro-
duces a pedestal error for 67µs typically and BUSY is
set to 1. In acquisition mode, the calibration routine
operates continuously, first on channel 1 and then on
channel 2, until the channel-input offset voltage error
has been reduced to within 50µV. The time taken for
both channels to complete acquisition depends upon
the initial channel offset voltage error but should never
be longer than 112ms. In tracking mode, a pair of offset
calibration trials, first on channel 1 and then on channel
2, are made each time DOCAL is set to 1 or every 20ms
if the SELFTIME bit is set to 1. To reject noise, the offset
trim DAC code (not shown in the Functional Diagram)
only increments or decrements after the results of 16
calibration trials have been averaged.
Internal. Leave REFDAC
unconnected.
Internal. Connect a 0.1µF capacitor
to REFDAC for extra decoupling
and better noise performance.
1
1
X = Don’t care.
DAC input register is transferred to the appropriate DAC
output register. Automatic calibration of the high wiper is
initiated if the HCAL bit in the DAC input register is set to
1 when the appropriate LDAC command is issued.
LOWIPE1 and LOWIPE2 (Read/Write)
Write to the Coarse DAC1/DAC2 Low Wiper Input regis-
ter by sending the appropriate command byte followed
by data bits D15–D0 (see Table 10). Bits D14–D8 are
don’t care. Read the Coarse DAC1/DAC2 Low Wiper
Input register by sending the appropriate read com-
mand byte. The DAC output is not updated until an
LDAC command is issued, at which point the DAC
input register is transferred to the appropriate DAC out-
put register. Automatic calibration of the low wiper is
initiated if the LCAL bit in the DAC input register is set
to 1 when the appropriate LDAC command is issued.
Set FIRSTB to 0 and DOCAL to 1 to initiate an acquisi-
tion calibration. Acquisition must be done before track-
ing the first time a PGA calibration is commanded. Set
FIRSTB to 1, DOCAL to 1, and SELFTIME to 0 to trigger
an offset calibration trial on PGA1 and PGA2. At the
end of the routine, DOCAL returns to 0. Set FIRSTB to
1, DOCAL to 1 (optional to trigger calibration once
immediately before SELFTIME starts periodic calibra-
tions), and SELFTIME to 1, just once, to trigger periodic
offset-calibration trials (approximately every 20ms). Set
SELFTIME to 0 to halt the periodic calibration.
FINECAL1 and FINECAL2 (Write)
Write to the Fine DAC1/DAC2 Input register with auto-
calibration by sending the appropriate write command
byte followed by data bits D15–D0 (see Table 11). Bits
D15–D10 are don’t care. A write to these registers trig-
gers the autocalibration but does not automatically
update the output of the DAC. Write to the Software
LDAC register (LDAC) to transfer the Fine DAC Input
register contents to the Fine DAC Output register,
thereby updating the output of the DAC. POR contents
for these registers are all zeros. Read the DAC input
register values written to Fine DAC1 and DAC2 Input
registers through the Fine DAC1/DAC2 Input Read reg-
ister. These read registers contain the latest user-write
to any Fine DAC1 or Fine DAC2 Input Read register
and do not contain autocalibration-corrected values.
FINE1 and FINE2 (Write)
Write to the Fine DAC1/DAC2 Input register without auto-
calibration by sending the appropriate write command
byte followed by data bits D15–D0 (see Table 13). Bits
D15–D10 are don’t care. A write to these registers does
not trigger the autocalibration and does not automatically
update the output of the DAC. Write to the Software
LDAC register (LDAC) to transfer the DAC input register
contents to the Fine DAC Output register, thereby updat-
ing the output of the fine DAC. POR contents for these
registers are all zeros. Read the DAC input register val-
ues written to Fine DAC1 and DAC2 Input registers
through the Fine DAC1/DAC2 Input Read register. These
read registers contain the latest user-write to any Fine
DAC1 or Fine DAC2 Input Read register and do not con-
tain autocalibration corrected values.
PGACAL (Write)
Write to the PGA Calibration Control register to calibrate
PGA1 and PGA2 internal amplifiers. Write to the PGA
Calibration Control register by sending the appropriate
write command byte followed by data bits D15–D0 (see
FINETHRU1 and FINETHRU2 (Write)
Write to the Fine DAC1/DAC2 Write-Through Input reg-
ister without autocalibration by sending the appropriate
write command byte followed by data bits D15–D0 (see
______________________________________________________________________________________ 31
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
Table 8. ALMSCFG (Read/Write)
ꢂIT NAME
DATA ꢂIT
POR
FUNCTION
X
D15–D12
X
Don’t care
1 = Temp/current thresholds set to POR state
0 = Temp/current thresholds unaffected
ALMSCLR
D11
D10
0
0
1 = ALARM in output-comparator mode
0 = ALARM in output-interrupt mode
ALARMCMP
Thresholds hysteresis (ALARMHYST1 is MSB)
00 = 8 LSBs of hysteresis
ALARMHYST1
D9
0
01 = 16 LSBs of hysteresis
10 = 32 LSBs of hysteresis
11 = 64 LSBs of hysteresis
ALARMHYST0
TALARM2
D8
D7
0
0
1 = SAFE2 and ALARM dependent on channel 2 temperature
0 = SAFE2 and ALARM not dependent on channel 2 temperature
1 = Channel 2 temperature thresholds are in window-threshold mode
0 = Channel 2 temperature thresholds are in hysteresis-threshold mode
TWIN2
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
5/MAX1386
1 = SAFE2 and ALARM dependent on channel 2 current
0 = SAFE2 and ALARM not dependent on channel 2 current
IALARM2
IWIN2
1 = Channel 2 current thresholds are in window-threshold mode
0 = Channel 2 current thresholds are in hysteresis-threshold mode
1 = SAFE1 and ALARM dependent on channel 1 temperature
0 = SAFE1 and ALARM not dependent on channel 1 temperature
TALARM1
TWIN1
1 = Channel 1 temperature thresholds are in threshold-window mode
0 = Channel 1 temperature thresholds are in hysteresis-threshold mode
1 = SAFE1 and ALARM dependent on channel 1 current
0 = SAFE1 and ALARM not dependent on channel 1 current
IALARM1
1 = Channel 1 current thresholds are in window-threshold mode
0 = Channel 1 current thresholds are in hysteresis-threshold mode
IWIN1
X = Don’t care.
Table 9. HIWIPE1 and HIWIPE2 (Read/Write)
ꢂIT NAME
DATA ꢂIT
POR
FUNCTION
1 = High wiper autocalibration.
0 = No high wiper autocalibration.
HCAL
D15
1
X
—
—
D14–D8
D7–D0
Don’t care.
0000 0000 8-bit coarse high wiper DAC input code. D7 is the MSB.
Table 14). Bits D15–D10 are don’t care. A write to these
registers does not trigger the autocalibration but imme-
diately updates the output of the DAC by transferring
the DAC input register to the DAC output register (writ-
ing through the input register). POR contents for these
registers are all zeros. Read the DAC input register val-
ues written to Fine DAC1 and DAC2 Input registers
through the Fine DAC1/DAC2 Input Read register.
These read registers contain the latest user write to any
Fine DAC1 or Fine DAC2 Input Read register and do
not contain autocalibration corrected values.
32 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 10. LOWIPE1 and LOWIPE2 (Read/Write)
ꢂIT NAME
DATA ꢂIT
POR
FUNCTION
1 = Low wiper autocalibration.
0 = No low wiper autocalibration.
LCAL
D15
1
X
—
—
D14–D8
D7–D0
Don’t care.
0000 0000 8-bit coarse low wiper DAC input code. D7 is the MSB.
ALMHCFG (Read/Write)
Table 11. FINECAL1 and FINECAL2 (Write)
The Hardware Alarm Configuration register controls
SAFE1, SAFE2, and ALARM outputs. Write to the
Hardware Alarm Configuration register by sending the
appropriate write command byte followed by data bits
D15–D0 (see Table 15). Bits D15–D8 are don’t care.
Read the Hardware Alarm Configuration register by
sending the appropriate read command byte.
DATA ꢂIT
POR
FUNCTION
Don’t care.
D15–D10
X
10-bit fine DAC input code.
D9 is the MSB.
D9–D0
00 0000 0000
2) Set SAFE1OPN and SAFE2OPN to 0s.
Set SETSAFE1 to 1 to immediately force SAFE1 active.
This is especially useful when SAFE1 is connected to
OPSAFE1, giving the user software control over shut-
ting down the LDMOS transistor. Set SETSAFE1 to 0 for
normal operation. SETSAFE2 has the same functionality
as SETSAFE1 but for channel 2.
This ensures that when SAFE1 and SAFE2 are assert-
ed, and connected to OPSAFE1 and OPSAFE2, the
LDMOS transistors are shut off.
ADCCON (Write)
The Analog-to-Digital Conversion register selects which
inputs to the ADC are converted. Write to the Analog-to-
Digital Conversion register by sending the appropriate
write command byte followed by data bits D15–D0 (see
Table 16). Bits D15–D12 are don’t care. Bits D11–D8
are reserved bits and need to be set to 0. Read the
results of the conversions in the FIFO by sending the
appropriate read command byte. See the ADC
Description section for a complete description of the
ADC.
Set ALARMPOL to 1 to configure ALARM active-low. Set
it to 0 to configure ALARM active-high. Set ALARMOPN
to 1 to configure ALARM open-drain. Set it to 0 to config-
ure ALARM push-pull. Set SAFE1POL to 1 to configure
SAFE1 for active-low, and to 0 for active-high. Set
SAFE2POL to 1 to configure SAFE2 for active-low, and to
0 for active-high. Set SAFE1OPN to 1 to configure SAFE1
for open-drain, and to 0 for push-pull. Set SAFE2OPN
to 1 to configure SAFE2 for open-drain, and to 0 for
push-pull.
Set CONCONV to 1 to convert selected inputs to the
ADC continuously and to 0 to convert selected inputs to
the ADC only once. Set ADCSEL2 to 1 to select volt-
ages at ADCIN2 to be converted. Set IEXT2 to 1 to
select voltages at PGAOUT2 to be converted. Set
When connecting SAFE1 and SAFE2 outputs to
OPSAFE1 and OPSAFE2 inputs, configure the device
as follows:
1) Set SAFE1POL and SAFE2POL to 0s.
Table 12. PGACAL (Write)
ꢂIT NAME DATA ꢂIT RESET STATE
FUNCTION
RESERVED
X
D15–D8
D7–D3
0
X
Reserved. Set to 0.
Don’t care.
1 = Tracking calibration mode.
0 = Acquisition calibration mode.
FIRSTB
DOCAL
D2
D1
D0
0
0
0
1 = Initiate the calibration defined by FIRSTB (one time).
0 = Do not initiate a calibration.
1 = Initiate periodic calibrations defined by FIRSTB (every 15ms).
0 = Stop periodic calibrations.
SELFTIME
______________________________________________________________________________________ 33
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
TEXT2 to 1 to select the temperature at external diode 2
to be converted. Set ADCSEL1 to 1 to select voltages at
ADCIN1 to be converted. Set IEXT1 to 1 to select volt-
ages at PGAOUT1 to be converted. Set TEXT1 to 1 to
select the temperature at external diode 1 to be con-
verted. Set TINT to 1 to select the internal temperature
of the MAX1385/MAX1386 to be converted.
Table 13. FINE1 and FINE2 (Write)
DATA ꢂIT
POR
FUNCTION
Don’t care.
D15–D10
X
10-bit fine DAC input code. D9
is the MSB.
D9–D0
00 0000 0000
During continuous conversions (CONCONV = 1),
the ADC does not trigger the BUSY signal. When
CONCONV is set to 0, the current scan (not just the
current conversion) is completed and the ADC waits for
the next command. During continuous conversions, the
FIFO overflows if the user does not read it quickly
enough. When the FIFO overflows, it contains a mixture
of old and new conversion results (see the RDFLAG
(Read) section). Continuous conversion mode is only
available in clock modes 00 and 01.
Table 14. FINETHRU1 and FINETHRU2
(Write)
DATA ꢂIT
POR
FUNCTION
D15–D10
X
Don’t care.
10-bit fine DAC input code.
D9 is the MSB.
D9–D0
00 0000 0000
LDAC (Write)
The Software LDAC register controls the loading of the
DAC output registers with values from DAC input regis-
ters, allowing the user to update several changes to the
DAC all at once (see Table 18). Write to the Software
LDAC register by sending the appropriate write com-
mand byte followed by data bits D15–D0. Bits D15–D6
are don’t care. Any bit set to 1 in the Software LDAC
register is immediately set to 0 thereafter.
SSHUT (Write)
The Software Shutdown register shuts down all internal
blocks at once or the DAC, ADC, and PGA blocks indi-
vidually. Write to the Software Shutdown register by
sending the appropriate write command byte followed
by data bits D15–D0 (see Table 17). Bits D15–D8 and
D6, D5, and D4 are don’t care.
5/MAX1386
Set FULLPD to 1 to shut down all internal blocks and
reduce the AV
supply current to 0.2µA. FULLPD is
DD
set to 1 at power-up. To change to normal power mode,
write two commands to the Software Shutdown register.
The first command sets FULLPD to 0 (other bits in the
Software Shutdown register are ignored). A second
command is needed to activate any internal blocks.
FULLPD overrides all other shutdown bits; however, all
shutdown bits retain their data when FULLPD is set to
1. This means that if DAC1 and PGA1 are shut down
before FULLPD is set to 1, they remain shut down after
FULLPD is set to 0 again.
Table 15. ALMHCFG (Read/Write)
ꢂIT NAME DATA ꢂIT POR
FUNCTION
Don’t care
X
D15–D8
D7
X
0
1 = Force SAFE1 active
immediately
SETSAFE1
0 = Normal operation
1 = Force SAFE2 active
immediately
SETSAFE2
D6
0
0 = Normal operation
Set FBGON to 1 to force the internal bandgap refer-
ence to be powered at all times. Set FBGON to 0 to
transfer power-down control of the internal reference to
the ADC. In the event of DAC1PD or DAC2PD being set
to 0, the internal bandgap is forced on. Set OSCPD to 1
to shut down the internal oscillator. When the oscillator
is shut down, the ADC ceases conversions and internal
PGA calibration halts. Any interface command restarts
the oscillator and allows the system to resume from
where it left off. Set DAC2PD to 1 to shut down DAC2
and PGA2. Set DAC1PD to 1 to shut down DAC1 and
PGA1. DAC1PD and DAC2PD power down the individ-
ual blocks regardless of additional commands; howev-
er, writes are still permitted to the DACs and PGAs. For
maximum accuracy, do not command a DAC calibra-
tion while a DAC is powered down or powering up.
1 = ALARM is active-low
0 = ALARM is active-high
ALARMPOL
ALARMOPN
SAFE1POL
SAFE1OPN
SAFE2POL
SAFE2OPN
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1 = ALARM is open-drain
0 = ALARM is push-pull
1 = SAFE1 is active-low
0 = SAFE1 is active-high
1 = SAFE1 is open-drain
0 = SAFE1 is push-pull
1 = SAFE2 is active-low
0 = SAFE2 is active-high
1 = SAFE2 is open-drain
0 = SAFE2 is push-pull
34 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 16. ADCCON (Write)
BIT NAME DATA BIT POR
FUNCTION
X
D15–D12
D11–D8
X
0
Don’t care
Reserved
Reserved; set these bits to 0
1 = Continuous conversions (repeated scans)
0 = Noncontinuous conversions (one scan)
CONCONV
ADCSEL2
IEXT2
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1 = Select voltages at ADCIN2 to be converted
0 = Do not select voltages at ADCIN2 to be converted
1 = Select voltages at PGAOUT2 to be converted
0 = Do not select voltages at PGAOUT2 to be converted
1 = Select temperature at remote diode 2 to be converted
0 = Do not select temperature at remote diode 2 to be converted
TEXT2
1 = Select voltages at ADCIN1 to be converted
0 = Do not select voltages at ADCIN1 to be converted
ADCSEL1
IEXT1
1 = Select voltages at PGAOUT1 to be converted
0 = Do not select voltages at PGAOUT1 to be converted
1 = Select temperature at remote diode 1 to be converted
0 = Do not select temperature at remote diode 1 to be converted
TEXT1
1 = Select internal temperature of device to be converted
0 = Do not select internal temperature of device to be converted
TINT
Set FINECH2 to 1 to load the fine DAC2 output register
with the latest write to DAC2 input registers FINE2 or
FINECAL2. This means that if FINE2 is written to after
FINECAL2, FINE2 is sent to the fine DAC2 output regis-
ter (no calibration code) when FINECH2 is set to 1. Set
HIGHCH2 to 1 to load DAC input register HIWIPE2 into
the Coarse DAC2 High Wiper register. Autocalibration
of the DAC2 high wiper occurs if the HCAL bit in
HIWIPE2 is set to 1. Set LOWCH2 to 1 to load DAC
input register LOWIPE2 into the Coarse DAC2 Low
Wiper register. Autocalibration of the DAC2 low wiper
occurs if the LCAL bit in LOWIPE2 is set to 1.
SCLR (Write)
Write to the Software Clear register to reset the DACs
and FIFO to their POR states (see Table 19). Write to the
Software Clear register by sending the appropriate write
command byte followed by data bits D15–D0. Bits
D15–D10 are don’t care. A write to bits D5–D0 in the
Software Clear register immediately changes the appro-
priate DAC output to its power-on state (regardless of
LDAC). To reset all registers at once, set FULLRESET to
0 and ARMRESET to 1. Next set FULLRESET to 1 and
ARMRESET to 0. This 2-byte reset operation protects the
registers from being fully reset by inadvertent user
writes. After a full reset, the device is in shutdown mode
and the SSHUT register needs to be written to for full
operation.
Set FINECH1 to 1 to load the fine DAC1 output register
with the latest write to DAC input registers FINE1 or
FINECAL1. If FINECAL1 is written to after FINE1,
FINECAL1 is sent to the fine DAC1 output register (with
calibration code) when FINECH1 is set to 1. Set HIGH-
CH1 to 1 to load DAC input register HIWIPE1 into the
Coarse DAC1 output register. Autocalibration of the
DAC1 high wiper occurs if the HCAL bit in HIWIPE1 is
set to 1. Set LOWCH1 to 1 to load DAC input register
LOWIPE1 into the coarse DAC1 output register.
Autocalibration of the DAC1 low wiper occurs if the
LCAL bit in LOWIPE1 is set to 1.
Set CLFIFO to 1 to clear the entire 15-word FIFO and
FIFO-associated flag bits in the Flag register. Set
HIGHCL2 to 1 to reset the Coarse DAC2 High Wiper
Output and Input registers to their POR states. Set
LOWCL2 to 1 to reset the coarse DAC2 High Wiper
Output and Input registers to their POR states. Set
FINECL1 to 1 to reset Fine DAC1 Output and Input reg-
isters to their POR states. Set HIGHCL1 to 1 to reset
the Coarse DAC1 High Wiper Output and Input regis-
ters to their POR states. Set LOWCL1 to 1 to reset the
______________________________________________________________________________________ 35
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
Table 1ꢃ. SSHUT (Write)
ꢂIT NAME
DATA ꢂIT
POR
FUNCTION
X
D15–D8
X
Don’t care
1 = Shut down all internal blocks
0 = Do not shut down all internal blocks
FULLPD
X
D7
D6, D5, D4
D3
1
X
0
Don’t care
1 = Force internal bandgap reference to be powered always
0 = Let the ADC control power-down of the internal reference
FBGON
1 = Shut down the internal oscillator
0 = Do not shut down the internal oscillator
OSCPD
DAC2PD
DAC1PD
D2
D1
D0
0
1
1
1 = Power down DAC2
0 = Do not power down DAC2
1 = Power down DAC1
0 = Do not power down DAC1
5/MAX1386
Table 18. LDAC (Write)
ꢂIT NAME
DATA ꢂIT
POR
FUNCTION
X
D15–D6
X
Don’t care
1 = Update fine DAC2 with FINE2 or FINECAL2
0 = Do not update DAC2
FINECH2
HIGHCH2
LOWCH2
FINECH1
HIGHCH1
LOWCH1
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
1 = Update coarse DAC2 with HIWIPE2
0 = Do not update DAC2
1 = Update coarse DAC2 with LOWIPE2
0 = Do not update DAC2
1 = Update fine DAC1 with FINE1 or FINECAL1
0 = Do not update DAC1
1 = Update coarse DAC1 with HIWIPE1
0 = Do not update DAC1
1 = Update coarse DAC1 with LOWIPE1
0 = Do not update DAC1
Coarse DAC1 Low Wiper Output and Input registers to
their POR states. Set FINECL2 to 1 to reset Fine DAC2
Output and Input registers to their POR states.
Wiper Input register by sending the appropriate read
command byte.
THRULO1/THRULO2 (Read/Write)
Write to the Coarse DAC1/DAC2 Write-Through Low
Wiper Input register by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 21). Bits D15–D8 are don’t care. Writing to one of
these registers automatically writes through to the
appropriate DAC output register, thereby updating the
DAC output immediately. Writing to one of these regis-
ters does not trigger automatic low wiper calibration.
Read the Coarse DAC1/DAC2 Write-Through Low
THRUHI1 and THRUHI2 (Read/Write)
Write to the Coarse DAC1/DAC2 Write-Through High
Wiper Input register by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 20). Bits D15–D8 are don’t care. Writing to one of
these registers automatically writes through to the
appropriate DAC output register, thereby updating the
DAC output immediately. Writing to one of these regis-
ters does not trigger automatic high wiper calibration.
Read the Coarse DAC1/DAC2 Write-Through High
36 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 19. SCLR (Write)
ꢂIT NAME
DATA ꢂIT
POR
FUNCTION
X
D15–D10
D9
X
Don’t care
Full reset of all DAC registers is a two write operation:
1) FULLRESET = 0, ARMRESET = 1
FULLRESET
N/A
ARMRESET
X
D8
D7
0
X
2) FULLRESET = 1, ARMRESET = 0
Don’t care
1 = Clear FIFO and FIFO flag bits
0 = Do not clear FIFO or FIFO flag bits
CLFIFO
HIGHCL2
LOWCL2
FINECL1
HIGHCL1
LOWCL1
FINECL2
D6
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 = Reset coarse DAC2 high wiper to its POR state
0 = Do not reset coarse DAC2 high wiper to its POR state
1 = Reset coarse DAC2 low wiper to its POR state
0 = Do not reset coarse DAC2 low wiper to its POR state
1 = Reset fine DAC1 to its POR state
0 = Do not reset fine DAC1 to its POR state
1 = Reset coarse DAC1 high wiper to its POR state
0 = Do not reset coarse DAC1 high wiper to its POR state
1 = Reset coarse DAC1 high wiper to its POR state
0 = Do not reset coarse DAC1 high wiper to its POR state
1 = Reset fine DAC2 to its POR state
0 = Do not reset fine DAC2 to its POR state
Wiper Input register by sending the appropriate read
command byte.
the FIFO when the FIFO is empty results in the current
contents of the Flag read register to be sent.
FINETHRUCAL1 and FINETHRUCAL2 (Write)
Write to the Fine DAC1/DAC2 Write-Through Input reg-
ister with autocalibration by sending the appropriate
write command byte followed by data bits D15–D0 (see
Table 22). Bits D15–D10 are don’t care. A write to these
registers not only triggers the autocalibration but imme-
diately updates the output of the DAC by transferring
the DAC input register with correction code to the Fine
DAC output register. POR contents for these registers
are all zeros. Read the DAC Input register values writ-
ten to Fine DAC1 and DAC2 Input registers through the
Fine DAC1/DAC2 Input Read register. These read reg-
isters contain the latest user-write to any Fine DAC1 or
Fine DAC2 Input register and do not contain autocali-
bration-corrected values.
RDFINE1 and RDFINE2 (Read)
Read the Fine DAC1/DAC2 Input Read register by
sending the appropriate read command byte and read-
ing out data bits D15–D0 (see Table 24). Data contains
the last write to any Fine DAC1/DAC2 Input registers
and does not contain autocalibration-corrected values.
RDFLAG (Read)
The Flag register contains important system information
regarding ADC/FIFO status and alarm conditions. Read
the Flag register by sending the appropriate read com-
mand byte and reading out data bits D15–D0 (see
Table 25). Bits D15–D12 are don’t care. ADCBUSY is
set to 1 when the ADC is busy, an ALARM value is
being checked, or the ADC results are being loaded
into the FIFO. ADCBUSY is set to 0 when the ADC has
completed all the conversions in the current scan.
FIFO (Read)
Read the oldest result in the FIFO by sending the
appropriate read command byte and reading out data
bits D15–D0 (see Table 23). Bits D15–D12 are channel
tag bits that indicate the source of the conversion. Bits
D11–D0 contain the conversion result. Reading from
ALUBUSY is set to 1 when the ALU is busy and set to 0
when it is not. ALUBUSY is set to 1 for 134µs at power-
up for initialization. FIFOEMP is set to 1 when the FIFO
is empty and set to 0 when the FIFO contains data.
Writing to the appropriate bit in the Software Clear reg-
ister empties the FIFO and sets the FIFOEMP bit to 1.
______________________________________________________________________________________ 3ꢃ
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
FIFOOVER is set to 1 when the FIFO overflows.
FIFOOVER is set to 0 after reading the Flag register.
Table 20. THRUHI1 and THRUHI2
(Read/Write)
All threshold-related bits in the Flag register can be
cleared at once by writing to the ALMSCLR bit in the
Software Alarm Configuration register (see the ALMSCFG
(Read/Write) section). HIGHI2 is set to 1 when the chan-
nel 2 current exceeds its high threshold. HIGHI2 resets to
0 after reading the Flag register. LOWI2 is set to 1 when
the channel 2 current drops below its low threshold.
LOWI2 resets to 0 after reading the Flag register.
HIGHT2 is set to 1 when the channel 2 temperature
measurement exceeds its high threshold. HIGHT2
resets to 0 after reading the Flag register. The LOWT2
is set to 1 when the channel 2 temperature measure-
ment drops below its low threshold. LOWT2 resets to 0
after reading the Flag register.
DATA ꢂIT
POR
FUNCTION
D15–D8
X
Don’t care.
8-bit coarse high wiper DAC
input code. D7 is the MSB.
D7–D0
0000 0000
Table 21. THRULO1 and THRULO2
(Read/Write)
DATA ꢂIT
POR
FUNCTION
D15–D8
X
Don’t care.
8-bit coarse high wiper DAC input
code. D7 is the MSB.
D7–D0
0000 0000
HIGHI1 is set to 1 when the channel 1 current exceeds
its high threshold. HIGHI1 resets to 0 after reading the
Flag register. LOWI1 is set to 1 when the channel 1 cur-
rent drops below its low threshold. LOWI1 resets to 0
after reading the Flag register. HIGHT1 is set to 1 when
the channel 1 temperature measurement exceeds its
high threshold. HIGHT1 resets to 0 after reading the
Flag register. LOWT1 is set to 1 when the channel 1
temperature measurement drops below its low thresh-
old. LOWT1 resets to 0 after reading the Flag register.
5/MAX1386
Table 22. FINETHRUCAL1 and
FINETHRUCAL2 (Write)
DATA ꢂIT
POR
FUNCTION
Don’t care.
D15–D10
X
10-bit fine DAC input code. D9
is the MSB.
D9–D0
00 0000 0000
Digital Serial Interface
The MAX1385/MAX1386 contain an I2C-/SPI-compati-
ble serial interface for configuration. Connect the mode-
select input, SEL, to DGND to select I2C mode. In I2C
mode, the MAX1385/MAX1386 provide address inputs
A0 to A2 to allow eight devices to be connected on the
same bus (see the Slave Address Byte section).
2) Send the appropriate write command byte (see the
Command Byte section). The MAX1385/MAX1386
answer with an ACK bit.
3) Send the most significant 8-bit section of the 16-bit
data word, sending the MSBs first (see the Data
Bytes section). The MAX1385/MAX1386 answer with
an ACK bit.
Connect SEL to DV
to select SPI mode. In SPI mode,
DD
4) Send the least significant 8-bit section of the 16-bit
data word, sending the MSBs first. The MAX1385/
MAX1386 answer with an ACK bit.
drive A0/CSB low to select the device. The MAX1385/
MAX1386 support fast (400kHz) and high-speed
(1.7MHz or 3.4MHz) data-transfer modes. Data trans-
fers occur in 8-bit bytes with acknowledge (ACK) or
not-acknowledge (NACK) bits following each byte. The
MAX1385/ MAX1386 are permanent slaves and do not
generate their own clock signals. Figure 11 shows the
various read/write formats.
5) Generate a (repeated) START or STOP condition (Sr
or P).
To write to a block of registers, use the same steps as
above but repeat steps 2, 3, and 4 without any START,
STOP, or repeated START conditions (Sr). Finish the
block write by generating a STOP condition.
Write Format
Use the following sequence to write a single word (see
Figure 11):
Read Format
All read operations can begin with a Sr as well as an S
condition. One type of read is a 5-byte operation, one is
a 3-byte operation, and the other is a continuous read
operation. The 5-byte operation reads from the register
address contained in one of the 5 bytes sent. The 3-
byte operation reads from the last register address
accessed. Use the following 5-byte sequence to read
1) After generating a START condition (S or Sr),
address the MAX1385/MAX1386 by sending the
appropriate slave address byte with its correspond-
ing R/W bit set to zero (see the Slave Address Byte
section). The MAX1385/MAX1386 answer with an
ACK bit (see the Acknowledge Bits section).
38 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 23. FIFO (Read)
DATA ꢂITS
CONꢁERSION ORIGIN
D15
D14
D13
D12
D11
D0
0
0
0
0
MSB
LSB
Internal temperature sensor
Channel 1 external temperature
Channel 1 drain current (PGAOUT1)
ADCIN1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MSB
MSB
MSB
MSB
MSB
MSB
—
LSB
LSB
LSB
LSB
LSB
LSB
—
Channel 2 external temperature
Channel 2 drain current (PGAOUT2)
ADCIN2
Reserved
—
—
Reserved
—
—
Reserved
—
—
Reserved
—
—
Reserved
—
—
Reserved
—
—
Reserved
Conversion may be corrupted. This occurs only when
arriving data causes the FIFO to overflow at the same time
data is being read out.
1
1
1
1
1
1
0
1
MSB
MSB
LSB
LSB
Empty FIFO. The current value of the Flag register is
provided in place of the FIFO data.
16 bits of data from a MAX1385/MAX1386 register (see
Figure 11):
Table 24. RDFINE1 and RDFINE2 (Read)
DATA ꢂITS
POR
FUNCTION
Don’t care.
1) After generating a START condition (S or Sr),
address the MAX1385/MAX1386 by sending the
appropriate slave address byte and its correspond-
ing R/W bit set to a 0 (see the Slave Address Byte
section). The MAX1385/MAX1386 then answer with
an ACK bit (see the Acknowledge Bits section).
D15–D10
X
10-bit fine DAC input code.
D9 is the MSB.
D9–D0
00 0000 0000
6) The master issues a NACK bit and then generates a
repeated START or STOP condition (Sr or P).
2) Send the appropriate read command byte (see the
Command Byte section). The MAX1385/MAX1386
answer with an ACK bit.
Continue to poll the current register or read multiple
words (e.g., empty FIFO of several conversion results)
by omitting step 6 and keep issuing ACK bits after each
data byte. Use the following 3-byte sequence to read
16 bits of data from the last accessed MAX1385/
MAX1386 register:
3) After generating a repeated START condition (Sr),
address the MAX1385/MAX1386 once more by
sending the appropriate slave address byte and its
R/W bit set to 1. The MAX1385/MAX1386 answer
with an ACK bit.
1) After generating a START condition (S or Sr),
address the MAX1385/MAX1386 by sending the
appropriate 7-bit slave address byte and its corre-
sponding R/W bit set to 1 (see the Slave Address
Byte section). The MAX1385/MAX1386 then answer
with an ACK bit (see the Acknowledge Bits section).
4) The MAX1385/MAX1386 transmit the most signifi-
cant 8-bit data byte of the 16-bit data word with the
MSB first. Afterwards, the master needs to send an
ACK bit.
5) The MAX1385/MAX1386 transmit the least signifi-
cant 8-bit byte of the 16-bit word with the MSB first.
______________________________________________________________________________________ 39
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
WRITE WORD FORMAT
WRITE
COMMAND
S OR Sr
R/W
ADDRESS
7 BITS
ACK
ACK
DATA
ACK
DATA
ACK
Sr OR P
8 BITS (LSB)
8 BITS (MSB)
0
8 BITS
WRITE BLOCK FORMAT
WRITE
COMMAND
R/W
S OR Sr
ADDRESS
7 BITS
ACK
ACK
DATA
ACK
DATA
ACK
Sr OR P
8 BITS (LSB)
8 BITS (MSB)
8 BITS
0
N 3-BYTE SEQUENCES (S, Sr, AND P NOT NEEDED)
5-BYTE READ
S OR Sr
READ
COMMAND
Sr OR P
NACK
R/W
R/W
ADDRESS
7 BITS
ACK
ACK
Sr
ADDRESS
7 BITS
ACK
DATA
ACK
DATA
8 BITS (LSB)
5/MAX1386
8 BITS
8 BITS (MSB)
0
1
3-BYTE READ
S OR Sr
R/W
ADDRESS
7 BITS
ACK
DATA
ACK
DATA
8 BITS (LSB)
NACK
Sr OR P
8 BITS (MSB)
1
Figure 11. Read/Write Formats
2) The MAX1385/MAX1386 then transmit the contents
of the last register accessed starting with the most
significant 8-bit byte of the 16-bit word. MSBs are
sent first. Afterwards, the master needs to send an
ACK bit.
Figure 13 shows another useful sequence for a read-
modify-write application.
Slave Address ꢂyte
The MAX1385/MAX1386 include a 7-bit-long slave
address. The first 4 bits (MSBs) of the slave address
are factory programmed and always 0x4h. The logic
state of the address inputs (A2, A1, and A0) determine
the 3 LSBs of the device address (see Figure 14).
3) The MAX1385/MAX1386 transmit the least signifi-
cant 8-bit byte of the 16-bit word. MSBs are sent
first.
4) The master issues a NACK bit and then generates a
repeated START or STOP condition (Sr or P).
Connect A2, A1, and A0 to DV
or DGND. A maxi-
DD
mum of eight MAX1385/MAX1386 devices can be con-
nected on the same bus at one time using these
address inputs.
Poll the current register by omitting step 4 and continu-
ing to issue ACK bits after each data byte.
The 8th bit of the address byte is a R/W bit. The
address byte R/W bit is set to 0 to notify the device that
a command byte will be written to the device next. The
address byte R/W bit is set to 1 to notify the device that
a control byte will not be sent and to immediately send
data from the last accessed register.
Stringing Commands
The MAX1385/MAX1386 allow commands to be strung
together to minimize configuration time, which is espe-
cially useful in HS mode. Figure 12 shows an example
of stringing a write and read command together to form
a write/readback command.
40 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 25. RDFLAG (Read)
ꢂIT NAME
DATA ꢂIT
POR
FUNCTION
X
D15– D12
X
Don’t care
1 = ADC is busy
0 = ADC is not busy
ADCBUSY
ALUBUSY
FIFOEMP
FIFOOVER
HIGHI2
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
0
0
0
0
0
0
1 = ALU is busy
0 = ALU is not busy
1 = FIFO is empty
0 = FIFO is not empty
1 = FIFO overflowed
0 = FIFO not overflowed
1 = Channel 2 high current threshold exceeded
0 = Channel 2 high current threshold not exceeded
1 = Channel 2 low current threshold surpassed
0 = Channel 2 low current threshold not surpassed
LOWI2
1 = Channel 2 high temperature threshold exceeded
0 = Channel 2 high temperature threshold not exceeded
HIGHT2
LOWT2
1 = Channel 2 low temperature threshold surpassed
0 = Channel 2 low temperature threshold not surpassed
1 = Channel 1 high current threshold exceeded
0 = Channel 1 high current threshold not exceeded
HIGHI1
1 = Channel 1 low current threshold surpassed
0 = Channel 1 low current threshold not surpassed
LOWI1
1 = Channel 1 high temperature threshold exceeded
0 = Channel 1 high temperature threshold not exceeded
HIGHT1
LOWT1
1 = Channel 1 low temperature threshold surpassed
0 = Channel 1 low temperature threshold not surpassed
Command ꢂyte
while SCL is high and stable are considered control
The MAX1385/MAX1386 use read and write command
bytes (see Figure 15). The command byte consists of 8
bits and contains the address of the register. The com-
mand byte also communicates to the device whether a
read or write operation occurs. See the Register
Description section for details on how to access specif-
ic registers through the command byte.
signals (see the START and STOP Conditions section).
Both SDA and SCL remain high when the bus is not
active. The interface can support fast (400kHz) and
high-speed (1.7MHz or 3.4MHz) data-transfer modes.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high (Figure 17). A repeated
START condition (Sr) can be used in place of a STOP
condition to leave the bus active and the interface
transfer speed unchanged (see the Fast/High-Speed
Modes section).
Data ꢂytes
Data bytes are clocked in/out of the device with the
MSB first and the LSB last (see Figure 16). See the
Register Description section for a description of data
bytes for each register.
ꢂit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
______________________________________________________________________________________ 41
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
WRITE
COMMAND
ACK
ADDRESS
7 BITS
R/W
ACK
DATA
ACK
DATA
S OR Sr
ACK
8 BITS
8 BITS (MSB)
8 BITS (LSB)
0
Sr
DATA
DATA
NACK
R/W
ACK
ACK
Sr OR P
ADDRESS
7 BITS
8 BITS (MSB)
8 BITS (LSB)
1
Figure 12. Write/Readback Sequence
READ
COMMAND
ACK
DATA
8 BITS (MSB)
DATA
8 BITS (LSB)
NACK
ACK
ADDRESS
7 BITS
R/W
Sr
S OR Sr ADDRESS
7 BITS
R/W ACK
ACK
5/MAX1386
1
0
8 BITS
WRITE
COMMAND
ACK
DATA
ACK
R/W
ACK
DATA
Sr
ADDRESS
7 BITS
ACK
Sr OR P
8 BITS (MSB)
8 BITS
8 BITS (LSB)
0
Figure 13. Read-Modify-Write Sequence
S
0
1
SDA
ACK
R/W
1
0
0
A2
5
A1
6
A0
7
SCL
9
3
4
8
2
Figure 14. Slave Address Byte
Acknowledge ꢂits
Monitoring NACK bits allow for detection of unsuccess-
ful data transfers. NACK bits can also be used by the
master to interrupt the current data transfer to start
another data transfer. The MAX1385/MAX1386 do not
issue an ACK after the last byte of a full reset write to
the Software Clear register.
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX1385/MAX1386 generate ACK bits.
To generate an ACK, SDA must be pulled low before
the rising edge of the ninth clock pulse and kept low
during the high period of the ninth clock pulse (see
Figure 20). To generate a NACK, SDA is pulled high
before the rising edge of the ninth clock pulse and is
left high for the duration of the ninth clock pulse.
Fast/High-Speed Modes
At power-up, the bus timing is set for slow-/fast-speed
mode (FS mode), which allows bus speeds up to
400kHz. The MAX1385/MAX1386 are configurable for
42 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
C6
2
C3
5
C2
6
C1
7
C7
1
C5
3
C4
4
C0
8
ACK
9
SDA
SCL
Figure 15. Command Byte
NACK
OR ACK
D15
1
D13
3
D12
4
D10
6
D9
7
D8
8
D4
13
D14
2
D11
ACK
9
D6
11
D5
D3
14
D2
15
D0
17
D7
D1
16
SDA
SCL
5
10
12
18
Figure 16. Data Bytes
S
Sr
P
SDA
SCL
Figure 17. START and STOP Conditions
high-speed mode (HS mode), allowing bus speeds up
to 3.4MHz. Execute the following procedure to change
from FS mode to HS mode (see Figure 21).
SPI Digital Serial Interface
The MAX1385/MAX1386 feature a 4-wire SPI-compati-
ble serial interface capable of supporting data rates up
to 16MHz. Full data transfers occur in 24-bit sections.
The first 8-bit byte is a command byte (C7–C0). The
next 16 bits are data bits (D15–D0). Clock signal SCL
may idle low or high but data is always clocked in on
the rising edge of SCL (CPOL = CPHA).
1) Generate a START condition (S).
2) Send byte 00001XXX (X = don’t care). The MAX1385/
MAX1386 issue a NACK bit.
3) HS mode is entered on the 10th rising clock edge.
To remain in HS mode, use repeated START conditions
(Sr) in place of the normal STOP conditions (P) (see
Figure 22). All the same write and read formats sup-
ported in FS mode are supported in HS mode (with the
replacement of repeated START conditions for STOP
conditions). Generating a STOP condition (P) while in
HS mode changes the bus speed back to FS mode.
Write Format
Use the following sequence to write 16 bits of data to a
MAX1385/MAX1386 register (see Figure 18):
1) Pull CSB low to select the device.
2) Send the appropriate write command byte (see the
Command Byte section). The command byte is
clocked in on the rising edge of SCL.
______________________________________________________________________________________ 43
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
A RISING EDGE OF CSB
DURING THIS PERIOD
COMPLETES A VALID
WRITE COMMAND.
CSB
SCL
C6 C5 C4
C3 C2 C1 C0
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
DIN
CR/W
Figure 18. SPI Write Format
CSB
SCL
C6 C5 C4 C3 C2 C1 C0
DIN
CR/W
5/MAX1386
D15
D14 D13 D12 D11 D10 D9 D8
D7
D6 D5 D4 D3 D2 D1
D0
DOUT
Figure 19. SPI Read Format
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
8
1
9
2
SCL
Figure 20. Acknowledge Bits
3) Send 16 bits of data (D15–D0) starting with the most
significant bit and ending with the least significant
bit. Data is clocked in on the rising edges of SCL.
Command ꢂyte
The MAX1385/MAX1386 use read and write command
bytes. The command byte consists of 8 bits and contains
the address of the register (C7–C0, see Figures 18 and
19). The command byte also communicates to the
device whether a read or write operation occurs. See the
Register Description section for details on how to access
specific registers through the command byte.
4) Pull CSB high.
Read Format
Use the following sequence to read 16 bits of data from
a MAX1385/MAX1386 register (see Figure 19):
1) Pull CSB low to select the device.
Data ꢂytes
Data bytes are clocked in/out of the device with the
most significant bit first and the least significant bit last
(D15–D0, see Figures 18 and 19). See the Register
Description section for a description of data bytes for
each register.
2) Send the appropriate read command byte (see the
Command Byte section). The command byte is
clocked in on the rising edges of SCL.
3) Receive 16 bits of data. Data is clocked out on the
falling edges of SCL.
4) Pull CSB high.
44 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
HS-MODE MASTER CODE
A
Sr
0
X
0
0
0
1
X
X
S
SDA
SCL
HS MODE
FS MODE
Figure 21. Changing to HS Mode
MASTER TO SLAVE
SLAVE TO MASTER
FS MODE
FS MODE
FS MODE
A
Sr
A
P
A
S
MASTER CODE
SLAVE ADDRESS
COMMAND/DATA
R/W
N BYTES PLUS ACK
HS MODE CONTINUES
SLAVE ADD
Sr
HS MODE CAN ALSO BE CONTINUED
WITH A COMMAND BYTE
Figure 22. Changing to FS Mode or Staying in HS Mode
Leap-Frogging the DACs for 18 Bits of
Resolution
Each DAC stage is configurable for leapfrog operation
by using the 8-bit coarse DACs in conjunction with the
10-bit fine DAC. Use the following procedure for setting
18 bits of resolution:
Applications Information
ADC Clock Mode 11
See Figure 23 for an example of configuring a conver-
sion scan for internal temperature, PGAOUT1, and
ADCIN1 in clock mode 11 using the internal reference.
Timing symbols are referenced in the Miscellaneous
Timing Characteristics section.
1) Write to the Coarse DAC1/DAC2 Write-Through Low
Wiper Input register (THRULO1/THRULO2)
See Figure 24 for an example of configuring a conver-
sion scan for ADCIN1, external temperature sensor 2,
and PGAOUT2 in clock mode 11 using the internal ref-
erence. Timing symbols are referenced in the
Miscellaneous Timing Characteristics section.
2) Write to the Coarse DAC1/DAC2 Write-Through High
Wiper Input register (THRUHIGH1/THRUHIGH2) with
a value one higher or one lower than written to the
low wiper register.
Temperature-Threshold Examples
Table 26 shows some examples of temperature settings
in two’s-complement form.
______________________________________________________________________________________ 45
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
t
t
CNV11
t
ACQ11
ACQ11
CNVST
BUSY
IDLE, BUT REF
AND TEMP
SENSOR STAY
POWERED UP
IDLE, BUT REF
AND TEMP
SENSOR STAY
POWERED UP
END OF SCAN, REF
AND TEMP SENSOR
POWER DOWN
INTERNAL
INT REFERENCE POWERS
TEMP CONVERSION
UP IN ~60µs
IN ~40µs
AUTOMATICALLY
INTERNAL TEMPERATURE
CONVERSION RESULT IS
STORED IN FIFO
ADCIN1
CONVERSION RESULT
STORED IN FIFO
PGAOUT1
CONVERSION RESULT
STORED IN FIFO
USER WRITES TO THE ANALOG-TO-DIGITAL CONVERSION REGISTER
TO SET UP CONVERSION SCAN OF INTERNAL
TEMPERATURE, PGAOUT1, AND ADCIN1
5/MAX1386
Figure 23. ADC Clock Mode 11, Example 1
t
t
CNV11
ACQ11
t
APUINT
CNVST
BUSY
END OF SCAN, REF
AND TEMP SENSOR
POWER DOWN
IDLE, BUT REF
AND TEMP
SENSOR STAY
POWERED UP
IDLE, BUT
REF STAYS
POWERED UP
TEMP CONVERSION
INT REFERENCE POWERS
INTERNAL
IN ~40µs
UP IN ~60µs
AUTOMATICALLY
ADCIN2 CONVERSION
RESULT STORED IN FIFO
PGAOUT2
CONVERSION RESULT
STORED IN FIFO
EXTERNAL TEMPERATURE
SENSOR 2
CONVERSION RESULT
STORED IN FIFO
USER WRITES TO THE ANALOG-TO-DIGITAL
CONVERSION REGISTER TO SET UP CONVERSION
SCAN OF ADCIN2, EXTERNAL TEMPERATURE
SENSOR2, AND PGAOUT2
Figure 24. ADC Clock Mode 11, Example 2
3) Write to the Fine DAC1/DAC2 Write-Through Input
register without autocalibration (FINETHRU1/
FINETHRU2). If the coarse DAC1/DAC2 low wiper is
higher than the coarse DAC1/DAC2 high wiper,
invert the fine DAC1/DAC input register code.
The resulting output when the high wiper is higher than
the low wiper is shown below:
V
V
DACREF
DACREF
×FINECODE+
×LOWCODE
18
8
2
2
where FINECODE is the value written to the Fine
DAC1/DAC2 Input register, and LOWCODE is the value
46 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 2ꢃ. ꢂasic Software Initialization
COMMAND
ꢂYTE
DATA
WORD
DESCRIPTION
0x64
0x64
0x20
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x60
0x74
0x76
0x7A
0x7C
0x52
0x56
0x0008
0x0008
0x02A8
0x0EC0
0x02C1
0x0106
0x02A8
0x0EC0
0x02C1
0x0106
0x000F
0x0000
0x0000
0x00CC
0x0066
0x00CC
0x0066
0x01FF
0x01FF
Bring the device out of shutdown mode.
Set internal reference and both DAC channels on.
Set the channel 1 high-temperature threshold to +85°C.
Set the channel 1 low-temperature threshold to -40°C.
Set the channel 1 high-current threshold to 4.3A for 50mΩ R
, Av
= 2, and V
= 2.5V.
= 2.5V.
SENSE
PGA
REFADC
= 2, and V
PGA REFADC
Set the channel 1 low-current threshold to 1.6A for 50mΩ R
Set the channel 2 high-temperature threshold to +85°C.
Set the channel 2 low-temperature threshold to -40°C.
, Av
SENSE
Set the channel 2 high-current threshold to 4.3A for 50mΩ R
, Av
= 2, and V
= 2.5V.
= 2.5V.
SENSE
PGA
REFADC
= 2, and V
PGA REFADC
Set the channel 2 low-current threshold to 1.6A for 50mΩ R
, Av
SENSE
Set Av
and Av
to 2, clock mode to 00 and ADC/DAC references to internal.
PGA2
PGA1
Set ALARM, SAFE1, and SAFE2 to depend on nothing (POR).
Set ALARM, SAFE1, and SAFE2 for push-pull/active-high (POR).
Set coarse DAC1 high wiper to 204.
Set coarse DAC1 low wiper to 102 (V
Set coarse DAC2 high wiper to 204.
Set coarse DAC2 low wiper to 102 (V
Set fine DAC1 to midscale.
= 1.99V for MAX1385, V
= 3.98V for MAX1386).
GATE
GATE
GATE
= 1.99V for MAX1385, V
= 3.98V for MAX1386).
GATE
Set fine DAC2 to midscale.
Regulating VGS vs. Temperature
Table 26. Temperature-Threshold
Settings Examples
The MAX1385/MAX1386 can be used along with a
microcontroller to perform closed-loop regulation of the
LDMOS FET bias current. For example, software can
read the temperature and use a calibrated look-up
table to determine a new value for the gate drive.
TEMPERATURE SETTING
TWO’S COMPLEMENT
-40°C
-1.625°C
0°C
1110 1100 0000
1111 1111 0011
0000 0000 0000
0000 1101 1001
0011 0100 1000
As an example, in noncontinuous conversion mode,
read temperature from remote diode 1 by writing to the
ADCCON register (0x62) with bit D1 set to 1. Wait for
BUSY to go high and then low. Read the ADC result
from the FIFO (0x80). The result bits D15–D12 = 0001
indicate the measurement source is the external tem-
perature sensor DXP1/DXN1, and bits D11–D3 indicate
two’s-complement temperature in degrees Celsius. Bits
D2, D1, and D0 are temperature subLSBs.
+27.125°C
+105°C
written to the Coarse DAC1/DAC2 Input Low Wiper reg-
ister. The resulting output when the low wiper is higher
than the high wiper is:
V
V
DACREF
DACREF
−
×FINECODE+
×LOWCODE
Gate voltage drive range must be previously deter-
mined during initialization by setting the coarse DAC1
high and low limits. Write a new value to FINETHRU1 to
immediately change the output GATE1 between the
high and low wiper limits based on the previous tem-
perature measurement.
18
8
2
2
Basic Software Initialization
The MAX1385/MAX1386 do not power on all internal
blocks when full power is first applied. Software must
write to register 0x64 twice with bit D7 set to 0 during
initialization to enable full operation. A basic initializa-
tion sequence is shown in Table 27.
The regulation software may also use the alarm thresh-
old limits to determine whether temperature and current
______________________________________________________________________________________ 4ꢃ
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
Table 28. DAC Write Commands Without Autocalibration
OTHER POSSIꢂLE COMMAND
SEQUENCES
ACTION REQUIRED
RECOMMENDED COMMAND SEQUENCE
Update fine DAC_ without triggering
autocalibration.
Write to FINE_. Write to LDAC to update fine Write to FINETHRU_ to immediately
DAC_.
update fine DAC_.
Update high wiper coarse DAC_ without
triggering autocalibration.
Write to HIWIPE_ with HCAL set to 0. Write
to LDAC to update high wiper coarse DAC_. update high wiper coarse DAC_.
Write to THRUHI_ to immediately
Update low wiper coarse DAC_ without
triggering autocalibration.
Write to LOWIPE_ with LCAL set to 0. Write
to LDAC to update low wiper coarse DAC_.
Write to THRULO_ to immediately
update low wiper coarse DAC_.
Immediately update fine DAC_ without
triggering autocalibration.
Write to FINETHRU_.
Write to THRUHI_.
Write to THRULO_.
None.
None.
None.
Immediately update high wiper coarse
DAC_ without triggering autocalibration.
Immediately update low wiper coarse
DAC_ without triggering autocalibration.
5/MAX1386
Update the high, low, and fine components
of DAC_ simultaneously without triggering
autocalibration.
Write to HIWIPE_, LOWIPE, and FINE_.
Write to LDAC to update DAC_.
None.
V
0111 1111 1111
0111 1111 1110
0111 1111 1101
REFADC
1111 1111 1111
FULL-SCALE TRANSITION
1 LSB = +0.125°C
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0001
0000 0000 0000
1111 1111 1111
V
REFADC
1 LSB =
4096
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
1000 0000 0010
1000 0000 0001
1000 0000 0000
+255.875°C
0
-256°C
0°C
2
3
4093 4095
INPUT VOLTAGE (LSB)
1
TEMPERATURE (°C)
Figure 25. ADC Transfer Function
Figure 26. Temperature Transfer Function
limits are within the safe operating area. Configure the
ADC for continuous conversions to allow continuous
measurement and testing against configured alarm
thresholds. Connect SAFE_ to OPSAFE_ to immediately
force the gate drive to GATEGND in the event of an
alarm-related condition (current or temperature).
Triggering DAC Calibration
Performing the autocalibration routines requires use of
the internal ADC, the internal ALU, and can also
increase the power dissipation of the part. Tables 28
and 29 detail which commands trigger autocalibration
and which commands do not.
48 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Table 29. DAC Write Commands with Autocalibration
RECOMMENDED COMMAND
SEQUENCE
OTHER POSSIꢂLE COMMAND
SEQUENCES
ACTION REQUIRED
Write to FINECAL_. Autocalibration
begins after writing to FINECAL_. Write
to LDAC to update fine DAC_.
Update fine DAC_ and trigger
autocalibration.
Write to FINECALTHRU_ to immediately
update fine DAC_.
Write to HIWIPE_ with HCAL set to 1.
Autocalibration begins after writing to
LDAC and high wiper coarse DAC_ is
updated thereafter.
Update high wiper coarse DAC_ and
trigger autocalibration.
None.
Write to LOWIPE_ with LCAL set to 1.
Autocalibration begins after writing to
LDAC and low wiper coarse DAC_ is
updated thereafter.
Update low wiper coarse DAC_ and trigger
autocalibration.
None.
None.
None.
Immediately update fine DAC_ and trigger
autocalibration.
Write to FINECALTHRU_.
This action is not possible. See the
recommended sequence above
“Update high wiper coarse DAC_ and
trigger autocalibration.”
Immediately update high wiper coarse
DAC_ and trigger autocalibration.
This action is not possible. See the
recommended sequence “Update low
wiper coarse DAC_ and trigger
autocalibration.”
Immediately update low wiper coarse
DAC_ and trigger autocalibration.
None.
HIWIPE_ and LOWIPE_ can be written to in
any order but must be followed by LDAC
and then a fine DAC_ write (to
FINECALTHRU_ or FINECAL_ with another
LDAC). This ensures that the fine DAC_
autocalibration is run after the coarse
DAC_ autocalibration.
Write to HIWIPE_ with HCAL set to 1.
Write LOWIPE_ with LCAL set to 1. Write
Update the high, low, and fine components to LDAC to update high and low wipers
of DAC_.
with autocalibrated values. Write to
FINECALTHRU_ to trigger fine DAC_
autocalibration and update DAC_.
______________________________________________________________________________________ 49
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
2
Typical Operating Circuit (I C Mode)
5V
5V
EXTERNAL
REFERENCE
DRAIN
GATEV
AV
REFDAC REFADC
DV
DD
DD
DD
SUPPLY
SCL
SDA
SCL
SDA/DIN
ALARM
BUSY
CS1+
C *
F
MICROCONTROLLER
R *
F
CS1-
SAFE2
SAFE1
+5V
GATE1
DGND
A0/CSB
5/MAX1386
MAX1385
MAX1386
RF
OUTPUT
A1/DOUT
A2/N.C.
RF INPUT
SEL
ADCIN1
ADCIN2
OPSAFE1
OPSAFE2
CNVST
DRAIN
SUPPLY
(AT LDMOSFET)
(AT LDMOSFET)
DXP1
CS2+
C *
F
DXN1
DXP2
R *
F
CS2-
5V
DXN2
GATE2
PGAOUT1 PGAOUT2
AGND
GATEGND
RF
OUTPUT
RF INPUT
*SELECT R AND C BASED ON DESIRED FILTER CUT-OFF FREQUENCY.
F
F
LIMIT R TO MINIMIZE OFFSET ERRORS.
F
50 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
5/MAX1386
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
TOP VIEW
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
27 26 25
36 35 34 33 32 31 30 29 28
48 TQFN-EP
T4877-6
21-0044
GATEV
37
38
39
40
24
N.C.
DD
23 GATEGND
N.C.
N.C.
AGND
AGND
AGND
22
21
PGAOUT1
A2/N.C. 41
N.C. 42
20
19
18
N.C.
AV
DD
MAX1385
MAX1386
SCL 43
SDA/DIN 44
A1/DOUT 45
17 PGAOUT2
16
15
14
13
ADCIN2
ADCIN1
DXN2
46
N.C.
BUSY 47
*EXPOSED PAD
48
DV
DXP2
DD
+
10 11 12
9
1
2
3
4
5
6
7
8
TQFN
*EXPOSED PAD INTERNALLY CONNECTED TO AGND
______________________________________________________________________________________ 51
Dual RF LDMOS Bias Controllers
2
with I C/SPI Interface
of the part, irrespective of power-supply ramp speed
and starts the device regulating to 312.5mV on both
channels. Change the THRUDAC writes to change the
voltage across the sense resistor. Note it should be run
after the power supplies have stabilized.
Appendix: Recommended
Power-Up Code Sequence
The following section shows the recommended startup
code for the MAX1385. This code ensures clean startup
REGISTER
MNEMONIC
REGISTER
ADDRESS (hex)
CODE
WRITTEN
NOTES
SHUT
0x64
0x64
0x0080
0x0080
Removes the global power.
Powers up all parts of the MAX1385 and forces the internal reference to
remain powered. The internal oscillator is required for the subsequent
reset command.
SHUT
SCLR
SCLR
SCLR
SCLR
SHUT
0x68
0x68
0x68
0x68
0x64
0x0100
0x0200
0x0100
0x0200
0x0080
Arms the full reset.
Completes the full reset.
Arms the full reset.*
Completes the full reset.*
Removes the global power.
5/MAX1386
Powers up all parts of the MAX1385 and forces the internal reference to
remain powered. The internal oscillator is required for the subsequent
reset command.
SHUT
DCFIG
0x64
0x30
0x4E
0x0080
0x000A
0x0002
Selects internal references for both DAC and ADC.
Runs autocalibration on both PGA channels to set the input referred
offset to < 50µV. Busy goes low after approximately 30ms and then the
PGACAL
V
DACs can be set.
GATE
*Double reset. This ensures that the internal ROM is reset correctly after power-up and that the ROM data is latched correctly irre-
spective of power-supply ramp speed.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
52 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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