MAX1409CAP+T [MAXIM]
Analog Circuit, 1 Func, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20;
| 型号： | MAX1409CAP+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20 |
| 文件： | 总48页 (文件大小：1108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2229; Rev 0; 10/01
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
General Description
Features
The MAX1407/MAX1408/MAX1409/MAX1414 are low-
power, general-purpose, multichannel data-acquisition
systems (DAS). These devices are optimized for low-
power applications. All the devices operate from a sin-
gle +2.7V to +3.6V power supply and consume a
maximum of 1.15mA in Run mode and only 2.5µA in
Sleep mode.
ꢀ +2.7V to +3.6V Supply Voltage Range in Standby,
Idle, and Run Mode (Down to 1.8V in Sleep Mode)
ꢀ 1.15mA Run Mode Supply Current
ꢀ 2.5µA Sleep Mode Supply Current (Wake-Up, RTC,
and Voltage Monitor Active)
ꢀ Multichannel 16-Bit Sigma-Delta ADC
1.5 ꢀSB (typ) Integral ꢁonlinearity
30Hz or 60Hz Continuous Conversion Rate
Buffered or Unbuffered Mode
Gain of +1/3, +1, or +2V/V
The MAX1407/MAX1408/MAX1414 feature a differential
8:1 input multiplexer to the ADC, a programmable
three-state digital output, an output to shutdown an
external power supply, and a data ready output from
the ADC. The MAX1408 has eight auxiliary analog
inputs, while the MAX1407/MAX1414 include four auxil-
iary analog inputs and two 10-bit force/sense DACs.
The MAX1414 features a 50mV trip threshold for the
signal-detect comparator while the others have a 0mV
trip threshold. The MAX1409 is a 20-pin version of the
DAS family with a differential 4:1 input multiplexer to the
ADC, one auxiliary analog input, and one 10-bit
force/sense DAC.
Unipolar or Bipolar Mode
On-Chip Offset Calibration
ꢀ 10-Bit Force/Sense DACs
ꢀ Buffered 1.25V, 18ppm/°C (typ) Bandgap
Reference Output
ꢀ SPI™/QSPI™ or MICROWIRE™-Compatible Serial
Interface
The MAX1407/MAX1408/MAX1414 are available in
space-saving 28-pin SSOP packages, while the
MAX1409 is available in a 20-pin SSOP package.
ꢀ System Support Functions
RTC (Valid til 9999) and Alarm
High-Frequency Pꢀꢀ Clock Output (2.4576MHz)
+1.8V and +2.7V RESET and Power-Supply
Voltage Monitors
Applications
Medical Instruments
Industrial Control Systems
Portable Equipment
Data-Acquisition System
Automatic Testing
Signal Detect Comparator
Interrupt Generator (INT and DRDY)
Three-State Digital Output
Wake-Up Circuitry
ꢀ 28-Pin SSOP (MAX1407/MAX1408/MAX1414),
20-Pin SSOP (MAX1409)
Robotics
Pin Configurations
Ordering Information
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
28 SSOP
TOP VIEW
FB2
DO
1
2
28 OUT2
27 IN3
MAX1407CAI
MAX1408CAI
MAX1409CAP
MAX1414CAI
28 SSOP
FB1
3
26 DV
DD
20 SSOP
OUT1
IN0
4
25 DGND
24
5
CS
28 SSOP
REF
6
23 SCLK
22 DIN
AGND
7
MAX1407
MAX1414
Pin Configurations continued at end of data sheet.
Typical Operating Circuit appears at end of data sheet.
AV
8
21 DOUT
20 INT
DD
CPLL
WU1
9
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
10
19 CLKIN
18 CLKOUT
17 FOUT
16 DRDY
15 SHDN
WU2 11
RESET 12
IN1 13
IN2 14
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ABSOLUTE MAXIMUM RATINGS
AV
AV
to AGND .........................................................-0.3V to +6V
Analog Outputs to AGND ......................-0.3V to +(AV
Digital Outputs to DGND .......................-0.3V to +(AV
REF to AGND.........................................-0.3V to +(AV
Operating Temperature Range:
MAX14__CA_......................................................0°C to +70°C
MAX14__EA_ ...................................................-40°C to +85°C
Lead Temperature (soldering, 10s) ................................+300 °C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
+ 0.3V)
+ 0.3V)
+ 0.3V)
DD
DD
DD
DD
DD
to DV ...................................................... -0.3V to +0.3V
DD
Analog Inputs to AGND.........................-0.3V to +(AV
Digital Inputs to DGND.............................................-0.3V to +6V
Maximum Current Input Into Any Pin ..................................50mA
+ 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
20-Pin SSOP (derate 8.0mW/°C above +70°C) ...........640mW
28-Pin SSOP (derate 9.52mW/°C above +70°C) .........762mW
DV
to DGND.........................................................-0.3V to +6V
DD
AGND to DGND.....................................................-0.3V to +0.3V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DV
= AV
= +2.7V to 3.6V, 4.7µF at REF, internal V
, 18nF between CPLL and AV , 32.768kHz crystal across CLKIN and
REF DD
DD
DD
CLKOUT, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
ADC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
RES
16
Bits
Unbuffered mode, Unipolar mode, gain = 1,
1.5
3.5
V
= 0.2V, fully differential input (Note 7)
NEG
Unbuffered mode, Unipolar mode, gain = 2,
= 0.625V, pseudo-differential input
1.75
1.70
2.50
V
NEG
INL
LSB
Unbuffered mode, Bipolar mode, gain = 1,
= 0.625V, fully differential input
V
NEG
Buffered mode, Bipolar mode, gain = 2,
V
= 0.625V, fully differential input
NEG
Gain = 2
±5
±10
Unipolar
Gain = 1
Gain = 1/3
Gain = 2
Gain = 1
Gain = 1/3
±30
Output RMS Noise (Note 1)
µV
RMS
±8
Bipolar Mode
±16.5
±±8.5
Offset Error
Offset Drift
Gain Error
Gain Drift
On-chip calibration removes this error
±1
±1
% of FSR
µV/°C
±0.5
±1
Excludes offset and reference errors
Excludes offset and reference errors
% of FSR
ppm/°C
2
_______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DV
= AV
= +2.7V to 3.6V, 4.7µF at REF, internal V
, 18nF between CPLL and AV , 32.768kHz crystal across CLKIN and
DD
DD
REF DD
CLKOUT, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
1/3
1
MAX
UNITS
PGA Gain
See PGA Gain section
V/V
2
Power-Supply Rejection Ratio
Output Update Rate
Gain = 1, unipolar and buffered mode
70
30
60
50
dB
Hz
µs
RATE bit = 0
RATE bit = 1
Continuous
conversion
Turn-On Time
Excluding reference
SIGNAL DETECT COMPARATOR
MAX1407/MAX1408/MAX1409
MAX1414
-10
44
0
0
10
56
Differential Input-Detection
Threshold Voltage
mV
50
Common-Mode Input Voltage
Turn-On Time
0.8
V
10
µs
ANALOG INPUTS
ADC gain = 1
0
0
0
V
REF
Unipolar mode
Bipolar mode
ADC gain = 2
ADC gain = 1/3
ADC gain = 1
ADC gain = 2
ADC gain = 1/3
V
REF/2
AV
DD
REF
Differential Input Voltage Range
Absolute Input Voltage Range
V
V
-V
V
REF
-V
V
REF/2
REF/2
-AV
AV
DD
DD
DD
Unbuffered
Buffered
-0.05
0.05
AV
1.40
AV
Unbuffered
Buffered
AGND
0.05
DD
Common-Mode Input Voltage
Range
V
1.40
Common-Mode Rejection Ratio
Gain = 1, unipolar and buffered mode
90
15.360
30.720
0.5
dB
kHz
30Hz data rate
FOUT = 2.4576MHz
Input Sampling Rate
60Hz data rate
Input Current
Buffered mode
nA
pF
Input Capacitance
15
FORCE-SENSE DAC (all measurements made with FB1(2) shorted to OUT1(2), unless otherwise noted).
(MAX1407/MAX1409/MAX1414 only)
Resolution
10
Bits
LSB
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Guaranteed monotonic (Note 2)
1.0
1.0
20
(Note 2)
(Note 3)
LSB
mV
Offset Drift
5
µV/°C
mV
Gain Error
Excludes offset and reference drift
Excludes offset and reference drift
3.6
Gain Drift
10
190
0.5
ppm/°C
µV/V
nA
Line Regulation
Current into FB1(2)
_______________________________________________________________________________________
3
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DV
= AV
= +2.7V to 3.6V, 4.7µF at REF, internal V
, 18nF between CPLL and AV , 32.768kHz crystal across CLKIN and
DD
DD
REF DD
CLKOUT, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
Output Slew Rate
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
010hex to 3FFhex and 3FFhex to 010hex
18.0
V/ms
code swing, R = 12kΩ, C = 200pF
L
L
To 1/2 LSB (at 10-bit accuracy) of full-
scale with code transition from 010hex
Output Settling Time
65
µs
to 3FFhex, R = 12kΩ, C = 200pF
L
L
Turn-On Time
100
µs
V
AV
- 0.2
DD
OUT1, OUT2 Output Range
No Load (Note 4)
0.05
EXTERNAL REFERENCE (internal reference powered down)
Input Voltage Range
Input Resistance
Input Current
1.25 0.10
540
V
kΩ
µA
2.3
INTERNAL REFERENCE (AV
= 3V, unless otherwise noted)
DD
Output Voltage
T
A
= +25°C
1.225
1.25
18
1.275
V
Output Voltage Temperature
Coefficient
ppm/°C
Output Short-Circuit Current
3.4
80
mA
Line Regulation
∆V /∆V
REF
2.7<AV <3.6V
µV/V
DD
DD
I
I
= 0µA to 500µA, T = +25°C
1
2
SOURCE
A
Load Regulation
µV/µA
µVp-p
= 0µA to 50µA, T = +25°C
SINK
A
0.1Hz to 10Hz
40
400
70
3
Noise Voltage
e
OUT
10Hz to 10kHz
100mV, f = 120Hz
Power-Supply Rejection Ratio
Turn-On Time
dB
ms
µP RESET
Supply Voltage Range
For valid RESET
1
3.6
1.930
2.80
V
V
Bit VM = 1
Bit VM = 0
1.800
2.70
1.865
2.75
RESET Trip Threshold Low
V
AV
falling
DD
TH
For Normal, Idle, and Standby modes,
Low AV
Trip Threshold
2.70
2.75
2.80
0.4
V
V
DD
AV
falling
DD
RESET Output Low Voltage
(Open-Drain Output)
I
= 1mA, AV
= 1.8V
DD
SINK
4
_______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DV
= AV
= +2.7V to 3.6V, 4.7µF at REF, internal V
, 18nF between CPLL and AV , 32.768kHz crystal across CLKIN and
DD
DD
REF DD
CLKOUT, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
RESET Output Leakage
Turn-On Time
SYMBOL
CONDITIONS
MIN
TYP
0.002
2
MAX
UNITS
µA
AV
AV
> V , RESET deasserted
0.1
DD
DD
TH
ms
CRYSTAL OSCILLATOR
Crystal Frequency
Crystal Load Capacitance
Oscillator Stability
Oscillator Startup Time
PLL
= +3V
32.768
kHz
pF
6
0
AV = +1.8V to +3.6V, excluding crystal
ppm/V
s
DD
1.5
FOUT Frequency
AV
= +3V
2.4576
10
MHz
ns
DD
Absolute Clock Jitter
Cycle-to-cycle
Overtemperature excluding crystal,
0
ppm/°C
T
= T to T
MIN MAX
Frequency Tolerance/Stability
A
Oversupply voltage, +2.7V< AV < +3.6V
0
ppm/mV
DD
FOUT Rise/Fall Time
Duty Cycle
20% to 80% waveform, C = 30pF
15
50
30
60
ns
%
L
40
DIGITAL INPUTS (DIN, SCLK, CS, WU1, WU2)
0.7 x
Input High Voltage
DV
= +1.8V to +3.6V
V
V
DD
DV
DD
0.3 x
Input Low Voltage
DV
DV
= +1.8V to +3.6V
= +3V
DD
DD
DV
DD
Input Hysteresis
200
0.01
0.01
10
mV
µA
µA
µA
pF
DIN, SCLK, CS, Input Current
WU1, WU2 Input Current
WU1, WU2 Pullup Current
Input Capacitance
V
V
V
= 0 or V = DV
10
10
IN
IN
IN
IN
DD
= AV
= 0
DD
10
DIGITAL OUTPUTS (DOUT, FOUT, INT, DRDY, SHDN, D0)
DOUT, FOUT, DRDY, INT
V
I
= 1mA, DV = +1.8V to +3.6V
DD
0.4
10
V
V
OL
SINK
Output Low Voltage
DOUT, FOUT, DRDY, INT,
SHDN Output High Voltage
V
I
= 0.2mA, DV
= +1.8V to +3.6V 0.8 x DV
DD DD
OH
SOURCE
DOUT Three-State Leakage
0.01
15
µA
pF
DOUT Three-State Capacitance
I
I
= 1mA, DV
= +1.8V to +3.6V
= +1.8V to +3.6V
0.4
SINK
SINK
DD
SHDN Output Low Voltage
(MAX1407/MAX1408/MAX1414
only)
V
0.04 x
= 50µA, DV
DD
DV
DD
_______________________________________________________________________________________
5
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DV
= AV
= +2.7V to 3.6V, 4.7µF at REF, internal V
, 18nF between CPLL and AV , 32.768kHz crystal across CLKIN and
DD
DD
REF DD
CLKOUT, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
D0 Output Low Voltage
(MAX1407/MAX1408/MAX1414
only)
I
I
= 200µA, DV
= +2.7V to +3.6V
DD
0.7
mV
SINK
D0 Output High Voltage
(MAX1407/MAX1408/MAX1414
only)
DV
- 0.1
DD
= 2mA, DV = +2.7V to +3.6V
V
SOURCE
DD
POWER REQUIREMENTS
Run, Idle, and Standby mode
Sleep mode
2.7
1.8
3.6
3.6
Supply Voltage Range
V
V
DD
MAX1407/MAX1414
1.15
1.03
1.09
650
530
590
Run mode
Idle mode
mA
MAX1408
MAX1409
MAX1407/MAX1414
MAX1408
Supply Current (Note 5)
I
DD
MAX1409
µA
MAX1407/MAX1408/
MAX1409/MAX1414
Standby mode
Sleep mode
330
2.5
MAX1407/MAX1408/
MAX1409/MAX1414
1.7
V
= 2.7V
DD
TIMING CHARACTERISTICS
(MAX1407/MAX1408/MAX1409/MAX1414: AV = DV = 2.7V to 3.6V, T = T
to T
unless otherwise noted.)
MAX,
DD
DD
A
MIN
PARAMETER
TIMING PARAMETERS
SCLK Operating Frequency
SCLK Cycle Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
2.1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
t
476
190
190
100
0
CYC
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
t
CH
t
t
CL
DS
DH
DO
DIN to SCLK Hold
t
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
t
C = 50pF (see load circuit)
200
240
240
L
t
C = 50pF (see load circuit)
L
DV
t
C = 50pF (see load circuit)
L
TR
t
100
0
CSS
CSH
t
6
_______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
TIMING CHARACTERISTICS (continued)
(MAX1407/MAX1408/MAX1409/MAX1414: AV = DV = 2.7V to 3.6V, T = T
to T
unless otherwise noted.)
MAX,
DD
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TYPICAL TIMING PARAMETERS
Input impedance > 1MΩ
(MAX1407/MAX1409/MAX1414 only)
OUT1/OUT2 Turn-Off Time
100
µs
The delay for the sleep voltage monitor
output, RESET, to go high after AV rises
DD
Sleep Voltage Monitor Timeout
Period
above the reset threshold (+1.8V when bit
VM = 1 and +2.7V, when bit VM = 0); this is
largely driven by the startup of the 32kHz
oscillator
t
1.54
s
DSLP
Minimum pulse width required to detect a
wake-up event
WU1 or WU2 Pulse Width
t
1
1
µs
µs
WU
The delay for SHDN to go high after a valid
wake-up event
Shutdown Deassert Delay
t
DPU
The turn-on time for the high-frequency
clock; it is gated by an AND function with
three signals—the RESET signal, the internal
low voltage V
monitor signal, and the
DD
FOUT Turn-On Time
t
31.25
7.82
ms
ms
DFON
assertion of the PLL; the time delay is timed
from when the low-voltage monitor trips or
the RESET going high, whichever happens
later; FOUT always starts in the low state
The delay for INT to go low after the FOUT
clock output has been enabled; INT is used
as an interrupt signal to inform the µP the
high-frequency clock has started
INT Delay
t
DFI
The delay after a shutdown command has
asserted and before FOUT is disabled; this
gives the microcontroller time to clean up
and go into Sleep mode properly
FOUT Disable Delay
t
1.95
2.93
ms
ms
DFOF
The delay after a shutdown command has
asserted and before SHDN is pulled low
(turning off the DC-DC converter) (Note 6)
SHDN Assertion Delay
t
DPD
Note 1: Single conversion.
Note 2: DNL and INL are measured between code 010hex and 3FFhex.
Note 3: Offset error is referenced to code 010hex.
Note 4: Output swing is a function of external gain-setting feedback resistors and REF voltage.
Note 5: Measured with no load on FOUT, DOUT, and the DAC amplifiers. SCLK is idle, and all digital inputs are at DGND or DV
.
DD
Note 6: SHDN stays high if the PLL is on.
Note 7: Actual worst-case performance is 2.5LSꢀ. Guaranteed limit of 3.5LSꢀ is due to production test limitation.
Note 8: Guaranteed by design. Not production tested.
_______________________________________________________________________________________
7
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Load Circuits
DV
DV
DD
DD
6kΩ
6kΩ
DOUT
DOUT
DOUT
DOUT
C
C
LOAD
50pF
LOAD
50pF
C
C
LOAD
50pF
LOAD
50pF
6kΩ
6kΩ
DGND
DGND
DGND
a) V TO HIGH-Z
DGND
a) HIGH-Z TO V AND V TO V
OH
b) V TO HIGH-Z
b) HIGH-Z TO V AND V TO V
OL OH OL
OH
OH
OL
OL
LOAD CIRCUITS FOR DISABLE TIME
LOAD CIRCUITS FOR ENABLE TIME
Typical Operating Characteristics
(A
= D
= 3V, MAX1407 used, T = +25°C, unless otherwise noted.)
VDD
VDD
A
SUPPLY CURRENT vs.
SUPPLY VOLTAGE
SUPPLY CURRENT vs.
TEMPERATURE
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
RUN MODE
IDLE MODE
RUN MODE
IDLE MODE
STANDBY
STANDBY
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
TEMPERATURE (°C)
SLEEP MODE SUPPLY CURRENT
vs. TEMPERATURE
SLEEP CURRENT vs. FALLING V
DD
4.0
3.5
3.0
2.5
2.0
1.5
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0
1.80
2.30
2.80
3.30
-40
-15
10
35
60
85
SUPLLY VOLTAGE (V)
TEMPERATURE (°C)
8
_______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
= 3V, MAX1407 used, T = +25°C, unless otherwise noted.)
VDD A
(A
= D
VDD
MAXIMUM INL vs. V
(UNIPOLAR MODE, T = +25°C,
PSEUDO-DIFFERENTIAL INPUT)
DD
MAXIMUM INL vs. V
(BIPOLAR MODE, T = +25°C,
FULLY DIFFERENTIAL INPUT)
DD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5
4
3
2
1
0
A
B
A
B
2.7
2.9
3.1
3.3
3.5
2.7
2.9
3.1
3.3
3.5
V
(V)
DD
V
(V)
DD
A: GAIN = 1, UNBUFFERED MODE, 60sps
B: GAIN = 1, UNBUFFERED MODE, 30sps
A: GAIN = 2, BUFFERED MODE, 60sps
B: GAIN = 2, BUFFERED MODE, 30sps
MAXIMUM INL vs. TEMPERATURE
MAXIMUM INL vs. TEMPERATURE
(UNIPOLAR MODE, V = 3V,
(BIPOLAR MODE, V = 3V,
DD
DD
PSEUDO-DIFFERENTIAL INPUT)
FULLY DIFFERENTIAL INPUT)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
B
A
A
B
0
20
40
60
80
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
A: GAIN = 1, UNBUFFERED MODE, 60sps
B: GAIN = 1, UNBUFFERED MODE, 30sps
A: GAIN = 2, BUFFERED MODE, 60sps
B: GAIN = 2, BUFFERED MODE, 30sps
_______________________________________________________________________________________
9
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
(A
= D
= 3V, MAX1407 used, T = +25°C, unless otherwise noted.)
VDD
VDD
A
MAXIMUM INL vs. COMMON-MODE
INPUT VOLTAGE (BIPOLAR MODE,
INL vs. FULLY DIFFERENTIAL
INPUT VOLTAGE (BIPOLAR MODE,
GAIN = 1, UNBUFFERED MODE,
BUFFERED MODE, V = 2.7V, 30sps,
DD
FULLY DIFFERENTIAL INPUT, T = +25°C)
V
= 0.625V, V = 3V, T = +25°C)
CM
DD
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
B
A
-0.5
-1.0
-1.5
-2.0
0.3
0.5
COMMON-MODE INPUT VOLTAGE (V)
A: GAIN = 1
B: GAIN = 2
0.7
0.9
1.1
-1.25
-0.75
-0.25
0.25
0.75
1.25
DIFFERENTIAL INPUT VOLTAGE (V)
INL vs. PSEUDO-DIFFERENTIAL INPUT
VOLTAGE RANGE (UNIPOLAR MODE,
GAIN = 1, UNBUFFERED MODE,
UNCORRECTED OFFSET ERROR
vs. TEMPERATURE
V
= 0, V = 3V, T = +25°C)
(UNBUFFERED MODE, V = 3V)
NEG
DD
DD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
A
0.5
0
-0.5
-1.0
-1.5
-2.0
B
0
0.2
0.4
0.6
0.8
1.0
1.2
0
20
40
60
80
DIFFERENTIAL VOLTAGE (V)
TEMPERATURE (°C)
A: GAIN = 1, UNIPOLAR MODE
B: GAIN = 2, BIPOLAR MODE
10 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
= 3V, MAX1407 used, T = +25°C, unless otherwise noted.)
VDD A
(A
= D
VDD
REFERENCE VOLTAGE vs.
REFERENCE VOLTAGE vs.
OUTPUT SOURCE CURRENT
TEMPERATURE
GAIN ERROR vs. TEMPERATURE
0.02
0
0.12
0.11
0.10
0.09
0.08
0.07
0.06
1.24410
1.24405
1.24400
1.24395
1.24390
1.24385
1.24380
V
= 3V
V
REF
= 1.24406V
DD
REF
= 0
I
B
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
D
A
C
0
20
40
60
80
-40
-15
10
35
60
85
0
200
400
600
800 1000 1200
TEMPERATURE (°C)
TEMPERATURE (°C)
SOURCE CURRENT (µA)
A: GAIN = 1, UNIPOLAR MODE, UNBUFFERED MODE
B: GAIN = 1, BIPOLAR MODE, UNBUFFERED MODE
C: GAIN = 2, UNIPOLAR MODE, BUFFERED MODE
D: GAIN = 2, BIPOLAR MODE, BUFFERED MODE
REFERENCE VOLTAGE vs.
SUPPLY VOLTAGE
DAC OFFSET ERROR vs.
TEMPERATURE
DAC OFFSET ERROR vs.
SUPPLY VOLTAGE
1.24412
1.24410
1.24408
1.24406
1.24404
1.24402
1.24400
1.24398
-3.4
-3.6
-3.8
-4.0
-4.2
-4.4
-4.6
-4.8
-5.0
-5.2
-4.400
-4.425
-4.450
-4.475
-4.500
-4.525
-4.550
-4.575
-4.600
NO LOAD
IDLE MODE
IDLE MODE
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
= 3V, MAX1407 used, T = +25°C, unless otherwise noted.)
VDD A
(A
= D
VDD
DAC GAIN ERROR vs.
TEMPERATURE
DAC INTEGRAL NONLINEARITY
DAC GAIN ERROR vs.
SUPPLY VOLTAGE
vs. DIGITAL CODE (AV = 2.7V)
DD
0.15
0.10
0.05
0
0.15
0
0.10
0.05
0
IDLE MODE
IDLE MODE
-0.15
-0.30
-0.45
-0.60
-0.05
-0.10
-0.15
-0.20
-0.75
-0.90
-1.05
-1.20
-1.35
-0.05
-0.10
-0.15
INTERNAL REF USED
INTERNAL REF USED
-1.50
-40
-15
10
35
60
85
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGE (V)
0
100 200 300 400 500 600 700 800 90010001100
CODE
TEMPERATURE (°C)
DAC INTEGRAL NONLINEARITY
DAC DIFFERENTIAL NONLINEARITY
DAC DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE (AV = 3.6V)
vs. DIGITAL CODE (AV = 2.7V)
vs. DIGITAL CODE (AV = 3.6V)
DD
DD
DD
0.15
0.10
0.05
0
0.100
0.075
0.050
0.025
0
0.100
0.075
0.050
0.025
0
-0.025
-0.050
-0.075
-0.100
-0.025
-0.050
-0.075
-0.100
-0.05
-0.10
-0.15
0
100 200 300 400 500 600 700 800 90010001100
CODE
0
100 200 300 400 500 600 700 800 90010001100
CODE
0
100 200 300 400 500 600 700 800 90010001100
CODE
DAC LARGE-SIGNAL OUTPUT
STEP RESPONSE
MAX1407 toc25
CS
2V/DIV
OUT_
500mV/DIV
V
= 1.25V, AV = 3.0V, R = 0
DD L
REF
12 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
= 3V, MAX1407 used, T = +25°C, unless otherwise noted.)
VDD A
(A
= D
VDD
DAC OUTPUT VOLTAGE
vs. SINK CURRENT
DAC OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
DAC OUTPUT VOLTAGE
vs. SOURCE CURRENT
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.2450
1.2445
1.2440
1.2435
1.2430
1.30
1.25
1.20
1.15
1.10
1.05
1.00
OUTPUT AT FULL SCALE
NO LOAD
DAC BUFFER IN UNITY GAIN
OUTPUT AT FULL SCALE
DAC BUFFER IN UNITY GAIN
0
5
10 15 20 25 30 35 40
SINK CURRENT (µA)
2.7
3.0
3.3
3.6
0
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
LOAD CURRENT (mA)
VOLTAGE MONITOR THRESHOLD
vs. TEMPERATURE
DAC OUTPUT VOLTAGE vs.
TEMPERATURE
0.15
0.12
0.09
0.06
0.03
0
0.10
0.05
0
V
REF
= 1.24406V
REF
= 0
I
V
= 1.865V
1.8V_THRESHOLD
-0.05
-0.10
-0.15
-0.20
-0.25
-0.03
-0.06
-0.09
-0.12
V
= 2.75V
35
2.7V_THRESHOLD
-0.15
-40
-15
10
35
60
85
-40
-15
10
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________________________________ 13
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Pin Description
MAX1407
MAX1414
MAX1408
MAX1409
PIN
FUNCTION
Force/Sense DAC2 Feedback Input
1
—
—
2
—
1
—
—
1
Fꢀ2
IN7
Analog Input. Analog input to the negative mux only.
Force/Sense DAC1 Feedback Input
—
2
Fꢀ1
D0
—
—
—
2
Digital Output. Three-state general-purpose digital output.
Force/Sense DAC1 Feedback Input
3
—
3
Fꢀ1
IN6
—
4
Analog Input. Analog input to the negative mux only.
Force/Sense DAC1 Output
—
4
OUT1
IN4
—
5
—
3
Analog Input. Analog input to the positive mux only.
Analog Input. Analog input to both the positive and negative mux.
5
IN0
1.25V Reference ꢀuffer Output/External Reference Input. Reference voltage
for the ADC and the DAC. Connect a 4.7µF capacitor to REF between REF
and AGND.
6
6
4
REF
Analog Ground. Reference point for the analog circuitry. AGND connects to
the IC substrate.
7
8
9
7
8
9
5
6
7
AGND
AV
Analog Supply Voltage
DD
PLL Capacitor Connection Pin. Connect an 18nF ceramic capacitor between
CPLL
WU1
WU2
CPLL and AV
.
DD
Active-Low Wake-Up Input. Internally pulled up. The device will wake-up from
Sleep mode to Standby mode when WU1 is asserted.
10
11
10
11
8
9
Active-Low Wake-Up Input. Internally pulled up. The device will wake-up from
Sleep mode to Standby mode when WU2 is asserted.
Active-Low RESET Output. It remains low while AV
is below the threshold
DD
and stays low for a timeout period after AV
rises above the threshold.
12
12
10
RESET
DD
RESET is an open-drain output.
13
14
15
13
14
15
—
—
—
IN1
IN2
Analog Input. Analog input to both the positive and negative mux.
Analog Input. Analog input to both the positive and negative mux.
Programmable Shutdown Output. Goes low in Sleep mode.
SHDN
Active-Low Data Ready Output. A logic low indicates that a new conversion
result is available in the Data register. DRDY returns high upon completion of
a full output word read operation. DRDY also signals the end of an ADC
offset-calibration.
16
16
—
DRDY
17
17
11
FOUT
2.4576MHz Clock Output. FOUT can be used to drive the input clock of a µP.
32kHz Crystal Output. Connect a 32kHz crystal between CLKIN and
CLKOUT.
18
19
18
19
12
13
CLKOUT
CLKIN
32kHz Crystal Input. Connect a 32kHz crystal between CLKIN and CLKOUT.
14 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Pin Description (continued)
MAX1407
MAX1414
MAX1408
MAX1409
PIN
INT
FUNCTION
Active-Low Interrupt Output. INT goes low when the PLL output is ready,
when the signal-detect comparator is tripped, or when the alarm is triggered.
20
21
22
20
21
22
14
15
16
Serial Data Output. DOUT outputs serial data from the internal shift register
on SCLK’s falling edge. When CS is high, DOUT is three-stated.
DOUT
DIN
Serial Data Input. Data on DIN is written to the input shift register and is
clocked in at SCLK’s rising edge when CS is low.
Serial Clock Input. Apply an external serial clock to transfer data to and from
the device. This serial clock can be continuous, with data transmitted in a
train of pulses, or intermittent while CS is low.
23
24
23
24
17
18
SCLK
Active-Low Chip-Select Input. CS is used to select the active device in
systems with more than one device on the serial bus. Data will not be
clocked into DIN unless CS is low. When CS is high, DOUT is three-stated.
CS
25
26
27
28
—
25
26
27
—
28
19
20
—
—
—
DGND
Digital Ground. Reference point for digital circuitry.
Digital Supply Voltage
DV
DD
IN3
Analog Input. Analog input to both the positive and negative mux.
Force/Sense DAC2 Output
OUT2
IN5
Analog Input. Analog input to the positive mux only.
MAX1409/MAX1414 feature sets and Figures 1, 2, 3 for
Detailed Information
the Functional Diagrams). These DAS directly interface
to various sensor outputs and once configured provide
the stimulus, conditioning, and data conversion, as well
as microprocessor support. Figure 4 is a Typical
Application Circuit for the MAX1407/MAX1414.
The MAX1407/MAX1408/MAX1409/MAX1414 are low-
power, general-purpose, multichannel DAS featuring a
multiplexed fully differential 16-bit ∑∆ analog-to-digital
converter (ADC), 10-bit force/sense digital-to-analog
converters (DAC), a real-time clock (RTC) with an
alarm, a bandgap voltage reference, a signal detect
comparator, two power-supply voltage monitors, wake-
up control circuitry, and a high-frequency phase-locked
loop (PLL) clock output all controlled by a 3-wire serial
interface. (See Table 1 for the MAX1407/MAX1408/
The 16-bit ∑∆ ADC is capable of programmable contin-
uous conversion rates of 30Hz or 60Hz and gains of
1/3, 1, and 2V/V to suit applications with different power
and dynamic range constraints. The force/sense DACs
provide 10-bit linearity for precise sensor applications.
Table 1. MAX1407/MAX1408/MAX1409/MAX1414 Feature Sets
EXTERNAL
POWER-
SUPPLY
SHUTDOWN
CONTROL
ADC
THREE-
STATE
DIGITAL
FORCE/
SENSE
DAC
COMPARATOR
THRESHOLD
(mV)
ADC DATA
READY
(DRDY)
ADC
DIFFERENTIAL
INPUT MUX
AUXILIARY
ANALOG
INPUTS
RTC
PART
OUTPUT
MAX1407
MAX1414
MAX1408
MAX1409
4
4
8
1
2
2
0
1
Yes
Yes
Yes
No
0
50
0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
No
8
8
8
4
0
______________________________________________________________________________________ 15
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
AV
DD
CPLL
FOUT
CLKIN CLKOUT
DV
DD
CS
SCLK
DIN
32.768kHz
OSCILLATOR
RTC AND
ALARM
WU2
2.4576MHz
PLL
SERIAL
INTERFACE
WAKE-UP
LOGIC
WU1
SHDN
DOUT
MAX1407/MAX1414
COMPARATOR
INT
INTERRUPT
GENERATOR
OUT2
OUT1
DRDY
IN3
IN2
IN1
IN0
8:1
INPUT
MUX
BUF
BUF
DIGITAL
OUTPUT
D0
REF
16-BIT ADC
PGA
AV
DD
FB2
FB1
IN3
1.8V/2.7V
µP
1.25V
BANDGAP
REFERENCE
10-BIT DAC
OUT1
FB1
8:1
INPUT
MUX
SUPERVISORS
IN2
IN1
IN0
REF
AGND
BUF
RESET
GENERATOR
10-BIT DAC
OUT2
FB2
RESET
AGND
REF
DGND
*MAX1414 HAS A +50mV SIGNAL-DETECT COMPARATOR THRESHOLD.
Figure 1. MAX1407/MAX1414 Functional Diagram
With the use of two external resistors, the DAC output
can go from 0.05V to AV - 0.2V. The ADCs and
Analog Mux
The MAX1407/MAX1408/MAX1414 include a dual 8 to 1
multiplexer for the positive and negative inputs of the
ADC. The MAX1409 has a dual 4 to 1 multiplexer at the
inputs of the ADC. Figures 1, 2, and 3 illustrate which
signals are present at the inputs of each multiplexer for
the MAX1407/MAX1408/MAX1409/MAX1414. The
MUXP and MUXN bits of the MUX register choose
which inputs will be seen at the input to the ADC
(Tables 4 and 5) and the signal-detect comparator. See
the MUX Register description under the On-Chip
Registers section for multiplexer functionality.
DD
DACs both utilize a precise low-drift 1.25V internal
bandgap reference for conversions and setting of the
full-scale range. For applications that require increased
accuracy, power-down the internal reference and con-
nect an external reference at REF. The RTC is leap year
compensated until 9999 and provides an alarm function
that can be used to wake-up the system or cause an
interrupt at a predefined time. The power-supply volt-
age monitors detect when AV
falls below a trip
DD
threshold voltage at either +1.8V or +2.7V causing the
reset to be asserted. The 4-wire serial interface is used
to communicate directly between SPI, QSPI, and
MICROWIRE devices for system configuration and
readback functions.
Input Buffers
The MAX1407/MAX1408/MAX1409/MAX1414 provide
input buffers to isolate the analog inputs from the capaci-
tive load presented by the ADC modulator (Figure 5 and
6). The buffers are chopper stabilized to reduce the effect
of their DC offsets and low-frequency noise. Since the
buffers can represent more than 25% of the total analog
power dissipation (typically 220µA), they may be shut
down in applications where minimum power dissipation is
required and the capacitive input load is not a concern
(see ADC and Power1 Registers). Disable the buffers in
applications where the inputs must operate close to
AGND or above +1.4V. The buffers are individually
enabled or disabled.
Analog Input Protection
Internal protection diodes clamp the analog input to
AV
and AGND, which allow the channel input pins to
DD
swing from AGND - 0.3V to AV
+ 0.3V without dam-
DD
age. However, for accurate conversions near full scale,
the inputs must not exceed AV by more than 50mV
DD
or be lower than AGND by 50mV.
16 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
AV
CPLL
FOUT
CLKIN CLKOUT
DV
DD
DD
CS
SCLK
DIN
32.768kHz
OSCILLATOR
RTC AND
ALARM
WU2
2.4576MHz
PLL
SERIAL
INTERFACE
WAKE-UP
LOGIC
WU1
SHDN
DOUT
INT
INTERRUPT
GENERATOR
IN5
COMPARATOR
IN4
DRDY
IN3
8:1
INPUT
MUX
IN2
IN1
IN0
BUF
BUF
DIGITAL
OUTPUT
D0
REF
16-BIT ADC
PGA
AV
DD
IN7
IN6
1.8V/2.7V
1.25V
µP
BANDGAP
IN3
IN2
8:1
INPUT
MUX
SUPERVISORS
REFERENCE
IN1
MAX1408
IN0
BUF
RESET
GENERATOR
REF
AGND
RESET
AGND
REF
DGND
Figure 2. MAX1408 Functional Diagram
AV
CPLL
FOUT
CLKIN CLKOUT
DV
DD
DD
CS
SCLK
32.768kHz
OSCILLATOR
RTC AND
ALARM
WU2
2.4576MHz
PLL
SERIAL
INTERFACE
WAKE-UP
LOGIC
WU1
DIN
DOUT
INTERRUPT
GENERATOR
INT
COMPARATOR
OUT1
REF
4:1
INPUT
MUX
IN0
BUF
BUF
AV
DD
16-BIT ADC
PGA
1.8V/2.7V
µP
SUPERVISORS
1.25V
BANDGAP
REFERENCE
FB1
IN0
10-BIT DAC
OUT1
FB1
4:1
INPUT
MUX
REF
BUF
RESET
GENERATOR
AGND
MAX1409
RESET
AGND
REF
DGND
Figure 3. MAX1409 Functional Diagram
______________________________________________________________________________________ 17
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
V
= 3.3V OR V
BAT
DD
LX
OUT
RST
10µF
LX
18nF
0.1µF
0.1µF
MAX1833
0.1µF
SHDN
BATT
CPLL
SHDN
AV
DV
V
DD
DD
DD
GND
RESET
CLKIN
RESET
CLKIN
µP/µC
IN0
REF
32.768kHz
10µF
V
BAT
4.7µF
R
L
CLKOUT
FOUT
IN1
CS
SCLK
DIN
OUTPUT
SCK
R
T
MAX1407
MAX1414
MOSI
MISO
DOUT
OUT1
INPUT
INPUT
INT
R
F
DRDY
FB1
FB2
WU1
WU2
I/O
I/O
WE
RE
CE
SENSOR
OUT2
V
SS
AGND
DGND
Figure 4. MAX1407/MAX1414 Typical Application Circuit
R
R
EXT
R
IN
MUX
C
C
C
C
ST
AMP
EXT
PIN
C
C
C
SAMPLE
Figure 5. Analog Input—Buffered Mode
Buffered Mode
small dynamic load is present from the chopper. The
multiplexer exhibits an input leakage current of 0.5nA
(typ). With high-source resistances, this leakage cur-
rent may result in a large DC offset error.
When used in buffered mode, the buffers isolate the
inputs from the sampling capacitors. The sampling-
related gain error is dramatically reduced since only a
18 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ADC Offset Calibration
The MAX1407/MAX1408/MAX1409/MAX1414 are capa-
ble of performing digital offset correction to eliminate
R
R
MUX
R
EXT
SW
changes due to power-supply voltage or system tem-
perature. At the end of a calibration cycle, a 16-bit cali-
bration value is stored in the Offset register in two’s
compliment format. After completing a conversion, the
MAX1407/MAX1408/MAX1409/MAX1414 subtract the
calibration value from the ADC conversion result and
write the offset compensated data to the Data register
(see Offset Register section). Either a positive or nega-
tive offset can be calibrated. During offset calibration,
DRDY will go high. DRDY goes low after calibration is
complete. The offset register can be programmed to
C
C
C
C
C
C
EXT
ST
SAMPLE
PIN
Figure 6. Analog Input—Unbuffered Mode
Unbuffered Mode
When used in unbuffered mode, the switched capacitor
sampling front end of the modulator presents a dynam-
ic load to the driving circuitry. The size of the internal
sampling capacitor and the input sampling frequency
(Figure 6) determines the dynamic load (see Dynamic
Input Impedance section). As the gain increases, the
input sampling capacitance also increases. Since the
MAX1407/MAX1408/MAX1409/MAX1414 sample at a
constant rate for all gain settings, the dynamic load pre-
sented by the inputs varies with the gain setting.
15
skew the ADC offset with a maximum range from -2 to
15
(+2 - 1)LSꢀs, e.g., if the programmed 2’s complement
value is +2LSꢀ (-2LSꢀ), this translates to a -2LSꢀ
(+2LSꢀ) shift in bipolar mode or a -4LSꢀ (+4LSꢀ) shift in
unipolar mode.To maintain optimum performance, recal-
ibrate the ADC if the temperature changes by more than
20°C. Offset calibration should also be performed after
any changes in PGA gain, bipolar/unipolar input range,
buffered/unbuffered mode, or conversion speed. During
calibration, the two mulitplexers will be disabled and the
inputs to the ADC will internally be shorted to a com-
mon-mode voltage.
PGA Gain
An integrated programmable-gain amplifier (PGA) pro-
vides three user-selectable gains: +1/3V/V, +1V/V, and
+2V/V to maximize the dynamic range of the ADC. ꢀits
GAIN1 and GAIN0 set the desired gain (see ADC
Register). The gain of +1/3V/V allows the direct mea-
surement of the supply voltage through an internal mul-
tiplexer input or through an auxillary input.
ADC Digital Filter
The on-chip digital filter processes the 1-bit data
stream from the modulator using a SINC3 filter function.
The SINC3 filters settle in three data word periods. The
settling time is 3/60Hz or 50ms (for RATE bit in ADC
register set to 1) and 3/30Hz or 100ms (for RATE bit set
to “0”).
ADC Modulator
The MAX1407/MAX1408/MAX1409/MAX1414 perform
analog-to-digital conversions using a single-bit, sec-
ond-order, switched-capacitor delta-sigma modulator.
The delta-sigma modulation converts the input signal
into a digital pulse train whose average duty cycle rep-
resents the digitized signal information. The pulse train
is then processed by a digital decimation filter.
ADC Digital Filter Characteristics
The transfer function for a SINC3 filter function is that of
three cascaded SINC1 filters. This can be described in
the Z-domain by:
−N 3
1− z
(
)
1
N
The modulator provides 2nd-order frequency shaping
of the quantization noise resulting from the single bit
quantizer. The modulator is fully differential for maxi-
mum signal-to-noise ratio and minimum susceptibility to
power-supply noise. The modulator operates at one of
two different sampling rates resulting in an output data
rate of either 30Hz or 60Hz (see ADC Register).
H z =
( )
1− z−1
(
)
and in the frequency domain by:
3
ƒ
sin Nπ
ƒ
M
1
N
H ƒ =
( )
ƒ
sin π
ƒ
M
where N, the decimation factor, is the ratio of the modu-
lator frequency f to the output frequency f .
M
N
______________________________________________________________________________________ 19
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Shorting Fꢀ1(2) and OUT1(2) configures the DAC in a
0
-20
-40
-60
-80
unity-gain setting. Connecting resistors in a voltage-
divider configuration between OUT1(2), Fꢀ1(2), and
GND sets a different closed-loop gain for the output
amplifier (see the Applications Information section).
1
/
The DAC output amplifier typically settles to
2LSꢀ
from a full-scale transition within 65µs, when it is con-
nected in unity gain and loaded with 12kΩ in parallel
with 200pF. Loads less than 2kΩ may degrade perfor-
mance. See the Typical Operating Characteristics sec-
tion for the source-and-sink capabilty of the DAC
output.
-100
-120
-140
-160
The MAX1407/MAX1409/MAX1414 feature a software-
programmable shutdown mode for the DACs that
reduce the total power consumption when they are not
used. The two DACs can be powered-down indepen-
dently or simultaneously by clearing the DA1E and
DA2E bits (see Power1 Register). DAC outputs OUT1
and OUT2 go high impedance when powered down.
The DACs are automatically powered up and ready for
a conversion when Idle or Run mode is entered.
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (Hz)
Figure 7. Frequency Response of the SINC3 Filter (Notch at
60Hz)
Figure 7 shows the filter frequency response. The
SINC3 characteristic cutoff frequency is 0.262 times the
first notch frequency. This results in a cutoff frequency
of 15.72Hz for a first filter notch frequency of 60Hz (out-
put data rate of 60Hz). The response shown in Figure 7
is repeated at either side of the digital filter’s sample
Voltage Monitors
The MAX1407/MAX1408/MAX1409/MAX1414 include
two on-board voltage monitors. When AV
is below
DD
the RESET trip threshold, RESET goes low and the RST
bit of the Status register is set to “1”. When AV is
frequency (f ) (f = 15.36kHz for 30Hz and f =
M
M
M
DD
30.72kHz for 60Hz) and at either side of the related har-
monics (2f , 3f ,....).
below the Low V
trip threshold, the LVD bit of the
DD
M
M
Status register is set to 1.
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. Therefore, for the plot of Figure 7
where the first notch of the filter is at 60Hz, the output
data rate is 60Hz. The notches of this (sinx/x)3 filter are
repeated at multiples of the first notch frequency. The
SINC3 filter provides an attenuation of better than
100dꢀ at these notches.
RESET Voltage Monitor
The RESET voltage monitor is powered up at all times
(provided that VM = 0 and LVDE = 1 or VM = 1 and
LSDE = 1). A threshold voltage of either +1.8V or +2.7V
may be selected for the RESET voltage monitor (see
Power2 Register). At initial power-up, the RESET trip
threshold is set to 2.7V. If the RESET voltage monitor is
tripped, the RST bit of the status register is set to “1”
and RESET goes low. RESET is held low for 1.54
For step changes at the input, enough settling time
must be allowed before valid data can be read. The
settling time depends upon the output data rate chosen
for the filter. The settling time of the SINC3 filter to a full-
scale step input can be up to four times the output data
period, or three times if the step change is synchrozied
with FSYNC.
seconds (typ) after AV
rises above the RESET voltage
DD
DD
monitor threshold. If AV
is no longer below the RESET
threshold, reading the Status register will clear RST.
Low V Voltage Monitor
DD
When the device is operating in Run, Idle, or Standby
mode (see Power Modes) and AV goes below +2.7V,
DD
Force/Sense DAC
(MAX1407/MAX1409/MAX1414)
the low V
monitor trips, indicating that the supply volt-
DD
age is below the safe minimum for proper operation.
When tripped, the Low V Voltage Monitor sets the LVD
The MAX1407/MAX1414 incorporate two 10-bit force/
sense DACs while the MAX1409 has one. The DACs
use a precise 1.25V internal bandgap reference for set-
ting the full-scale range. Program the DAC1 and DAC2
registers through the serial interface to set the output
voltages of the DACs seen at OUT1 and OUT2.
DD
bit of the Status register to 1. If AV
is no longer below
DD
+2.7V, reading the Status register will clear LVD. The low
V
DD
monitor is powered down in Sleep mode. When it is
powered down, the LVD bit stays unchanged. The LVD is
cleared if it is read in Sleep mode.
20 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
modes except the sleep mode (see Power Modes). To
Internal/External Reference
The MAX1407/MAX1408/MAX1409/MAX1414 have an
internal low-drift +1.25V reference used for both ADC
and DAC conversion. The buffered reference output
can be used as a reference source for other devices in
the system. The internal reference requires a 4.7µF low-
ESR ceramic capacitor or tantalum capacitor connect-
ed between REF and AGND. For applications that
require increased accuracy, power-down the internal
reference by writing a 0 to the REFE bit of the Power1
register and connect an external reference source to
REF. The valid external reference voltage range is
1.25V 100mV.
reactivate the PLL, the following conditions must be
met: AV
is greater than the low V
voltage monitor
DD
DD
threshold, RESET is deasserted, and the PLLE bit is
equal to “1”. FOUT is enabled 31.25ms (t ) after
DFON
the PLL is activated. At initial power-up, the PLL is
enabled. If RESET is asserted while the PLL is running,
the PLL does not shut down.
Real-Time Clock (RTC)
The integrated RTC provides the current second,
minute, hour, date, month, day, year, century, and mil-
lenium information. An internally generated reference
clock of 1.024kHz (derived from the 32.768kHz crystal)
drives the RTC. The RTC operates in either 24-hour or
12-hour format with an AM/PM indicator (see RTC_Hour
Register). An internal calendar compensates for months
with less than 31 days and includes leap year correc-
tion through the year 9999. The RTC operates from a
supply voltage of +1.8V to +3.6V and consumes less
than 1µA current.
Crystal Oscillator
The on-chip oscillator requires an external crystal (or
resonator) connected between CLKIN and CLKOUT
with an operating frequency of 32.768kHz. This oscilla-
tor is used for the RTC, alarm, signal-detect compara-
tor, and PLL. The oscillator is operational down to 1.8V.
In any crystal-based oscillator circuit, the oscillator fre-
quency is based on the characteristics of the crystal. It
is important to select a crystal that meets the design
Time of Day Alarm
The MAX1407/MAX1408/MAX1409/MAX1414 offer a time
of day alarm which generates an interrupt when the RTC
reaches a preset combination of seconds, minutes,
hours, and day (see Alarm Registers). In addition to set-
ting a “single-shot” alarm, the Time of Day Alarm can
also be programmed to generate an alarm every sec-
ond, minute, hour, day, or week. “Don’t care” states can
be inserted into one or more fields if it is desired for them
to be ignored for the alarm condition. The Time of Day
Alarm wakes up the device into Standby mode if it is in
Sleep mode. The Time of Day Alarm operates from a
supply voltage of +1.8V to +3.6V.
requirements, especially the capacitive load (C ) that
L
must be placed across the crystal pins in order for the
crystal to oscillate at its specified frequency. C is the
L
capacitance that the crystal needs to “see” from the
oscillator circuit; it is not the capacitance of the crystal
itself. The MAX1407/MAX1408/MAX1409/MAX1414
have 6pF of capacitance across the CLKIN and CLK-
OUT pins. Choose a crystal with a 32.768kHz oscillation
frequency and a 6pF capacitive load such as the C-
002RX32-E from Epson Crystal. Using a crystal with a
C that is larger than the load capacitance of the oscil-
L
lator circuit will cause the oscillator to run faster than
the specified nominal frequency of the crystal.
Interrupt (INT)
INT indicates one of three conditions. After receiving a
valid interrupt (INT goes low), read the Status register
and the Al_Status register (if the alarm is enabled) to
identify the source of the interrupt. The three sources of
interrupts are from the CLK, SDC, and ALIRQ bits.
Conversely, using a crystal with a C that is smaller
L
than the load capacitance of the oscillator circuit will
cause the oscillator to run slower than the specified
nominal frequency of the crystal.
Phase-Locked Loop (PLL) and FOUT
An on-board phase-locked loop generates a
2.4576MHz clock at FOUT from the 32.768kHz crystal
oscillator. FOUT can be used to clock a µP or other dig-
ital circuitry. Connect an 18nF ceramic capacitor from
PLL Ready
On power-up, INT is high. 7.82ms (t ) after the PLL
DFI
output appears on FOUT, INT goes low (see Figure 15).
The CLK bit of the Status register is set to “1” after
FOUT is enabled. Reading the Status register clears the
CLK bit. INT remains low until the device detects a start
bit through the serial interface from the µP. The purpose
of this interrupt is to inform the µP that the FOUT clock
signal is present.
CPLL to AV
to create the 2.4576MHz clock signal at
DD
FOUT. To power down the PLL, clear PLLE in the
Power2 register (see Power2 Register) or write to the
Sleep register. FOUT will be active for 1.95ms (t
)
DFOF
after receiving either power-down command and then
go low. This provides extra clock signals to the µP to
complete a shutdown sequence. The PLL is active in all
______________________________________________________________________________________ 21
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
CS
SCLK
DIN
1
0
A4 A3 A2 A1 A0
x
D7 D6 D5 D4 D3 D2 D1 D0
1
1 A4 A3 A2 A1 A0 x
ADC
CONV
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
DRDY
Figure 8. ADC Conversion Timing Diagram
Signal Detect
SHDN is not available on the MAX1409. Note: Entering
Sleep mode automatically sets PLLE and SHDE to 0.
Any wake-up event will cause SHDN to go high. (See
Wake-Up section.)
The INT pin will also go low and stay low when the dif-
ferential voltage on the selected analog inputs exceeds
the signal-detect comparator trip threshold (0mV for the
MAX1407/MAX1408/MAX1409 and 50mV for the
MAX1414). This will latch the SDC bit of the Status reg-
ister to one. Additional signal detect interrupts cannot
be generated unless the SDC bit is cleared. To clear
the SDC bit, the Status register must be read and the
input must be below the signal-detect threshold.
Powering down the signal detect-comparator without
reading the Status register will also clear the SDC bit.
Similar to the power-up case, INT goes high when the
device detects a start bit through the serial interface
from the µP.
Data Ready (DRDY)
This pin will go low and stay low upon completion of an
ADC conversion or end of an ADC calibration. This sig-
nals the µP that a valid conversion or calibration result
has been written to the DATA or the OFFSET register.
The DRDY pin goes high either when the µP has fin-
ished reading the conversion/calibration result on the
last rising edge of SCLK (see Figure 8), or when the
next conversion result is about to be written to the
DATA register. When no read operation is performed,
DRDY pulses at 60Hz with a pulse high time of
162.76µs (or 30Hz with a pulse high time of 325.52µs)
DRDY is not available on the MAX1409. To see when
the ADC has completed a normal conversion or a cali-
bration conversion for the MAX1409, check the status
of the ADD bit in the Status register.
Time of Day Alarm
If the device is in Sleep mode, the alarm will wake up
the device and set the ALIRQ bit. INT is asserted when
the PLL is turned on. If an alarm occurs while the
device is awake (ꢀIASE = 1), the ALIRQ bit will be set
and INT will go low. INT remains low until the device
detects a start bit through the serial interface from the
µP. ALIRQ is reset to 0 when any alarm register is read
or written to.
Serial Digital Interface
The SPI/QSPI/MICROWIRE-serial interface consists of
chip select (CS), serial clock (SCLK), data in (DIN), and
data out (DOUT) (See Figure 9). The serial interface
provides access to 29 on-chip registers, allowing con-
trol to all the power modes and functional blocks,
including the ADCs, DACs, and RTC. Table 2 lists the
address and read/write accessibility of all the registers.
Shutdown (SHDN)
SHDN is an active-low output that can be used to con-
trol an external power supply. Powering up the PLL
(PLLE = 1) or writing a “1” to the SHDE bit of the
Power2 register causes SHDN to go high. SHDN goes
low when the SHDE bit is set to 0 only if the PLL is pow-
ered down (PLLE = 0). The SHDN output stays high for
) after receiving a power-down command,
allowing the external power supply to stay alive so that
the µP can properly complete a shutdown sequence.
A logic high on CS three-states DOUT and causes the
MAX1407/MAX1408/MAX1409/MAX1414 to ignore any
signals on SCLK and DIN. To clock data into or out of
the internal shift register, drive CS low. SCLK synchro-
nizes the data transfer. The rising edge of SCLK clocks
DIN into the shift register, and the falling edge of SCLK
2.93ms (t
DPD
22 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
clocks DOUT out of the shift register. DIN and DOUT are
transferred as MSꢀ first (data is left justified). Figure 10
shows detailed serial interface timing.
between writes to the MAX1407/MAX1408/MAX1409/
MAX1414. Figures 11–14 show the read and write timing
for 8- and 16-bit data. Data is updated on the last rising
edge of the SCLK in the command word. CS should not
go high between data transfers. If CS is toggled before
the end of a write or read operation, the device can
enter an incorrect mode. Clock in 72 zeros to clear this
state and re-arm the serial interface.
All communication with the MAX1407/MAX1408/
MAX1409/MAX1414 begins with a command byte on
DIN, where the first logic 1 on DIN will be recognized as
the START bit (MSꢀ) for the command byte (Table 3).
The following seven clock cycles load the command into
a shift register. These seven bits specify which of the
registers will be accessed, whether a read or write oper-
ation will take place, and the length of the subsequent
data (0-bit, 8-bit, 16-bit, or burst mode). Idle DIN low
After loading the command byte into the shift register,
additional clocks shift out data on DOUT for a read and
shift in data on DIN for a write operation.
CLKIN
µP/µC
32.768kHz
CLKOUT
FOUT
CLKIN
RESET
RESET
CS
SCLK
DIN
OUTPUT
SCK
MAX1407
MAX1408
MAX1409
MAX1414
MOSI
MISO
DOUT
INPUT
INPUT
INT
DRDY
WU1
WU2
I/O
I/O
DRDY NOT AVAILABLE ON MAX1409
Figure 9. SPI/QSPI Interface Connections
CS
• • •
• • •
t
t
t
t
CSH
CSS
CYC
CH
t
t
CL
CSH
SCLK
t
DS
t
DH
DIN
• • •
• • •
t
DV
t
t
TR
DO
DOUT
Figure 10. Detailed Serial Interface Timing
______________________________________________________________________________________ 23
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
CS
SCLK
1
0
A4 A3 A2 A1 A0
x
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIN
DOUT
Figure 11. Serial Interface 16-Bit Write Timing Diagram
CS
SCLK
1
0
A4 A3 A2 A1 A0
x
D7 D6 D5 D4 D3 D2 D1 D0
DIN
DOUT
Figure 12. Serial Interface 8-Bit Write Timing Diagram
CS
SCLK
1
1
A4 A3 A2 A1 A0
x
DIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
Figure 13. Serial Interface 16-Bit Read Timing Diagram
CS allows the SCLK, DIN, and DOUT signals to be
shared among several devices. When short on proces-
sor I/O pins, connect CS to DGND, and operate the seri-
al digital interface in CPOL = 1, CPHA = 1 or CPOL = 0,
CPHA = 0 modes using SCLK, DIN, and DOUT.
24 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
CS
SCLK
DIN
1
1
A4 A3 A2 A1 A0
x
D7 D6 D5 D4 D3 D2 D1 D0
DOUT
Figure 14. Serial Interface 8-Bit Read Timing Diagram
Table 2. Register Summary and Addressing
TARGET REGISTER
RTC_Sec Register
RTC_Min Register
RTC_Hour Register
RTC_Date Register
RTC_Month Register
RTC_Day Register
RTC_Year Register
RTC_Century Register
Power1 Register
Power2 Register
Sleep Register
R/W ACCESS
ADD4:ADD0
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
TARGET REGISTER
ADC Register
R/W ACCESS
ADD4:ADD0
00000
00001
00010
00011
00100
00101
00110
01000
01001
01010
01011
01100
01101
01110
01111
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
MUX Register
Data Register
Offset Register
R/W
R/W
R/W
R
DAC1 Register
DAC2 Register
Status Register
Al_ꢀurst Register
Al_Sec Register
Al_Min Register
Al_Hour Register
Al_Day Register
Al_Status Register
Alarm/Clock_Ctrl Register
RTC_ꢀurst Register
R/W
R/W
R/W
R/W
R/W
R
Standby Register
Idle Register
W
W
R/W
R/W
Run Register
W
Table 3. Command Byte Format
COMMAND
Write
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
1
1
0
1
ADD4:ADD0 (see Table 2)
ADD4:ADD0 (see Table 2)
X
X
Read
______________________________________________________________________________________ 25
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
On-Chip Registers
ADC REGISTER (00000)
FIRST BIT (MSB)
(LSB)
NAME
MODE
0
RATE
GAIN1
0
GAIN0
0
ꢀUFP
0
ꢀUFN
0
ꢀIP
0
STA1
0
DEFAULTS
0
MODE: Conversion Mode bit. A logic zero selects a
normal ADC conversion, while a logic 1 selects an offset
calibration conversion. After completing a calibration
conversion, MODE automatically resets to zero.
BIP: Unipolar/ꢀipolar bit. A logic zero selects unipolar
mode while a logic 1 selects bipolar mode.
STA1: Start bit. Setting STA1 to a logic 1 resets the reg-
isters inside the ADC filter, updates the ADC configura-
tion according to the ADC register, and initiates an
analog-to-digital conversion or offset calibration. The
initial conversion requires three cycles for valid output
data, and each subsequent conversion cycle will output
valid data. After completing the intial conversion, STA1
automatically resets to 0; however, the ADC will contin-
ue to do conversions until it is powered down.
RATE: Conversion Rate bit. A logic zero selects a 30Hz
conversion rate while a logic 1 selects a 60Hz conver-
sion rate.
GAIN1, GAIN0: Gain bits. The Gain bits select the PGA
gain. For an ADC gain of +1/3, +1, and 2V/V, [GAIN1
GAIN0] are 00, 01, and 10, respectively.
BUFP: Positive ꢀuffer bit. When this bit is 0, the positive
input buffer is bypassed and powered down. When this
bit is 1 and the ꢀUFE bit in the Power1 register is 1, the
positive input buffer drives the ADC input sampling
capacitors.
Writing to the ADC register with STA1 set to 0 updates
the ADC register without changing the ADC configura-
tion and allows the ADC to continue conversions unin-
terrupted. This allows the ADC and MUX configuration
to be updated simultaneously. See STA2 bit of the MUX
register.
BUFN: Negative ꢀuffer bit. When this bit is 0, the nega-
tive input buffer is bypassed and powered-down. When
this bit is 1 and the ꢀUFE bit in the Power1 register is 1,
the negative input buffer drives the ADC input sampling
capacitors.
MUX REGISTER (00001)
FIRST BIT (MSB)
(LSB)
NAME
MUXP2
0
MUXP1
0
MUXP0
0
MUXN2
0
MUXN1
0
MUXN0
0
DꢀIT
0
STA2
0
DEFAULTS
MUXP2, MUXP1, MUXP0: Positive Multiplexer bits.
MUXP[2:0] direct one-of-eight positive inputs to the
positive input of the ADC. Table 4 relates the MUXP bits
to the positive multiplexer inputs.
STA2: Start bit. Setting STA2 to a logic 1 updates the
mux selection, resets the registers inside the ADC filter,
updates the ADC configuration according to the ADC
register, and initiates an analog-to-digital conversion.
The initial conversion requires three cycles for valid out-
put data, and each subsequent conversion cycle will
output valid data. STA2 automatically resets to 0 after
the initial conversion completes. The ADC will continue
to do conversions until it is powered down. Writing to
the MUX register with the STA2 bit set to 0, updates the
MUX register and selection, but leaves the ADC config-
uration unchanged. The MUX input can be switched
with the ADC continuously converting without the digital
filter resetting.
MUXN2, MUXN1, MUXN0: Negative Multiplexer bits.
MUXN[2:0] direct one-of-eight (one-of-four for the
MAX1409) negative inputs to the negative input of the
ADC. Table 5 relates the MUXN bits to the negative
multiplexer inputs.
DBIT: Digital Output bit. This bit controls the output
state of D0. When the output buffer is enabled, D0 is
low if Dbit is equal to 0, and high if Dbit is equal to 1.
D0 is enabled by the D0E bit of the Power2 register.
26 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Table 4. Positive Mux Decoding
POSITIVE MUX INPUT
MAX1408
MUXP2
MUXP1
MUXP0
MAX1407/MAX1414
AV
MAX1409
AV
AV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DD
DD
DD
REF
REF
REF
OUT1
IN0
IN4
IN0
IN1
IN2
IN3
IN5
OUT1
IN0
—
IN1
IN2
—
IN3
—
OUT2
—
Table 5. Negative Mux Decoding
NEGATIVE MUX INPUT
MUXN2
MUXN1
MUXN0
MAX1407/MAX1414
MAX1408
AGND
REF
MAX1409
AGND
REF
FB1
IN0
AGND
REF
FB1
IN0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN6
IN0
IN1
IN1
—
IN2
IN2
—
IN3
IN3
—
FB2
IN7
—
DATA REGISTER—Read-Only (00010)
FIRST BIT (MSB)
ADC15
ADC14
ADC6
ADC13
ADC5
ADC12
ADC4
ADC11
ADC3
ADC10
ADC2
ADC9
ADC1
ADC8
ADC0
(LSB)
ADC7
The Data register contains the 16-bit result from the
most recently completed ADC conversion. The data for-
mat is binary for unipolar mode and two’s complement
for bipolar mode. After power-up, the DATA register
contains all zeros.
______________________________________________________________________________________ 27
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
OFFSET REGISTER (00011)
FIRST BIT (MSB)
OFF15
OFF14
OFF6
OFF13
OFF5
OFF12
OFF4
OFF11
OFF3
OFF10
OFF2
OFF9
OFF1
OFF8
OFF0
(LSB)
OFF7
The Offset register contains the 16-bit result from the
most recently completed ADC offset calibration. The
data format is two’s complement and is subtracted from
the filter output before writing to the Data register. After
power-up, the Offset register contains all zeros.
Force Sense DAC Registers
(MAX1407/MAX1409/MAX1414 only)
Writing to the DAC1 register updates the output of
DAC1. Writing to the DAC2 register updates the output
of DAC2. The DAC data is 10-bit long and left justified.
Follow the timing diagrams of Figure 11 and Figure 13
to program these registers. Writing a logic 0 to the
DA1E or DA2E bit in the POWER2 register disables
DAC1 or DAC2, respectively. At power-up, DAC1 and
DAC2 are disabled.
Each change in ambient operating condition (power
supply and temperature), PGA gain, bipolar/unipolar
input range, buffered/unbuffered mode, or conversion
speed requires an offset calibration. The offset for a
given ADC configuration can be read and stored by the
µP to avoid ADC recalibration. When returning to an
ADC configuration where the offset was stored, write
back the stored offset to the Offset register. The stored
offset stays valid as long as the ambient operating con-
dition remains unchanged (within 20°C).
DAC1 REGISTER (00100)
FIRST BIT (MSB)
DAC1[9]
DAC1[1]
DAC1[8]
DAC1[0]
DAC1[7]
x
DAC1[6]
x
DAC1[5]
x
DAC1[4]
x
DAC1[3]
x
DAC1[2]
x
(LSB)
Writing to the DAC1 register will update the DAC1 output
(OUT1). The output voltage in a unity gain configuration is
REF
(0 to 1023), and V
DAC. The DAC1 data is 10-bit long and left justified. After
power-up, the DAC1 register contains all zeros.
is the reference voltage for the
REF
V
x N/(210), where N is the integer value of DAC1[9:0]
DAC2 REGISTER (00101)
FIRST BIT (MSB)
DAC2[9]
DAC2[8]
DAC2[0]
DAC2[7]
x
DAC2[6]
x
DAC2[5]
x
DAC2[4]
x
DAC2[3]
x
DAC2[2]
x
DAC2[1]
(LSB)
Writing to the DAC2 register will update the DAC2 output
(OUT2). The output voltage in a unity-gain configuration is
REF
(0 to 1023), and V
DAC. The DAC2 data is 10-bit long and left justified. After
power-up, the DAC2 register contains all zeros.
is the reference voltage for the
REF
V
x N/(210), where N is the integer value of DAC2[9:0]
28 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
STATUS REGISTER (00110)
FIRST BIT (MSB)
(LSB)
—
NAME
WU2
0
WU1
0
RST
1
LVD
1
SDC
0
CLK
0
ADD
0
DEFAULT
0
Alarm Registers
WU2: Wake-Up2 status bit. When WU2 is pulled low,
WU2 is set to a logic 1. Reading the Status register
clears WU2, unless WU2 is still low. When WU2 is
pulled low when the device is awake (not in Sleep
mode), WU2 is cleared.
The Al_Sec, Al_Min, Al_Hour, Al_Day registers are pro-
grammed through the serial port to store the preset
time data in binary-coded decimal format (ꢀCD). See
Table 6 for decimal to ꢀCD conversion. These registers
can be accessed individually or consecutively using
burst mode (see Al_Burst Register section).
WU1: Wake-Up1 status bit. When WU1 is pulled low,
WU1 is set to a logic 1. Reading the Status register
clears WU1, unless WU1 is still low. When WU1 is
pulled low when the device is awake (not in Sleep
mode), WU1 is cleared.
To enable the alarm, set the AE bit of the
Alarm/Clock_Ctrl Register to 1 (see Alarm and RTC
Programming section). When an alarm occurs in any
mode, the ALIRQ bit of the AL_Status register will
change from 0 to 1, and the INT output will go low
unless you are in Sleep mode. If not already awake, the
device will wake-up from Sleep mode to Standby mode
and INT goes low when the PLL output is available. The
crystal oscillator, RTC, wake-up circuitry, reset voltage
RST: Reset status bit. When AV
drops below the
DD
RESET Voltage Monitor trip threshold (+1.8V or +2.7V),
RST is set to 1. This corresponds to the assertion of the
RESET pin. Reading the Status register clears RST,
unless AV
is still below the RESET Voltage Monitor
DD
monitor, low V
voltage monitor (if applicable), and
the PLL are all powered up in standby mode.
DD
trip threshold. At power-up, RST is at a logic 1 until the
Status register is read.
Four alarm registers (Al_Sec, Al_Min, Al_Hour, and
Al_Day) are used to store the preset time value for the
alarm function. ꢀit 7 of the Al_Sec, Al_Min, Al_Hour,
Al_Day registers is the mask bit and is used to program
how often the alarm occurs. Table 7 shows how ꢀit 7 of
the four alarm registers should be set for the time of
day alarm to occur. Other combinations of mask bits
are possible to set different alarms.
LVD: Low V
status bit. When AV
drops below the
DD
DD
Low V
Voltage Monitor trip threshold (+2.7V), LVD is
DD
set to a logic 1. Reading the Status register clears LVD
unless AV is still below 2.7V. At power-up, LVD is at
DD
a logic 1 until the Status register is read. When the Low
V
Voltage Monitor is powered down (LVDE = 0), the
DD
LVD bit stays unchanged.
SDC: Signal-Detect Comparator status bit. SDC is set
to “1” when the differential polarity voltage across the
signal-detect comparator exceeds the signal-detect
threshold (0mV for the MAX1407/MAX1408/MAX1409
and 50mV for the MAX1414). This corresponds to the
assertion of the INT pin. Reading the Status register
clears SDC unless the condition remains true. SDC is
also reset to 0 when the signal-detect comparator is
powered down (SDCE = 0).
Table 6. BCD Conversion
DECIMAL DIGIT
BCD
0000
0001
0010
0011
0100
0101
0110
0111
0
1
2
3
4
5
6
7
8
9
CLK: FOUT Clock Enable status bit. CLK is set to “1”
after the FOUT clock pin has been enabled in t
DFON
milliseconds (see Figure 15). Reading the Status register
clears the CLK bit.
1000
1001
ADD: ADC Done Status bit. ADD is set to “1” to indicate
that the ADC has completed either a normal conversion
or a calibration conversion, and the conversion result is
available to be read. This corresponds to the assertion
of the DRDY pin. Reading either the Data or Offset
register clears the ADD bit. Reading the Status register
WILL NOT clear this bit.
UNUSED CODES
1010
1011
1100
1101
1110
1111
______________________________________________________________________________________ 29
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Table 7. Common Mask Bits Combinations
ALARM REGISTER MASK BITS (BIT 7)
FUNCTION
HOW OFTEN?
AL_SEC
AL_MIN
M_HOUR
M_DAY
1
0
1
1
1
1
1
1
Alarm occurs once per second
Once per second
Once per minute
Alarm occurs when seconds match
Alarm occurs when minutes and
seconds match
0
0
0
0
0
0
1
0
0
1
1
0
Once per hour
Once per day
Once per week
Alarm occurs when hours, minutes, and
seconds match
Alarm occurs when day, hours, minutes,
and seconds match
AL_BURST REGISTER (01000)
Writing to this register begins the alarm burst mode
transfer. All the alarm clock registers are consecutively
read from or written to starting with ꢀit7 of the Al_Sec
register followed by the Al_Min register, Al_Hour regis-
ter, and finally the Al_Day register.
AL_SEC REGISTER (01001)
FIRST BIT (MSB)
(LSB)
NAME
M_SEC
0
10SEC2
0
10SEC1
0
10SEC0
0
SEC3
0
SEC2
0
SEC1
0
SEC0
0
DEFAULT
M_SEC: Alarm mask bit. A logic 1 masks out the sec-
onds alarm comparator.
SEC[3:0]: These are the second bits (0–9 seconds) of
the alarm.
10SEC[2:0]: These are the 10-second bits (0–50 sec-
onds) of the alarm.
AL_MIN REGISTER (01010)
FIRST BIT (MSB)
(LSB)
NAME
M_MIN
0
10MIN2
0
10MIN1
0
10MIN0
0
MIN3
0
MIN2
0
MIN1
0
MIN0
0
DEFAULT
M_MIN: Alarm mask bit. A logic 1 masks out the minute
alarm comparator.
MIN[3:0]: These are the minute bits (0–9 minutes) of
the alarm.
10MIN[2:0]: These are the 10-minute bits (0–50 min-
utes) of the alarm.
30 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
AL_HOUR REGISTER (01011)
FIRST BIT (MSB)
(LSB)
HR0
0
NAME
M_HR
0
12/24
0
AP
0
10HR
0
HR3
0
HR2
0
HR1
0
DEFAULT
M_HR: Alarm mask bit. A logic 1 masks out the hour
AP: AM/PM bit. In 12-hour mode, a logic 1 indicates
PM and a logic 0 indicates AM. In 24-hour mode, this
bit is the second 10-hour bit (20 hours).
alarm comparator.
12/24: 12/24-hour mode bit. A logic 1 selects 12-hour
mode while a logic 0 selects 24-hour mode. This bit
must be the same as the 12/24-bit of the RTC_Hour
register for correct operation.
10HR: This is the 10-hour bit (0–10 hours) of the alarm.
HR[3:0]: These are the hour bits (0–9 hours) of the
alarm.
AL_DAY REGISTER (01100)
FIRST BIT (MSB)
(LSB)
NAME
M_DAY
0
—
—
—
—
DAY2
0
DAY1
0
DAY0
1
DEFAULT
0
0
0
0
M_DAY: Alarm mask bit. A logic 1 masks out the day
alarm comparator.
DAY[2:0]: These are the day of the week bits (Sunday
–Saturday). The following table is the Hex code for
each day of the week.
AL_DAY
DAY[2:0]
SUN
1h
MON
2h
TUE
3h
WED
4h
THU
5h
FRI
6h
SAT
7h
AL_STATUS REGISTER (01101)
FIRST BIT (MSB)
(LSB)
NAME
ALIRQ
0
—
—
—
—
—
—
—
DEFAULT
0
0
0
0
0
0
0
ALIRQ: Alarm Interrupt Request ꢀit. A logic 1 indicates
that the current time has matched the preset time in the
alarm registers (this corresponds to the assertion of the
INT pin). ALIRQ resets to 0 when any alarm register is
read or written to.
______________________________________________________________________________________ 31
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ALARM/CLOCK_CTRL REGISTER (01110)
FIRST BIT (MSB)
(LSB)
AE
NAME
WE
0
—
—
—
—
—
—
DEFAULT
0
0
0
0
0
0
0
WE: Write Enable bit. WE must be set to “1” before any
write operation to the clock and the alarm register. A
logic 0 disables write operations to the clock and alarm
registers, including the AE bit. The WE signal takes
effect after the 8th SCLK rising edge for an 8-bit write.
sequentially with the MSꢀ of the Seconds register first.
They must all be read out as a group of eight registers
of eight bits each, for proper execution of the burst
read function. The worst-case error that can occur
between the “actual” time and the “reported” time is
one second. As with a read operation, using single
writes to update the RTC can lead to collisions. To
guarantee an accurate update of the RTC, use the
ꢀurst Write mode (see Alarm and RTC Programming
section).
AE: Alarm Enable bit. A logic 0 disables the alarm func-
tion. When AE equals “1”, the ALIRQ bit in the Al_Status
register will be set to 1 whenever the current time
matches that of the alarm registers.
Real-Time Clock (RTC)
The RTC_Sec, RTC_Min, RTC_Hour, RTC_Date,
RTC_Month, RTC_Day, RTC_Year, and RTC_Century
registers can be accessed one register at a time or in
ꢀurst mode (see RTC_BURST REGISTER section). The
RTC runs continuously and does not stop for read or
write operations. To prevent the data from changing
during a read operation, complete all read operations
on the RTC registers (single register reads and burst
reads) in less than 1ms.
The RTC defaults to 24-hr mode, 00:00:00, Sunday,
January 01, 1970 during power-up. January 01, 1970
falls on a Thursday, but since this RTC is not time-
based, the default values do not have an impact on the
functionality of the clock, and they merely provide some
means for testing. If the alarm or RTC registers are pro-
grammed to some unused states, the device chooses
the default values.
RTC_BURST REGISTER (01111)
Writing to this address begins the burst mode transfer.
In this mode, all the real-time clock registers are contin-
uously read or written starting with ꢀit 7 of the
RTC_Sec, RTC_Min, RTC_Hour, RTC_Date,
RTC_Month, RTC_Day, RTC_Year, and RTC_Century
registers. When reading, the contents of DIN will be
ignored and each register’s 8-bit data will be clocked
out at DOUT on the falling edge of SCLK (total of 64
clock cycles). When writing, start with the Seconds’
register MSꢀ first and continue through the Century
register (see Alarm and RTC Programming section).
Using single reads to read all the RTC registers could
lead to errors as much as a century. Since the registers
are updated between read operations, the register con-
tents may change before all RTC registers have been
read, when reading one register at a time. The most
accurate way to get the time information of the RTC
registers is with a burst read. In the burst read, a snap-
shot of the eight RTC registers (RTC_Sec, RTC_Min,
RTC_Hour, RTC_Date, RTC_Month, RTC_Day,
RTC_Year, RTC_Century) is taken once and read
RTC_SEC REGISTER (10000)
FIRST BIT (MSB)
(LSB)
NAME
CH
0
10SEC2
0
10SEC1
0
10SEC0
0
SEC3
0
SEC2
0
SEC1
0
SEC0
0
DEFAULT
CH: Clock Halt bit. Writing a “1” to CH disables the
real-time clock and oscillator.
SEC[3:0]: These are the second bits (0–9 seconds) of
the RTC.
10SEC[2:0]: These are the 10 second bits (10–50 sec-
onds) of the RTC.
32 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
RTC_MIN REGISTER (10001)
FIRST BIT (MSB)
(LSB)
MIN0
0
NAME
—
10MIN2
10MIN1
0
10MIN0
0
MIN3
0
MIN2
0
MIN1
0
DEFAULT
0
0
10MIN[2:0]: These are the 10 minute bits (0–50 min-
utes) of the RTC.
MIN[3:0]: These are the minute bits (0–9 minutes) of
the RTC.
RTC_HOUR REGISTER (10010)
FIRST BIT (MSB)
(LSB)
NAME
—
12/24
0
AP
0
10HR
0
HR3
0
HR2
0
HR1
0
HR0
0
DEFAULT
0
12/24: 12/24-hour mode bit. A logic 1 selects 12-hour
mode while a logic 0 selects 24-hour mode. This bit
must be the same as the 12-/24-bit of the AL_Hour reg-
ister for correct operation.
AP: AM/PM-bit. In 12-hour mode, a logic 1 indicates
PM and a logic 0 indicates AM. In 24 hour mode, this
bit is the second 10-hour bit (20 hours).
10HR: This is the 10-hour bit (0–10 hours) of the RTC.
HR[3:0]: These are the hour bits (0–9 hours) of the RTC.
RTC_DATE REGISTER (10011)
FIRST BIT (MSB)
(LSB)
NAME
—
—
10DATE1
0
10DATE0
0
DATE3
0
DATE2
0
DATE1
0
DATE0
1
DEFAULT
0
0
10DATE[1:0]: These are the 10 day bits (0–30 days) of
the RTC.
DATE[3:0]: These are the day bits (0–9 days) of the RTC.
RTC_MONTH REGISTER (10100)
FIRST BIT (MSB)
(LSB)
NAME
—
—
—
10MO
0
MO3
0
MO2
0
MO1
0
MO0
1
DEFAULT
0
0
0
10MO: This is the 10 month bit (0–10 months) of the RTC.
______________________________________________________________________________________ 33
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
10MO: This is the 10 month bit (10–12 months)
MO[3:0]: These are the month bits (0–9 months) for the
RTC. The following table is the Hex code for the twelve
months of the year.
MONTH
10MO MO[3:0]
MONTH
JAN
01h
JUL
07h
FEB
02h
AUG
08h
MAR
03h
SEP
09h
APR
04h
OCT
10h
MAY
05h
NOV
11h
JUN
06h
DEC
12h
10MO MO[3:0]
RTC_DAY REGISTER (10101)
FIRST BIT (MSB)
(LSB)
NAME
—
—
—
—
—
DAY2
0
DAY1
0
DAY0
1
DEFAULT
0
0
0
0
0
DAY[2:0]: These bits select the day of the week
(Sunday–Saturday). The following table is the Hex code
for day of the week.
AL_DAY
DAY[2:0]
SUN
1h
MON
2h
TUE
3h
WED
4h
THU
5h
FRI
6h
SAT
7h
RTC_YEAR REGISTER (10110)
FIRST BIT (MSB)
(LSB)
NAME
10YEAR3
0
10YEAR2
10YEAR1
1
10YEAR0
1
YEAR3
0
YEAR2
YEAR1
0
YEAR0
0
DEFAULT
1
0
10YEAR[3:0]: These are the 10 year bits (0–90 years) of
the RTC.
YEAR[3:0]: These are the year bits (0–9 years) of the RTC.
RTC_CENTURY REGISTER (10111)
FIRST BIT (MSB)
(LSB)
NAME
MILL3
0
MILL2
0
MILL1
0
MILL0
1
CENT3
1
CENT2
0
CENT1
0
CENT0
1
DEFAULT
MILL[3:0]: These are the millennium bits (0000–9000
years) of the RTC.
CENT[3:0]: These are the century bits (000–900 years)
of the RTC.
34 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Table 8. Related Bit Values During Specified Mode
CIRCUIT BLOCK
32kHz Oscillator
RTC
BIT
CH
CH
INITIAL POWER-UP
0 (oscillator is on)
0 (RTC is on)
SLEEP
N/A
STANDBY
N/A
IDLE
N/A
RUN
N/A
WAKE-UP EVENT
N/A
N/A
N/A
N/A
N/A
N/A
Low V
Monitor (2.7V)
Voltage
1 (2.7V monitor is
on)
1 if VM = 0
0 if VM = 1
DD
LVDE
LSDE
1
1
1
1
RESET Voltage
Monitor (1.8V)
0 (1.8V monitor is
off)
0 if VM = 0 0 if VM = 0 0 if VM = 0 0 if VM = 0
1 if VM = 1 1 if VM = 1 1 if VM = 1 1 if VM = 1
N/A
Reset ꢀit
RST
LVD
1 (RESET asserted)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 (low V )
DD
Low V
Status ꢀit
DD
Voltage-Monitor
Threshold Selection
VM
0 (select 2.7V)
N/A
0
N/A
1
N/A
1
N/A
1
N/A
1
ꢀiase = 1 (biase
circuit is on)
ꢀias Circuit
ꢀIASE
PLL
PLLE
PLLE
SHDE
DA1E
DA2E
MUX
1 (PLL is on)
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PLL Output
SHDN Output
DAC1
1 (FOUT is enabled)
1
1 (SH D N pin = high)
1
0
0
0
0
N/A
N/A
N/A
N/A
DAC2
ADC MUX
ꢀandgap Reference
REFE
Signal-Detect
Comparator
SDCE
0
0
0
1
1
N/A
ADC ꢀuffers
ADC
ꢀUFE
ADC
0
0
0
0
0
0
0
0
1
1
N/A
N/A
N/A: Programming the part into these modes would not alter the content of the corresponding bit.
Power-Control Registers
Table 8 shows the bit values of some key registers in
different power modes under various conditions. Use
this as a quick reference when programming the
MAX1407/MAX1408/MAX1409/MAX1414 family.
POWER1 REGISTER (11000)
FIRST BIT (MSB)
(LSB)
NAME
REFE
0
ADCE
0
BUFE
0
MUXE
0
DA1E
0
DA2E
0
—
—
DEFAULT
0
0
REFE: Internal Reference Power Enable. When REFE is
set to 1, the internal reference is powered up. When
REFE is set to 0, the internal reference is powered down
allowing an external reference to be connected to REF.
BUFE: ADC Input ꢀuffer Power Enable. A logic 1
enables the power-up of the ADC input buffers, while a
logic 0 powers-down the buffers.
MUXE: Multiplexer enable. A logic 0 disables the multi-
plexer outputs while a logic 1 enables them.
ADCE: ADC Power Enable. When ADCE is set to 1, the
ADC is powered up. When ADCE is set to 0, the ADC is
powered down.
______________________________________________________________________________________ 35
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
DA1E: DAC1 Power Enable. A logic 1 powers DAC1,
while a logic 0 powers it down. The output buffer goes
high impedance in power-down mode.
DA2E: DAC2 Power Enable. A logic 1 powers DAC2,
while a logic 0 powers it down. The output buffer goes
high impedance in power-down mode.
POWER2 REGISTER (11001)
FIRST BIT (MSB)
(LSB)
NAME
SHDE
PLLE
1
LVDE
1
LSDE
0
SDCE
0
D0E
0
VM
0
ꢀIASE
1
DEFAULT
1
SLEEP REGISTER (11010)
SHDE: Shutdown Enable bar. If SHDE is set to 1,
SHDN is pulled high. A wake-up event such as an
assertion of WU1 or WU2, a time-of-day alarm, or by
writing to the Power1, Power2, Standby, Idle, or Run
registers sets this bit to 1 and drives SHDN high. If the
SHDE bit is set to 0 in Standby, Idle, or Run mode and
the PLL is still operational (PLLE = 1), the SHDN pin will
Addressing the Sleep register places the MAX1407/
MAX1408/MAX1409/MAX1414 in Sleep mode. This
occurs after the last bit of the command byte is clocked
into the device. It requires an 8-bit write, no data bits
are needed. Sleep mode powers down all functional
blocks except for the crystal oscillator, RTC, alarm, ser-
ial interface, wake-up circuitry, and RESET voltage
monitor. While in Sleep mode, pulling either WU1 or
WU2 low or an alarm event places the device into
Standby mode.
remain high until 2.93ms (t
) after PLLE is set to 0.
DPD
PLLE: Phase-Locked Loop Power Enable. A logic 1
powers the PLL and enables FOUT while a logic 0 pow-
ers down the PLL and disables FOUT. A wake-up event
sets this bit to 1. See Wake-Up section.
STANDBY REGISTER (11011)
Addressing the Standby register places the MAX1407/
MAX1408/MAX1409/MAX1414 in Standby mode. This
occurs after the last bit of the address byte is clocked
into the device. It requires an 8-bit write, no data bits
are needed. Standby mode powers up the same blocks
as Sleep mode, as well as the master bias circuitry, the
LVDE: +2.7V Voltage Monitor Power Enable. A logic 1
powers the +2.7V voltage comparator circuitry, while a
logic 0 powers down the +2.7V voltage comparator cir-
cuitry. A wake-up event sets LVDE to 1. See Wake-Up
section.
LSDE: +1.8V Voltage Monitor Power Enable. A logic 1
powers the +1.8V voltage comparator circuitry, while a
logic 0 powers down the +1.8V voltage comparator cir-
cuitry. See Wake-Up section.
PLL, and the Low V
Voltage Monitor. FOUT is also
enabled and SHDN is set high in Standby mode.
DD
IDLE REGISTER (11100)
SDCE: Signal-Detect Comparator Power Enable. A
logic 1 powers the signal-detect comparator while a
logic 0 powers down this comparator.
Addressing the Idle register places the MAX1407/
MAX1408/MAX1409/MAX1414 in Idle mode. This
occurs after the last bit of the address byte is clocked
into the device. Requires an 8-bit write, no data bits are
needed. In Idle mode, all circuits are powered up with
the exception of the ADC and the ADC Input ꢀuffers.
D0E: D0 Enable bit. A logic 0 three-states the D0
ouput. When D0E is set to “1”, the output of D0 is con-
tolled by the state of DꢀIT in the MUX register.
Programming the device in different modes does not
alter the state of this bit.
RUN REGISTER (11101)
Addressing the Run register puts the MAX1407/
MAX1408/MAX1409/MAX1414 into Run mode. This
occurs after the last bit of the address byte is clocked
into the device. Requires an 8-bit write, no data bits are
needed. All the functional blocks are powered up in
Run mode.
VM: RESET Voltage Monitor Threshold Selection bit. A
logic 0 selects a +2.7V threshold while a logic 1 selects
a +1.8V threshold for the RESET Voltage Monitor. The
VM bit effects the LVDE and LSDE bits in different
modes of operation (see Table 8).
BIASE: ꢀias Enable. A logic 1 powers up the master
bias circuit block. A wake-up event sets this bit to a
logic 1. See Wake-Up section.
36 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Idle Mode
Applications Information
In Idle mode, only the ADC and ADC input buffers are
Alarm and RTC Programming
Three write operations are needed for every update of
the ALARM and RTC registers. First set the WE bit of
the Alarm/Clock_CTRL Register to 1. Update the Alarm,
RTC, and Alarm/Clock_CTRL Register with the new val-
ues, and then set the WE bit back to 0. This will avoid
collisions in setting the time.
shutdown. All the other blocks are powered up. Enter
Idle mode by addressing the Idle register.
Run Mode
In Run mode, all the functional blocks are powered up
and the ADC is ready to start conversion. Enter Run
mode by either writing to the Run register or by individu-
ally powering up each circuit through the serial interface.
Power-On Reset or Power-Up
At initial power-up, the MAX1407/MAX1408/MAX1409/
MAX1414 are in Standby mode. Figure 15 illustrates the
timing of various signals during initial Power-Up, Sleep
Wake-Up
Wake-Up mode is entered whenever a wake-up event,
such as an assertion of WU1 or WU2 or a time-of-day
alarm occurs. The Low V
monitor, PLL, FOUT are
DD
mode, and Wake-Up. t
after AV
exceeds +2.7V,
DD
DSLP
enabled, and SHDN goes high. Different from the
Standby mode, the status of the other power blocks
remains unchanged.
RESET goes high. t
after RESET goes high, FOUT
DFON
is enabled. INT is enabled to t
after FOUT is
DFI
enabled.
Analog Filtering
The digital filter does not provide any rejection close to
the harmonics of the modulator sample frequency.
However, due to the high oversampling ratio of the
MAX1407/MAX1408/MAX1409/MAX1414, these bands
occupy only a small fraction of the spectrum and most
broadband noise is filtered. Therefore, the analog filter-
ing requirements in front of the MAX1407/MAX1408/
MAX1409/MAX1414 are considerably reduced com-
pared to a conventional converter with no on-chip filter-
ing. In addition, because the part’s common-mode
rejection of 90dꢀ extends out to several kHz, common-
mode noise susceptibility in this frequency range is
substantially reduced.
Power Modes
The MAX1407/MAX1408/MAX1409/MAX1414 have fou
distinct power modes, Sleep mode, Standby mode, Idle
mode, and Run mode. Table 9 lists the power-on status
of the various blocks of the MAX1407/MAX1408/
MAX1409/MAX1414. Each individual circuit block can
be powered up through the serial interface by writing to
the appropriate power registers.
Sleep Mode
In Sleep mode, only the crystal oscillator, RTC, data
registers, wake-up circuitry, and RESET Voltage
Monitor are powered up. Sleep mode is entered by
addressing the Sleep register through the serial inter-
face. Sleep mode preserves any data in the data regis-
ters. To exit Sleep mode, pull either WU1 or WU2 low or
address other Power mode registers (Standby, Idle,
Run, Power1, or Power2 registers). Asserting WU1 or
WU2 or the occurence of a Time of Day Alarm while in
Sleep mode places the device in Standby mode.
Depending on the application, it may be necessary to
provide filtering prior to the MAX1407/MAX1408/
MAX1409/MAX1414 to eliminate unwanted frequencies
the digital filter does not reject. It may also be necessary
in some applications to provide additional filtering to
ensure that differential noise signals outside the frequen-
cy band of interest do not saturate the analog modulator.
Standby Mode
After initial power-up or after exiting Sleep mode
through a wake-up event, the MAX1407/MAX1408/
MAX1409/MAX1414 are in Standby mode. Standby
mode can also be entered by addressing the Standby
register. In Standby mode, SHDN is high, FOUT is
If passive components are placed in front of the
MAX1407/MAX1408/MAX1409/MAX1414 when the part
is used in unbuffered mode, ensure that the source
impedance is low enough not to introduce gain errors in
the system. This can significantly limit the amount of
passive anti-aliasing filtering that can be applied in
front of the MAX1407/MAX1408/MAX1409/MAX1414 in
unbuffered mode. However, when the part is used in
buffered mode, large source impedances will simply
result in a small DC offset error (a 1kΩ source resis-
tance will cause an offset error of less than 0.5µV).
Therefore, where significant source impedances are
required, operate the device in buffered mode.
enabled, the Low V
voltage monitor and the PLL are
DD
powered up, and INT is low. INT will return to a logic
high after the µP begins writing to any register through
the serial interface (once a start bit is detected through
the serial interface).
______________________________________________________________________________________ 37
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
4
AV
DD
3
2
2.7V
1
0v
HI
RESET
(OPEN-DRAIN)
t
DSLP
LO
HI
LO
HI
32kHz CLOCK
WU1,WU2
(INT. PULLUP)
t
WU
LO
HI
t
DPU
SHDN
LO
HI
t
t
DFON
t
DPD
DFON
FOUT
(2.4576MHz)
LO
HI
t
t
DFOF
t
DFI
DFI
INT
LO
HI
DRDY
DOUT
CS
LO
HI
THREE-STATED
LO
HI
SLEEP
WRITE
LO
HI
SCLK,
DIN
LO
INITIAL POWER-UP
SLEEP MODE
WAKE-UP
Figure 15. Initial Power-up, Sleep Mode, and Wake-Up Timing Diagram with AV
>2.7V
DD
tages of series input resistance. A series resistor
reduces the transient current impulse to the external
driving amplifier. This improves the amplifier phase
margin and reduces the possibility of ringing. The resis-
Dynamic Input Impedance
When designing with the MAX1407/MAX1408/
MAX1409/MAX1414, as with any other switched-capac-
itor ADC input, consider the advantages and disadvan-
38 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Table 9. Power States of Individual Blocks at Different Modes of Operation
POWER MODES
CIRCUIT BLOCKS
SLEEP
x
STANDBY
IDLE
x
RUN
x
WAKE-UP EVENT
Serial Interface
x
x
x
x
Wake-Up Circuitry
Crystal Oscillator
RTC with Alarm
x
x
x
x
x
x
x
x
x
x
x
x
x
RESET Voltage Monitor
x
x
x
x
x
Low V
Voltage Monitor
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
DD
Master Bias Circuit
PLL
x
x
x
x
x
x
x
x
FOUT
x
x
x
x
SHDN = High
DAC1
x
x
x
x
—
—
—
—
—
—
—
—
x
x
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DAC2
x
x
Bandgap
x
x
Bandgap Buffer
Signal Detect Comparator
ADC Multiplexer
ADC Input Buffers
ADC
x
x
x
x
x
x
—
—
x
x
x = powered-up
N/A = programming the parts into the wake-up mode would not alter the content of these blocks
Table 10. REXT, CEXT Values for Less than 16-Bit Gain Error in Unbuffered Mode
EXTERNAL RESISTANCE R
(kΩ)
EXT
PGA GAIN
(V/V)
C
= 0pF
C
= 50pF
56
C
= 100pF
33
C
= 200pF
C = 500pF
EXT
EXT
EXT
EXT
EXT
1
2
194
100
19
9
9
30
16
4.5
tor spreads the transient-load current from the sampler
over time due to the RC time constant of the circuit.
However, an improperly chosen series resistance can
hinder performance in high-resolution converters. The
settling time of the RC network can limit the speed at
which the converter can operate properly, or reduce
the settling accuracy of the sampler. In practice, this
means ensuring that the RC time constant, resulting
from the product of the driving source impedance and
the capacitance presented by both the device’s input
and any external capacitance is sufficiently small to
allow settling to the desired accuracy. Table 10 sum-
marizes the maximum allowable series resistance vs.
external shunt capacitance for each different gain set-
ting in order to ensure 16-bit performance in unbuffered
mode (for 60sps conversion rate).
Performing a Conversion or Offset-
Calibration with the ADC
Upon power-up, the MAX1407/MAX1408/MAX1409/
MAX1414 are in Standby mode. At this point, the ADC
register default settings are set for a normal ADC conver-
sion (MODE = 0), conversion rate of 30Hz (RATE = 0),
gain of 1/3 V/V (GAIN [00]), input buffers bypassed and
powered down (ꢀUFP = ꢀUFN = 0), and unipolar mode
______________________________________________________________________________________ 39
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
R1
R2
REF
MAX1407/MAX1409/MAX1414
FB1
FB_
+5V
V
OUT
DAC 1
REF
OUT1
OUT2
DAC_
OUT_
-5V
FB2
R2 = R1
MAX1407/MAX1409/MAX1414
DAC 2
Figure 18. Bipolar Output Circuit
DGND
AGND
will keep doing conversions at a rate of 30Hz until pow-
ered down.
THE MAX1409 HAS ONE DAC
= 1.25V
V
REF
To perform an on-chip offset calibration on a specific
configuration, write to the ADC register with the MODE
bit and STA1 bit set to 1. The ADC will do one calibra-
tion using the inputs to the ADC specified in the MUX
register and then stop. The calibration result will be
stored in the Offset register in two’s complement form.
Subsequent ADC conversion results will have the offset
value subtracted before written to the DATA register.
The MODE bit will be reset to 0 automatically upon
completion of the calibration. The ADC is now ready for
a normal conversion.
Figure 16. Unipolar Output Circuit
10kΩ
MAX1407/MAX1409/MAX1414
FB1
FB2
10kΩ
DAC 1
REF
OUT1
OUT2
The offset for a given ADC configuration can be stored
by the µP to avoid another ADC recalibration. Write the
stored offset back to the offset register when returning
back to that particular ADC configuration where the cal-
ibration was taken. Subsequent ADC conversion results
will have the offset value subtracted before they are
written to the DATA register.
10kΩ
10kΩ
DAC 2
DGND
AGND
DAC Unipolar Output
For a unipolar output, the output voltages and the refer-
ence have the same polarity. Figure 16 shows the
MAX1407/MAX1409/MAX1414s’ unipolar output circuit,
which is also the typical operating circuit for the DACs.
Table 11 lists some unipolar input codes and their cor-
responding output voltages.
THE MAX1409 HAS ONE DAC
REF
V
= 1.25V
Figure 17. Unipolar Rail-to-Rail Output Circuit
For larger output swing see Figure 17. This circuit
shows the output amplifiers configured with a closed-
loop gain of +2V/V to provide 0 to 2.5V full-scale range
with the 1.25V reference.
(ꢀIP = 0). To initiate an ADC conversion: 1) Enter Run
mode by addressing the Run register 2) Select the
desired channels for conversion by writing to the MUX
register, (e.g., 94h selects IN1 for the positive channel
and IN2 for the negative channel) 3) Initiate the conver-
sion by writing to the ADC register, (e.g., 01h). The first
conversion result becomes available in 100ms. The ADC
DAC Bipolar Output
The MAX1407/MAX1409/MAX1414 DAC outputs can be
configured for bipolar operation using the application
circuit on Figure 18:
40 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Table 12. Bipolar Code Table
Table 11. Unipolar Code Table
DAC CONTENTS
DAC CONTENTS
ANALOG OUTPUT
ANALOG OUTPUT
MSB
LSB
MSB
LSB
1111 1111 11
1000 0000 01
1000 0000 00
0111 1111 11
0000 0000 01
0000 0000 00
+V
(511/512)
(1/512)
1111 1111 11
1000 0000 01
1000 0000 00
0111 1111 11
0000 0000 01
0000 0000 00
+V
(1023/1024)
(513/1024)
REF
REF
+V
+V
REF
REF
0
+V
(512/1024) = +V
/2
REF
REF
-V
(1/512)
+V
(511/1024)
(1/1024)
REF
REF
-V
REF
(511/512)
+V
REF
-V
(512/512) = -V
0
REF
REF
V
= 3.3V OR V
BAT
DD
LX
OUT
RST
10µF
10µH
18nF
0.1µF
0.1µF
0.1µF
MAX1833
SHDN
BATT
CPLL
SHDN
AV
DV
V
DD
DD
DD
GND
RESET
WU1
RESET
INPUT
MAX1407
MAX1408
MAX1414
µP/µC
IN0
10µF
V
E1*
BAT
AGND
DGND
V
SS
*ONE Li+ COIN, TWO ALKALINE, OR TWO BUTTON CELLS
Figure 19. Power-Supply Circuit Using MAX1833 Step-Up DC-DC Converter
0.33µF
CXN CXP
V
= 3.3V
DD
IN
OUT
POK
10µF
18nF
0.1µF
0.1µF
0.1µF
MAX1759
SHDN
GND PGND
CPLL
AV
DD
DV
V
DD
DD
FB
SHDN
IN0
RESET
WU1
RESET
INPUT
MAX1407
MAX1408
MAX1414
µP/µC
R
AGND
DGND
V
R
SS
10µF
V
E1*
BAT
*ONE Li+ COIN, ONE Li+, 2-3 ALKALINE, 2-3 NIMH, OR 2-3 BUTTON CELLS
Figure 20. Power-Supply Circuit Using MAX1759 Buck-Boost DC-DC Converter
______________________________________________________________________________________ 41
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
100µH
V
(+3.3V)
DD
V+
LX
MAX640
D1
SHDN
100µF
18nF
0.1µF
0.1µF
0.1µF
VOUT
CPLL
AV
DV
V
DD
DD
DD
LBI
VFB
GND
RESET
WU1
RESET
INPUT
MAX1407
MAX1408
MAX1409
MAX1414
µP/µC
2R
IN0
R
V
BAT
E1*
AGND
DGND
V
33µF
SS
*ONE TRANSISTOR (9V), ONE J CELL (6V), OR FOUR ALKALINE CELLS
Figure 21. Power-Supply Circuit Using MAX640 Step-Down DC-DC Converter
20, 21, and 22 are power-supply circuits using a step-up
converter, buck-boost converter, step-down converter,
and a direct battery, respectively. Choose the correct
power-supply circuit for your specific application.
10µF
18nF
0.1µF
V
BAT
E1*
0.1µF
0.1µF
Connect the MAX1407/MAX1408/MAX1409/MAX1414
AV
and DV
power supplies together. While the
DD
DD
CPLL
AV
DV
V
DD
DD
DD
latch-up performance of the MAX1407/MAX1408/
MAX1409/MAX1414 is adequate, it is important that
power is applied to the device before the analog input
signals (IN_) to avoid latch-up. If this is not possible,
limit the current flow into any of these pins to 50mA.
RESET
WU1
RESET
µP/µC
INPUT
MAX1407
MAX1408
MAX1409
MAX1414
AGND
DGND
V
SS
Electrochemical Sensor Operation
The MAX1407/MAX1408/MAX1409/MAX1414 family inter-
face with electrochemical sensors. The 10-bit DACs with
the force/sense buffers have the flexibility to connect to
many different types of sensors. Figure 23 shows how to
interface with a two electrode potentiostat. A single DAC
is required to set the bias across the sensor relative to
ground and an external precision resistor completes the
transimpedance amplifier configuration to convert the
current generated by the sensor to a voltage to be mea-
sured by the ADC. The induced error from this source is
negligible due to Fꢀ1’s extremely low input bias current.
Internally, the ADC can differentially measure directly
*ONE Li+ COIN OR TWO BUTTON CELLS
Figure 22. Power-Supply Circuit Using Direct Battery Connection
2Nꢀ
1024
V
= V
−1
OUT
REF
where Nꢀ is the decimal value of the DAC’s binary
input code. Table 12 shows digital codes (offset binary)
and corresponding output voltages for Figure 18
assuming R1 = R2.
across the external transimpedance resistor, R , eliminat-
F
ing any errors due to voltages drifting over time, tempera-
ture, or supply voltage. Figure 24 shows a two electrode
potentiostat application that is driven at the working elec-
trode and measured at the counter electrode. With this
application, the DAC connected to the working electrode
is configured in unity gain and the DAC connected to the
Power Supplies
Power to the MAX1407/MAX1408/MAX1409/MAX1414
family can be supplied in a number of ways. Figures 19,
42 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
MAX1407
MAX1409
MAX1414
MAX1407
MAX1414
REF
OUT1
FB1
10-BIT DAC
REF
10-BIT DAC
OUT1
FB1
F
I
F
R
IN0
AUX.
VOLTAGE
INPUTS
IN1
IN2
IN3
F
I
F
R
WE
IN0
SENSOR
AUX.
VOLTAGE
INPUTS
WE
IN1
IN2
IN3
CE
REF
SENSOR
OUT2
FB2
CE
10-BIT DAC
REF
BAND
GAP
BUF
REF
BAND
GAP
BUF
4.7µF
4.7µF
ALL I/O AVAILABLE AS INPUTS TO ADC AND COMPARATOR.
MAX1409 HAS IN0, OUT1, FB1, AND REF ONLY.
ALL I/O AVAILABLE AS INPUTS TO ADC AND COMPARATOR.
Figure 23. Self-Biased Two Electrode Potentiostat Application
Figure 24. Driven Two Electrode Potentiostat Application
V
BAT
MAX1407
MAX1414
LED
MAX1407
MAX1414
REF
REF
OUT1
FB1
OUT1
10-BIT DAC
10-BIT DAC
QB
F
I
F
R
IN0
IN1
IN2
IN3
AUX.
VOLTAGE
INPUTS
FB1
FB2
B
R
WE
RE
CE
REF
OUT2
REF
10-BIT DAC
OUT2
SENSOR
10-BIT DAC
F
I
F
R
FB2
REF
IN0
AUX.
VOLTAGE
INPUTS
REF
BAND
GAP
IN1
IN2
IN3
BAND
GAP
PHOTO-
DIODE
BUF
BUF
4.7µF
4.7µF
ALL I/O AVAILABLE AS INPUTS TO ADC AND COMPARATOR.
ALL I/O AVAILABLE AS INPUTS TO ADC AND COMPARATOR.
Figure 25. Driven Three Electrode Potentiostat Application
Figure 26. Optical Reflectometry Application
counter electrode is configured as a transimpedance
amplifier to measure the current. Figure 25 shows a three
electrode potentiostat application that is driven at all the
electrodes and measured at the working electrode. With
this application, the DAC connected to the working elec-
trode sets the bias voltage relative to the reference elec-
trode and also measures the current that the sensor pro-
duces. The DAC connected to the reference and counter
electrodes takes advantage of the force/sense outputs to
______________________________________________________________________________________ 43
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
REF
R
L
REF
IN0
8:1
MUX
16b ADC
DRDY
INT
R
T
INTERRUPT
GENERATOR
CMP
8:1
MUX
AGND
WAKE-UP
MAX1407
MAX1408
MAX1409
MAX1414
BAND
GAP
REF
4.7µF
BUF
DRDY NOT AVAILABLE ON THE MAX1409
Figure 27. Thermistor Application Circuit
CJC
REF
THERMOCOUPLE
JUNCTION
IN0
R
R
8:1
MUX
16b ADC
IN1
C
C
DRDY
INT
INTERRUPT
GENERATOR
CMP
AGND
IN2
8:1
MUX
WAKE-UP
REF
BAND
GAP
MAX1407
MAX1408
MAX1414
BUF
4.7µF
Figure 28. Thermocouple Application Circuit
maintain the reference electrode bias voltage by virtue of
the feedback path through the sensor.
photodiode. Set the LED bias current externally if the
MAX1409 is used in this application.
Optical Reflectometry
Figure 26 illustrates the MAX1407/MAX1414 in an optical
reflectometry application. The first DAC is used with an
external transistor to set the bias current through the LED
and the second DAC is used to properly bias and convert
the photodiode current to a voltage measured by the
ADC. The low input bias current into the DAC feedback
pin (FB2) allows the measurement of very small currents.
The DACs provide the flexibility in setting an accurate
and stable LED current and adjusting the bias across the
Thermistor Measurement
A thermistor connected in a half-bridge configuration
as shown in Figure 27 is used to measure temperatures
very accurately with the MAX1407/MAX1408/
MAX1409/MAX1414. The internal reference drives the
thermistor as well as the ADC, so the reference varia-
tion is cancelled out when calculating the temperature.
The only significant errors are from the R resistor and
L
the thermistor itself. The ADC performs a unipolar con-
version with the PGA set to a gain of 1V/V.
44 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
REF OR AV
DD
REF
IN0
8:1
MUX
R
R
A
B
16-BIT ADC
DRDY
INT
INTERRUPT
GENERATOR
CMP
IN1
R
R
8:1
MUX
D
C
WAKE-UP
MAX1407
MAX1408
MAX1414
BAND
GAP
REF
4.7µF
BUF
DRDY NOT AVAILABLE ON THE MAX1409
Figure 29. Strain-Gauge Application Circuit
MAX1408/MAX1409/MAX1414. In systems where multi-
ple devices require AGND to DGND connections, the
connection should still be made at only one point. Make
the star ground as close to the MAX1407/MAX1408/
MAX1409/MAX1414 as possible.
Thermocouple Measurement
Figure 28 shows a thermocouple connected to the dif-
ferential inputs of the MAX1407/MAX1408/MAX1409/
MAX1414. In this application, the internal buffers are
enabled to allow for the decoupling shown at the input.
The decoupling eliminates noise pickup from the ther-
mocouple. With the internal buffers enabled, the input
common-mode range is reduced so the IN2 input is
biased to the internal reference voltage at +1.25V. When
the buffer is enabled, the IN1 input is limited to +1.4V.
Avoid running digital lines under the device because
these may couple noise onto the die. Run the analog
ground plane under the MAX1407/MAX1408/
MAX1409/MAX1414 to minimize coupling of digital
noise. Make the power-supply lines to the MAX1407/
MAX1408/MAX1409/MAX1414 as wide as possible to
provide low-impedance paths and reduce the effects of
glitches on the power-supply line.
Strain-Gauge Operation
Connect the differential inputs of the MAX1407/
MAX1408/MAX1409/MAX1414 to the bridge network of
the strain gauge as shown in Figure 29. When connect-
ed to the internal reference, the ADC can resolve below
10µV at the differential inputs. The internal buffers pro-
vide a high input impedance as long as the signal is
within the reduced common-mode range of the input
buffers. The bridge may also be driven directly from the
supply voltage. In this configuration, the ADC first mea-
sures the supply voltage and then the differential input
in sequence, and then calculates the ratio.
Shield fast switching signals such as clocks with digital
ground to avoid radiating noise to other sections of the
board. Avoid running clock signals near the analog
inputs. Avoid crossover of digital and analog signals.
Traces on opposite sides of the board should run at
right angles to each other. This will reduce the effects
of feedthrough on the board. A microstrip technique is
best, but is not always possible with double-sided
boards. In this technique, the component side of the
board is dedicated to ground planes while signals are
placed on the solder side.
Grounding and Layout
For best performance, use printed circuit boards with
separate analog and digital ground planes. The device
perfomance will be highly degraded when using wire-
wrap boards.
Good coupling is important when using high-resolution
ADCs. Decouple all analog supplies with 1µF capaci-
tors in parallel with 0.1µF HF ceramic capacitors to
AGND. Place these components as close to the device
as possible to achieve the best decoupling.
Design the printed circuit board so that the analog and
digital sections are separated and confined to different
areas of the board. Join the digital and analog ground
planes at one point. If the MAX1407/MAX1408/
MAX1409/MAX1414 is the only device requiring an
AGND to DGND connection, then the ground planes
should be connected at the AGND pin of the MAX1407/
Crystal Layout
Since it is possible for noise to be coupled onto the
crystal pins, care must be taken when placing the
external crystal on a PC board layout. It is very impor-
tant to follow a few basic layout guidelines concerning
______________________________________________________________________________________ 45
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
the placement of the crystal on the PC board layout to
insure that extra clock “ticks” do not couple onto the
crystal pins.
to CLKIN or CLKOUT.
5) It may also be helpful to place a local ground plane
on the PC board layer immediately below the crystal
guard ring. This helps to isolate the crystal from
noise coupling from signals on other PC board lay-
ers. Note: The ground plane needs to be in the
vicinity of the crystal only and not on the entire
board.
1) It is important to place the crystal as close as possi-
ble to the CLKIN and CLKOUT pins. Keeping the
trace lengths between the crystal and pins as small
as possible reduces the probability of noise cou-
pling by reducing the length of the “antennae”.
Keeping the trace lengths small also decreases the
amount of stray capacitance.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function (with offset and gain error
removed) from a straight line. This straight line can be
either a best straight-line fit or a line drawn between the
endpoints of the transfer function, once offset and gain
errors have been nullified. The static linearity parame-
ters for the MAX1407/MAX1408/MAX1409/MAX1414 are
measured using the endpoint method.
2) Keep the crystal bond pads and trace width to the
CLKIN and CLKOUT pins as small as possible. The
larger these bond pads and traces are, the more
likely it is that noise can couple from adjacent signals.
3) If possible, place a guard ring (connect to ground)
around the crystal. This helps to isolate the crystal
from noise coupled from adjacent signals.
4) Insure that no signals on other PC board layers run
directly below the crystal or below the traces to the
CLKIN and CLKOUT pins. The more the crystal is
isolated from other signals on the board, the less
likely it is that noise will be coupled into the crystal.
There should be a minimum of 0.200 inches
between any digital signal and any trace connected
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSꢀ. A
DNL error specification of less than 1LSꢀ guarantees
no missing codes and a monotonic transfer function.
Pin Configurations (continued)
TOP VIEW
FB1
OUT1
IN0
1
2
20 DV
DD
IN7
DO
1
2
28 IN5
27 IN3
19 DGND
18
3
CS
IN6
3
26 DV
DD
REF
4
17 SCLK
16 DIN
IN4
4
25 DGND
24
MAX1409
AGND
5
IN0
5
CS
AV
DD
6
15 DOUT
REF
AGND
6
23 SCLK
22 DIN
CPLL
7
14
INT
7
MAX1408
8
13 CLKIN
12 CLKOUT
11 FOUT
AV
8
21 DOUT
20 INT
WU1
WU2
DD
9
CPLL
WU1
WU2
9
RESET
10
10
11
19 CLKIN
18 CLKOUT
17 FOUT
RESET 12
IN1 13
16
DRDY
IN2 14
15 SHDN
46 ______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Circuit
LX
OUT
RST
DC-DC
CONVERTER
SHDN
BATT
CPLL
AV
DV
V
DD
DD
DD
GND
SHDN
RESET
CLKIN
RESET
CLKIN
µP/µC
IN0
REF
V
BAT
CLKOUT
FOUT
IN1
CS
SCLK
DIN
OUTPUT
SCK
MAX1407
MAX1414
MOSI
MISO
DOUT
OUT1
INPUT
INPUT
INT
DRDY
FB1
FB2
WU1
WU2
I/O
I/O
WE
RE
CE
SENSOR
OUT2
AGND
DGND
V
SS
______________________________________________________________________________________ 47
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
48 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX140CMH+
ADC, Dual-Slope, 24-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PQFP44, MQFP-44
MAXIM
MAX140CMH+T
ADC, Dual-Slope, 24-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PQFP44, MQFP-44
MAXIM
MAX140CPL+
ADC, Dual-Slope, 24-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDIP40, PLASTIC, DIP-40
MAXIM
©2020 ICPDF网 联系我们和版权申明