MAX1421_V01 [MAXIM]
12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference;
| 型号： | MAX1421_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference |
| 文件： | 总17页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1900; Rev 1; 5/06
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
General Description
Features
The MAX1421 is a 3.3V, 12-bit analog-to-digital con-
verter (ADC), featuring a fully-differential input,
pipelined, 12-stage ADC architecture with wideband
track-and-hold (T/H) and digital error correction incor-
porating a fully-differential signal path. The MAX1421 is
optimized for low-power, high-dynamic performance
applications in imaging and digital communications.
The converter operates from a single 3.3V supply, con-
suming only 188mW while delivering a typical signal-to-
noise ratio (SNR) of 66dB at an input frequency of
15MHz and a sampling frequency of 40Msps. The fully-
differential input stage has a small signal -3dB band-
width of 400MHz and may be operated with
single-ended inputs.
♦ Single 3.3V Power Supply
♦ 67dB SNR at f = 5MHz
IN
♦ 66dB SNR at f = 15MHz
IN
♦ Internal, 2.048V Precision Bandgap Reference
♦ Differential, Wideband Input T/H Amplifier
♦ Power-Down Modes
180mW (Reference Shutdown Mode)
10µW (Shutdown Mode)
♦ Space-Saving 48-Pin TQFP Package
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure accommodates an internal or externally
applied buffered or unbuffered reference for applica-
tions requiring increased accuracy or a different input
voltage range.
Ordering Information
PIN-
PKG
PART*
TEMP RANGE
PACKAGE CODE
MAX1421CCM
MAX1421ECM
MAX1421ECM+
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
48 TQFP
48 TQFP
48 TQFP
C48-2
C48-2
C48-2
In addition to low operating power, the MAX1421 fea-
tures two power-down modes, a reference power-down
and a shutdown mode. In reference power-down, the
internal bandgap reference is deactivated, resulting in
a typical 2mA supply current reduction. For idle peri-
ods, a full shutdown mode is available to maximize
power savings.
+Denotes lead-free package.
Pin Configuration
The MAX1421 provides parallel, offset binary, CMOS-
compatible three-state outputs.
The MAX1421 is available in a 7mm x 7mm, 48-pin
TQFP package, and is specified over the commercial
(0°C to +70°C) and the extended industrial (-40°C to
+85°C) temperature ranges.
AGND
1
2
36 D9
35 D8
34 D7
33 D6
Pin-compatible higher- and lower-speed versions of the
MAX1421 are also available. Please refer to the
MAX1420 data sheet for a frequency of 60Msps and
the MAX1422 data sheet for a frequency of 20Msps.
AV
AV
DD
DD
3
AGND
AGND
INP
4
5
32 DV
31 DV
DD
DD
6
MAX1421
________________________Applications
INN
7
30 DGND
29 DGND
AGND
AGND
8
Medical Ultrasound Imaging
CCD Pixel Processing
Data Acquisition
D5
D4
D3
D2
9
28
27
26
25
AV
DD
10
11
12
AV
DD
AGND
Radar
IF and Baseband Digitization
48-TQFP
Functional Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
ABSOLUTE MAXIMUM RATINGS
AV , DV
to AGND..............................................-0.3V to +4V
to DGND..............................................-0.3V to +4V
Maximum Junction Temperature .....................................+150°C
Operating Temperature Ranges
DD
DD
DD
DV , AV
DD
MAX1421CCM ...................................................0°C to +70°C
MAX1421ECM ................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Continuous Power Dissipation (T = +70°C)
A
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
f
= V
= 3.3V, AGND = DGND = 0, V =
IN
1.024V, differential input voltage at -0.5dB FS, internal reference,
AVDD
DVDD
= 40MHz (50% duty cycle), digital output load C ≈ 10pF, T ≥ +25°C guaranteed by production test, T < +25°C guarnateed
A
A
CLK
L
A
by design and characterization. Typical values are at T = +25°C.)
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
-1
TYP
MAX
+1
UNITS
Resolution
RES
DNL
12
Bits
T
A
T
A
T
A
= +25°C, no missing codes
Differential Nonlinearity
LSB
= T
to T
0.5
2
MIN
MIN
MAX
MAX
Integral Nonlinearity
Midscale Offset
INL
= T
to T
LSB
MSO
-3
.75
+3
%FSR
Midscale Offset Temperature
Coefficient
-4
✕
MSOTC
GE
3
10
%/°C
%FSR
%/°C
Internal reference (Note 1)
-5
-5
+0.1
3
+5
+5
External reference applied to REFIN (Note 2)
Gain Error
External reference applied to REFP, CML,
and REFN (Note 3)
-1.5
0.5
+1.5
Gain-Error Temperature
Coefficient
External reference applied to REFP, CML,
and REFN (Note 3)
-6
✕
GETC
15 10
DYNAMIC PERFORMANCE (f
= 40MHz, 4096-point FFT)
CLK
f
f
f
f
f
f
f
f
f
f
= 5MHz
67
66
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Signal-to-Noise Ratio
SNR
SFDR
THD
dB
dBc
dBc
dB
= 15MHz, T = +25°C
62
64
A
= 5MHz
73
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-To-Noise Plus Distortion
Effective Number of Bits
= 15MHz, T = +25°C
70
A
= 5MHz
-74
-69
66
= 15MHz, T = +25°C
-62
A
= 5MHz
SINAD
ENOB
= 15MHz, T = +25°C
60
60
63.5
10.7
10.3
A
= 5MHz
Bits
dBc
= 15MHz, T = +25°C
A
Two-Tone Intermodulation
Distortion
f
= 11.569MHz, f
= 13.445MHz
IN1
IN2
IMD
-80
TT
(Note 4)
2
_______________________________________________________________________________________
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
f
= V
= 3.3V, AGND = DGND = 0, V =
IN
1.024V, differential input voltage at -0.5dB FS, internal reference,
AVDD
CLK
DVDD
= 40MHz (50% duty cycle), digital output load C ≈ 10pF, T ≥ +25°C guaranteed by production test, T < +25°C guarnateed
A
A
L
A
by design and characterization. Typical values are at T = +25°C.)
PARAMETER
Differential Gain
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DG
DP
1
%
Differential Phase
0.25
degrees
ANALOG INPUTS (INP, INN, CML)
Input Resistance
R
C
Either input to ground
Either input to ground
32.5
4
kΩ
IN
Input Capacitance
pF
IN
Common-Mode Input Level
(Note 5)
V
AVDD
× 0.5
V
V
V
CML
Common-Mode Input Voltage
Range (Note 5)
V
CML
5%
V
CMVR
Differential Input Range
Small-Signal Bandwidth
Large-Signal Bandwidth
V
V
- V
(Note 6)
V
DIFF
V
IN
INP
INN
BW
(Note 7)
(Note 7)
400
MHz
MHz
-3dB
FPBW
150
-3dB
Clock
Cycle
✕
Overvoltage Recovery
OVR
1.5 FS input
1
INTERNAL REFERENCE (REFIN bypassed with 0.22µF in parallel with 1nF)
Common-Mode Reference Input
Voltage
V
AVDD
V
At CML
V
V
CML
REFP
REFN
✕
0.5
Positive Reference Voltage
Range
V
CML
+ 0.512
V
V
At REFP
Negative Reference Voltage
Range
V
CML
- 0.512
At REFN
(Note 6)
V
V
Differential Reference Voltage
Range
1.024
5%
V
DIFF
Differential Reference
Temperature Coefficient
REFTC
100
ppm/°C
EXTERNAL REFERENCE (V
REFIN Input Resistance
REFIN Input Capacitance
= 2.048V)
REFIN
R
(Note 8)
5
kΩ
IN
IN
C
10
pF
2.048
10%
REFIN Reference Input Voltage
V
V
V
REFIN
✕
✕
0.92
V
1.08
V
V
REFIN /
2
Differential Reference Voltage
V
(Note 6)
DIFF
REFIN /
2
REFIN /
2
EXTERNAL REFERENCE (V
= AGND, reference voltage applied to REFP, REFN, and CML)
REFIN
REFP, REFN, CML Input Current
I
-200
+200
µA
pF
IN
REFP, REFN, CML Input
Capacitance
C
15
IN
_______________________________________________________________________________________
3
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
f
= V
= 3.3V, AGND = DGND = 0, V =
IN
1.024V, differential input voltage at -0.5dB FS, internal reference,
AVDD
CLK
DVDD
= 40MHz (50% duty cycle), digital output load C ≈ 10pF, T ≥ +25°C guaranteed by production test, T < +25°C guarnateed
A
A
L
A
by design and characterization. Typical values are at T = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Reference Voltage
Range
1.024
10%
V
V
(Note 6)
V
DIFF
CML
1.65
10%
CML Input Voltage Range
REFP Input Voltage Range
REFN Input Voltage Range
V
V
V
V
CML
DIFF
+
/ 2
V
REFP
V
REFN
V
V
-
CML
V
/ 2
DIFF
DIGITAL INPUTS (CLK, CLK, OE, PD)
✕
0.7
Input Logic-High
Input Logic-Low
V
V
V
IH
V
DVDD
✕
0.3
V
V
IL
DVDD
CLK, CLK
PD
330
Input Current
µA
pF
-20
-20
+20
+20
OE
Input Capacitance
10
DIGITAL OUTPUTS (D0–D11)
V
DVDD
- 0.5
Output Logic-High
V
I
I
= 200µA
= -200µA
V
V
OH
OH
DVDD
Output Logic-Low
V
0
0.5
V
OL
OL
Three-State Leakage
Three-State Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
-10
+10
µA
pF
2
V
V
3.135
2.7
3.3
3.3
52
3.465
3.6
V
V
AVDD
DVDD
AVDD
I
65
mA
Analog Supply Current with
Internal Reference in Shutdown
REFIN = AGND
50
63
20
mA
Analog Shutdown Current
Digital Supply Current
Digital Shutdown Current
Power Dissipation
PD = DV
µA
mA
DD
I
5.5
DVDD
PD = DV
20
µA
DD
P
Analog power
(Note 9)
188
1
214
mW
mV/V
DISS
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
Clock Frequency
PSRR
f
Figure 5
0.1
40.0
MHz
ns
CLK
Clock High
t
Figure 5, clock period 25ns
Figure 5, clock period 25ns
12.5
12.5
CH
Clock Low
t
ns
CL
4
_______________________________________________________________________________________
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
f
= V
= 3.3V, AGND = DGND = 0, V =
IN
1.024V, differential input voltage at -0.5dB FS, internal reference,
AVDD
CLK
DVDD
= 40MHz (50% duty cycle), digital output load C ≈ 10pF, T ≥ +25°C guaranteed by production test, T < +25°C guarnateed
A
A
L
A
by design and characterization. Typical values are at T = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
CLK
Pipeline Delay (Latency)
Figure 5
7
cycles
Aperture Delay
Aperture Jitter
t
Figure 9
Figure 9
Figure 5
Figure 4
Figure 4
2
2
ns
AD
t
ps
AJ
Data Output Delay
Bus Enable Time
Bus Disable Time
t
5
10
5
14
ns
OD
t
ns
BE
t
5
ns
BD
Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
Note 2: External 2.048V reference applied to REFIN.
Note 3: Internal reference disabled. V
= 0, V
= 2.162V, V
= 1.65V, and V
= 1.138V.
REFIN
REFP
CML
REFN
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1421.
Note 6: V = V - V
.
REFN
DIFF
REFP
Note 7: Input bandwidth is measured at a 3dB level.
Note 8: V is internally biased to 2.048V through a 10kΩ resistor.
REFIN
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a 5% change in V
using the internal reference.
AVDD
Typical Operating Characteristics
(V
AVDD
= V
= 3.3V, AGND = DGND = 0, V
=
1.024V, differential input voltage, f
= 40MHz (50% duty cycle), digital output
DVDD
IN
CLK
load C = 10pF, T = T
to T unless otherwise noted. Typical values are at T = +25°C.)
MAX, A
L
A
MIN
FFT PLOT, 4096-POINT RECORD,
DIFFERENTIAL INPUT
FFT PLOT, 4096-POINT RECORD,
DIFFERENTIAL INPUT
FFT PLOT, 4096-POINT RECORD,
DIFFERENTIAL INPUT
0
-20
0
-20
0
-20
f
A
= 7.54MHz
f
A
= 38.54MHz
= -0.49dB FS
IN
f
A
= 19.90MHz
IN
IN
IN
= -0.45dB FS
IN
= -0.50dB FS
IN
f
IN
-40
-40
-40
HD2
HD3
HD2
HD3
-60
-60
-60
HD3
HD2
-80
-80
-80
-100
-120
-100
-120
-100
-120
0
5
10
15
20
0
5
10
15
20
0
5
10
15
20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
Typical Operating Characteristics (continued)
(V
AVDD
= V
= 3.3V, AGND = DGND = 0, V
=
1.024V, differential input voltage, f
= 40MHz (50% duty cycle), digital output
DVDD
IN
CLK
load C = 10pF, T = T
to T unless otherwise noted. Typical values are at T = +25°C.)
MAX, A
L
A
MIN
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
TWO-TONE IMD, 8192-POINT RECORD,
DIFFERENTIAL INPUT
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
85
77
69
61
53
45
0
70
66
62
58
54
50
f
f
= 11.51MHz
= 13.51MHz
IN1
IN2
-20
-40
A
= A = -6.5dB FS
IN2
IN1
f
f
IN2
IN1
-60
IM3
IM2
-80
-100
-120
0
5
10 15 20 25 30 35 40 45 50 55
ANALOG INPUT FREQUENCY (MHz)
0
2
4
6
8
10 12 14 16 18 20
0
5
10 15 20 25 30 35 40 45 50 55
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
vs. ANALOG INPUT POWER (f = 15MHz)
IN
-50
-56
-62
-68
-74
-80
70
66
62
58
54
50
80
70
60
50
40
30
20
0
5
10 15 20 25 30 35 40 45 50 55
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 55
ANALOG INPUT FREQUENCY (MHz)
-60
-50
-40
-30
-20
-10
0
ANALOG INPUT POWER (dBFS)
SIGNAL-TO-NOISE RATIO
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWER (f = 15MHz)
vs. ANALOG INPUT POWER (f = 15MHz)
vs. ANALOG INPUT POWER (f = 15MHz)
IN
IN
IN
80
70
60
50
40
30
20
10
0
-30
-40
-50
-60
-70
-80
80
70
60
50
40
30
20
10
0
-60
-50
-40
-30
-20
-10
0
-60
-50
-40
-30
-20
-10
0
-60
-50
-40
-30
-20
-10
0
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
6
_______________________________________________________________________________________
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
Typical Operating Characteristics (continued)
(V
AVDD
= V
= 3.3V, AGND = DGND = 0, V
=
1.024V, differential input voltage, f
= 40MHz (50% duty cycle), digital output
DVDD
IN
CLK
load C = 10pF, T = T
to T unless otherwise noted. Typical values are at T = +25°C.)
MAX, A
L
A
MIN
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
84
80
76
72
68
64
-70
-72
-74
-76
-78
-80
70
68
66
64
62
60
f
IN
= 5.52MHz
f = 5.52MHz
IN
f
IN
= 5.52MHz
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
vs. DIGITAL OUTPUT CODE
2.0
1.5
1.0
0.5
0.500
0.375
0.250
0.125
70
68
66
64
62
60
f
IN
= 5.52MHz
0
0
-0.5
-1.0
-1.5
-0.125
-0.250
-0.375
-0.500
-2.0
1024
2048
3072
4096
0
1024
2048
3072
4096
0
-40
-15
10
35
60
85
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
TEMPERATURE (°C)
GAIN ERROR vs. TEMPERATURE, EXTERNAL
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
REFERENCE (V
= 2.048V)
REFIN
0.50
0.25
0
70
60
50
40
30
12
10
8
C ≈ 10pF
L
-0.25
-0.50
6
4
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
________________________________________________________________________________________
7
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
Typical Operating Characteristics (continued)
(V
AVDD
= V
= 3.3V, AGND = DGND = 0, V
=
1.024V, differential input voltage, f
= 40MHz (50% duty cycle), digital output
DVDD
IN
CLK
load C = 10pF, T = T
to T unless otherwise noted. Typical values are at T = +25°C.)
MAX, A
L
A
MIN
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
SNR/SINAD, -THD/SFDR
vs. CLOCK FREQUENCY
2.0750
2.0625
2.0500
2.0375
2.0250
80
-THD
SFDR
75
70
65
SNR
60
55
50
45
SINAD
f
= 5MHz
35
IN
40
3.1
3.2
3.3
(V)
3.4
3.5
10
15
20
25
30
40
V
CLOCK FREQUENCY (MHz)
DD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OUTPUT NOISE HISTOGRAM (DC-INPUT)
50,000
45,000
40,000
2.10
2.08
2.06
2.04
2.02
2.00
43707
35,000
30,000
25,000
20,000
15,000
10,000
5000
10824
N+1
10709
N-1
179
N-2
116
N+2
1
0
0
N-3
N
N+3
-40
-15
10
35
60
85
DIGITAL OUTPUT NOISE
TEMPERATURE (°C)
8
_______________________________________________________________________________________
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
Pin Description
PIN
NAME
FUNCTION
1, 4, 5, 8,
9, 12, 13,
16, 19, 41,
48
AGND
Analog Ground. Connect all return paths for analog signals to AGND.
2, 3, 10,
11, 14, 15,
20, 42, 47
Analog Supply Voltage. For optimum performance bypass each pin to the closest AGND with a
parallel combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor
AV
DD
combination between AV
and AGND.
DD
6
INP
Positive Analog Signal Input
7
INN
Negative Analog Signal Input
17
CLK
Clock Frequency Input. Clock frequency input ranges from 100kHz to 40MHz.
Complementary Clock Frequency Input. This input is used for differential clock inputs. If the ADC is
driven with a single-ended clock, bypass CLK with a 0.1µF capacitor to AGND.
18
CLK
Digital Supply Voltage. For optimum performance bypass each pin to the closest DGND with a
parallel combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor
21, 31, 32,
DV
DD
combination between DV
and DGND.
DD
22, 29, 30
23–28
DGND
D0–D5
D6–D11
Digital Ground
Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB.
Digital Data Outputs. D6 through D11, where D11 represents the MSB.
33–38
Output Enable Input. A logic “1” on OE places the outputs D0–D11 into a high-impedance state. A
logic “0” allows for the data bits to be read from the outputs.
39
40
OE
PD
Shutdown Input. A logic “1” on PD places the ADC into shutdown mode.
External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To
disable the internal reference, connect REFIN to AGND.
43
REFIN
Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF.
44
45
46
REFP
REFN
CML
With the internal reference disabled (REFIN = AGND), REFP should be biased to V
+ V
/ 2.
CML
DIFF
Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF.
With the internal reference disabled (REFIN = AGND), REFN should be biased to V - V / 2.
CML
DIFF
Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel
with 1nF. With the internal reference disabled (REFIN = AGND).
_______________________________________________________________________________________
9
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
(OTA) input, and open simultaneously with S1, sam-
Detailed Description
pling the input waveform. The resulting differential volt-
age is held on capacitors C2a and C2b. Switches S4a
and S4b are then opened before switches S3a and S3b,
connecting capacitors C1a and C1b to the output of the
amplifier, and switch S4c is closed. The OTA is used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. This value is then pre-
sented to the first-stage quantizer and isolates the
pipeline from the fast-changing input. The wide-input
bandwidth, T/H amplifier allows the MAX1421 to track
and sample/hold analog inputs of high frequencies
beyond Nyquist. The analog inputs INP and INN can be
driven either differentially or single-ended. Match the
impedance of INP and INN and set the common-mode
The MAX1421 uses a 12-stage, fully-differential, pipe-
lined architecture (Figure 1) that allows for high-speed
conversion while minimizing power consumption. Each
sample moves through a pipeline stage every half-
clock-cycle. Including the delay through the output latch,
the latency is seven clock cycles.
A 2-bit (2-comparator) flash ADC converts the held-
input voltage into a digital code. The following digital-to-
analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held-input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage. This process is
repeated until the signal has been processed by all 12
stages. Each stage provides a 1-bit resolution. Digital
error correction compensates for ADC comparator off-
sets in each pipeline stage and ensures no missing
codes.
voltage to midsupply (AV
mance.
/ 2) for optimum perfor-
DD
Analog Input and Reference Configuration
The full-scale range of the MAX1421 is determined by
the internally generated voltage difference between
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input T/H circuit in both track-and-hold modes. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuit passes the input
signal to the two capacitors (C2a and C2b) through-
switches (S4a and S4b). Switches S2a and S2b set the
common mode for the transconductance amplifier
REFP (AV
REFIN
/ 2 + V
/ 4) and REFN (AV
/ 2 -
DD
DD
REFIN
V
/ 4). The MAX1421’s full-scale range is
adjustable through REFIN, which provides a high input
impedance for this purpose. REFP, CML (AV
/ 2), and
DD
REFN are internally buffered low impedance outputs.
MDAC
INTERNAL
BIAS
CML
S5a
V
V
IN
OUT
x2
Σ
T/H
S2a
C1a
S3a
TO NEXT
STAGE
FLASH
ADC
DAC
S4a
S4b
2 BITS
OUT
OUT
C2a
C2b
S4c
S1
OTA
C1b
V
IN
STAGE 1
STAGE 2
STAGE 12
S3b
DIGITAL CORRECTION LOGIC
12
S2b
S5b
CML
INTERNAL
BIAS
D11–D0
Figure 1. Pipelined Architecture
Figure 2. Internal Track-and-Hold Circuit
10 ______________________________________________________________________________________
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
AV
DD
50Ω
AV
2
DD
CML
( )
R
0.22µF
50Ω
1nF
1nF
AV
DD
2
R
AV
DD
+ 1V
REFP
(
)
MAX4284
2
0.22µF
R
R
AV
DD
2
MAX1421
AV
4
DD
R
50Ω
AV
2
DD
REFN
+ 1V
(
)
MAX4284
R
0.22µF
1nF
R
R
AV
4
DD
REFIN
AGND
+1V
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
The MAX1421 provides three modes of reference oper-
ation:
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (< 2ns). In particu-
lar, sampling occurs on the rising edge of the clock sig-
nal, requiring this edge to have the lowest possible
jitter. Any significant aperture jitter limits the SNR per-
formance of the ADC according to the following rela-
tionship:
•
•
•
Internal reference mode
Buffered external reference mode
Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN are left floating. For stability purposes,
bypass REFIN, REFP, REFN, and CML with a capacitor
network of 0.22µF, in parallel with a 1nF capacitor to
AGND.
1
SNR = 20 × log
dB
10
2π × ƒ × t
IN
AJ
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
where f represents the analog input frequency and
IN
t
AJ
is the aperture jitter.
In unbuffered external reference mode, REFIN is con-
nected to AGND, which deactivates the on-chip buffers
of REFP, CML, and REFN. With their buffers shut down,
these nodes become high impedance and can be dri-
ven by external reference sources, as shown in Figure 3.
Clock jitter is especially critical for high input frequency
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log or digital signal lines.
The MAX1421 clock input operates with a voltage
threshold set to AV
/ 2. Clock inputs must meet the
CLK
Clock Inputs (CLK,
)
DD
specifications for high and low periods, as stated in the
The MAX1421’s CLK and CLK inputs accept both sin-
gle-ended and differential input operation, and accept
CMOS-compatible clock signals. If CLK is driven with a
Electrical Characteristics.
______________________________________________________________________________________ 11
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
OE
INP
ADC
D11–D0
INN
t
t
BD
BE
A
VDD
OUTPUT
DATA D11–D0
HIGH-Z
HIGH-Z
VALID DATA
10kΩ
10kΩ
10kΩ
CLK
Figure 5. Output Enable Timing
10kΩ
cycle latency between any particular sample and its
valid output data. The output coding is in offset binary
format (Table 1).
CLK
MAX1421
AGND
The capacitive load on the digital outputs D0 through
D11 should be kept as low as possible (≤ 10pF), to avoid
large digital currents that could feed back into the analog
portion of the MAX1421, thereby degrading its dynamic
performance. The use of digital buffers (e.g.,
74LVCH16244) on the digital outputs of the ADC can fur-
ther isolate the digital outputs from heavy capacitive
loads. To further improve the dynamic performance of
the MAX1421, add small-series resistors of 100Ω to the
digital output paths, close to the ADC. Figure 5 displays
the timing relationship between output enable and data
output.
Figure 4. Simplified Clock Input Circuit
Figure 4 shows a simplified model of the clock input cir-
cuit. This circuit consists of two 10kΩ resistors to bias
the common-mode level of each input. This circuit may
be used to AC-couple the system clock signal to the
MAX1421 clock input.
OE
Output Enable ( ), Power-Down (PD), and
Output Data (D0–D11)
With OE high, the digital outputs enter a high-imped-
ance state. If OE is held low with PD high, the outputs
are latched at the last value prior to the power-down. All
data outputs, D0 (LSB) through D11 (MSB), are
TTL/CMOS-logic compatible. There is a seven clock-
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1421
samples at the rising edge of CLK (falling edge of CLK)
and output data is valid seven clock cycles (latency)
later. Figure 6 also displays the relationship between
the input clock parameters and the valid output data.
Table 1. MAX1421 Output Code for
Differential Inputs
Applications Information
DIFFERENTIAL
INPUT VOLTAGE*
DIFFERENTIAL
INPUT
OFFSET
BINARY
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal ref-
erence provides an AV
/ 2 output voltage for level-
DD
+FULL SCALE -
1LSB
V
V
× 2047/2048
× 2046/2048
1111 1111 1111
1111 1111 1110
REF
REF
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associat-
+FULL SCALE -
2LSB
ed with high-speed op amps. Select the R
and C
IN
ISO
values to optimize the filter performance and to suit a
particular application. For the application in Figure 7, a
ISO
V
× 1/2048
0
+ 1 LSB
Bipolar Zero
- 1 LSB
1000 0000 0001
1000 0000 0000
0111 1111 1111
REF
R
of 50Ω is placed before the capacitive load to pre-
-V
× 1/2048
REF
vent ringing and oscillation. The 22pF C capacitor
IN
-FULL SCALE +
1 LSB
acts as a small bypassing capacitor.
-V
× 2046/2048
× 2047/2048
0000 0000 0001
0000 0000 0000
REF
Connecting C from INN to INP may further improve
IN
dynamic performance.
-V
-FULL SCALE
REF
*V
= V
- V
REFP REFN
REF
12 ______________________________________________________________________________________
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
7 CLOCK-CYCLE LATENCY
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
ANALOG INPUT
CLK
t
t
CH
DO
t
CL
CLK
N - 7
N - 6
N - 5
N - 4
N - 3
N - 2
N - 1
N
DATA OUTPUT
Figure 6. System and Output Timing Diagram
network of a 10µF bipolar capacitor in parallel with two
ceramic capacitors of 1nF and 0.1µF. Follow the same
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent solu-
tion to convert a single-ended signal to a fully differen-
tial signal, required by the MAX1421 for optimum
performance. Connecting the center tap of the trans-
rules to bypass the digital supply DV
to DGND.
DD
Multilayer boards with separate ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arrangement
to match the physical location of the analog ground
(AGND) and the digital output driver ground (DGND) on
the ADCs package. The two ground planes should be
joined at a single point so that the noisy digital ground
currents do not interfere with the analog ground plane.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground plane (e.g.,
downstream output buffer, DSP ground plane). Route
high-speed digital signal traces away from sensitive
analog traces and remove digital ground and power
planes from underneath digital outputs. Keep all signal
lines short and free of 90 degree turns.
former to CML provides an AV
/ 2 DC level shift to
DD
the input. Although a 1:1 transformer is shown, a 1:2 or
1:4 step-up transformer may be selected to reduce the
drive requirements.
In general, the MAX1421 provides better SFDR and
THD with fully differential input signals over single-
ended input signals, especially for very high input fre-
quencies. In differential input mode, even-order
harmonics are suppressed and each of the inputs
requires only half the signal swing compared to single-
ended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended applica-
tion, using a MAX4108 op amp. This configuration pro-
vides high-speed, high-bandwidth, low noise, and low
distortion to maintain the integrity of the input signal.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight-
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once off-
set and gain errors have been nullified. The static lin-
earity parameters for the MAX1421 are measured using
the best straight-line fit method.
Grounding, Bypassing, and
Board Layout
The MAX1421 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side of
the board as the ADC, using surface-mount devices for
minimum inductance. Bypass REFP, REFN, REFIN, and
CML with a parallel network of 0.22µF capacitors and
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step-width and the ideal value of 1LSB. A DNL
1nF to AGND. AV
should be bypassed with a similar
DD
______________________________________________________________________________________ 13
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
+5V
0.1µF
LOWPASS FILTER
INP
MAX4108
R
50Ω
0.1µF
ISO
300Ω
C
22pF
*
IN
0.1µF
-5V
MAX1421
600Ω
0.1µF
44pF*
300Ω
600Ω
CML
0.1µF
0.22µF
1nF
+5V
+5V
0.1µF
0.1µF
600Ω
INPUT
0.1µF
0.1µF
LOWPASS FILTER
MAX4108
300Ω
300Ω
INN
MAX4108
R
ISO
C
22pF
*
IN
50Ω
-5V
-5V
300Ω
300Ω
300Ω
*TWO C (22pF) CAPS MAY BE REPLACED BY
IN
ONE 44pF CAP, TO IMPROVE PERFORMANCE.
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
error specification of less than 1LSB guarantees no
missing codes.
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADCs reso-
lution (N-bits):
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (t ), which is the
AJ
SNR
= (6.02 ✕ N + 1.76)dB
(MAX)
sample-to-sample variation in the aperture delay.
In reality, there are other noise sources besides quanti-
zation noise e.g., thermal noise, reference noise, clock
jitter, etc. SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec-
tral components minus the fundamental, the first four
harmonics, and the DC offset.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 10).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
14 ______________________________________________________________________________________
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
25Ω
INP
*
22pF
MAX1421
0.1µF
*
1
2
3
6
5
4
44pF
T1
V
IN
N.C.
CML
0.22µF
1nF
MINICIRCUITS
T1–1T–KK81
25Ω
INN
*
22pF
*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN
INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.
Figure 8. Using a Transformer for AC-Coupling
R
50Ω
ISO
V
IN
0.1µF
INP
MAX4108
C
IN
22pF
100Ω
100Ω
1kΩ
MAX1421
CML
1nF
0.22µF
R
ISO
50Ω
INN
C
IN
22pF
Figure 9. Single-Ended AC-Coupled Input Signal
Signal-to-Noise Plus Distortion (SINAD)
CLK
CLK
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
ANALOG
INPUT
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
t
AD
t
AJ
SAMPLED
DATA (T/H)
SINAD-1.76
ENOB =
6.02
HOLD
TRACK
TRACK
T/H
Figure 10. Track-and-Hold Aperture Timing
______________________________________________________________________________________ 15
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
Total Harmonic Distortion (THD)
Functional Diagram
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
CLK
CLK
AV
DD
MAX1421
AGND
INTERFACE
2
V22 + V32 + V42 + V5
(
)
THD = 20 × log10
INP
INN
OUTPUT
DRIVERS
D11–D0
T/H
PIPELINE ADC
V
1
DV
DD
BANDGAP
REFERENCE
REF SYSTEM +
BIAS
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order har-
monics.
PD
DGND
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
REFIN REFP CML REFN
OE
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are at -6.5dB full scale and their envelope is at -0.5dB
full scale.
16 ______________________________________________________________________________________
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 32/48L LQFP, 7x7x1.4mm
1
21-0054
F
2
PACKAGE OUTLINE, 32/48L LQFP, 7x7x1.4mm
2
21-0054
F
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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