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MAX1429

更新时间：2025-07-12 02:28:29
品牌：MAXIM
描述：15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications

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MAX1429 概述

15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications 15位， 100MSPS ADC与基带应用-77.7dBFS本底噪声

MAX1429 数据手册

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19-3434; Rev 0; 10/04  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
Ge n e ra l De s c rip t io n  
Fe a t u re s  
The MAX1429 is a 5V, high-speed, high-performance  
analog-to-digital converter (ADC) featuring a fully differ-  
ential wideband track-and-hold (T/H) and a 15-bit con-  
verter core. The MAX1429 is optimized for multichannel,  
multimode receivers, which require the ADC to meet very  
stringent dynamic performance requirements. With a  
noise floor of -77.7dBFS, the MAX1429 allows for the  
design of receivers with superior sensitivity.  
♦ 100Msps Minimum Sampling Rate  
♦ -77.7dBFS Noise Floor  
♦ Excellent Dynamic Performance  
75.1dB SNR at fIN = 15MHz and AIN = -1dBFS  
90dBc/94dBc Single-Tone SFDR1/SFDR2 at  
fIN = 15MHz and AIN = -1dBFS  
-100dBc Multitone SFDR at fIN1 = 10MHz  
and fIN2 = 15MHz  
The MAX1429 achieves two-tone, spurious-free dynamic  
range (SFDR) of -100dBc for input tones of 10MHz and  
15MHz. Its excellent signal-to-noise ratio (SNR) of 75.1dB  
and single-tone SFDR performance (SFDR1/SFDR2) of  
♦ Less than 0.25ps Sampling Jitter  
♦ Fully Differential Analog Input Voltage Range of  
90dBc/94dBc at f = 15MHz and a sampling rate of  
IN  
2.2VP-P  
80Msps make this part ideal for high-performance digital  
receivers.  
♦ CMOS-Compatible Two’s-Complement Data Output  
♦ Separate Data Valid Clock and Overrange Outputs  
♦ Flexible-Input Clock Buffer  
The MAX1429 operates from an analog 5V and a digital  
3V supply, features a 2.2V  
full-scale input range,  
P-P  
and allows for a sampling speed of up to 100Msps. The  
input T/H operates with a -1dB full-power bandwidth of  
260MHz.  
♦ EV Kit Available for MAX1429  
(Order MAX1427EVKIT)  
The MAX1429 features parallel, CMOS-compatible out-  
puts in two’s-complement format. To enable the interface  
with a wide range of logic devices, this ADC provides a  
separate output driver power-supply range of 2.3V to  
3.5V. The MAX1429 is manufactured in an 8mm x 8mm,  
56-pin thin QFN package with exposed paddle (EP) for  
low thermal resistance, and is specified for the extended  
industrial (-40°C to +85°C) temperature range.  
Ord e rin g In fo rm a t io n  
PART  
TEMP RANGE  
PIN-PACKAGE  
Note that IF parts MAX1418, MAX1428, and MAX1430  
(s e e Pin-Comp a tib le Hig he r/Lowe r Sp e e d Ve rs ions  
Selection table) are recommended for applications that  
require high dynamic performance for input frequen-  
MAX1429ETN  
-40°C to +85°C  
56 Thin QFN-EP*  
*
EP = Exposed paddle.  
cies greater than f /3. The MAX1429 is optimized for  
CLK  
input frequencies of less than f  
/3.  
CLK  
P in -Co m p a t ib le Hig h e r/Lo w e r  
S p e e d Ve rs io n s S e le c t io n  
Ap p lic a t io n s  
Cellular Base-Station Transceiver Systems (BTS)  
SPEED GRADE  
(Msps)  
TARGET  
APPLICATION  
PART  
Wireless Local Loop (WLL)  
Single- and Multicarrier Receivers  
Multistandard Receivers  
MAX1418  
65  
65  
IF  
Baseband  
Baseband  
IF  
MAX1419  
MAX1427  
MAX1428  
MAX1429  
MAX1430  
80  
E911 Location Receivers  
80  
Power Amplifier Linearity Correction  
Antenna Array Processing  
100  
100  
Baseband  
IF  
Pin Configuration appears at end of data sheet.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
ABSOLUTE MAXIMUM RATINGS  
AV , DV , DRV to GND.................................. -0.3V to +6V  
Operating Temperature Range ...........................-40°C to +85°C  
CC  
CC  
CC  
INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV + 0.3V)  
Thermal Resistance θ ...................................................21°C/W  
CC  
A
J
D0–D14, DAV, DOR to GND..................-0.3V to (DRV + 0.3V)  
Junction Temperature ......................................................+150°C  
Storage Temperature Range .............................-60°C to +150°C  
Lead Temperature (soldering, 10s) .................................+300°C  
CC  
Continuous Power Dissipation (T = +70°C)  
A
56-Pin Thin QFN (derate 47.6mW/°C above +70°C)...3809.5mW  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
ELECTRICAL CHARACTERISTICS  
(AV = 5V, DV = DRV = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially  
CC  
CC  
CC  
with a 2V  
sinusoidal input signal, C = 5pF at digital outputs, f  
= 100MHz, T = T  
to T , unless otherwise noted. Typical  
MAX  
P-P  
L
CLK  
A
MIN  
values are at T = +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-  
A
acterization.)  
PARAMETER  
DC ACCURACY  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Resolution  
15  
Bits  
LSB  
LSB  
mV  
Integral Nonlinearity  
Differential Nonlinearity  
Offset Error  
INL  
f
= 15MHz  
±1.5  
±0.4  
IN  
DNL  
f
IN  
= 15MHz, no missing codes guaranteed  
-12  
-4  
+12  
+4  
Gain Error  
%FS  
ANALOG INPUT (INP, INN)  
Fully differential inputs drive,  
= V - V  
Differential Input Voltage Range  
Common-Mode Input Voltage  
Differential Input Resistance  
V
2.20  
3.33  
V
P-P  
DIFF  
V
DIFF  
INP  
INN  
V
Self-biased  
V
CM  
1
15%  
R
kΩ  
IN  
Differential Input Capacitance  
Full-Power Analog Bandwidth  
CONVERSION RATE  
C
1
pF  
IN  
FPBW  
-1dB rolloff for a full-scale input  
260  
MHz  
-1dB  
Maximum Clock Frequency  
Minimum Clock Frequency  
Aperture Jitter  
f
100  
MHz  
MHz  
CLK  
f
20  
CLK  
t
0.21  
ps  
RMS  
AJ  
CLOCK INPUT (CLKP, CLKN)  
Full-Scale Differential Input  
Voltage  
0.5 to  
3.0  
V
Fully differential input drive, V  
- V  
CLKN  
V
V
DIFFCLK  
CLKP  
Common-Mode Input Voltage  
Differential Input Resistance  
V
CM  
Self-biased  
2.4  
2
15%  
R
kΩ  
pF  
INCLK  
INCLK  
Differential Input Capacitance  
C
1
DYNAMIC CHARACTERISTICS  
Thermal + Quantization Noise  
Floor  
NF  
Analog input <-35dBFS  
-77.7  
dBFS  
2
_______________________________________________________________________________________  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
ELECTRICAL CHARACTERISTICS (continued)  
(AV = 5V, DV = DRV = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially  
CC  
CC  
CC  
with a 2V  
sinusoidal input signal, C = 5pF at digital outputs, f  
= 100MHz, T = T  
to T , unless otherwise noted. Typical  
MAX  
P-P  
L
CLK  
A
MIN  
values are at T = +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-  
A
acterization.)  
PARAMETER  
SYMBOL  
CONDITIONS  
= 5MHz at -1dBFS  
MIN  
TYP  
75.3  
75.1  
74.8  
75.0  
74.9  
71.1  
90.0  
90.0  
74.0  
96.0  
94.0  
92.0  
MAX  
UNITS  
f
IN  
Signal-to-Noise  
Ratio (Note 1)  
SNR  
f
IN  
= 15MHz at -1dBFS  
= 35MHz at -1dBFS  
= 5MHz at -1dBFS  
= 15MHz at -1dBFS  
= 35MHz at -1dBFS  
= 5MHz at -1dBFS  
= 15MHz at -1dBFS  
= 35MHz at -1dBFS  
= 5MHz at -1dBFS  
= 15MHz at -1dBFS  
= 35MHz at -1dBFS  
72.1  
dB  
f
IN  
f
IN  
Signal-to-Noise  
and Distortion  
(Note 1)  
SINAD  
SFDR1  
dB  
dBc  
dBc  
f
IN  
71.7  
84.0  
85.0  
f
IN  
f
IN  
Spurious-Free Dynamic Range  
(HD2 and HD3)  
f
IN  
(Note 1)  
f
IN  
f
IN  
Spurious-Free Dynamic Range  
(HD4 and Higher)  
(Note 1)  
SFDR2  
TTIMD  
f
IN  
f
IN  
Two-Tone Intermodulation  
Distortion  
f
f
= 10MHz at -7dBFS,  
= 15MHz at -7dBFS  
IN1  
-85  
dBc  
IN2  
Two-Tone Spurious-Free  
Dynamic Range  
f
= 10MHz at -10dBFS < f  
= 15MHz at -10dBFS < f < -100dBFS  
IN2  
< -100dBFS,  
IN1  
IN1  
SFDR  
-100  
dBFS  
TT  
f
IN2  
DIGITAL OUTPUTS (D0–D14, DAV, DOR)  
Digital Output-Voltage Low  
Digital Output-Voltage High  
TIMING CHARACTERISTICS (DV  
CLKP/CLKN Duty Cycle  
V
0.5  
V
V
OL  
DRV  
- 0.5  
CC  
V
OH  
= DRV  
= 2.5V)  
CC  
CC  
50  
5
Duty Cycle  
%
Effective Aperture Delay  
Output Data Delay  
Data Valid Delay  
t
230  
4.5  
6.5  
ps  
ns  
ns  
AD  
t
(Note 3)  
(Note 3)  
3.0  
5.3  
7.5  
8.7  
DAT  
DAV  
t
Clock  
cycles  
Pipeline Latency  
t
(Note 3)  
(Note 3)  
(Note 3)  
(Note 3)  
(Note 3)  
3
LATENCY  
CLKP Rising Edge to DATA Not  
Valid  
t
2.6  
3.4  
3.8  
5.2  
5.7  
8.6  
ns  
ns  
ns  
ns  
DNV  
DGV  
CLKP Rising Edge to DATA Valid  
(guaranteed)  
t
DATA Setup Time (Before DAV  
Rising Edge)  
t
t
t
+
CLKP  
- 0.5  
CLKP  
+ 1.3  
CLKP  
2.4  
t
SETUP  
DATA Hold Time (After DAV  
Rising Edge)  
t
-
t
-
t
-
CLKN  
3.6  
CLKN  
2.8  
CLKN  
2.0  
t
HOLD  
_______________________________________________________________________________________  
3
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
ELECTRICAL CHARACTERISTICS (continued)  
(AV = 5V, DV = DRV = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially  
CC  
CC  
CC  
with a 2V  
sinusoidal input signal, C = 5pF at digital outputs, f  
= 100MHz, T = T  
to T , unless otherwise noted. Typical  
MAX  
P-P  
L
CLK  
A
MIN  
values are at T = +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-  
A
acterization.)  
PARAMETER  
TIMING CHARACTERISTICS (DV  
CLKP/CLKN Duty Cycle  
Effective Aperture Delay  
Output Data Delay  
SYMBOL  
= DRV  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
= 3.3V)  
CC  
CC  
Duty Cycle  
50  
5
%
ps  
ns  
ns  
t
230  
4.1  
6.3  
AD  
t
(Note 3)  
(Note 3)  
2.8  
5.3  
6.5  
8.6  
DAT  
DAV  
Data Valid Delay  
t
Clock  
cycles  
Pipeline Latency  
t
3
LATENCY  
CLKP Rising Edge to DATA Not  
Valid  
t
(Note 3)  
(Note 3)  
(Note 3)  
(Note 3)  
2.5  
3.2  
3.4  
4.4  
5.2  
7.4  
ns  
ns  
ns  
ns  
DNV  
DGV  
CLKP Rising Edge to DATA Valid  
(guaranteed)  
t
DATA Setup Time (Before DAV  
Rising Edge)  
t
+
-
t
+
-
t
+
CLKP  
0.2  
CLKP  
1.7  
CLKP  
2.8  
t
SETUP  
DATA Hold Time (After DAV  
Rising Edge)  
t
t
t
-
CLKN  
3.5  
CLKN  
2.7  
CLKN  
2.0  
t
HOLD  
POWER REQUIREMENTS  
5
Analog Supply Voltage Range  
AV  
V
V
CC  
±3%  
2.3 to  
2.5  
Digital-Supply Voltage Range  
DV  
(Note 2)  
(Note 2)  
CC  
2.3 to  
2.5  
Output-Supply Voltage Range  
Analog Supply Current  
DRV  
V
CC  
I
390  
440  
44  
mA  
mA  
mW  
AVCC  
I
I
+
DVCC  
Digital + Output Supply Current  
Total Power Dissipation  
f
= 100MHz, C = 5pF  
38  
CLK L  
DRVCC  
PDISS  
2045  
Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of f  
= 100.007936MHz, an  
SAMPLE  
input frequency of f = f  
x (4915/32768) = 15.000580MHz, and a frequency bin size of 3052Hz. Close-in (f  
±
IN  
SAMPLE  
IN  
36.6kHz) and low-frequency (DC to 73.2kHz) bins are excluded from the spectrum analysis.  
Note 2: Apply the same voltage levels to DV and DRV  
.
CC  
CC  
Note 3: Guaranteed by design and characterization.  
4
_______________________________________________________________________________________  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s  
(AV = 5V, DV = DRV = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially  
CC  
CC  
CC  
with a 2V  
sinusoidal input signal, C = 5pF at digital outputs, f  
= 100MHz, T = +25°C. All AC data is based on a 32k-point  
CLK A  
P-P  
L
FFT record and under coherent sampling conditions.)  
FFT PLOT (32,768-POINT DATA RECORD,  
COHERENT SAMPLING)  
FFT PLOT (32,768-POINT DATA RECORD,  
COHERENT SAMPLING)  
FFT PLOT (32,768-POINT DATA RECORD,  
COHERENT SAMPLING)  
0
-20  
0
-20  
0
-20  
f
= 100.0997MHz  
= 15.0021MHz  
= -0.96dBFS  
f
f
IN  
= 100.0997MHz  
= 34.9973MHz  
A = -1.01dBFS  
IN  
CLK  
f
= 100.0997MHz  
= 10.0014MHz  
CLK  
CLK  
f
IN  
f
IN  
A
IN  
A
= -1.05dBFS  
IN  
SNR = 75.3dBc  
SNR = 75dBc  
SNR = 75.6dBc  
SINAD = 75.4dBc  
SFDR1 = 90dBc  
SFDR2 = 96.4dBc  
HD2 = -91dBFS  
HD3 = -95.5dBFS  
SINAD = 74.8dBc  
SFDR1 = 86.7dBc  
SFDR2 = 93.9dBc  
HD2 = -87.6dBFS  
HD3 = -90.2dBFS  
SINAD = 70.6dBc  
SFDR1 = 73dBc  
SFDR2 = 93.9dBc  
HD2 = -83.6dBFS  
HD3 = -74dBFS  
-40  
-40  
-40  
-60  
-60  
-60  
-80  
-80  
-80  
-100  
-120  
-100  
-120  
-100  
-120  
0
5
10 15 20 25 30 35 40 45 50  
ANALOG INPUT FREQUENCY (MHz)  
0
5
10 15 20 25 30 35 40 45 50  
ANALOG INPUT FREQUENCY (MHz)  
0
5
10 15 20 25 30 35 40 45 50  
ANALOG INPUT FREQUENCY (MHz)  
TWO-TONE IMD PLOT (32,768-POINT DATA  
RECORD, COHERENT SAMPLING)  
SNR vs. ANALOG INPUT FREQUENCY  
(f = 100.0997MHz, A = -1dBFS)  
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY  
(f = 100.0997MHz, A = -1dBFS)  
CLK IN  
CLK  
IN  
0
77  
76  
75  
74  
73  
72  
71  
70  
115  
105  
95  
f
= 100.0997MHz  
= 10.1022MHz  
IN1  
CLK  
f
IN1  
-20  
SFDR2  
A
= -7.09dBFS  
= 15.0021MHz  
A = -7dBFS  
IN2  
f
IN2  
f
f
IN2  
IN1  
-40  
IMD = -84.9dBc  
-60  
85  
f
- f  
IN2 IN1  
f
+ f  
IN1 IN2  
-80  
75  
SFDR1  
-100  
-120  
65  
55  
0
5
10 15 20 25 30 35 40 45 50  
ANALOG INPUT FREQUENCY (MHz)  
5
10 15 20 25 30 35 40 45 50  
(MHz)  
5
10 15 20 25 30 35 40 45 50  
(MHz)  
f
IN  
f
IN  
HD2/HD3 vs. ANALOG INPUT FREQUENCY  
SFDR1/SFDR2 vs. SAMPLING FREQUENCY  
(f = 15MHz, A = -1dBFS)  
SNR vs. SAMPLING FREQUENCY  
(f = 15MHz, A = -1dBFS)  
(f  
CLK  
= 100.0997MHz, A = -1dBFS)  
IN  
IN  
IN  
IN  
IN  
-65  
-70  
105  
100  
95  
78  
77  
76  
75  
74  
73  
72  
71  
70  
SFDR2  
HD3  
-75  
-80  
90  
-85  
85  
-90  
HD2  
80  
-95  
SFDR1  
75  
-100  
-105  
70  
5
10 15 20 25 30 35 40 45 50  
(MHz)  
20 30 40 50 60 70 80 90 100  
(MHz)  
20 30 40 50 60 70 80 90 100  
(MHz)  
f
IN  
f
f
CLK  
CLK  
_______________________________________________________________________________________  
5
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )  
(AV = 5V, DV = DRV = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially  
CC  
CC  
CC  
with a 2V  
sinusoidal input signal, C = 5pF at digital outputs, f  
= 100MHz, T = +25°C. All AC data is based on a 32k-point  
CLK A  
P-P  
L
FFT record and under coherent sampling conditions.)  
HD2/HD3 vs. SAMPLING FREQUENCY  
(f = 15MHz, A = -1dBFS)  
SFDR1/SFDR2 vs. ANALOG INOUT AMPLITUDE  
SNR vs. ANALOG INOUT AMPLITUDE  
= 100.0997MHz, f = 15.0021MHz)  
(f  
CLK  
= 100.0997MHz, f = 15.0021MHz)  
IN  
(f  
CLK  
IN  
IN  
IN  
-75  
-80  
120  
115  
110  
105  
100  
95  
79  
78  
77  
76  
75  
74  
73  
72  
71  
HD2  
SFDR2  
-85  
-90  
-95  
90  
HD3  
85  
SFDR1  
-100  
-105  
-110  
80  
75  
70  
20 30 40 50 60 70 80 90 100  
(MHz)  
-70 -60 -50 -40 -30 -20 -10  
ANALOG INPUT AMPLITUDE (dBFS)  
0
-70 -60 -50 -40 -30 -20 -10  
ANALOG INPUT AMPLITUDE (dBFS)  
0
f
CLK  
HD2/HD3 vs. ANALOG INPUT AMPLITUDE  
SNR vs. TEMPERATURE (f  
= 100.0997MHz,  
CLK  
(f  
CLK  
= 100.0997MHz, f = 15.0021MHz)  
IN  
f
= 15.0021MHz, A = -1dBFS)  
IN  
IN  
-70  
-80  
78  
77  
76  
75  
74  
73  
72  
71  
70  
HD3  
-90  
-100  
-110  
-120  
-130  
-140  
HD2  
-70 -60 -50 -40 -30 -20 -10  
ANALOG INPUT AMPLITUDE (dBFS)  
0
-40  
-15  
10  
35  
60  
85  
TEMPERATURE (°C)  
6
_______________________________________________________________________________________  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )  
(AV = 5V, DV = DRV = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially  
CC  
CC  
CC  
with a 2V  
sinusoidal input signal, C = 5pF at digital outputs, f = 100MHz, T = +25°C. All AC data is based on a 32k-point  
CLK A  
P-P  
L
FFT record and under coherent sampling conditions.)  
SINAD vs. TEMPERATURE (f = 100.0997MHz,  
SFDR1/SFDR2 vs. TEMPERATURE  
CLK  
f
IN  
= 15.0021MHz, A = -1dBFS)  
IN  
(f  
CLK  
105  
= 100.0997MHz, f = 15.0021MHz, A = -1dBFS)  
IN  
IN  
78  
77  
76  
75  
74  
73  
72  
71  
70  
100  
95  
90  
85  
80  
75  
70  
SFDR2  
SFDR1  
-40  
-15  
10  
35  
60  
85  
-40  
-15  
10  
35  
60  
85  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
HD2/HD3 vs. TEMPERATURE  
= 100.0997MHz, f = 15.0021MHz, A = -1dBFS)  
POWER DISSIPATION vs. TEMPERATURE  
= 100.0997MHz, f = 15.0021MHz, A = -1dBFS)  
(f  
CLK  
-70  
(f  
CLK  
2180  
IN  
IN  
IN  
IN  
-75  
-80  
2150  
2120  
2090  
2060  
2030  
2000  
HD3  
-85  
-90  
-95  
-100  
-105  
-110  
-115  
HD2  
10  
-40  
-15  
35  
60  
85  
-40  
-15  
10  
35  
60  
85  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
POWER DISSIPATION vs. SUPPLY VOLTAGE  
= 100.0997MHz, f = 15.0021MHz, A = -1dBFS)  
(f  
CLK  
2300  
IN  
IN  
2250  
2200  
2150  
2100  
2050  
2000  
4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25  
SUPPLY VOLTAGE (V)  
_______________________________________________________________________________________  
7
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
P in De s c rip t io n  
PIN  
NAME  
FUNCTION  
1, 2, 3, 6, 9, 12, 14–17,  
20, 23, 26, 27, 30, 52–56, EP  
Converter Ground. Analog, digital, and output driver grounds are internally  
connected to the same potential. Connect the converter’s EP to GND.  
GND  
4
5
CLKP  
CLKN  
Differential Clock, Positive Input Terminal  
Differential Clock, Negative Input Terminal  
Analog Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF  
capacitors.  
7, 8, 18, 19, 21, 22, 24, 25, 28  
AV  
CC  
10  
11  
13  
INP  
Differential Analog Input, Positive Terminal  
Differential Analog Input, Negative/Complementary Terminal  
Common-Mode Reference Terminal  
INN  
CM  
Digital Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF  
capacitors.  
29  
DV  
CC  
Digital Output Driver Supply Voltage. Provide local bypassing to ground with  
0.1µF to 0.22µF capacitors.  
31, 41, 42, 51  
DRV  
CC  
Data Overrange Bit. This control line flags an overrange condition in the ADC.  
If DOR transitions high, an overrange condition is detected. If DOR remains low, the  
ADC operates within the allowable full-scale range.  
32  
DOR  
33  
34  
35  
36  
37  
38  
39  
40  
43  
44  
45  
46  
47  
48  
49  
D0  
D1  
Digital CMOS Output Bit 0 (LSB)  
Digital CMOS Output Bit 1  
Digital CMOS Output Bit 2  
Digital CMOS Output Bit 3  
Digital CMOS Output Bit 4  
Digital CMOS Output Bit 5  
Digital CMOS Output Bit 6  
Digital CMOS Output Bit 7  
Digital CMOS Output Bit 8  
Digital CMOS Output Bit 9  
Digital CMOS Output Bit 10  
Digital CMOS Output Bit 11  
Digital CMOS Output Bit 12  
Digital CMOS Output Bit 13  
Digital CMOS Output Bit 14 (MSB)  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
D10  
D11  
D12  
D13  
D14  
Data Valid Output. This output can be used as a clock control line to drive an  
external buffer or data-acquisition system. The typical delay time between the  
falling edge of the converter clock and the rising edge of DAV is 6.5ns.  
50  
DAV  
8
_______________________________________________________________________________________  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
De t a ile d De s c rip t io n  
AV  
CC  
GND DV  
DRV  
CC  
CC  
Figure 1 provides an overview of the MAX1429 archi-  
tecture. The MAX1429 employs an input T/H amplifier,  
which has been optimized for low thermal noise and  
low distortion. The high-impedance differential inputs to  
the T/H a mp lifie r (INP a nd INN) a re s e lf-b ia s e d a t  
3.33V, and support a full-scale differential input voltage  
INP  
MULTISTAGE  
PIPELINE ADC CORE  
T/H  
MAX1429  
INN  
CM  
INTERNAL  
REFERENCE  
of 2.2V . The output of the T/H amplifier is fed to a  
P-P  
multistage pipelined ADC core, which has also been  
optimized to achieve a very low thermal noise floor and  
low distortion.  
CLKP  
CLKN  
CORRECTION  
LOGIC + OUTPUT  
BUFFERS  
INTERNAL  
TIMING  
CLOCK  
BUFFER  
A clock buffer receives a differential input clock wave-  
form and generates a low-jitter clock signal for the input  
T/H. The signal at the analog inputs is sampled at the  
rising edge of the differential clock waveform. The dif-  
fe re ntia l c loc k inp uts (CLKP a nd CLKN) a re hig h-  
impedance inputs, are self-biased at 2.4V, and support  
15  
DAV  
DATA BITS D0 THROUGH D14  
Figure 1. Simplified MAX1429 Diagram  
differential clock waveforms from 0.5V  
to 3.0V  
.
P-P  
P-P  
The outputs from the multistage pipelined ADC core  
are delivered to error correction and formatting logic,  
which in turn, deliver the 15-bit output code in two’s-  
complement format to digital output drivers. The output  
drivers provide CMOS-compatible outputs with levels  
programmable over a 2.3V to 3.5V range.  
T/H AMPLIFIER  
INP  
TO 1. QUANTIZER STAGE  
500Ω  
BUFFER  
1kΩ  
INTERNAL REFERENCE  
AND BIASING CIRCUIT  
An a lo g In p u t s a n d  
Co m m o n Mo d e (INP , INN, CM)  
CM  
500Ω  
The signal inputs to the MAX1429 (INP and INN) are  
balanced differential inputs. This differential configura-  
tion provides immunity to common-mode noise coupling  
and rejection of even-order harmonic terms. The differ-  
ential signal inputs to the MAX1429 should be AC-cou-  
pled and carefully balanced in order to achieve the best  
dynamic performance (see the Applications Information  
section for more detail). AC-coupling of the input signal  
is easily accomplished because the MAX1429 inputs  
are self-biasing as illustrated in Figure 2. Although the  
T/H inputs are high impedance, the actual differential  
input impedance is nominally 1kΩ because of the two  
500Ω bias resistors connected from each input to the  
common-mode reference.  
T/H AMPLIFIER  
INN  
TO 1. QUANTIZER STAGE  
Figure 2. Simplified Analog and Common-Mode Input Architecture  
The CM pin provides a monitor of the input common-  
mode self-bias potential. In most applications, in which  
the input signal is AC-coupled, this pin is not connect-  
ed. If DC-coupling of the input signal is required, this  
pin may be used to construct a DC servo loop to con-  
trol the inp ut c ommon-mod e p ote ntia l. Se e the  
Applications Information section for more details.  
_______________________________________________________________________________________  
9
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
On -Ch ip Re fe re n c e Circ u it  
The MAX1429 incorporates an on-chip 2.5V, low-drift  
bandgap reference. This reference potential establish-  
es the full-scale range for the converter, which is nomi-  
Clo c k In p u t s (CLKP , CLKN)  
The differential clock buffer for the MAX1429 has been  
designed to accept an AC-coupled clock waveform.  
Like the signal inputs, the clock inputs are self-biasing.  
In this case, the common-mode bias potential is 2.4V  
and each input is connected to the reference potential  
through a 1kΩ resistor. Consequently, the differential  
input resistance associated with the clock inputs is  
na lly 2.2V  
d iffe re ntia l. The inte rna l re fe re nc e  
P-P  
potential is not accessible to the user, so the full-scale  
range for the MAX1429 cannot be externally adjusted.  
Figure 3 shows how the reference is used to generate  
the common-mode bias potential for the analog inputs.  
The c ommon-mod e inp ut b ia s is s e t to one d iod e  
potential above the bandgap reference potential, and  
so varies over temperature.  
2kΩ. While differential clock signals as low as 0.5V  
P-P  
may be used to drive the clock inputs, best dynamic  
performance is achieved with clock input voltage levels  
of 2V  
to 3V . Jitter on the clock signal translates  
P-P  
P-P  
d ire c tly to jitte r (nois e ) on the s a mp le d s ig na l.  
Therefore, the clock source should be a low-jitter (low-  
phase noise) source. See the Applications Information  
section for additional details on driving the clock inputs.  
S ys t e m Tim in g Re q u ire m e n t s  
Figure 4 depicts the timing relationships for the signal  
input, clock input, data output, and DAV output. The  
variables shown in the figure correspond to the various  
timing specifications in the Electrical Characteristics  
table. These include:  
500Ω  
500Ω  
1mA  
2.5V  
INP/INN  
COMMON-MODE  
REFERENCE  
1kΩ  
• t  
: Delay from the rising edge of the clock until the  
50% point of the output data transition  
DAT  
• t : Delay from the falling edge of the clock until the  
DAV  
2mA  
50% point of the DAV rising edge  
• t  
: Time from the rising edge of the clock until data  
is no longer valid  
DNV  
Figure 3. Simplified Reference Architecture  
INP  
INN  
t
t
AD  
t
CLKP  
CLKN  
CLKN  
N
N + 1  
N + 2  
N + 3  
CLKP  
t
DGV  
t
t
DNV  
DAT  
D0–D14  
DOR  
N - 3  
N - 2  
N - 1  
N
t
S
t
DAV  
t
H
DAV  
Figure 4. System and Output Timing Diagram  
10 ______________________________________________________________________________________  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
• t  
: Time from the rising edge of the clock until data  
is guaranteed to be valid  
(<10pF). Large capacitive loads result in large charging  
currents during data transitions, which may feed back into  
the analog section of the ADC and create distortion terms.  
The loading capacitance is kept low by keeping the output  
traces short and by driving a single CMOS buffer or latch  
input (as opposed to multiple CMOS inputs).  
DGV  
• t  
: Time from data guaranteed valid until the ris-  
SETUP  
ing edge of DAV  
• t  
: Time from the rising edge of DAV until data is  
HOLD  
no longer valid  
Inserting small series resistors (220Ω or less) between  
the MAX1429 outputs and the digital load, placed as  
closely as possible to the output pins, is helpful in con-  
trolling the size of the charging currents during data  
transitions and can improve dynamic performance.  
Keep the trace length from the resistor to the load as  
short as possible to minimize trace capacitance.  
• t  
: Time from the 50% point of the rising edge to  
the 50% point of the falling edge of the clock signal  
CLKP  
• t  
: Time from 50% point of the falling edge to the  
CLKN  
50% point of the rising edge of the clock signal  
The MAX1429 samples the input signal on the rising  
edge of the input clock. Output data is valid on the ris-  
ing edge of the DAV signal, with a data latency of three  
clock cycles. Note that the clock duty cycle must be  
50% 5% for proper operation.  
The output data is in two’s complement format, as illus-  
trated in Table 1.  
Data is valid at the rising edge of DAV (Figure 4), and  
DAV may be used as a clock signal to latch the output  
data. The DAV output provides twice the drive strength  
of the data outputs, and may therefore be used to drive  
multiple data latches.  
Dig it a l Ou t p u t s (D0 –D1 4 , DAV, DOR)  
The logic “high” level of the CMOS-compatible digital  
outputs (D0–D14, DAV, and DOR) may be set in the  
2.3V to 3.5V range. This is accomplished by setting the  
The DOR output is used to identify an overrange condi-  
tion. If the input signal exceeds the positive or negative  
full-scale range for the MAX1429, then DOR is asserted  
high. The timing for DOR is identical to the timing for  
the data outputs, and DOR therefore provides an over-  
range indication on a sample-by-sample basis.  
voltage at the DV  
logic-high level. Note that the DV  
ages must be the same value.  
and DRV  
pins to the desired  
CC  
CC  
and DRV  
volt-  
CC  
CC  
For best performance, the capacitive loading on the digital  
outputs of the MAX1429 should be kept as low as possible  
Table 1. MAX1429 Digital Output Coding  
INP  
INN  
ANALOG VOLTAGE LEVEL  
D14–D0  
TWO’S COMPLEMENT CODE  
ANALOG VOLTAGE LEVEL  
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1  
(positive full scale)  
V
REF  
+ 0.64V  
V
REF  
- 0.64V  
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  
(midscale + δ)  
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1  
V
REF  
V
REF  
(midscale - δ)  
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0  
(negative full scale)  
V
REF  
- 0.64V  
V
REF  
+ 0.64V  
______________________________________________________________________________________ 11  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
BACK-TO-BACK DIODE  
AV DV DRV  
CC  
CC  
CC  
0.1µF  
T2-1T–KK81  
50Ω  
50Ω  
INP  
D0–D14  
MAX1429  
15  
INN  
0.1µF  
0.01µF 0.1µF  
0.01µF  
CLKP  
GND  
CLKN  
Figure 5. Transformer-Coupled Clock Input Configuration  
held to 3V  
differential or less. If a larger amplitude  
P-P  
Ap p lic a t io n s In fo rm a t io n  
signal is provided (to maximize the zero-crossing slew  
rate), then the diodes serve to limit the differential sig-  
nal swing at the clock inputs.  
Diffe re n t ia l, AC-Co u p le d Clo c k In p u t  
The clock inputs to the MAX1429 are designed to be  
driven with an AC-coupled differential signal, and best  
p e rforma nc e is a c hie ve d und e r the s e c ond itions .  
However, it is often the case that the available clock  
source is single ended. Figure 5 demonstrates one  
method for converting a single-ended clock signal into  
a differential signal through a transformer. In this exam-  
ple, the transformer turns ratio from the primary to sec-  
ond a ry s id e is 1:1.414. The imp e d a nc e ra tio from  
primary to secondary is the square of the turns ratio, or  
1:2, so that terminating the secondary side with a 100Ω  
differential resistance results in a 50Ω load looking into  
the primary side of the transformer. The termination  
resistor in this example comprises the series combina-  
tion of two 50Ω resistors with their common node AC-  
coupled to ground. Alternatively, a single 100Ω resistor  
across the two inputs with no common-mode connec-  
tion could be employed.  
Any differential mode noise coupled to the clock inputs  
translates to clock jitter and degrades the SNR perfor-  
mance of the MAX1429. Any differential mode coupling  
of the analog input signal into the clock inputs results in  
harmonic distortion. Consequently, it is important that  
the clock lines be well isolated from the analog signal  
input and from the digital outputs. See the PC Board  
Layout Considerations sections for more discussion on  
noise coupling.  
Diffe re n t ia l, AC-Co u p le d An a lo g In p u t  
The analog inputs (INP and INN) are designed to be dri-  
ven with a differential AC-coupled signal. It is extremely  
important that these inputs be accurately balanced. Any  
common-mode signal applied to these inputs degrade  
even-order distortion terms. Therefore, any attempt at  
driving these inputs in a single-ended fashion results in  
significant even-order distortion terms.  
In the example of Figure 5, the secondary side of the  
transformer is coupled directly to the clock inputs.  
Since the clock inputs are self-biasing, the center tap of  
the transformer must be AC-coupled to ground or left  
floating. If the center tap of the secondary were DC-  
coupled to ground, then it would be necessary to add  
blocking capacitors in series with the clock inputs.  
Figure 6 presents one method for converting a single-  
ended signal to a balanced differential signal using a  
transformer. The primary-to-secondary turns ratio in this  
example is 1:1.414. The impedance ratio is the square  
of the turns ratio, so in this example, the impedance  
ratio is 1:2. In order to achieve a 50Ω input impedance  
at the primary side of the transformer, the secondary  
side is terminated with a 112Ω differential load. This  
load, in shunt with the differential input resistance of the  
MAX1429, results in a 100Ω differential load on the sec-  
ondary side. It is reasonable to use a larger transformer  
turns ratio in order to achieve a larger signal step-up,  
and this may be desirable in order to relax the drive  
requirements for the circuitry driving the MAX1429.  
Clock jitter is generally improved if the clock signal has  
a hig h s le w ra te a t the time of its ze ro c ros s ing .  
Therefore, if a sinusoidal source is used to drive the  
clock inputs, it is desirable that the clock amplitude be  
as large as possible to maximize the zero-crossing  
slew rate. The back-to-back Schottky diodes shown in  
Figure 5 are not required as long as the input signal is  
12 ______________________________________________________________________________________  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
AV DV DRV  
CC  
CC  
CC  
SINGLE-ENDED  
INPUT TERMINAL  
INP  
0.1µF  
D0–D14  
T2-1T–KK81  
56Ω  
56Ω  
MAX1429  
15  
INN  
GND  
0.1µF  
0.01µF  
CLKP  
CLKN  
Figure 6. Transformer-Coupled Analog Input Configuration  
AV DV DRV  
CC  
CC  
CC  
POSITIVE  
TERMINAL  
INP  
0.1µF  
D0–D14  
T2-1T–KK81  
T2-1T–KK81  
56Ω  
MAX1429  
15  
INN  
56Ω  
GND  
0.1µF  
0.1µF  
CLKP  
CLKN  
Figure 7. Transformer-Coupled Analog Input Configuration with Primary-Side Transformer  
However, the larger the turns ratio, the larger the effect  
of the differential input resistance of the MAX1429 on  
the primary referred input resistance. At a turns ratio of  
1:4.47, the 1kΩ d iffe re ntia l inp ut re s is ta nc e of the  
MAX1429 by itself results in a primary referred input  
resistance of 50Ω.  
Although the center tap of the transformer in Figure 6 is  
s hown floa ting , it ma y b e AC-c oup le d to g round .  
However experience has shown that better balance is  
achieved if the center tap is left floating.  
ord e r d is tortion p e rforma nc e . Fig ure 7 p rovid e s  
improved balance over the circuit of Figure 6 by adding  
a balun on the primary side of the transformer, and can  
yield substantial improvement in even-order distortion  
terms over the circuit of Figure 6.  
One note of caution in relation to transformers is impor-  
tant. Any DC current passed through the primary or  
secondary windings of a transformer may magnetically  
b ia s the tra ns forme r c ore . Whe n this ha p p e ns , the  
transformer is no longer accurately balanced and a  
degradation in the distortion of the MAX1429 may be  
observed. The core must be demagnetized in order to  
return to balanced operation.  
As stated previously, the signal inputs to the MAX1429  
must be accurately balanced to achieve the best even-  
______________________________________________________________________________________ 13  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
The MAX1427 evaluation board (MAX1427 EV kit) pro-  
vides an excellent frame of reference for board layout,  
and the discussion that follows is consistent with the  
practices incorporated on the evaluation board.  
POSITIVE  
INPUT  
TO INP  
OA1  
La ye r As s ig n m e n t s  
The MAX1427 EV kit is a s ix-la ye r b oa rd , a nd the  
assignment of layers is discussed in this context. It is  
recommended that the ground plane be on a layer  
between the signal routing layer and the supply routing  
layer(s). This practice prevents coupling from the sup-  
ply lines into the signal lines. The MAX1427 EV kit PC  
board places the signal lines on the top (component)  
layer and the ground plane on layer 2. Any region on  
the top layer not devoted to signal routing is filled with  
ground plane with vias to layer 2. Layers 3 and 4 are  
devoted to supply routing, layer 5 is another ground  
plane, and layer 6 is used for the placement of addi-  
tional components and for additional signal routing.  
R
R
C1  
F1  
R
G1  
OA3  
FROM CM  
TO INN  
R
G2  
R
F1  
R
C2  
OA2  
NEGATIVE  
INPUT  
A four-layer implementation is also feasible using layer  
1 for signal lines, layer 2 as a ground plane, layer 3 for  
supply routing, and layer 4 for additional signal routing.  
However, care must be taken to make sure that the  
clock and signal lines are isolated from each other and  
from the supply lines.  
Figure 8. DC-Coupled Analog Input Configuration  
DC-Co u p le d An a lo g In p u t  
While AC-coupling of the input signal is the proper  
means for achieving the best dynamic performance, it  
is possible to DC-couple the inputs by making use of  
the CM p ote ntia l. Fig ure 8 s hows one me thod for  
a c c omp lis hing DC-c oup ling . The c ommon-mod e  
potentials at the outputs of amplifiers OA1 and OA2 are  
“servoed” by the action of amplifier OA3 to be equal to  
the CM potential of the MAX1429. Care must be taken  
to ensure that the common-mode loop is stable, and  
S ig n a l Ro u t in g  
To preserve good even-order distortion, the signal lines  
(those traces feeding the INP and INN inputs) must be  
carefully balanced. To accomplish this, the signal traces  
should be made as symmetric as possible, meaning that  
each of the two signal traces should be the same length  
and should see the same parasitic environment. As men-  
tioned previously, the signal lines must be isolated from  
the supply lines to prevent coupling from the supplies to  
the inputs. This is accomplished by making the neces-  
sary layer assignments as described in the previous sec-  
tion. Additionally, it is crucial that the clock lines be  
isolated from the signal lines. On the MAX1427 EV kit,  
this is done by routing the clock lines on the bottom layer  
(la ye r 6). The c loc k line s the n c onne c t to the ADC  
through vias placed in close proximity to the device. The  
clock lines are isolated from the supply lines, by virtue of  
the ground plane on layer 5.  
the R /R ra tios of b oth ha lf c irc uits mus t b e we ll  
F
G
matched to ensure balance.  
P C Bo a rd La yo u t Co n s id e ra t io n s  
The p e rforma nc e of a ny hig h-d yna mic ra ng e , hig h  
sample-rate converter may be compromised by poor  
PC board layout practices. The MAX1429 is no excep-  
tion to the rule, and careful layout techniques must be  
ob s e rve d in ord e r to a c hie ve the s p e c ifie d p e rfor-  
mance. Layout issues are addressed in the following  
four categories:  
The digital output traces should be kept as short as  
possible to minimize capacitive loading. The ground  
plane on layer 2 beneath these traces should not be  
removed so that the digital ground return currents have  
an uninterrupted path back to the bypass capacitors.  
1) Layer assignments  
2) Signal routing  
3) Grounding  
4) Supply routing and bypassing  
14 ______________________________________________________________________________________  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
beads are also used on each of the supply lines to  
enhance supply bypassing (Figure 9).  
Gro u n d in g  
The practice of providing a split ground plane in an  
attempt to confine digital ground return currents has  
often been recommended in ADC application literature.  
However, for converters such as the MAX1429, it is  
strongly recommended to employ a single, uninterrupt-  
ed ground plane. The MAX1427 EV kit achieves excel-  
lent dynamic performance with such a ground plane.  
Small value (0.01µF to 0.1µF) surface-mount capacitors  
should be placed at each supply pin or each grouping  
of supply pins to attenuate high-frequency supply noise  
(Figure 9). It is recommended to place these capacitors  
on the topside of the board and as close to the device  
as possible with short connections to the ground plane.  
The EP of the MAX1429 should be soldered directly to  
a ground pad on layer 1 with vias to the ground plane  
on layer 2. This provides excellent electrical and ther-  
mal connections to the printed circuit  
S t a t ic P a ra m e t e r De fin it io n s  
In t e g ra l No n lin e a rit y (INL)  
Integral nonlinearity is the deviation of the values on an  
actual transfer function from a straight line. This straight  
line can be either a best straight-line fit or a line drawn  
between the end points of the transfer function, once  
offset and gain errors have been nullified. However, the  
static linearity parameters for the MAX1429 are mea-  
sured using the histogram method with an input fre-  
quency of 15MHz.  
S u p p ly Byp a s s in g  
The MAX1427 EV kit uses 220µF capacitors on each  
supply line (AV , DV , and DRV ) to provide low-  
CC  
CC  
CC  
fre q ue nc y b yp a s s ing . The los s (s e rie s re s is ta nc e )  
associated with these capacitors is actually of some  
benefit in eliminating high-Q supply resonances. Ferrite  
BYPASSING—ADC LEVEL  
BYPASSING—BOARD LEVEL  
FERRITE BEAD  
AV  
CC  
AV  
CC  
DV  
CC  
ANALOG  
220µF  
10µF  
10µF  
10µF  
47µF  
47µF  
47µF  
0.1µF  
0.1µF  
POWER-SUPPLY SOURCE  
GND  
GND  
DV  
CC  
FERRITE BEAD  
D0–D14  
MAX1429  
DIGITAL  
POWER-SUPPLY SOURCE  
220µF  
15  
0.1µF  
DRV  
CC  
FERRITE BEAD  
GND  
DRV  
CC  
OUTPUT DRIVER  
POWER-SUPPLY SOURCE  
220µF  
Figure 9. Grounding, Bypassing, and Decoupling Recommendations for MAX1429  
______________________________________________________________________________________ 15  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
Diffe re n t ia l No n lin e a rly (DNL)  
Differential nonlinearity is the difference between an  
actual step width and the ideal value of 1 LSB. A DNL  
error specification of less than 1 LSB guarantees no  
missing codes and a monotonic transfer function. The  
MAX1429’s DNL specification is measured with the his-  
togram method based on a 15MHz input tone.  
S in g le -To n e S p u rio u s -Fre e  
Dyn a m ic Ra n g e (S FDR)  
SFDR is the ratio of RMS amplitude of the carrier fre-  
quency (maximum signal component) to the RMS value  
of the next-largest noise or harmonic distortion compo-  
nent. SFDR is usually measured in dBc with respect to  
the carrier frequency amplitude or in dBFS with respect  
to the ADC’s full-scale range.  
Dyn a m ic P a ra m e t e r De fin it io n s  
Tw o -To n e S p u rio u s -Fre e  
Ap e rt u re De la y  
Dyn a m ic Ra n g e (S FDR  
)
TT  
Aperture delay (t ) is the time defined between the  
AD  
SFDR represents the ratio of the RMS value of either  
TT  
rising edge of the sampling clock and the instant when  
an actual sample is taken (Figure 4).  
input tone to the RMS value of the peak spurious com-  
ponent in the power spectrum. This peak spur can be  
an intermodulation product of the two input test tones.  
Ap e rt u re J it t e r  
The aperture jitter (t ) is the sample-to-sample varia-  
tion in the aperture delay.  
AJ  
Tw o -To n e In t e rm o d u la t io n Dis t o rt io n (IMD)  
The two-tone IMD is the ratio expressed in decibels of  
either input tone to the worst 3rd-order (or higher) inter-  
modulation products. The individual input tone levels  
are at -7dB full scale.  
S ig n a l-t o -No is e Ra t io (S NR)  
For a waveform perfectly reconstructed from digital  
samples, the theoretical maximum SNR is the ratio of  
the full-scale analog input (RMS value) to the RMS  
quantization error (residual error). The ideal, theoretical  
minimum analog-to-digital noise is caused by quantiza-  
tion error only and results directly from the ADC’s reso-  
lution (N bits):  
P in Co n fig u ra t io n  
TOP VIEW  
56 55 54 53 52 51 50 49 48 47 46 45 44 43  
SNR  
= 6.02 x N + 1.76  
dB dB  
dB[max]  
42 DRV  
CC  
GND  
GND  
GND  
CLKP  
CLKN  
GND  
1
2
3
4
5
6
7
8
9
EP  
In reality, other noise sources such as thermal noise,  
clock jitter, signal phase noise, and transfer function  
nonlinearities are also contributing to the SNR calcula-  
tion and should be considered when determining the  
SNR in ADC. For a near-full-scale analog input signal  
(-0.5dBFS to -1dBFS), thermal and quantization noise  
are uniformly distributed across the frequency bins.  
Error energy caused by transfer function nonlinearities  
on the other hand is not distributed uniformly, but con-  
fined to the first few hundred odd-order harmonics.  
41 DRV  
CC  
40 D7  
39 D6  
38 D5  
37 D4  
36 D3  
35 D2  
34 D1  
33 D0  
32 DOR  
31 DRV  
AV  
CC  
MAX1429  
AV  
CC  
GND  
INP 10  
INN 11  
GND 12  
CM 13  
GND 14  
BTS applications, which are the main target application  
for the MAX1429 usually do not care about excess  
noise and error energy in close proximity to the carrier  
frequency or to DC. These low-frequency and sideband  
errors are test frequency artifacts and are of no conse-  
quence to the BTS channel sensitivity. They are there-  
fore excluded from the SNR calculation.  
CC  
30 GND  
29 DV  
CC  
15 16 17 18 19 20 21 22 23 24 25 26 27 28  
THIN QFN  
S ig n a l-t o -No is e P lu s Dis t o rt io n (S INAD)  
SINAD is computed by taking the ratio of the RMS sig-  
nal to all spectral components excluding the fundamen-  
tal and the DC offset.  
16 ______________________________________________________________________________________  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
P a c k a g e In fo rm a t io n  
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,  
go to www.maxim-ic.com/packages.)  
______________________________________________________________________________________ 17  
1 5 -Bit , 1 0 0 Ms p s ADC w it h -7 7 .7 d BFS  
No is e Flo o r fo r Ba s e b a n d Ap p lic a t io n s  
P a c k a g e In fo rm a t io n (c o n t in u e d )  
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,  
go to www.maxim-ic.com/packages.)  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
18 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0  
© 2004 Maxim Integrated Products  
Printed USA  
is a registered trademark of Maxim Integrated Products.  

MAX1429 相关器件

型号 制造商 描述 价格 文档
MAX1429ETN MAXIM 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications 获取价格
MAX1429ETN+D MAXIM 最高分辨率:15;最大数据速率:100M;元器件封装:56-TQFN; 获取价格
MAX1429ETN+TD MAXIM ADC, Proprietary Method, 15-Bit, 1 Func, 1 Channel, Parallel, Word Access, 8 X 8 MM, 0.8 MM HEIGHT, ROHS COMPLIANT, MO-220, TQFN-56 获取价格
MAX1429ETN-D MAXIM ADC, Proprietary Method, 15-Bit, 1 Func, 1 Channel, Parallel, Word Access, 8 X 8 MM, 0.8 MM HEIGHT, MO-220, TQFN-56 获取价格
MAX1429ETN-TD MAXIM ADC, Proprietary Method, 15-Bit, 1 Func, 1 Channel, Parallel, Word Access, 8 X 8 MM, 0.8 MM HEIGHT, MO-220, TQFN-56 获取价格
MAX1430 MAXIM 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications 获取价格
MAX1430ETN+D MAXIM ADC, Proprietary Method, 15-Bit, 1 Func, 1 Channel, Parallel, Word Access, 8 X 8 MM, 0.8 MM HEIGHT, ROHS COMPLIANT, MO-220WLLD-5, QFN-56 获取价格
MAX1430ETN+TD MAXIM ADC, Proprietary Method, 15-Bit, 1 Func, 1 Channel, Parallel, Word Access, 8 X 8 MM, 0.8 MM HEIGHT, ROHS COMPLIANT, MO-220WLLD-5, QFN-56 获取价格
MAX1430ETN-TD MAXIM ADC, Proprietary Method, 15-Bit, 1 Func, 1 Channel, Parallel, Word Access, 8 X 8 MM, 0.8 MM HEIGHT, MO-220WLLD-5, QFN-56 获取价格
MAX1434 MAXIM Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 获取价格

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