MAX1429 [MAXIM]

15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications; 15位, 100MSPS ADC与基带应用-77.7dBFS本底噪声
MAX1429
元器件型号: MAX1429
生产厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述和应用:

15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications
15位, 100MSPS ADC与基带应用-77.7dBFS本底噪声

PDF文件: 总18页 (文件大小:220K)
下载文档:  下载PDF数据表文档文件
型号参数:MAX1429参数
是否无铅 含铅
是否Rohs认证 不符合
生命周期Obsolete
零件包装代码QFN
包装说明8 X 8 MM, 0.8 MM HEIGHT, MO-220, TQFN-56
针数56
Reach Compliance Codenot_compliant
ECCN代码3A001.A.5.A.5
HTS代码8542.39.00.01
风险等级5.92
转换器类型ADC, PROPRIETARY METHOD
JESD-30 代码S-XQCC-N56
长度8 mm
模拟输入通道数量1
位数15
功能数量1
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
输出位码2'S COMPLEMENT BINARY
输出格式PARALLEL, WORD
封装主体材料UNSPECIFIED
封装代码HVQCCN
封装形状SQUARE
封装形式CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度)NOT SPECIFIED
认证状态Not Qualified
采样速率100 MHz
采样并保持/跟踪并保持TRACK
座面最大高度0.8 mm
标称供电电压5 V
表面贴装YES
温度等级INDUSTRIAL
端子形式NO LEAD
端子节距0.5 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度8 mm
Base Number Matches1
MAX34334CSE前5页PDF页面详情预览
19-3434; Rev 0; 10/04
KIT
ATION
EVALU
BLE
AVAILA
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
General Description
Features
100Msps Minimum Sampling Rate
-77.7dBFS Noise Floor
Excellent Dynamic Performance
75.1dB SNR at f
IN
= 15MHz and A
IN
= -1dBFS
90dBc/94dBc Single-Tone SFDR1/SFDR2 at
f
IN
= 15MHz and A
IN
= -1dBFS
-100dBc Multitone SFDR at f
IN1
= 10MHz
and f
IN2
= 15MHz
Less than 0.25ps Sampling Jitter
Fully Differential Analog Input Voltage Range of
2.2V
P-P
CMOS-Compatible Two’s-Complement Data Output
Separate Data Valid Clock and Overrange Outputs
Flexible-Input Clock Buffer
EV Kit Available for MAX1429
(Order MAX1427EVKIT)
MAX1429
The MAX1429 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differ-
ential wideband track-and-hold (T/H) and a 15-bit con-
verter core. The MAX1429 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -77.7dBFS, the MAX1429 allows for the
design of receivers with superior sensitivity.
The MAX1429 achieves two-tone, spurious-free dynamic
range (SFDR) of -100dBc for input tones of 10MHz and
15MHz. Its excellent signal-to-noise ratio (SNR) of 75.1dB
and single-tone SFDR performance (SFDR1/SFDR2) of
90dBc/94dBc at f
IN
= 15MHz and a sampling rate of
80Msps make this part ideal for high-performance digital
receivers.
The MAX1429 operates from an analog 5V and a digital
3V supply, features a 2.2V
P-P
full-scale input range,
and allows for a sampling speed of up to 100Msps. The
input T/H operates with a -1dB full-power bandwidth of
260MHz.
The MAX1429 features parallel, CMOS-compatible out-
puts in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1429 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see
Pin-Compatible Higher/Lower Speed Versions
Selection
table) are recommended for applications that
require high dynamic performance for input frequen-
cies greater than f
CLK
/3. The MAX1429 is optimized for
input frequencies of less than f
CLK
/3.
Ordering Information
PART
MAX1429ETN
*
EP
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
56 Thin QFN-EP*
= Exposed paddle.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
MAX1418
MAX1419
MAX1427
MAX1428
MAX1429
MAX1430
SPEED GRADE
(Msps)
65
65
80
80
100
100
TARGET
APPLICATION
IF
Baseband
Baseband
IF
Baseband
IF
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
MAX1429
ABSOLUTE MAXIMUM RATINGS
AV
CC
, DV
CC
, DRV
CC
to GND.................................. -0.3V to +6V
INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV
CC
+ 0.3V)
D0–D14, DAV, DOR to GND..................-0.3V to (DRV
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin Thin QFN (derate 47.6mW/°C above +70°C)...3809.5mW
Operating Temperature Range ...........................-40°C to +85°C
Thermal Resistance
θ
J
A
...................................................21°C/W
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT (INP, INN)
Differential Input Voltage Range
Common-Mode Input Voltage
Differential Input Resistance
Differential Input Capacitance
Full-Power Analog Bandwidth
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
Aperture Jitter
CLOCK INPUT (CLKP, CLKN)
Full-Scale Differential Input
Voltage
Common-Mode Input Voltage
Differential Input Resistance
Differential Input Capacitance
DYNAMIC CHARACTERISTICS
Thermal + Quantization Noise
Floor
NF
Analog input <-35dBFS
-77.7
dBFS
V
DIFFCLK
V
CM
R
INCLK
C
INCLK
Fully differential input drive, V
CLKP
- V
CLKN
Self-biased
0.5 to
3.0
2.4
2
±15%
1
V
V
kΩ
pF
f
CLK
f
CLK
t
AJ
100
20
0.21
MHz
MHz
ps
RMS
V
DIFF
V
CM
R
IN
C
IN
FPBW
-1dB
-1dB rolloff for a full-scale input
Fully differential inputs drive,
V
DIFF
= V
INP
- V
INN
Self-biased
2.20
3.33
1
±15%
1
260
V
P-P
V
kΩ
pF
MHz
INL
DNL
f
IN
= 15MHz
f
IN
= 15MHz, no missing codes guaranteed
-12
-4
15
±1.5
±0.4
+12
+4
Bits
LSB
LSB
mV
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
Signal-to-Noise
Ratio (Note 1)
Signal-to-Noise
and Distortion
(Note 1)
Spurious-Free Dynamic Range
(HD2 and HD3)
(Note 1)
Spurious-Free Dynamic Range
(HD4 and Higher)
(Note 1)
Two-Tone Intermodulation
Distortion
Two-Tone Spurious-Free
Dynamic Range
Digital Output-Voltage Low
Digital Output-Voltage High
SYMBOL
SNR
CONDITIONS
f
IN
= 5MHz at -1dBFS
f
IN
= 15MHz at -1dBFS
f
IN
= 35MHz at -1dBFS
f
IN
= 5MHz at -1dBFS
SINAD
f
IN
= 15MHz at -1dBFS
f
IN
= 35MHz at -1dBFS
f
IN
= 5MHz at -1dBFS
SFDR1
f
IN
= 15MHz at -1dBFS
f
IN
= 35MHz at -1dBFS
f
IN
= 5MHz at -1dBFS
SFDR2
f
IN
= 15MHz at -1dBFS
f
IN
= 35MHz at -1dBFS
TTIMD
SFDR
TT
f
IN1
= 10MHz at -7dBFS,
f
IN2
= 15MHz at -7dBFS
f
IN1
= 10MHz at -10dBFS < f
IN1
< -100dBFS,
f
IN2
= 15MHz at -10dBFS < f
IN2
< -100dBFS
85.0
84.0
71.7
72.1
MIN
TYP
75.3
75.1
74.8
75.0
74.9
71.1
90.0
90.0
74.0
96.0
94.0
92.0
-85
-100
dBc
dBFS
dBc
dBc
dB
dB
MAX
UNITS
MAX1429
DIGITAL OUTPUTS (D0–D14, DAV, DOR)
V
OL
V
OH
DRV
CC
- 0.5
0.5
V
V
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 2.5V)
CLKP/CLKN Duty Cycle
Effective Aperture Delay
Output Data Delay
Data Valid Delay
Pipeline Latency
CLKP Rising Edge to DATA Not
Valid
CLKP Rising Edge to DATA Valid
(guaranteed)
DATA Setup Time (Before DAV
Rising Edge)
DATA Hold Time (After DAV
Rising Edge)
Duty Cycle
t
AD
t
DAT
t
DAV
t
LATENCY
t
DNV
t
DGV
t
SETUP
t
HOLD
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
2.6
3.4
t
CLKP
- 0.5
t
CLKN
-
3.6
3.0
5.3
50
±5
230
4.5
6.5
3
3.8
5.2
t
CLKP
+ 1.3
t
CLKN
-
2.8
5.7
8.6
t
CLKP
+
2.4
t
CLKN
-
2.0
7.5
8.7
%
ps
ns
ns
Clock
cycles
ns
ns
ns
ns
_______________________________________________________________________________________
3
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
MAX1429
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
CLKP/CLKN Duty Cycle
Effective Aperture Delay
Output Data Delay
Data Valid Delay
Pipeline Latency
CLKP Rising Edge to DATA Not
Valid
CLKP Rising Edge to DATA Valid
(guaranteed)
DATA Setup Time (Before DAV
Rising Edge)
DATA Hold Time (After DAV
Rising Edge)
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital-Supply Voltage Range
Output-Supply Voltage Range
Analog Supply Current
Digital + Output Supply Current
Total Power Dissipation
AV
CC
DV
CC
DRV
CC
I
AVCC
I
DVCC
+
I
DRVCC
PDISS
f
CLK
= 100MHz, C
L
= 5pF
(Note 2)
(Note 2)
5
±3%
2.3 to
2.5
2.3 to
2.5
390
38
2045
440
44
V
V
V
mA
mA
mW
SYMBOL
Duty Cycle
t
AD
t
DAT
t
DAV
t
LATENCY
t
DNV
t
DGV
t
SETUP
t
HOLD
(Note 3)
(Note 3)
(Note 3)
(Note 3)
2.5
3.2
(Note 3)
(Note 3)
2.8
5.3
CONDITIONS
MIN
TYP
50
±5
230
4.1
6.3
3
3.4
4.4
5.2
7.4
6.5
8.6
MAX
UNITS
%
ps
ns
ns
Clock
cycles
ns
ns
ns
ns
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 3.3V)
t
CLKP
+ t
CLKP
+ t
CLKP
+
0.2
1.7
2.8
t
CLKN
-
3.5
t
CLKN
-
2.7
t
CLKN
-
2.0
Note 1:
Dynamic performance is based on a 32,768-point data record with a sampling frequency of f
SAMPLE
= 100.007936MHz, an
input frequency of f
IN
= f
SAMPLE
x (4915/32768) = 15.000580MHz, and a frequency bin size of 3052Hz. Close-in (f
IN
±
36.6kHz) and low-frequency (DC to 73.2kHz) bins are excluded from the spectrum analysis.
Note 2:
Apply the same voltage levels to DV
CC
and DRV
CC
.
Note 3:
Guaranteed by design and characterization.
4
_______________________________________________________________________________________
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
MAX1429
Typical Operating Characteristics
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= +25°C. All AC data is based on a 32k-point
FFT record and under coherent sampling conditions.)
FFT PLOT (32,768-POINT DATA RECORD,
FFT PLOT (32,768-POINT DATA RECORD,
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
COHERENT SAMPLING)
COHERENT SAMPLING)
MAX1429 toc01
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
0
5
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
f
CLK
= 100.0997MHz
f
IN
= 10.0014MHz
A
IN
= -1.05dBFS
SNR = 75.6dBc
SINAD = 75.4dBc
SFDR1 = 90dBc
SFDR2 = 96.4dBc
HD2 = -91dBFS
HD3 = -95.5dBFS
-20
-40
-60
-80
-100
-120
f
CLK
= 100.0997MHz
f
IN
= 15.0021MHz
A
IN
= -0.96dBFS
SNR = 75.3dBc
SINAD = 74.8dBc
SFDR1 = 86.7dBc
SFDR2 = 93.9dBc
HD2 = -87.6dBFS
HD3 = -90.2dBFS
MAX1429 toc02
-20
-40
-60
-80
-100
-120
f
CLK
= 100.0997MHz
f
IN
= 34.9973MHz
A
IN
= -1.01dBFS
SNR = 75dBc
SINAD = 70.6dBc
SFDR1 = 73dBc
SFDR2 = 93.9dBc
HD2 = -83.6dBFS
HD3 = -74dBFS
10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT (32,768-POINT DATA
RECORD, COHERENT SAMPLING)
MAX1429 toc04
SNR vs. ANALOG INPUT FREQUENCY
(f
CLK
= 100.0997MHz, A
IN
= -1dBFS)
MAX1429 toc05
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 100.0997MHz, A
IN
= -1dBFS)
MAX1429 toc06
0
-20
AMPLITUDE (dBFS)
-40
-60
f
IN2
- f
IN1
-80
-100
-120
0
5
f
IN1
+ f
IN2
f
IN1
f
IN2
f
CLK
= 100.0997MHz
f
IN1
= 10.1022MHz
A
IN1
= -7.09dBFS
f
IN2
= 15.0021MHz
A
IN2
= -7dBFS
IMD = -84.9dBc
77
76
75
SNR (dBc)
74
73
72
71
70
115
105
SFDR1/SFDR2 (dBc)
95
85
75
SFDR1
65
55
SFDR2
10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
5
10
15
20
25
30
35
40
45
50
5
10
15
20
25
30
35
40
45
50
f
IN
(MHz)
f
IN
(MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 100.0997MHz, A
IN
= -1dBFS)
MAX1429 toc07
SNR vs. SAMPLING FREQUENCY
(f
IN
= 15MHz, A
IN
= -1dBFS)
MAX1429 toc08
SFDR1/SFDR2 vs. SAMPLING FREQUENCY
(f
IN
= 15MHz, A
IN
= -1dBFS)
100
SFDR1/SFDR2 (dBc)
95
90
85
80
75
70
SFDR2
MAX1429 toc09
-65
-70
-75
HD2/HD3 (dBFS)
-80
-85
-90
-95
-100
-105
5
10
15
20
25
30
35
40
45
HD2
HD3
78
77
76
SNR (dBc)
75
74
73
72
71
70
105
SFDR1
50
20
30
40
50
60
70
80
90
100
20
30
40
50
60
70
80
90
100
f
IN
(MHz)
f
CLK
(MHz)
f
CLK
(MHz)
_______________________________________________________________________________________
MAX1429 toc03
0
0
0
5
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    MAX1429
    描述和应用

    15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications
    15位, 100MSPS ADC与基带应用-77.7dBFS本底噪声

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