MAX1429 [MAXIM]

15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications; 15位， 100MSPS ADC与基带应用-77.7dBFS本底噪声


元器件型号：	MAX1429
生产厂家：	MAXIM INTEGRATED PRODUCTS
描述和应用：	15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications 15位， 100MSPS ADC与基带应用-77.7dBFS本底噪声
PDF文件：	总18页 (文件大小：220K)
下载文档：	下载PDF数据表文档文件
型号参数：MAX1429参数
是否无铅	含铅
是否Rohs认证	不符合
生命周期	Obsolete
零件包装代码	QFN
包装说明	8 X 8 MM, 0.8 MM HEIGHT, MO-220, TQFN-56
针数	56
Reach Compliance Code	not_compliant
ECCN代码	3A001.A.5.A.5
HTS代码	8542.39.00.01
风险等级	5.92
转换器类型	ADC, PROPRIETARY METHOD
JESD-30 代码	S-XQCC-N56
长度	8 mm
模拟输入通道数量	1
位数	15
功能数量	1
端子数量	56
最高工作温度	85 °C
最低工作温度	-40 °C
输出位码	2'S COMPLEMENT BINARY
输出格式	PARALLEL, WORD
封装主体材料	UNSPECIFIED
封装代码	HVQCCN
封装形状	SQUARE
封装形式	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
采样速率	100 MHz
采样并保持/跟踪并保持	TRACK
座面最大高度	0.8 mm
标称供电电压	5 V
表面贴装	YES
温度等级	INDUSTRIAL
端子形式	NO LEAD
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	8 mm
Base Number Matches	1

MAX34334CSE前5页PDF页面详情预览

19-3434; Rev 0; 10/04

KIT

ATION

EVALU

BLE

AVAILA

15-Bit, 100Msps ADC with -77.7dBFS

Noise Floor for Baseband Applications

General Description

Features

♦

100Msps Minimum Sampling Rate

♦

-77.7dBFS Noise Floor

♦

Excellent Dynamic Performance

75.1dB SNR at f

= 15MHz and A

= -1dBFS

90dBc/94dBc Single-Tone SFDR1/SFDR2 at

= 15MHz and A

= -1dBFS

-100dBc Multitone SFDR at f

IN1

= 10MHz

and f

IN2

= 15MHz

♦

Less than 0.25ps Sampling Jitter

♦

Fully Differential Analog Input Voltage Range of

2.2V

P-P

♦

CMOS-Compatible Two’s-Complement Data Output

♦

Separate Data Valid Clock and Overrange Outputs

♦

Flexible-Input Clock Buffer

♦

EV Kit Available for MAX1429

(Order MAX1427EVKIT)

MAX1429

The MAX1429 is a 5V, high-speed, high-performance

analog-to-digital converter (ADC) featuring a fully differ-

ential wideband track-and-hold (T/H) and a 15-bit con-

verter core. The MAX1429 is optimized for multichannel,

multimode receivers, which require the ADC to meet very

stringent dynamic performance requirements. With a

noise floor of -77.7dBFS, the MAX1429 allows for the

design of receivers with superior sensitivity.

The MAX1429 achieves two-tone, spurious-free dynamic

range (SFDR) of -100dBc for input tones of 10MHz and

15MHz. Its excellent signal-to-noise ratio (SNR) of 75.1dB

and single-tone SFDR performance (SFDR1/SFDR2) of

90dBc/94dBc at f

= 15MHz and a sampling rate of

80Msps make this part ideal for high-performance digital

receivers.

The MAX1429 operates from an analog 5V and a digital

3V supply, features a 2.2V

P-P

full-scale input range,

and allows for a sampling speed of up to 100Msps. The

input T/H operates with a -1dB full-power bandwidth of

260MHz.

The MAX1429 features parallel, CMOS-compatible out-

puts in two’s-complement format. To enable the interface

with a wide range of logic devices, this ADC provides a

separate output driver power-supply range of 2.3V to

3.5V. The MAX1429 is manufactured in an 8mm x 8mm,

56-pin thin QFN package with exposed paddle (EP) for

low thermal resistance, and is specified for the extended

industrial (-40°C to +85°C) temperature range.

Note that IF parts MAX1418, MAX1428, and MAX1430

(see

Pin-Compatible Higher/Lower Speed Versions

Selection

table) are recommended for applications that

require high dynamic performance for input frequen-

cies greater than f

CLK

/3. The MAX1429 is optimized for

input frequencies of less than f

CLK

/3.

Ordering Information

PART

MAX1429ETN

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

56 Thin QFN-EP*

= Exposed paddle.

Applications

Cellular Base-Station Transceiver Systems (BTS)

Wireless Local Loop (WLL)

Single- and Multicarrier Receivers

Multistandard Receivers

E911 Location Receivers

Power Amplifier Linearity Correction

Antenna Array Processing

Pin-Compatible Higher/Lower

Speed Versions Selection

PART

MAX1418

MAX1419

MAX1427

MAX1428

MAX1429

MAX1430

SPEED GRADE

(Msps)

100

TARGET

APPLICATION

Baseband

Pin Configuration appears at end of data sheet.

________________________________________________________________

Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

15-Bit, 100Msps ADC with -77.7dBFS

Noise Floor for Baseband Applications

MAX1429

ABSOLUTE MAXIMUM RATINGS

, DV

, DRV

to GND.................................. -0.3V to +6V

INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV

+ 0.3V)

D0–D14, DAV, DOR to GND..................-0.3V to (DRV

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

56-Pin Thin QFN (derate 47.6mW/°C above +70°C)...3809.5mW

Operating Temperature Range ...........................-40°C to +85°C

Thermal Resistance

...................................................21°C/W

Junction Temperature ......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AV

= 5V, DV

= DRV

= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially

with a 2V

P-P

sinusoidal input signal, C

= 5pF at digital outputs, f

CLK

= 100MHz, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical

values are at T

= +25°C, unless otherwise noted.

≥+25°C

guaranteed by production test, <+25°C guaranteed by design and char-

acterization.)

PARAMETER

DC ACCURACY

Resolution

Integral Nonlinearity

Differential Nonlinearity

Offset Error

Gain Error

ANALOG INPUT (INP, INN)

Differential Input Voltage Range

Common-Mode Input Voltage

Differential Input Resistance

Differential Input Capacitance

Full-Power Analog Bandwidth

CONVERSION RATE

Maximum Clock Frequency

Minimum Clock Frequency

Aperture Jitter

CLOCK INPUT (CLKP, CLKN)

Full-Scale Differential Input

Voltage

Common-Mode Input Voltage

Differential Input Resistance

Differential Input Capacitance

DYNAMIC CHARACTERISTICS

Thermal + Quantization Noise

Floor

Analog input <-35dBFS

-77.7

dBFS

DIFFCLK

INCLK

Fully differential input drive, V

CLKP

- V

CLKN

Self-biased

0.5 to

3.0

2.4

±15%

kΩ

CLK

100

0.21

MHz

RMS

DIFF

FPBW

-1dB

-1dB rolloff for a full-scale input

Fully differential inputs drive,

DIFF

= V

INP

- V

INN

Self-biased

2.20

3.33

±15%

260

P-P

kΩ

MHz

INL

DNL

= 15MHz

= 15MHz, no missing codes guaranteed

-12

-4

±1.5

±0.4

+12

Bits

LSB

%FS

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

_______________________________________________________________________________________

15-Bit, 100Msps ADC with -77.7dBFS

Noise Floor for Baseband Applications

ELECTRICAL CHARACTERISTICS (continued)

(AV

= 5V, DV

= DRV

= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially

with a 2V

P-P

sinusoidal input signal, C

= 5pF at digital outputs, f

CLK

= 100MHz, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical

values are at T

= +25°C, unless otherwise noted.

≥+25°C

guaranteed by production test, <+25°C guaranteed by design and char-

acterization.)

PARAMETER

Signal-to-Noise

Ratio (Note 1)

Signal-to-Noise

and Distortion

(Note 1)

Spurious-Free Dynamic Range

(HD2 and HD3)

(Note 1)

Spurious-Free Dynamic Range

(HD4 and Higher)

(Note 1)

Two-Tone Intermodulation

Distortion

Two-Tone Spurious-Free

Dynamic Range

Digital Output-Voltage Low

Digital Output-Voltage High

SYMBOL

SNR

CONDITIONS

= 5MHz at -1dBFS

= 15MHz at -1dBFS

= 35MHz at -1dBFS

= 5MHz at -1dBFS

SINAD

= 15MHz at -1dBFS

= 35MHz at -1dBFS

= 5MHz at -1dBFS

SFDR1

= 15MHz at -1dBFS

= 35MHz at -1dBFS

= 5MHz at -1dBFS

SFDR2

= 15MHz at -1dBFS

= 35MHz at -1dBFS

TTIMD

SFDR

IN1

= 10MHz at -7dBFS,

IN2

= 15MHz at -7dBFS

IN1

= 10MHz at -10dBFS < f

IN1

< -100dBFS,

IN2

= 15MHz at -10dBFS < f

IN2

< -100dBFS

85.0

84.0

71.7

72.1

MIN

TYP

75.3

75.1

74.8

75.0

74.9

71.1

90.0

74.0

96.0

94.0

92.0

-85

-100

dBc

dBFS

dBc

MAX

UNITS

MAX1429

DIGITAL OUTPUTS (D0–D14, DAV, DOR)

DRV

- 0.5

0.5

TIMING CHARACTERISTICS (DV

= DRV

= 2.5V)

CLKP/CLKN Duty Cycle

Effective Aperture Delay

Output Data Delay

Data Valid Delay

Pipeline Latency

CLKP Rising Edge to DATA Not

Valid

CLKP Rising Edge to DATA Valid

(guaranteed)

DATA Setup Time (Before DAV

Rising Edge)

DATA Hold Time (After DAV

Rising Edge)

Duty Cycle

DAT

DAV

LATENCY

DNV

DGV

SETUP

HOLD

(Note 3)

2.6

3.4

CLKP

- 0.5

CLKN

3.6

3.0

5.3

±5

230

4.5

6.5

3.8

5.2

CLKP

+ 1.3

CLKN

2.8

5.7

8.6

CLKP

2.4

CLKN

2.0

7.5

8.7

Clock

cycles

_______________________________________________________________________________________

15-Bit, 100Msps ADC with -77.7dBFS

Noise Floor for Baseband Applications

MAX1429

ELECTRICAL CHARACTERISTICS (continued)

(AV

= 5V, DV

= DRV

= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially

with a 2V

P-P

sinusoidal input signal, C

= 5pF at digital outputs, f

CLK

= 100MHz, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical

values are at T

= +25°C, unless otherwise noted.

≥+25°C

guaranteed by production test, <+25°C guaranteed by design and char-

acterization.)

PARAMETER

CLKP/CLKN Duty Cycle

Effective Aperture Delay

Output Data Delay

Data Valid Delay

Pipeline Latency

CLKP Rising Edge to DATA Not

Valid

CLKP Rising Edge to DATA Valid

(guaranteed)

DATA Setup Time (Before DAV

Rising Edge)

DATA Hold Time (After DAV

Rising Edge)

POWER REQUIREMENTS

Analog Supply Voltage Range

Digital-Supply Voltage Range

Output-Supply Voltage Range

Analog Supply Current

Digital + Output Supply Current

Total Power Dissipation

DRV

AVCC

DVCC

DRVCC

PDISS

CLK

= 100MHz, C

= 5pF

(Note 2)

±3%

2.3 to

2.5

2.3 to

2.5

390

2045

440

SYMBOL

Duty Cycle

DAT

DAV

LATENCY

DNV

DGV

SETUP

HOLD

(Note 3)

2.5

3.2

(Note 3)

2.8

5.3

CONDITIONS

MIN

TYP

±5

230

4.1

6.3

3.4

4.4

5.2

7.4

6.5

8.6

MAX

UNITS

Clock

cycles

TIMING CHARACTERISTICS (DV

= DRV

= 3.3V)

CLKP

+ t

CLKP

+ t

CLKP

0.2

1.7

2.8

CLKN

3.5

CLKN

2.7

CLKN

2.0

Note 1:

Dynamic performance is based on a 32,768-point data record with a sampling frequency of f

SAMPLE

= 100.007936MHz, an

input frequency of f

= f

SAMPLE

x (4915/32768) = 15.000580MHz, and a frequency bin size of 3052Hz. Close-in (f

36.6kHz) and low-frequency (DC to 73.2kHz) bins are excluded from the spectrum analysis.

Note 2:

Apply the same voltage levels to DV

and DRV

Note 3:

Guaranteed by design and characterization.

_______________________________________________________________________________________

15-Bit, 100Msps ADC with -77.7dBFS

Noise Floor for Baseband Applications

MAX1429

Typical Operating Characteristics

(AV

= 5V, DV

= DRV

= 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially

with a 2V

P-P

sinusoidal input signal, C

= 5pF at digital outputs, f

CLK

= 100MHz, T

= +25°C. All AC data is based on a 32k-point

FFT record and under coherent sampling conditions.)

FFT PLOT (32,768-POINT DATA RECORD,

COHERENT SAMPLING)

MAX1429 toc01

-20

AMPLITUDE (dBFS)

-40

-60

-80

-100

-120

AMPLITUDE (dBFS)

CLK

= 100.0997MHz

= 10.0014MHz

= -1.05dBFS

SNR = 75.6dBc

SINAD = 75.4dBc

SFDR1 = 90dBc

SFDR2 = 96.4dBc

HD2 = -91dBFS

HD3 = -95.5dBFS

-20

-40

-60

-80

-100

-120

CLK

= 100.0997MHz

= 15.0021MHz

= -0.96dBFS

SNR = 75.3dBc

SINAD = 74.8dBc

SFDR1 = 86.7dBc

SFDR2 = 93.9dBc

HD2 = -87.6dBFS

HD3 = -90.2dBFS

MAX1429 toc02

-20

-40

-60

-80

-100

-120

CLK

= 100.0997MHz

= 34.9973MHz

= -1.01dBFS

SNR = 75dBc

SINAD = 70.6dBc

SFDR1 = 73dBc

SFDR2 = 93.9dBc

HD2 = -83.6dBFS

HD3 = -74dBFS

10 15 20 25 30 35 40 45 50

ANALOG INPUT FREQUENCY (MHz)

10 15 20 25 30 35 40 45 50

ANALOG INPUT FREQUENCY (MHz)

10 15 20 25 30 35 40 45 50

ANALOG INPUT FREQUENCY (MHz)

TWO-TONE IMD PLOT (32,768-POINT DATA

RECORD, COHERENT SAMPLING)

MAX1429 toc04

SNR vs. ANALOG INPUT FREQUENCY

CLK

= 100.0997MHz, A

= -1dBFS)

MAX1429 toc05

SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY

CLK

= 100.0997MHz, A

= -1dBFS)

MAX1429 toc06

-20

AMPLITUDE (dBFS)

-40

-60

IN2

- f

IN1

-80

-100

-120

IN1

+ f

IN2

IN1

IN2

CLK

= 100.0997MHz

IN1

= 10.1022MHz

IN1

= -7.09dBFS

IN2

= 15.0021MHz

IN2

= -7dBFS

IMD = -84.9dBc

SNR (dBc)

115

105

SFDR1/SFDR2 (dBc)

SFDR1

SFDR2

10 15 20 25 30 35 40 45 50

ANALOG INPUT FREQUENCY (MHz)

(MHz)

HD2/HD3 vs. ANALOG INPUT FREQUENCY

CLK

= 100.0997MHz, A

= -1dBFS)

MAX1429 toc07

SNR vs. SAMPLING FREQUENCY

= 15MHz, A

= -1dBFS)

MAX1429 toc08

SFDR1/SFDR2 vs. SAMPLING FREQUENCY

= 15MHz, A

= -1dBFS)

100

SFDR1/SFDR2 (dBc)

SFDR2

MAX1429 toc09

-65

-70

-75

HD2/HD3 (dBFS)

-80

-85

-90

-95

-100

-105

HD2

HD3

SNR (dBc)

105

SFDR1

100

(MHz)

CLK

(MHz)

CLK

(MHz)

_______________________________________________________________________________________

MAX1429 toc03

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