MAX1455AUE+ [MAXIM]
Analog Circuit, 1 Func, CMOS, PDSO16, 4.40 MM, TSSOP-16;
| 型号： | MAX1455AUE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO16, 4.40 MM, TSSOP-16 光电二极管 |
| 文件： | 总25页 (文件大小：1000K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX1455
Low-Cost Precision Sensor Signal Conditioner
General Description
Features
● Provides Amplification, Calibration, and Temperature
The MAX1455 is a highly integrated, sensor signal pro-
cessor for resistive element sensors. The MAX1455 pro-
vides amplification, calibration, and temperature compen-
sation that enable an overall performance approaching
the inherent repeatability of the sensor. The fully analog
signal path introduces no quantization noise in the output
signal while enabling digitally controlled trimming with
integrated 16-bit digital-to-analog converters (DACs).
Offset and span are also calibrated using 16-bit DACs,
allowing sensor products to be truly interchangeable.
Compensation
● Selectable Output Clipping Limits
● Accommodates Sensor Output Sensitivities
from 5mV/V to 40mV/V
● Single-Pin Digital Programming
● No External Trim Components Required
● 16-Bit Offset and Span Calibration Resolution
● Fully Analog Signal Path
● PRT Bridge Can Be Used for Temperature-Correction
The MAX1455 architecture includes a programmable
sensor excitation, a 16-step programmable-gain amplifier
(PGA), a 768-byte (6144 bits) internal EEPROM, four 16-bit
DACs, an uncommitted op amp, and an on-chip tempera-
ture sensor. In addition to offset and span compensation,
the MAX1455 provides a unique temperature compensa-
tion strategy that was developed to provide a remarkable
degree of flexibility while minimizing testing costs.
Input
● On-Chip Lookup Table Supports Multipoint
Calibration Temperature Correction
● Fast 3.2kHz Frequency Response
● On-Chip Uncommitted Op Amp
● Secure-Lock™ Prevents Data Corruption
The MAX1455 is available in die form, and in 16-pin
SSOP and TSSOP packages.
Ordering Information
PART
TEMP. RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 SSOP
MAX1455AAE
MAX1455AUE*
MAX1455EAE
MAX1455EUE*
MAX1455C/D
Customization
16 TSSOP
16 SSOP
Maxim can customize the MAX1455 for high-volume
dedicated applications. Using our dedicated cell library of
more than 2000 sensor-specific function blocks, Maxim
can quickly provide a modified MAX1455 solution. Contact
Maxim for further information.
16 TSSOP
Dice**
*Future Product—Contact factory for availability.
*Dice are tested at T = +25°C, DC parameters only.
A
Applications
● Pressure Sensors and Transducers
● Piezoresistive Silicon Sensors
● Strain Gauges
Pin Configuration
TOP VIEW
● Resistive Element Sensors
● Accelerometers
● Humidity Sensors
TEST1
OUT
INP
1
2
3
4
5
6
7
8
16 TEST2
15 TEST3
14 TEST4
13 DIO
● MR and GMR Sensors
MAX1455
BDR
INM
Outputs
● Ratiometric Voltage Output
● Programmable Output Clip Limits
12 UNLOCK
V
11
10 AMP-
AMPOUT
V
SS
DD2
V
DD1
A detailed Functional Diagram appears at end of data sheet.
AMP+
9
Secure-Lock is a trademark of Maxim Integrated Products, Inc.
SSOP/TSSOP
19-2088; Rev 2; 5/14
MAX1455
Low-Cost Precision Sensor Signal Conditioner
Absolute Maximum Ratings
Supply Voltage, V
to V ..................................... -0.3V, +6V
Operating Temperature Ranges (T
to T
)
MAX
DD_
SS
MIN
V
- V
............................................................ -0.3V, +0.6V
MAX1455C/D.................................................. -40°C to +85°C
MAX1455EAE................................................. -40°C to +85°C
MAX1455AAE............................................... -40°C to +125°C
MAX1455EUE................................................. -40°C to +85°C
MAX1455AUE............................................... -40°C to +125°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
DD1
DD2
All Other Pins .............................. (V - 0.3V) to (V
Short-Circuit Duration, OUT, BDR, AMPOUT............Continuous
Continuous Power Dissipation (T = +70°C)
+ 0.3V)
SS
DD_
A
16-Pin SSOP (derate 8.00mW/°C above +70°C)........640mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
= +5V, V = 0V, T = +25°C, unless otherwise noted.)
SS A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
4.5
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Supply Voltage
V
5.0
3.0
1
5.5
6.0
V
DD
Supply Current
I
I
+ I
(Note 1)
mA
MHz
DD
DD1
DD2
Oscillator Frequency
ANALOG INPUT
f
0.85
1.15
OSC
Input Impedance
R
1
MΩ
IN
Input-Referred Adjustable Offset
Range
Offset TC = 0 (Note 2), minimum gain
= T to T
±150
mV
Input-Referred Offset Tempco
T
±1
µV/°C
%
A
MIN
MAX
Amplifier Gain Nonlinearity
0.025
Specified for common-mode voltages
Common-Mode Rejection Ratio
CMRR
90
7
dB
between V and V
SS
DD
Minimum Input-Referred FSO
Range
(Note 3)
(Note 3)
mV/V
mV/V
Maximum Input-Referred FSO
Range
40
ANALOG OUTPUT
Minimum Differential Signal-Gain
Range
PGA [3:0] = 0000
PGA [3:0] = 1111
39
V/V
V/V
Maximum Differential Signal-
Gain Range
234
Low
High
Low
High
Low
High
Low
High
0.10
4.90
0.15
4.85
0.20
4.80
0.25
4.75
Clip[1:0] = 00
Clip[1:0] = 01
Clip[1:0] = 10
Clip[1:0] = 11
No load,
Output Clip Voltage Settings
V
V
OUT
T
= T
to T
A
MIN MAX
V
=+0.5V to +4.5V, T = T
to T
,
MAX
OUT
A
MIN
Load Current Source
1
mA
Clip[1:0] = 00
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Electrical Characteristics (continued)
(V
= +5V, V = 0V, T = +25°C, unless otherwise noted.)
DD
SS A
PARAMETER
SYMBOL
CONDITIONS
=+0.5V to +4.5V, T = T
Clip[1:0] = 00
MIN
TYP
MAX
UNITS
V
to T
,
MAX
OUT
A
MIN
Load Current Sink
2
mA
DC Output Impedance
Offset DAC Output Ratio
Offset TC DAC Output Ratio
Step Response
1
Ω
DV
DV
/DODAC
1.0
1.0
300
V/V
V/V
µs
OUT
/DOTCDAC
OUT
0% to 63% of final value
Output Capacitive Load
1000
nF
DC to 1kHz (gain = minimum, source
impedance = 5kΩ)
Output Noise
2.5
mV
RMS
BRIDGE DRIVE
Bridge Current
I
V
≤ 3.75V
BDR
0.1
0.5
12
2
mA
BDR
Current Mirror Ratio
Minimum FSODAC Code
mA/mA
Hex
Recommended minimum value
4000
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
16
Bits
DV
/DCODE, DAC reference = V
=
DD
OUT
ODAC Bit Weight
153
µV/Bit
+5.0V (Note 4)
DV /DCODE, DAC reference = V
2.5V (Note 4)
=
=
OUT
BDR
OTCDAC Bit Weight
FSODAC Bit Weight
FSOTCDAC Bit Weight
76
153
76
µV/Bit
µV/Bit
µV/Bit
DV /DCODE, DAC reference = V
=
OUT
DD
+5.0V (Note 4)
DV /DCODE, DAC reference = V
OUT
BDR
2.5V (Note 4)
COARSE-OFFSET DAC
IRODAC Resolution
Excluding sign bit
3
9
Bits
DV
/DCODE, input referred,
OUT
IRODAC Bit Weight
mV/Bit
DAC reference = V
= +5.0V (Note 4)
DD
INTERNAL RESISTORS
Current-Source Reference
R
75
75
kΩ
kΩ
ISRC
Full-Span Output (FSO) Trim
Resistor
∆R
STC
Resistor Temperature Coefficient
Minimum Resistance Value
Maximum Resistance Value
Resistor Matching
Applies to R
Applies to R
Applies to R
and DR
and DR
and DR
1333
60
ppm/°C
kΩ
ISRC
ISRC
ISRC
STC
STC
STC
90
kΩ
R
to DR
1
%
ISRC
STC
AUXILIARY OP AMP
Open-Loop Gain
90
dB
V
Input Common-Mode Range
V
V
V
DD
CM
SS
V
0.01
+
V
0.01
-
SS
DD
Output Swing
No load, T = T
to T
V
A
MIN
MAX
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Electrical Characteristics (continued)
(V
= +5V, V = 0V, T = +25°C, unless otherwise noted.)
DD
SS A
PARAMETER
SYMBOL
CONDITIONS
= (V + 0.25) to (V
MIN
TYP
MAX
UNITS
mA
Output Current Drive
V
V
- 0.25)
DD
-1
+1
OUT
SS
Common-Mode Rejection Ratio
CMRR
= V to V
70
±1
dB
CM
SS
DD
T
T
= +25°C
±20
A
V
= 2.5V unity-gain
buffer (Note 5)
IN
Input Offset Voltage
V
mV
OS
= T
to T
MAX
±25
A
MIN
Unity-Gain Bandwidth
2
MHz
TEMPERATURE-TO-DIGITAL CONVERTER
Temperature ADC Resolution
Offset
8
±3
Bits
Bits
Gain
1.45
±1
°C/Bit
LSB
Hex
Nonlinearity
Lowest Digital Output
Highest Digital Output
EEPROM
00
AF
Hex
Maximum Erase/Write Cycles
Erase Time
(Notes 6, 7)
(Note 8)
10k
Cycles
ms
7.1
Note 1: Excludes sensor or load current.
Note 2: This is the maximum allowable sensor offset.
Note 3: This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output of 4V and a bridge volt-
age of 2.5V.
Note 4: Bit weight is ratiometric to V
.
DD
Note 5: All units production tested at T = +25°C. Limits over temperature are guaranteed by design.
A
Note 6: Programming of the EEPROM at temperatures below +70°C is recommended.
Note 7: For operation above +70°C, limit erase/write cycle to 100.
Note 8: All erase commands require 7.1ms minimum time.
Typical Operating Characteristics
(V
= +5V, V = 0V, T = +25°C, unless otherwise noted.)
SS A
DD_
OFFSET DAC DNL
AMPLIFIER GAIN NONLINEARITY
OUTPUT NOISE
2.5
2.0
1.5
1.0
0.5
0
5.0
2.5
0
INP - INM SHORTED TOGETHER
PGA = 0HEX
ODAC = +6000HEX
OTCDAC = 0
FSODAC = 6000HEX
FSOTCDAC = 8000HEX
IRO = 2HEX
PGA = 0
OUT
10mV/div
-0.5
-1.0
-1.5
-2.0
-2.5
-2.5
-5.0
0
10k 20k 30k 40k 50k 60k 70k
DAC CODE
-50
-30
-10
10
30
50
400µs/div
INPUT VOLTAGE [INP - INM] (mV)
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Pin Description
PIN
NAME
FUNCTION
TEST1,
TEST3,
TEST2
1, 15, 16
Test Pins. Connect to V or leave unconnected.
SS
Analog Output. Internal voltage nodes can be accessed in digital mode. OUT can be parallel
connected to DIO. Bypass OUT to ground with a 0.1µF capacitor to reduce output noise.
2
OUT
3
4
INP
BDR
INM
Positive Input. Can be swapped to INM by the Configuration register.
Bridge Drive Output
5
Negative Input. Can be swapped to INP by the Configuration register.
Negative Supply Voltage
6
V
SS
7
V
Positive Supply Voltage 1. Connect a 0.1µF capacitor from V
Auxiliary Op Amp Positive Input
to V
.
DD1
DD
SS
8
AMP+
AMPOUT
AMP-
9
Auxiliary Op Amp Output
10
Auxiliary Op Amp Negative Input
Positive Supply Voltage 2. Connect a 0.47µF capacitor from V
to V . Connect V
to V
or
DD2
.
SS
DD2
DD1
11
12
V
DD2
for improved noise performance, connect a 1kΩ resistor to V
DD1
Secure-Lock Disable. There is a 150µA pulldown to V . Connect to V
SS
and enable serial communication.
to disable Secure-Lock
DD
UNLOCK
Digital Input Output. Single-pin serial communication port. There are no internal pullups on DIO.
13
14
DIO
Connect pullup resistor from DIO to V
when in digital mode.
DD
TEST4
Test Pin. Do not connect.
perature increments over a range of -40°C to +125°C.
For sensors that exhibit a characteristic temperature
performance, a select number of calibration points can
be used with a number of preset values that define the
temperature curve. The sensor and the MAX1455 should
be at the same temperature during calibration and use.
This allows the electronics and sensor errors to be com-
pensated together and optimizes performance. For appli-
cations where the sensor and electronics are at different
temperatures, the MAX1455 can use the sensor bridge as
an input to correct for temperature errors.
Detailed Description
The MAX1455 provides amplification, calibration, and tem-
perature compensation to enable an overall performance
approaching the inherent repeatability of the sensor. The
fully analog signal path introduces no quantization noise
in the output signal while enabling digitally controlled
trimming with the integrated 16-bit DACs. The MAX1455
includes four selectable high/low clipping limits set in dis-
crete 50mV steps from 0.1V/4.9V to 0.25V/4.75V. Offset
and span can be calibrated to within ±0.02% of span.
The MAX1455 architecture includes a programmable
sensor excitation, a 16-step PGA, a 768-byte (6144 bits)
internal EEPROM, four 16-bit DACs, an uncommitted op
amp, and an on-chip temperature sensor. The MAX1455
also provides a unique temperature compensation strat-
egy that was developed to provide a remarkable degree
of flexibility while minimizing testing costs.
The single pin, serial DIO communication architecture
and the ability to timeshare its activity with the sensor’s
output signal enables output sensing and calibration
programming on a single line by parallel connecting OUT
and DIO. The MAX1455 provides a Secure-Lock feature
that allows the customer to prevent modification of sen-
sor coefficients and the 52-byte user-definable EEPROM
data after the sensor has been calibrated. The Secure-
Lock feature also provides a hardware override to enable
factory rework and recalibration by assertion of logic high
on the UNLOCK pin.
The customer can select from 1 to 114 temperature
points to compensate their sensor. This allows the
latitude to compensate a sensor with a simple first-
order linear correction or match an unusual tempera-
ture curve. Programming up to 114 independent 16-bit
EEPROM locations corrects performance in 1.5°C tem-
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
The MAX1455 allows complete calibration and sensor
verification to be performed at a single test station. Once
calibration coefficients have been stored in the ASIC, the
customer can choose to retest in order to verify perfor-
mance as part of a regular QA audit or to generate final
test data on individual sensors. In addition, Maxim has
developed a pilot production test system to reduce time
to market. Engineering test evaluation and pilot produc-
tion of the MAX1455 can be performed without expending
the cost and time to develop in-house test capabilities.
Contact Maxim for additional information.
BIAS
GENERATOR
TEST 1
TEST 2
TEST 3
TEST 4
MAX1455
IRO
DAC
OSCILLATOR
CLIP-TOP
INP
INM
PGA
OUT
Σ
CLIP-BOT
CURRENT
SOURCE
ANAMUX
Frequency response can be user adjusted to values lower
than the 3.2kHz bandwidth by using the uncommitted op
amp and simple passive components.
BDR
TEMP
SENSOR
176-POINT
TEMPERATURE-
INDEXED
The MAX1455 (Figure 1) provides an analog amplification
path for the sensor signal. It uses a digitally controlled
analog path for nonlinear temperature correction. For
PRT applications, analog architecture is available for first-
order temperature correction. Calibration and correction
are achieved by varying the offset and gain of a PGA and
by varying the sensor bridge excitation current or voltage.
The PGA utilizes a switched capacitor CMOS technology,
with an input-referred offset trimming range of more than
±150mV with an approximate 3µV resolution (16 bits).
The PGA provides gain values from 39V/V to 234V/V in
16 steps.
FSO
COEFFICIENTS
8-BIT A/D
176-POINT
TEMPERATURE-
INDEXED
OFFSET
COEFFICIENTS
416 BITS FOR
USER DATA
CONFIG REG
V
DD1
V
DD2
AMP-
CONTROL
DIO
AMPOUT
UNLOCK
6144-BIT
EEPROM
V
SS
AMP+
Figure 1. Functional Diagram
The MAX1455 uses four 16-bit DACs with calibration
coefficients stored by the user in an internal 768 x 8
EEPROM (6144 bits). This memory contains the following
information, as 16-bit-wide words:
to +125°C. Every millisecond, the on-chip temperature
sensor provides indexing into the offset lookup table in
EEPROM and the resulting value is transferred to the
offset DAC register. The resulting voltage is fed into a
summing junction at the PGA output, compensating the
sensor offset with a resolution of ±76µV (±0.0019% FSO).
If the offset TC DAC is set to zero, then the maximum
temperature error is equivalent to 1°C of temperature drift
of the sensor, given that the Offset DAC has corrected the
sensor every 1.5°C. The temperature indexing boundar-
ies are outside the specified absolute maximum ratings.
The minimum indexing value is 00hex, corresponding to
approximately -69°C. All temperatures below this value
output the coefficient value at index 00hex. The maximum
indexing value is AFhex, which is the highest lookup table
entry. All temperatures higher than approximately +184°C
output the highest lookup table index value. No indexing
wraparound errors are produced.
•
•
•
•
•
•
Configuration register
Offset calibration coefficient table
Offset temperature coefficient register
FSO calibration coefficient table
FSO temperature correction register
52 bytes (416 bits) uncommitted for customer pro-
gramming of manufacturing data (e.g., serial number
and date)
Offset Correction
Initial offset correction is accomplished at the input stage
of the signal gain amplifiers by a coarse offset setting.
Final offset correction occurs through the use of a temper-
ature-indexed lookup table with one hundred seventy-six
16-bit entries. The on-chip temperature sensor provides
a unique 16-bit offset trim value from the table with an
indexing resolution of approximately 1.5°C from -40°C
FSO Correction
Two functional blocks control the FSO gain calibration.
First, a coarse gain is set by digitally selecting the gain
of the PGA. Second, FSODAC sets the sensor bridge
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
current or voltage with the digital input obtained from a
temperature indexed reference to the FSO lookup table
in EEPROM. FSO correction occurs through the use of a
temperature indexed lookup table with one hundred sev-
enty-six 16-bit entries. The on-chip temperature sensor
provides a unique FSO trim from the table with an index-
ing resolution approaching one 16-bit value every 1.5°C
from -40°C to +125°C. The temperature indexing bound-
aries are outside the specified absolute maximum ratings.
The minimum indexing value is 00hex, corresponding to
approximately -69°C. All temperatures below this value
output the coefficient value at index 00hex. The maximum
indexing value is AFhex, which is the highest lookup table
entry. All temperatures higher than approximately +184°C
output the highest lookup table index value. No indexing
wraparound errors are produced.
ed with the offset TC and FSOTC DACs, and the residual
higher order terms with the lookup table. The offset and
FSO compensation DACs provide unique compensation
values for approximately 1.5°C of temperature change
as the temperature indexes the address pointer through
the coefficient lookup table. Changing the offset does not
affect the FSO; however, changing the FSO affects the
offset due to the nature of the bridge. The temperature
is measured on both the MAX1455 die and at the bridge
sensor. It is recommended to compensate the first-order
temperature errors using the bridge sensor temperature.
Typical Ratiometric Operating Circuit
Ratiometric output configuration provides an output that is
proportional to the power-supply voltage. This output can
then be applied to a ratiometric ADC to produce a digital
value independent of supply voltage. Ratiometricity is an
important consideration for battery-operated instruments,
automotive, and some industrial applications.
Linear and Nonlinear Temperature
Compensation
Writing 16-bit calibration coefficients into the offset TC
and FSOTC registers compensates first-order tempera-
ture errors. The piezoresistive sensor is powered by a
current source resulting in a temperature-dependent
bridge voltage due to the sensor’s temperature coefficient
resistance (TCR). The reference inputs of the offset TC
DAC and FSOTC DAC are connected to the bridge volt-
age. The DAC output voltages track the bridge voltage
as it varies with temperature, and by varying the offset
TC and FSOTC digital code and a portion of the bridge
voltage, which is temperature dependent, is used to com-
pensate the first-order temperature errors.
The MAX1455 provides a high-performance ratiometric
output with a minimum number of external components
(Figure 2). These external components include the fol-
lowing:
•
•
One supply bypass capacitor
One optional output EMI suppression capacitor
Typical Nonratiometric Operating Circuit
(5.5VDC < VPWR < 28VDC)
Nonratiometric output configuration enables the sensor
power to vary over a wide range. A low-dropout volt-
age regulator, such as the MAX1615, is incorporated in
the circuit to provide a stable supply and reference for
MAX1455 operation. A typical example is shown in Figure
3. Nonratiometric operation is valuable when wide ranges
of input voltage are to be expected and the system A/D
or readout device does not enable ratiometric operation.
The internal feedback resistors (R
and R
) for
STC
ISRC
FSO temperature compensation are set to 75kΩ.
To calculate the required offset TC and FSOTC compen-
sation coefficients, two test temperatures are needed.
After taking at least two measurements at each tempera-
ture, calibration software (in a host computer) calculates
the correction coefficients and writes them to the internal
EEPROM.
Internal Calibration Registers
The MAX1455 has five 16-bit internal calibration registers
(ICRs) that are loaded from EEPROM, or loaded from the
serial digital interface.
With coefficients ranging from 0000hex to FFFFhex and a
+5V reference, each DAC has a resolution of 76µV. Two
of the DACs (offset TC and FSOTC) utilize the sensor
bridge voltage as a reference. Since the sensor bridge
voltage is approximately set to +2.5V, the FSOTC and
offset TC exhibit a step size of less than 38µV.
Data can be loaded into the ICRs under three different
circumstances.
Normal Operation, Power-On Initialization Sequence:
For high-accuracy applications (errors less than 0.25%),
the first-order offset TC and FSOTC should be compensat-
•
The MAX1455 has been calibrated, the Secure-Lock
byte is set (CL[7:0] = FFhex), and UNLOCK is low.
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
+5V V
OUT
DD
7
V
DD1
4
3
11
2
BDR
INP
V
DD2
OUT
MAX1455
5
SENSOR
INM
0.1µF
0.1µF
V
SS
6
GND
Figure 2. Basic Ratiometric Output Configuration
1
VPWR
IN
MAX1615
+5.5V TO +28V
5
4
SHDN
5/3
3
OUT
GND
2
7
1kΩ
V
DD1
4
5
11
2
V
DD2
BDR
INM
OUT
MAX1455
OUT
3
SENSOR
INP
0.1µF
0.1µF
0.1µF
0.47µF
V
SS
6
GND
Figure 3. Basic Nonratiometric Output Configuration
•
•
Power is applied to the device.
•
•
•
Power is applied to the device.
The power-on reset (POR) functions have been com-
pleted.
The POR functions have been completed.
The temperature index timer reaches a 1ms time
period.
•
•
Registers CONFIG, OTCDAC, and FSOTCDAC are
refreshed from EEPROM.
•
•
Registers CONFIG, OTCDAC, and FSOTCDAC are
refreshed from EEPROM.
Registers ODAC and FSODAC are refreshed from the
temperature indexed EEPROM locations.
Registers ODAC and FSODAC are refreshed from the
temperature indexed EEPROM locations.
Normal Operation, Continuous Refresh:
•
The MAX1455 has been calibrated, the Secure-Lock byte
has been set (CL[7:0] = FFhex), and UNLOCK is low.
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Calibration Operation, Registers Updated by Serial
Communications:
where temp-index is truncated to an 8-bit integer value.
Typical values for the temp-index register are given in
Table 4.
•
The MAX1455 has not had the Secure-Lock byte set
(CL[7:0] = 00hex) or UNLOCK is high.
Note that the EEPROM is 1 byte wide and the registers
that are loaded from EEPROM are 16 bits wide. Thus,
each index value points to 2 bytes in the EEPROM.
•
•
•
Power is applied to the device.
The POR functions have been completed.
Maxim programs all EEPROM locations to FFhex with
the exception of the oscillator frequency setting and
Secure-Lock byte. OSC[2:0] is in the Configuration
register (Table 5). These bits should be maintained at the
factory-preset values. Programming 00hex in the Secure-
Lock byte (CL[7:0] = 00hex) configures the DIO as an
asynchronous serial input for calibration and test purposes.
The registers can then be loaded from the serial digital
interface by use of serial commands. See the section
on serial I/O and commands.
Internal EEPROM
The internal EEPROM is organized as a 768 by 8-bit
memory. It is divided into 12 pages, with 64 bytes
per page. Each page can be individually erased. The
memory structure is arranged as shown in Table 1. The
look-up tables for ODAC and FSODAC are also shown,
with the respective temperature index pointer. Note
that the ODAC table occupies a continuous segment,
from address 000hex to address 15Fhex, whereas the
FSODAC table is divided in two parts, from 200hex to
2FFhex, and from 1A0hex to 1FFhex. With the exception
of the general-purpose user bytes, all values are 16-bit-
wide words formed by two adjacent byte locations (high
byte and low byte).
MAX1455 Digital Mode
A single-pin serial interface provided by the DIO accesses
the MAX1455’s control functions and memory. All com-
mand inputs to this pin flow into a set of 16 registers,
which form the interface register set (IRS). Additional lev-
els of command processing are provided by control logic,
which takes its inputs from the IRS. A bidirectional 16-bit
latch buffers data to and from the 16-bit Calibration regis-
ters and internal (8-bit-wide) EEPROM locations. Figure
5 shows the relationship between the various serial com-
mands and the MAX1455 internal architecture.
The MAX1455 compensates for sensor offset, FSO, and
temperature errors by loading the internal calibration
registers with the compensation values. These compen-
sation values can be loaded to registers directly through
the serial digital interface during calibration or loaded
automatically from EEPROM at power-on. In this way, the
device can be tested and configured during calibration
and test and the appropriate compensation values stored
in internal EEPROM. The device autoloads the registers
from EEPROM and is ready for use without further con-
figuration after each power-up. The EEPROM is configured
as an 8-bit-wide array so each of the 16-bit registers is
stored as two 8-bit quantities. The Configuration register,
FSOTCDAC, and OTCDAC registers are loaded from
the preassigned locations in the EEPROM. Table 2 is the
EEPROM ODAC and FSODAC lookup table memory map.
Communication Protocol
The DIO serial interface is used for asynchronous serial
data communications between the MAX1455 and a host
calibration test system or computer. The MAX1455 auto-
matically detects the baud rate of the host computer when
the host transmits the initialization sequence. Baud rates
between 4800 and 38400 can be detected and used. The
data format is always 1 start bit, 8 data bits, and 1 stop
bit. The 8 data bits are transmitted LSB first, MSB last. A
weak pullup resistor can be used to maintain logic 1 on
the DIO pin while the MAX1455 is in digital mode. This
is to prevent unintended 1 to 0 transitions on this pin,
which would be interpreted as a communication start bit.
Communications are only allowed when the Secure-Lock
byte is disabled (i.e., CL[7:0] = 00HEX ) or UNLOCK is
held high. Table 8 is the control location.
The ODAC and FSODAC are loaded from the EEPROM
lookup tables using an index pointer that is a function of
temperature. An ADC converts the integrated temperature
sensor to an 8-bit value every 1ms. This digitized value is
then transferred into the temp-index register. Table 3 lists
the registers.
Initialization Sequence
The first Command Byte sent to the MAX1455 after pow-
er-up, or following receipt of the reinitialization command,
is used by the MAX1455 to learn the communication baud
rate. The initialization sequence is a 1-byte transmiss of
01 hex, as follows:
The typical transfer function for the temp-index is as fol-
lows:
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
temp-index = 0.69 x Temperature (°C) + 47.58
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Table 1. EEPROM Memory Address Map
LOW-BYTE ADDRESS HIGH-BYTE ADDRESS
TEMP-INDEX[7:0]
(hex)
PAGE
CONTENTS
(hex)
(hex)
000
03E
040
07E
080
0BE
0C0
0FE
100
13E
140
15E
160
162
164
166
168
16A
16C
17E
180
19E
1A0
1BE
1C0
1FE
200
23E
240
27E
280
2BE
2C0
2FE
001
03F
041
07F
081
0BF
0C1
0FF
101
13F
141
15F
161
163
165
167
169
16B
16D
17F
181
19F
1A1
1BF
1C1
1FF
201
23F
241
27F
281
2BF
2C1
2FF
00
1F
0
1
2
3
4
20
3F
40
5F
ODAC
Lookup Table
60
7F
80
9F
A0
AF to FF
Configuration
Reserved
OTCDAC
5
Reserved
FSOTCDAC
Control Location
52 General-Purpose
User Bytes
6
80
8F
90
7
8
9
A
B
AF to FF
00
1F
FSODAC
Lookup Table
20
3F
40
5F
60
7F
The start bit, shown in bold above, initiates the baud rate
synchronization. The 8 data bits 01hex (LSB first) follow
this and then the stop bit, also shown in bold above. The
MAX1455 uses this sequence to calculate the time inter-
val for a 1-bit transmission as a multiple of the period of
its internal oscillator. The resulting number of oscillator
clock cycles is then stored internally as an 8-bit number
(BITCLK). Note that the device power supply should be
stable for a minimum period of 1ms before the initializa-
tion sequence is sent. This allows time for the POR func-
tion to complete and DIO to be configured by the Secure-
Lock byte or UNLOCK.
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Table 2. EEPROM ODAC and FSODAC Lookup Table Memory Map
EEPROM ADDRESS ODAC
LOW BYTE AND HIGH BYTE
EEPROM ADDRESS FSODAC
LOW BYTE AND HIGH BYTE
TEMP-INDEX[7:0]
00hex
to
000hex and 001hex
to
200hex and 201hex
to
7Fhex
0FEhex and 0FFhex
2FEhex and 2FFhex
80hex
to
100hex and 101hex
to
1A0hex and 1A1hex
to
AFhex
15Ehex and 15Fhex
1FEhex and 1FFhex
Table 3. Registers
REGISTER
CONFIG
DESCRIPTION
Configuration register
Offset DAC register
ODAC
OTCDAC
FSODAC
FSOTCDAC
Offset temperature coefficient DAC register
Full-span output DAC register
Full-span output temperature coefficient DAC register
Reinitialization Sequence
Table 4. Temp-Index Typical Values
The MAX1455 provides for reestablishing, or relearning,
the baud rate. The reinitialization sequence is a 1-byte
transmiss of FFhex, as follows:
TEMP-INDEX[7:0]
TEMPERATURE
(°C)
DECIMAL
HEXADECIMAL
-40
+25
20
14
41
6A
86
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
65
+85
106
When a serial reinitialization sequence is received, the
receive logic resets itself to its power-up state and waits
for the initialization sequence. The initialization sequence
must follow the reinitialization sequence in order to rees-
tablish the baud rate.
+125
134
WEAK PULLUP
REQUIRED
WEAK PULLUP
REQUIRED
DATA
DIO
0
0 0 0 0 0
0 0 0
0
1 1 1 1 1 1 1 1 1
X X
1 1 1 1 1 0 1 0 0 1 1 0 1
1 1 1 1 1 1 1 1 1 1
1
X X
HIGH-Z
RECEIVE
RECEIVE
TRANSMIT
RECEIVE
HIGH-Z
HIGH-Z
HOST
TRANSMIT
TRANSMIT
Figure 4. MAX1455 Serial Command Structure and Hardware Schematic
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Table 5. Configuration Register (CONFIG[15:0])
FIELD
15:13
12:11
10
NAME
DESCRIPTION
Oscillator frequency setting. Factory preset; do not change.
Sets output clip levels.
OSC[2:0]
CLIP[1:0]
PGA Sign
IRO Sign
IRO[2:0]
PGA[3:0]
Logic 1 inverts INM and INP polarity (Table 6).
Logic 1 for positive input-referred offset (IRO). Logic 0 for negative IRO.
Input-referred coarse-offset adjustment (Table 7).
Programmable-gain amplifier setting.
9
8:6
5:2
1
ODAC Sign Logic 1 for positive offset DAC output. Logic 0 for negative offset DAC output.
OTCDAC
0
Logic 1 for positive offset TC DAC output. Logic 0 for negative offset TC DAC output.
Sign
(IRSA) nibble and a 4-bit interface register set data (IRSD)
nibble. The IRS Command Byte is structured as follows:
Table 6. PGA Gain Setting (PGA[3:0])
PGA[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
PGA GAIN (V/V)
IRS[7:0] = IRSD[3:0], IRSA[3:0]
39
52
All commands are transmitted LSB first. The first bit fol-
lowing the start bit is IRSA[0] and the last bit before the
stop is IRSD[3] as follows:
65
IRSA
IRSD
78
1
1
1
1
1
0
1
2
3
0
1
2
3
1 1 1 1 1
1
0
91
Half of the register contents of the IRS are used for data
hold and steering information. Data writes to two locations
within the IRS cause immediate action (command execu-
tion). These locations are at addresses 9 and 15 and are
the Command Register to Internal Logic (CRIL) and reini-
tialize commands, respectively. Table 9 shows a full listing
of IRS address decoding.
104
117
130
143
156
169
182
195
208
221
234
1000
1001
1010
1011
1100
1101
1110
Command sequences can be written to the MAX1455
as a continuous stream, i.e., start bit, command byte,
stop bit, start bit, command byte, stop bit, etc. There are
no delay requirements between commands while the
MAX1455 is receiving data.
Command Register to Internal Logic
1111
A data write to the CRIL location (IRS address 9) causes
immediate execution of the command associated with
the 4-bit data nibble written. All EEPROM and Calibration
register read and write, together with EEPROM erase,
commands are handled through the CRIL location. CRIL
is also used to enable the MAX1455 analog output and to
place output data (serial digital output) on DIO. Table 10
shows a full listing of CRIL commands.
Serial Interface Command Format
All communication commands into the MAX1455 follow the
format of a start bit, 8 command bits (command byte), and
a stop bit. The Command Byte controls the contents of the
IRS and comprises a 4-bit interface register set address
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Table 7. Input Referred Offset (IRO[2:0])
INPUT-REFERRED OFFSET
CORRECTION AS % OF V
INPUT-REFERRED OFFSET, CORRECTION
IRO SIGN, IRO[2:0]
AT V
= 5VDC IN mV
DD
DD
1,111
1,110
1,101
1,100
1,011
1,010
1,001
1,000
0,000
0,001
0,010
0,011
0,100
0,101
0,110
0,111
+1.25
+1.08
+0.90
+0.72
+0.54
+0.36
+0.18
0
+63
+54
+45
+36
+27
+18
+9
0
0
0
-0.18
-0.36
-0.54
-0.72
-0.90
-1.08
-1.25
-9
-18
-27
-36
-45
-54
-63
Note that there are time intervals before and after the
MAX1455 sends the data byte when all devices on the
DIO line are three-stated. It is recommended that a weak
pullup resistor be applied to the DIO line during these time
intervals to prevent unwanted transitions (Figure 4). In
applications where DIO and analog output (OUT) are not
connected, a pullup resistor should be permanently con-
nected to DIO. If the MAX1455 DIO and analog outputs
are connected, then do not load this common line during
analog measurements. In this situation, perform the fol-
lowing sequence:
Serial Digital Output
DIO is configured as a digital output by writing a Read
IRS (RDIRS) command (5 hex) to the CRIL location. On
receipt of this command, the MAX1455 outputs a byte of
data, the contents of which are determined by the IRS
pointer (IRSP[3:0]) value at location IRSA[3:0] = 8hex.
The data is output as a single byte, framed by a start bit
and a stop bit. Table 11 lists the data returned for each
IRSP address value.
Once the RDIRS command has been sent, all connec-
tions to DIO must be three-stated to allow the MAX1455
to drive the DIO line. Following receipt of the RDIRS com-
mand, the MAX1455 drives DIO high after 1 byte time.
The MAX1455 holds DIO high for a single bit time and
then asserts a start bit (drives DIO low). The start bit is
then followed by the data byte and a stop bit. Immediately
following transmission of the stop bit, the MAX1455 three-
states DIO, releasing the line. The MAX1455 is then
ready to receive the next command sequence 1 byte time
after release of DIO.
1) Connect a pullup resistor to the DIO/OUT line, prefer-
ably with a relay.
2) Send the RDIRS command.
3) Three-state the user connection (set to high imped-
ance).
4) Receive data from the MAX1455.
5) Activate the user connection (pull DIO/OUT line high).
6) Release the pullup resistor.
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DIO
IRS COMMAND (8 BITS)
IRSA[3:0] IRSD[3:0]
DHR [7:0]
0000
0001
0010
0011
0100
0101
DHR [3:0]
DHR [7:4]
DHR [11:8]
DHR [15:12]
RESERVED
RESERVED
BIDIRECTIONAL
16-BIT
DATA
LATCH
DHR [15:8]
ICRA[3:0] CALIBRATION REGISTER
ICRA [3:0]
IEEA [3:0]
IEEA [7:4]
EEPROM
MEMORY
768 X 8 BITS
0110
0111
0000
0001
CONFIG
ODAC
0010
0011
0100
0101 TO
1111
OTCDAC
FSODAC
FSOTCDAC
IRSP [3:0]
IEEA [9:8]
1000
1001
CRIL [3.0]
(EXECUTE)
ADDR DATA
RESERVED
1010
1011
ATIM [3:0]
ALOC [3:0]
TABLE 16. INTERNAL CALIBRATION
REGISTERS
1100 TO
1110
RESERVED
CRIL[3:0]
0000
FUNCTION
LOAD ICR
RELEARN
BAUD RATE
1111
0001
0010
0011
WRITE EEPROM
ERASE EEPROM
READ ICR
TABLE 9. INTERFACE REGISTER
SET COMMANDS
LOOKUP
ADDRESS
0100
0101
0110
0111
READ EEPROM
READ IRS
ANALOG OUT
ERASE PAGE
TEMP INDEX [7:0]
ENABLE ANALOG OUTPUT
1000 TO
1111
RESERVED
TABLE 10. CRIL ACTIONS
OUTPUT
TIMER
OUT
OUTPUT
MUX
IRSP[3:0]
0000
RETURNS
DHR [7:0]
PGA
DHR [F:8]
0001
IEEA [7:4], ICRA [3:0]
CRIL [3:0], IRSP [3:0]
ALOC [3:0], ATIM [3.0]
IEEA [7:0]
0010
0011
0100
0101
IEED [7:0]
0110
TEMP-INDEX [7:0]
BITCLK [7:0]
0111
1000
1001
RESERVED
1010 TO
1111
11001010 - (USE TO
CHECK COMMUNICATION)
TABLE 11. IRS POINTER FUNCTIONS (READS)
Figure 5. Analog Output Timing
Figure 4 shows an example transmit/receive sequence
with the RDIRS command (59hex) being sent and the
MAX1455 responding with a byte value of 10hex.
internal registers are automatically refreshed from the
EEPROM.
When starting the MAX1455 in digital mode, pay
special attention to the 3 CLK bits: 3MSBs of the
Configuration register. The frequency of the MAX1455
internal oscillator is measured during production test-
ing and a 3-bit adjustment (calibration) code is calcu-
lated and stored in the upper 3 bits of EEPROM location
161hex (EEPROM upper configuration byte).
Internal Clock Settings
Following initial power-up, or after a power reset, all of the
calibration registers within the MAX1455 contain 0000hex
and must be programmed. Note that in analog mode, the
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Table 8. Control Location (CL[15:0])
FIELD
NAME
DESCRIPTION
15:8
CL[15:8]
Reserved
Control Location. Secure-Lock is activated by setting this to FFhex, which disables DIO serial
communications and connects OUT to PGA output.
7:0
CL[7:0]
Table 9. IRSA Decoding
IRSA[3:0]
DESCRIPTION
Write IRSD[3:0] to DHR[3:0] (Data Hold register)
Write IRSD[3:0] to DHR[7:4] (Data Hold register)
0000
0001
0010
0011
0100
0101
Write IRSD[3:0] to DHR[11:8] (Data Hold register)
Write IRSD[3:0] to DHR[15:12] (Data Hold register)
Reserved
Reserved
Write IRSD[3:0] to ICRA[3:0] or IEEA[3:0] (Internal Calibration register address or internal EEPROM
address nibble 0)
0110
0111
1000
Write IRSD[3:0] to IEEA[7:4] (internal EEPROM address, nibble 1)
Write IRSD[3:0] to IRSP[3:0] or IEEA[9:8] (Interface register set pointer where IRSP[1:0] is IEEA[9:8])
Write IRSD[3:0] to CRIL[3:0] (Command register to internal logic)
Write IRSD[3:0] to ATIM[3:0] (analog timeout value on read)
Write IRSD[3:0] to ALOC[3:0] (analog location)
1001
1010
1011
1100 to 1110
1111
Reserved
Write IRSD[3:0] = 1111bin to relearn the baud rate
The MAX1455 internal clock controls timing functions,
including the signal path gain, DAC functions, and com-
munications. It is recommended that, while in digital
mode, the Configuration register CLK bits be assigned the
values contained in EEPROM (upper configuration byte).
The 3 CLK bits represent a two’s-complement number
with a nominal clock adjustment of 9% per bit. Table 12
shows the codes and adjustment available.
The following example is based on a required CLK code
of 010 binary:
1) Read the CLK bits (3MSBs) from EEPROM location
161hex. CLK = 010 binary.
2) Set the CLK bits in the Configuration register to 001
binary.
3) Send the reinitialize command, followed by the initial-
ize (baud rate learning) command.
Any change to the CLK bit values contained in the
Configuration register must be followed by the MAX1455
baud rate learning sequence (reinitialize and initialize
commands). To maximize the robustness of the commu-
nication system during clock resetting only, change the
CLK bits by 1 LSB value at a time. The recommended set-
ting procedure for the Configuration register CLK bits is,
therefore, as follows. (Use a minimum baud rate of 9600
during the setting procedure to prevent potential overflow
of the MAX1455 baud rate counter with clock values near
maximum.)
4) Set the CLK bits in the Configuration register to 010
binary.
5) Send the reinitialize command, followed by the initialize
(baud rate learning) command.
The frequency of the internal oscillator can be checked at
any time by reading the value of BITCLK[7:0]. This 8-bit
number represents the number of internal oscillator cycles
corresponding to 1 cycle (1 bit time) of the communica-
tions baud rate.
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Table 10. CRIL Command Codes
CRIL[3:0]
0000
NAME
LdICR
EEPW
ERASE
RdICR
RdEEP
RdIRS
DESCRIPTION
Load Internal Calibration register at address given in ICRA with data from DHR[15:0].
EEPROM write of 8 data bits from DHR[7:0] to address location pointed by IEEA [9:0].
Erase all of EEPROM (all bytes equal FFhex).
0001
0010
0011
Read Internal Calibration register as pointed to by ICRA and load data into DHR[15:0].
Read internal EEPROM location and load data into DHR[7:0] pointed by IEEA [9:0].
Read Interface register set pointer IRSP[3:0]. See Table 11.
0100
0101
Output the multiplexed analog signal onto OUT. The analog location is specified in ALOC[3:0]
(Table 13) and the duration (in byte times) that the signal is asserted onto the pin is specified in
ATIM[3:0] (Table 14).
0110
RdAlg
Erases the page of the EEPROM as pointed by IEEA[9:6]. There are 64 bytes per page and thus 12
pages in the EEPROM.
0111
PageErase
Reserved
1000 to
1111
Reserved.
with the 8 data bits to be written (Data[7:0]). Send the
EEPROM WRITE command to CRIL (19hex).
Erasing and Writing to the EEPROM
The internal EEPROM must be erased (bytes set to
FFhex) prior to programming the desired contents. The
MAX1455 is supplied in a nominally erased state except
byte 161hex and byte 16Bhex. The 3MSBs of byte
161hex contain the internal oscillator calibration setting.
Byte 16Bhex is set to 00hex to allow serial communication
regardless of the UNLOCK status.
To read a byte from EEPROM:
1) Load IRS locations IEEA[9:8], IEEA[7:4], and IEEA[3:0]
with the byte address (Address[9:0]).
2) Send a READ EEPROM command to the CRIL regis-
ter (49hex); this loads the required EEPROM byte into
DHR[7:0].
When erasing the EEPROM, first save the 3MSBs of byte
161hex. Following erasure, these 3 bits must be rewrit-
ten, together with the Secure-Lock byte value of 00hex.
Failure to do this may cause the part to stop communi-
cating. Do not remove power from the device before
rewriting these values.
3) Load IRS location IRSP[3:0] with 00hex (return
DHR[7:0]).
4) Send the READ IRSP command to the CRIL register
(59hex).
Multiplexed Analog Output
The internal EEPROM can be entirely erased with the
ERASE command or partially erased with the PageErase
command (Table 10). It is necessary to wait 7.1ms after
issuing an erase or PageErase command. Any attempt
to communicate with the part or to interrupt power before
7.1ms have elapsed may produce indeterminate states
within the EEPROM.
The MAX1455 provides the facility to output analog signals
while in digital mode through the read analog (RdAlg) com-
mand. One byte time after receiving the RdAlg command,
the internal analog signal determined by the ALOC[3:0]
register (Table 13) is multiplexed to the MAX1455 OUT.
The signal remains connected to OUT for the duration set
by the ATIM[3:0] register. The ATIM function uses the com-
munication baud rate as a timing basis. See Table 14 for
details. At the end of the period determined by ATIM[3:0],
the analog signal is disconnected from the analog output
and OUT resumes a three-state condition. The MAX1455
can receive further commands on DIO 1 byte after resum-
ing a three-state condition on OUT. Figure 6 shows the
timing of this scheme.
To erase a page in EEPROM (PageErase command):
First load the required page number (Table 1) into the
IRS location IEEA[3:0]. Then send a CRIL PageErase
command (79hex).
To write a byte to EEPROM: Load IRS locations
IEEA[9:8], IEEA[7:4], and IEEA[3:0] with the byte address
(Address[9:0]). Load IRS locations DHR[7:4] and DHR[3:0]
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The MAX1455 DIO is three-state for the duration that the
analog output is active. This is to allow OUT and DIO to
be connected in parallel. When DIO and OUT are con-
nected in parallel, the host computer must also three-
state its communications connection to the MAX1455.
This requirement produces periods when all connections
to the DIO are three-stated simultaneously, making it
necessary to have a weak pullup resistor applied to DIO
during these periods.
Table 11. IRSP Decode
IRSP[3:0]
0000
0001
0010
0011
RETURNED VALUE
DHR[7:0]
DHR[15:8]
IEEA[7:4], ICRA[3:0] concatenated
CRIL[3:0], IRSP[3:0] concatenated
ALOC[3:0], ATIM[3:0] concatenated
IEEA[7:0] EEPROM address byte
IEED[7:0] EEPROM data byte
Temp-Index[7:0]
0100
0101
0110
A continuous output mode is available for the analog
output and is selected by setting ATIM[3:0] to Fhex.
This mode may only be used when DIO and OUT are
separate. While in this mode and following receipt of
the RdAlg command, or any other command, DIO three-
states for a period of 32,769 byte times. Once this period
0111
1000
1001
BitClock[7:0]
Reserved. Internal flash test data.
has elapsed, DIO enters receive mode and accepts fur-
ther command inputs. The analog output is always active
while in continuous mode.
11001010 (CAhex). This can be used to
test communication.
1010-1111
Table 12. CLK Code (3MSBs of
Configuration Register)
Note: The internal analog signals are not buffered when
connected to OUT. Any loading of OUT while one of these
internal signals is being measured is likely to produce
measurement errors. Do not load OUT when reading
internal signals such as BDR, FSOTC, etc.
CLK CODE (BIN)
CLOCK ADJUSTMENT (%)
011
010
001
000
111
110
101
+27
+18
+9
0
-9
-18
-27
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Communication Command Examples
Example 4. Write 8C40hex to the FSODAC register:
A selection of examples of the command sequences for
various functions within the MAX1455 follows.
COMMAND
00hex
ACTION
Load 0 hex to the DHR[3:0] register.
Load 4 hex to the DHR[7:4] register.
Load C hex to the DHR[11:8] register.
Load 8 hex to the DHR[15:12] register.
Load 3 (FSODAC) to the ICRA[3:0] register.
Ld ICR.
Example 1. Change the baud rate setting and check com-
munications. If the communication with the MAX1455 is
lost due to a system baud rate change before sending the
reinitialization command, apply a power reset to guaran-
tee the initialization condition:
41hex
C2hex
83hex
36hex
09hex
COMMAND
ACTION
Reinitialize part ready for baud rate learning.
Change system baud rate to new value.
Learn baud rate.
8C40 hex is written to the FSODAC register.
FFhex
Example 5. Write 8C40hex to the FSODAC lookup
table location at Temp-Index 40. This example uses the
page erase command to clear the relevant section of the
EEPROM and assumes that none of the existing data in
that section is required to be kept:
01hex
F8hex
59hex
Load 15 (Fhex) to IRSP[3:0] register.
Read IRS.
Host computer must be ready to receive data
on the serial line within 1 (baud rate) byte
time of sending the Read IRS command. The
MAX1455 returns CAhex. (IRSP values of
10 to 15 are configured to return CAhex for
communication checking purposes.)
COMMAND
A6hex
ACTION
Load Ahex (page number corresponding to
EEPROM locations 280hex and 281hex) to
the IEEA[3:0] register.
79hex
Page Erase command.
Example 2. Read the lookup table pointer (Temp-Index):
Wait 7.1ms before sending any further
commands.
COMMAND
78hex
ACTION
Load 7 to IRSP[3:0] register.
Read IRS.
06hex
87hex
Load 0hex to the IEEA[3:0] register.
Load 8hex to the IEEA[7:4] register.
59hex
Load 2hex to the IEEA[9:8] (IRSP[3:0])
register.
28hex
Host ready to receive data within 1 byte
time of sending the Read IRS command.
The MAX1455 returns the current Temp-
Index pointer value.
00hex
41hex
Load 0hex to the DHR[3:0] register.
Load 4hex to the DHR[7:4] register.
Write EEPROM. 40hex is loaded to
EEPROM address 280hex, which is the low
byte location corresponding to a Temp-Index
pointer value of 40.
Example 3. Enable BDR measurement on OUT pin for
3.4s duration with 9600 baud rate:
19hex
COMMAND
ACTION
Load 1 (BDR measurement) to ALOC[3:0]
register.
Load 1 to the IEEA[3:0] register. IEEA[7:4]
and IEEA[9:8] already contain 8 and 2,
respectively.
1Bhex
16hex
12
5
Load 12 to the ATIM[3:0] register: (2 +1)
8/9600 = 3.4s.
CAhex
69hex
C0hex
81hex
Load Chex to the DHR[3:0] register.
Load 8hex to the DHR[7:4] register.
RdAlg.
The DIO pin is three-stated and the OUT pin
is connected internally to the BDR pin for a
duration of approximately 3.4s.
Write EEPROM. 8Chex is loaded to
EEPROM address 281hex, which is the high
byte location corresponding to a Temp-Index
pointer value of 40.
19hex
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Table 13. ALOC Definition
ALOC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
ANALOG SIGNAL
DESCRIPTION
OUT
BDR
PGA Output
Bridge Drive
ISRC
Bridge Drive Current Setting
Internal Positive Supply
Internal Ground
VDD
VSS
CLIP-TOP
CLIP-BOTTOM
FSODAC
FSOTCDAC
ODAC
Clip Voltage High Value
Clip Voltage Low Value
Full-Scale Output DAC
Full-Scale Output TC DAC
Offset DAC
1000
1001
1010
1011
1100
1101
1110
OTCDAC
VREF
Offset TC DAC
Bandgap Reference Voltage (nominally 1.25V)
Internal Test Node
VPTATP
VPTATM
INP
Internal Test Node
Sensor’s Positive Input
Sensor’s Negative Input
1111
INM
WEAK PULLUP
REQUIRED
WEAK PULLUP
REQUIRED
ATIM
2
+ 1 BYTE TIMES
DATA
OUT
0
1 1 1 1 1
0
1
0
0
1
0
1 1
1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X 1 1 1 1 1 1 1 1 0
X X
X X
HIGH-Z
HIGH-Z
VALID OUTPUT
HIGH-Z
DIO
RECEIVE
RECEIVE
HIGH-Z
HOST
TRANSMIT
TRANSMIT
Figure 6. Automated Test System Concept
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Table 14. ATIM Definition
ATIM[3:0]
DURATION OF ANALOG SIGNAL SPECIFIED IN BYTE TIMES (8-BIT TIME)
0
5
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
2 + 1 = 2 byte times, i.e., (2 8) / baud rate
21 + 1 = 3 byte times
22 + 1 = 5 byte times
23 + 1 = 9 byte times
24 + 1 = 17 byte times
25 + 1 = 33 byte times
26 + 1 = 65 byte times
27 + 1 = 129 byte times
28 + 1 = 257 byte times
29 + 1 = 513 byte times
210 + 1 = 1025 byte times
211 + 1 = 2049 byte times
212 + 1 = 4097 byte times
213 + 1 = 8193 byte times
214 + 1 = 16,385 byte times
In this mode, OUT is continuous; however, DIO accepts commands after 32,769 byte times. Do not parallel
connect DIO to OUT.
1111
Table 15. IRCA Decode
ICRA[3:0]
0000
NAME
CONFIG
ODAC
DESCRIPTION
Configuration register
0001
Offset DAC register
0010
OTCDAC
FSODAC
Offset temperature coefficient DAC register
Full-scale output DAC register
0011
0100
FSOTCDAC Full-scale output temperature coefficient DAC register
0101
Reserved. Do not write to this location (EEPROM test).
0110 to
1111
Reserved. Do not write to this location.
values of offset, FSO, and bridge resistance) to pre-
vent overload of the MAX1455.
Sensor Compensation Overview
Compensation requires an examination of the sensor per-
formance over the operating pressure and temperature
range. Use a minimum of two test pressures (e.g., zero
and full span) and two temperatures. More test pressures
and temperatures result in greater accuracy. A typical
compensation procedure can be summarized as follows:
•
Set the initial bridge voltage (with the FSODAC) to
half of the supply voltage. Measure the bridge volt-
age using the BDR or OUT pins, or calculate based
on measurements.
•
•
Calibrate the output offset and FSO of the transducer
using the ODAC and FSODAC, respectively.
Set Reference Temperature (e.g., 25°C):
Store calibration data in the test computer or
MAX1455 EEPROM user memory.
•
Initialize each transducer by loading its respective
register with default coefficients (e.g., based on mean
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
DIO[1:N]
DIGITAL
DION
DIO2
MULTIPLEXER
DIO1
MODULE 1
MODULE 2
MODULE N
MAX1455
MAX1455
MAX1455
DATA
DATA
V
OUT
V
OUT
V
OUT
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
+5V
V
OUT
DVM
TEST OVEN
Figure 7. Comparison of an Uncalibrated Sensor and a Calibrated Transducer
Table 16. Effects of Compensation
TYPICAL UNCOMPENSATED INPUT (SENSOR)
Offset.....................................................................±100% FSO
FSO ..............................................................1mV/V to 40mV/V
Offset TC ...................................................................20% FSO
Offset TC Nonlinearity .................................................4% FSO
FSOTC .....................................................................-20% FSO
FSOTC Nonlinearity ....................................................5% FSO
Temperature Range........................................-40°C to +125°C
TYPICAL COMPENSATED TRANSDUCER OUTPUT
OUT.................................................Ratiometric to V at 5.0V
Offset at +25°C.................................................0.500V ±200µV
FSO at +25°C...................................................4.000V ±200µV
Offset Accuracy over Temp. Range...........±4mV (±0.1% FSO)
FSO Accuracy over Temp. Range .............±4mV (±0.1% FSO)
DD
Set Next Test Temperature:
Sensor Calibration and
Compensation Example
•
Calibrate offset and FSO using the ODAC and
FSODAC, respectively.
The MAX1455 temperature compensation design cor-
rects both sensor and IC temperature errors. This enables
the MAX1455 to provide temperature compensation
approaching the inherent repeatability of the sensor. An
example of the MAX1455’s capabilities is shown in Figure
8. Table 16 lists the effects of compensation.
•
Store calibration data in the test computer or
MAX1455 EEPROM user memory.
•
•
•
Calculate the correction coefficients.
Download correction coefficients to EEPROM.
Perform a final test.
A MAX1455 and a repeatable piezoresistive sensor with
an initial offset of 16.4mV and a span of 55.8mV were
converted into a compensated transducer with an offset of
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
UNCOMPENSATED SENSOR
TEMPERATURE ERROR
RAW SENSOR OUTPUT
(T = +25°C)
A
30
80
FSO
OFFSET
20
60
40
10
0
20
0
-10
-20
0
20
40
60
80
100
-50
0
50
TEMPERATURE (°C)
100
150
PRESSURE (kps)
COMPENSATED TRANSDUCER
(T = +25°C)
A
COMPENSATED TRANSDUCER ERROR
5
4
3
2
1
0
0.15
0.10
0.05
0
FSO
OFFSET
-0.05
-0.10
-0.15
-50
0
50
TEMPERATURE (°C)
150
0
20
40
60
80
100
100
PRESSURE (kps)
Figure 8. Comparison of an Uncalibrated Sensor and a Calibrated Transducer
0.5000V and a span of 4.0000V. Nonlinear sensor offset
and FSO temperature errors, which were on the order of
20% to 30% FSO, were reduced to under ±0.1% FSO.
Figure 8 shows the output of the uncompensated sensor
and the output of the compensated transducer. Six tem-
perature points were used to obtain this result.
2) Design/applications manual. This manual was devel-
oped for test engineers familiar with data acquisition of
sensor data and provides sensor compensation algo-
rithms and test procedures.
3) MAX1455 communication software, which enables
programming of the MAX1455 from a computer key-
board (IBM compatible), one module at a time.
•
Store calibration data in the test computer or MAX1455
EEPROM user memory.
4) Interface adapter, which allows the connection of the
evaluation board to a PC serial port.
MAX1455 Evaluation Kit
To expedite the development of MAX1455-based trans-
ducers and test systems, Maxim has produced the
MAX1455 evaluation kit (EV kit). First-time users of the
MAX1455 are strongly encouraged to use this kit.
The EV kit is designed to facilitate manual programming
of the MAX1455 with a sensor. It includes the following:
Chip Information
PROCESS: CMOS
1) Evaluation board with or without a silicon pressure
SUBSTRATE CONNECTED TO: V
SS
sensor, ready for customer evaluation.
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Detailed Functional Diagram
EEPROM
TEST 1
(LOOKUP PLUS CONFIGURATION DATA)
V
DD
TEST 2
TEST 3
TEST 4
EEPROM ADDRESS
USAGE
000H + 001H
OFFSET DAC LOOKUP TABLE
V
DD
5
(176 16 BITS)
:
16 BIT
15EH + 15FH
160H + 161H
162H + 163H
164H + 165H
166H + 167H
168H + 169H
16AH + 16BH
16CH + 16DH
FSO
DAC
V
V
DD1
CONFIGURATION REGISTER SHADOW
RESERVED
V
SS
OFFSET TC REGISTER SHADOW
RESERVED
SS
FSOTC REGISTER SHADOW
CONTROL LOCATION REGISTER
USER STORAGE (52 BYTES)
V
DD
SS
16 BIT
OFFSET
DAC
:
R
75kΩ
ISRC
R
75kΩ
STC
19EH + 19FH
1A0H + 1A1H
:
V
V
DD2
FSO DAC LOOKUP TABLE
5
(176 16 BITS)
V
SS
2FEH + 2FFH
V
DD
8-BIT
BANDGAP
TEMP
SENSOR
LOOKUP
ADDRESS
±1
16 BIT
∑
∆
FSOTC
DAC
BDR
UNLOCK
DIO
DIGITAL
INTERFACE
V
SS
V
FSOTC REGISTER
SS
INP
INM
CLIP-HIGH
DAC
PHASE
REVERSAL
MUX
PGA BANDWIDTH
3kHz 10%
x
MUX
24
PGA
MUX
∑
∑
OUT
DAC
CLIP-LOW
INPUT-REFERRED OFFSET
(COARSE OFFSET)
AMP-
PROGRAMMABLE GAIN STAGE
PGA (3:0) PGA GAIN TOTAL GAIN
V
SS
±1
IRO (3, 2:0) OFFSET (mV)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
39
52
1,111
1,110
1,101
1,100
1,011
1,010
1,001
1,000
0,000
0,001
0,010
0,011
0,100
0,101
0,110
0,111
63
54
45
36
27
18
9
AMPOUT
65
16 BIT
78
OFFSET
TC DAC
AMP+
91
104
117
130
143
156
169
182
195
208
221
234
V
SS
OTC REGISTER
0
UNCOMMITTED OP AMP
0
*INPUT-REFERRED
OFFSET VALUE IS
-9
PARAMETER
I/P RANGE
VALUE
TO V
-18
-27
-36
-45
-54
-63
V
SS
DD
PROPORTIONAL TO V
.
DD
VALUES GIVEN ARE FOR
= +5V.
I/P OFFSET
±20mV
V
DD
O/P RANGE
NO LOAD
1mA LOAD
V
, V ±0.01V
SS DD
, V ±0.25V
V
SS DD
UNITY GBW
10MHz TYPICAL
PGA BANDWIDTH 3kHz ±10%
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
LAND PATTERN NO.
16 SSOP
A16-2
U16-2
21-0056
21-0066
90-0106
90-0117
16 TSSOP
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MAX1455
Low-Cost Precision Sensor Signal Conditioner
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
2
7/01
Initial release
—
10/01
5/14
Added TSSOP package to data sheet.
1, 2, 24
1
Updated General Description
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2014 Maxim Integrated Products, Inc.
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