MAX14661ETI+T [MAXIM]
Beyond-the-Rails 16:2 Multiplexer;
| 型号： | MAX14661ETI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Beyond-the-Rails 16:2 Multiplexer |
| 文件： | 总27页 (文件大小：1256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX14661
Beyond-the-Rails 16:2 Multiplexer
General Description
The MAX14661 is a serially controlled, dual-channel
analog multiplexer allowing any of the 16 pins to be
connected to either common pin simultaneously in any
combination. The device features Beyond-the-Rails
capability so that ±5.5V signals can be passed with any
single supply between +1.6V and +5.5V.
Features and Benefits
●ꢀ Beyond-the-RailsꢀTechnologyꢀReducesꢀCostꢀandꢀ
Complexity
• Switch ±5.5V Signals from a +1.6V Single Supply
• Wide +1.6V to +5.5V Supply Range
TM
• Low 5.5W R
(typ) Across the Supply Range
ON
●ꢀ FlexibleꢀMultiplexingꢀEnablesꢀDesignꢀReuse
• 16:2 Matrix Switch Multiplexer Connects Any Input
Pin To Either Common Pin In Any Combination
2
The serial control is selectable between I C and SPI.
Both modes provide individual control of each indepen-
dent switch so that any combination of switches can
2
• Each Switch is Independently Controlled via I C or
SPI
2
be applied. I C mode provides two address-select pins
• Programmable Shadow Registers Allow
Simultaneous Updating
allowing for addressing up to four devices on a single bus.
The SPI mode includes a DOUT pin that can be used to
chain multiple devices together with a single select signal.
●ꢀ LowꢀDistortionꢀSwitchingꢀImprovesꢀSystemꢀ
Performance
The IC is available in a 28-pin (4mm x 4mm) TQFN pack-
age and is specified over the -40ºC to +85ºC extended
temperature range. The AB_ and COM_ pins provide
±10kV ESD protection (HBM).
• Total Harmonic Distortion + Noise 0.005% (typ)
• R ꢀFlatnessꢀ2.5mΩꢀ(typ)ꢀAcrossꢀCompleteꢀ
ON
Signal Range
●ꢀ IntegratedꢀProtectionꢀforꢀSystemꢀReliability
• ±10kV HBM ESD Protection on all AB_ and COM_
Pins, Even When Powered Down
Applications
●ꢀ SystemꢀDiagnostics
●ꢀ DataꢀAcquisition
●ꢀ I C Signal Switching
Ordering Information appears at end of data sheet.
2
●ꢀ AudioꢀInputꢀSelection
Beyond-the-Rails™ is a trademark Maxim Integrated Products, Inc.
19-6739; Rev 2; 1/15
MAX14661
Beyond-the-Rails 16:2 Multiplexer
Functional Diagram
MAX14661
COMA
AB01
AB02
AB03
AB04
AB05
AB06
AB07
AB08
AB09
AB10
AB11
AB12
AB13
AB14
AB15
AB16
COMB
SCLK/SCL
DIN/SDA
CS/A0
V
CC
GND
SERIAL CONTROL
2
SPI/I C
DOUT/A1
SD
MAX14661
Beyond-the-Rails 16:2 Multiplexer
Absolute Maximum Ratings
(All voltages referenced to GND.)
Continuous Power Dissipation
V
, DIN/SDA, SCLK/SCL, DOUT/A1,
28 TQFN (derate 28.6mW/ºC above +70ºC)..........2285.7mW
Operating Temperature Range............................-40ºC to +85ºC
Maximum Junction Temperature .....................................+150ºC
Storage Temperature Range.............................-65ºC to +150ºC
Lead Temperature (soldering, 10s) .................................+300ºC
Soldering Temperature (reflow).......................................+260ºC
CC
CS/A0, SD ....................................................... -0.3V to +6.0V
2
SPI/I C................................. -0.3V to min (V
to +0.3V, 6V)
CC
AB_, COM_ .........................................................-6.0V to +6.0V
Continuous Current (AB_ or COM_ to any switch)..........±50mA
Peak Current (AB_ or COM_ to any switch)
(pulsed at 1ms, maximum 10% duty cycle)................±100mA
(Note 1)
Package Thermal Characteristics
Junction-to-Case Thermal Resistance (θ
)
Junction-to-Ambient Thermal Resistance (θ
)
JA
JC
TQFN.................................................................................3ºC/W
TQFN...........................................................................35ºC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= +1.6V to +5.5V, T = -40ºC to +85ºC, unless otherwise noted. Typical values are at V
= +3.3V, T = +25ºC, unless otherwise
CC
A
CC A
noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Power-Supply Range
V
1.6
5.5
V
CC
R
ꢀ=ꢀ50Ω,
COM
Power-Supply Rejection Ratio
PSRR
-84
dB
V
V
V
V
= +3.3V ±0.1V, f = 10kHz
= +3.3V, all switches on
= +3.3V, two switches on
= +3.3V, SD = 0
CC
CC
CC
CC
675
115
1500
200
1
V
Supply Current
I
µA
CC
CC
ANALOG SWITCH
V
,
AB_
Analog Signal Range
-5.5
+5.5
V
V
V
COM_
V
> 2.5V
11
11
6
CC
Analog Signal Amplitude
(Notes 3, 4)
V
f < 500kHz
P-P
V
V
V
< 2.5V, f > 500kHz
= +5V
CC
CC
CC
8
On-Resistance
R
Ω
Ω
ON
= +1.8V
12
On-Resistance Match between
Channels
ΔR
V
= 3.3V, between COM_ and AB_
0.25
25
ON
CC
V
V
= 3.3V, I
= 10mA,
COM_
CC
On-Resistance Flatness
R
mΩ
FLAT
= -5.5V to +5.5V
COM_
V
V
V
= 3.3V, switch open,
CC
= -5.5V, +5.5V
COM_
AB_, COM_ Off-Leakage Current
I
-50
+50
nA
OFF
= +5.5V, -5.5V, unconnected
AB_
(Notes 3, 5)
Maxim Integrated
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Electrical Characteristics (continued)
(V
= +1.6V to +5.5V, T = -40ºC to +85ºC, unless otherwise noted. Typical values are at V
= +3.3V, T = +25ºC, unless otherwise
CC
A
CC A
noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
= 3.3V, switch closed,
CC
AB_, COM_ On-Leakage Current
I
-50
+50
nA
ON
= V
= ±5.5V (Notes 3, 5)
COM_
AB_
DYNAMIC PERFORMACE (Notes 6, 7)
V
= 3.0V, R ꢀ=ꢀ100Ω,ꢀC = 33pF,
L L
COM_
Turn-Off Time
t
5
µs
µs
OFF
open COM_ and AB_ together
V
= 3.0V, R ꢀ=ꢀ100Ω,ꢀC = 33pF,
COM_
L
L
Break-Before-Make Time
Turn-On Time
t
time for both switching channels are open
during transition
0
BBM
V
= 3.0V, R = 100W, C = 33pF;
L L
COM_
25
t
close AB_ and COMA or AB_ and COMB
together
13
µs
µs
ON
Time from when SD pin goes high to
when the device is ready to listen for
I2C/SPI comunications
Enable Time
t
300
EN
R
0.6V
= R ꢀ=ꢀ50Ωꢀ(Notesꢀ7,ꢀ8),ꢀV
=
S
L
COM_
Bandwidth -3dB
BW
60
MHz
%
P-P
Total Harmonic Distortion Plus
Noise
f = 20Hz to 20kHz, V
R
= 0.5V
,
COM_
P-P
THD + N
0.005
= R =ꢀ50Ω,ꢀDCꢀbiasꢀ=ꢀ0
L
S
R
= R ꢀ=ꢀ50Ω,ꢀV
= 0.6V
,
S
L
COM_
P-P
Off-Isolation
Crosstalk
V
-62
-80
dB
dB
ISO
f = 1MHz (Note 8)
R
= R =ꢀ50Ω,ꢀV
= 0.6V
,
S
L
COM
P-P
V
CT
f = 1MHz (Note 8)
Thermal Shutdown
Thermal Hysteresis
T
150
25
ºC
ºC
SDW
T
HYST
SPI TIMING CHARACTERISTICS (See Figure 12)
t
t
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Rise Time
DIN Hold Time
95
35
45
15
15
15
ns
ns
ns
ns
ns
ns
CH + CL
t
CH
t
CL
t
CSS
t
DH
t
DIN Setup Time
DS
C
C
C
= 15pF, V
≥ꢀ2.7V
40
80
L
L
L
CC
t
Output Data Propagation Delay
ns
DO
ꢀ=ꢀ15pF,ꢀ1.6Vꢀ≤ꢀV
< 2.7V
CC
tFT
DOUT Rise and Fall Times
CS Hold Time
= 15pF
10
ns
ns
t
60
CSH
I2C TIMING (See Figure 4)
I2CꢀSerial-ClockꢀFrequency
f
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
BUF
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Electrical Characteristics (continued)
(V
= +1.6V to +5.5V, T = -40ºC to +85ºC, unless otherwise noted. Typical values are at V
= +3.3V, T = +25ºC, unless otherwise
CC
A
CC A
noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
START Condition
Setup Time
t
0.6
µs
SU:STA
HD:STA
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
t
0.6
0.6
1.3
0.6
100
0
µs
µs
µs
µs
ns
ns
t
SU:STO
t
LOW
Clock High Period
t
HIGH
Data Valid to SCL Rise Time
Data Hold Time to SCL Fall
DIGITAL I/O
t
Write setup time
Write hold time
SU:DAT
HD:DAT
t
Input Logic-High Voltage
V
1.4
V
V
IH
Input Logic-Low Voltage
(DIN/SDA, SCLK/SCL, CS/A0)
V
0.5
0.4
IL_FAST
Input Logic-Low Voltage (DOUT/
A1 SD)
V
V
IL_SLOW
Input Leakage Current
SPI/I2C I2C Threshold
SPI/I2C SPI Threshold
I
-1
+1
µA
V
IN
V
0.4
I2C
SPI
V
1.5
V
Output Logic Low
(I2C mode)
V
I
= 3mA
0.4
5.5
V
V
V
OL_I2C
SINK
SPI/I2C SPI Supply Voltage
V
1.5
OVDD
Output Logic-Low
(SPI Mode)
V
I
I
= 200µA
0.15 x V
OVDD
OL_SPI
SINK
Output Logic-High
(SPI Mode)
V
= 200µA
0.85 x V
V
OH_SPI
SOURCE
OVDD
ESD PROTECTION
All AB_ and COM_ Pins
All Others Pins
HBM
HBM
±10
±2
kV
kV
Note 2: All devices are 100% production tested at T = +25ºC. Specifications over temperature are guaranteed by design.
A
Note 3: Guaranteed by design.
Note 4: See the Typical Operating Characteristics Maximum Signal Amplitude vs. Supply Voltage for f > 500kHz for more details.
Note 5: Test circuit Figure 1.
Note 6: Test circuit Figure 2.
Note 7: Supplyꢀvoltageꢀandꢀsignalꢀamplitudeꢀcanꢀaffectꢀtheꢀfrequencyꢀresponseꢀofꢀtheꢀdevice.ꢀSeeꢀamplitudeꢀfrequencyꢀstabilityꢀinꢀ
the Typical Operating Characteristics for more details.
Note 8: Test circuit Figure 3.
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Test Circuits/Timing Diagrams
MAX14661
AB_ OFF
LEAKAGE
COM_ OFF
LEAKAGE
AB_
COM_
V
AB_
V
COM_
A
A
ON
LEAKAGE
MAX14661
AB01
COM_
CHANNEL TO
CHANNEL LEAKAGE
V
COM_
A
AB02-16
V
AB_
A
Figure 1. On-/Off-/Channel-to-Channel Leakage Current
CS
MAX14661
+3V
t
ON
V
OUT
AB_
AB_
COM_
+3V
t
t
BBM
OFF
4
SPI
CONTROL
SPI
V
OUT
R
L
NOTE: V = 3V x
RIF
R
+ R
ON
L
0V
Figure 2. Turn-On/Turn-Off/Break-Before-Make
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
NETWORK
ANALYZER
50Ω
50Ω
V
V
IN
COM_
AB01
AB02-AB16
V
OUT
ON-LOSS = 20log
V
IN
OUT
MEAS
REF
MAX14661
50Ω
50Ω
50Ω
50Ω
50Ω
NETWORK
ANALYZER
COMA
COMB
50Ω
50Ω
V
V
IN
AB02-AB16
V
OUT
OFF-ISOLATION = 20log
V
IN
OUT
AB01
MEAS
REF
MAX14661
50Ω
50Ω
NETWORK
ANALYZER
50Ω
50Ω
V
V
IN
COM_
AB01
AB02-AB16
V
OUT
CROSSTALK = 20log
V
IN
OUT
MEAS
REF
MAX14661
50Ω
50Ω
Figure 3. Insertion Loss, Off-Isolation, and Crosstalk
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Typical Operating Characteristics
(V
= +1.6V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +3.3V, T = +25°C, unless otherwise
CC
A
CC A
noted.)
COM_ LEAKAGE CURRENT
vs. TEMPERATURE
ON-RESISTANCE vs. COM_ VOLTAGE
ON-RESISTANCE vs. COM_ VOLTAGE
10
8
10
8
6
COM_ = +5V
SWITCH ON
V
CC
= 1.8V
4
T
= +85°C
A
COM_ = +5V
SWITCH OFF
2
6
6
0
V
= 2.5V
CC
4
4
V
0
= 5.0V
CC
COM_ = -5V
SWITCH OFF
-2
-4
-6
T
= +25°C
A
T
= -40°C
A
2
2
COM_ = -5V
SWITCH ON
0
0
-6
-4
-2
0
2
4
6
-6
-4
-2
2
4
6
-40
-15
10
35
60
85
COM_ VOLTAGE (V)
COM_ VOLTAGE (V)
TEMPERATURE (°C)
COM_ LEAKAGE CURRENT
vs. COM_ VOLTAGE
COM_ LEAKAGE CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (TWO SWITCHES ON)
6
4
6
4
160
120
80
40
0
COM_ = +5V
SWITCH ON
COM_ = +5V
SWITCH OFF
2
2
SWITCH ON
0
0
SWITCH OFF
-2
-4
-6
-2
-4
-6
COM_ = -5V
SWITCH OFF
COM_ = -5V
SWITCH ON
-6
-4
-2
0
2
4
6
1.5
2.5
3.5
4.5
5.5
1.5
2.5
3.5
4.5
5.5
COM_ VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
(TWO SWITCHES ON)
FREQUENCY RESPONSE
0
-1
-2
-3
-4
-5
160
130
100
70
40
0.1
1
10
100
-40
-15
10
35
60
85
FREQUENCY (MHz)
TEMPERATURE (°C)
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Typical Operating Characteristics (continued)
(V
= +1.6V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C, unless otherwise
CC
A
CC A
noted.)
OFF-ISOLATION vs. FREQUENCY
CROSSTALK vs. FREQUENCY
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-100
0.1
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
+ NOISE (THD+N) vs. FREQUENCY
MAXIMUM SIGNAL AMPLITUDE
vs. SUPPLY VOLTAGE f > 500kHz
PSRR vs. FREQUENCY
0
-20
0.005
0.004
0.003
0.002
0.001
0
15
V
CC
= 3.3V ± 0.1V
THIS PLOT SHOWS THE MAXIMUM
SIGNAL AMPLITUDE THAT ALLOWS
DISTORTION-FREE OPERATION AT
A GIVEN SUPPLY VOLTAGE
12
9
-40
-60
-80
TYPICAL LIMIT
6
RECOMMENDED
OPERATING RANGE
-100
-120
-140
3
0
10
100
1k
FREQUENCY (Hz)
10k
100k
0
1.6 2 2.5
4
6
20
200
2k
20k
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Pin Configurations
TOP VIEW
21 20 19 18 17 16 15
14
13
SD 22
CS/A0 23
AB16
COMB
12 N.C.
24
25
26
27
28
SCLK/SCL
GND
MAX14661
GND
11
10
9
V
CC
COMA
AB08
AB07
DIN/SDA
DOUT/A1
*EP
6
+
8
1
2
3
4
5
7
TQFN
(4mm x 4mm)
*CONNECT EP TO GND
Pin Description
PIN
1
NAME
FUNCTION
2
2
SPI/ I C
Serial Mode Select SPI (high) or I C (low), Supply Input for DOUT
AB Connection to Switches 1A and 1B
AB Connection to Switches 2A and 2B
AB Connection to Switches 3A and 3B
AB Connection to Switches 4A and 4B
AB Connection to Switches 5A and 5B
AB Connection to Switches 6A and 6B
AB Connection to Switches 7A and 7B
AB Connection to Switches 8A and 8B
Common Connection to All A Switches
2
AB01
AB02
AB03
AB04
AB05
AB06
AB07
AB08
COMA
3
4
5
6
7
8
9
10
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Pin Description (continued)
PIN
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
GND
FUNCTION
Ground
N.C.
Not Connected
COMB
AB16
AB15
AB14
AB13
AB12
AB11
Common Connection to All B Switches
AB Connection to Switches 16A and 16B
AB Connection to Switches 15A and 15B
AB Connection to Switches 14A and 14B
AB Connection to Switches 13A and 13B
AB Connection to Switches 12A and 12B
AB Connection to Switches 11A and 11B
AB Connection to Switches 10A and 10B
AB Connection to Switches 9A and 9B
AB10
AB09
SD
Active-Low Shutdown/Low-Power Mode, Turns All Switches Off
2
CS/A0
SCLK/SCL
GND
I C Address Bit 0/SPI CS Signal
2
I C Serial Clock/SPI Serial Clock
Ground
V
Power-Supply Input
CC
2
I C Serial Data/SPI Data Input
DIN/SDA
DOUT/A1
2
I C Address Bit 1/SPI Data Output
Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance. Not intended as an electrical connection point.
—
EP
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Table 1. Register Map
ADDRESS
0x00
NAME
DIR0
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DEFAULT
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DESCRIPTION
Switches 8A–1A direct read/write access
0x01
DIR1
Switches 16A–9A direct read/write access
Switches 8B–1B direct read/write access
Switches 16B–9B direct read/write access
Switches 8A–1A shadow read/write access
Switches 16A–9A shadow read/write access
Switches 8B–1B shadow read/write access
Switches 16B–9B shadow read/write access
Set mux A command (reads 0x00)
0x02
DIR2
0x03
DIR3
0x10
SHDW0
SHDW1
SHDW2
SHDW3
CMD_A
CMD_B
0x11
0x12
0x13
0x14
0x15
Set mux B command (reads 0x00)
Register Types: RW = Read/Write
Table 2. Detailed Register Map
DIR0 0x00
BIT
7
6
5
0
4
0
3
0
2
0
1
0
0
0
BIT Name
Reset Value
Direct_SW8A–1A
0
0
Direct Register Data for SW8A–1A
0 = Switch open
Description
1 = Switch closed
DIR1 0x01
BIT
7
6
5
0
4
0
3
0
2
0
1
0
0
0
BIT Name
Reset Value
Direct_SW16A–9A
0
0
Direct Register Data for SW16A–9A
0 = Switch open
Description
1 = Switch closed
DIR2 0x02
BIT
7
6
5
0
4
0
3
0
2
0
1
0
0
0
BIT Name
Reset Value
Direct_SW8B–1B
0
0
Direct Register Data for SW8B–1B
0 = Switch open
Description
1 = Switch closed
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Table 2. Detailed Register Map (continued)
DIR3 0x03
BIT
7
6
5
4
0
3
0
2
0
1
0
0
0
BIT Name
Reset Value
Direct_SW16B–9B
0
0
0
Direct Register Data for SW16B–9B
0 = Switch open
Description
1 = Switch closed
SHDW0 0x10
BIT
7
6
5
0
4
0
3
0
2
0
1
0
0
0
BIT Name
Reset Value
Shadow_SW8A–1A
0
0
Shadow Register Data for SW8A–1A; temporarily holding registers that support simultaneous
updates.
0 = Switch open
1 = Switch closed
Description
SHDW1 0x11
BIT
7
6
5
0
4
0
3
0
2
0
1
0
0
0
BIT Name
Reset Value
Shadow_SW16A–9A
0
0
Shadow Register Data for SW16A–9A; temporarily holding registers that support simultaneous
updates.
0 = Switch open
1 = Switch closed
Description
SHDW2 0x12
BIT
7
6
5
0
4
0
3
0
2
0
1
0
0
0
BIT Name
Reset Value
Shadow_SW8B–1B
0
0
Shadow Register Data for SW8B–1B; temporarily holding registers that support simultaneous
updates.
0 = Switch open
1 = Switch closed
Description
SHDW3 0x13
BIT
7
6
5
0
4
0
3
0
2
0
1
0
0
0
BIT Name
Reset Value
Shadow_SW16B–1B
0
0
Shadow Register Data for SW16B–9B; temporarily holding registers that support simultaneous
updates.
0 = Switch open
1 = Switch closed
Description
Maxim Integrated
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Table 2. Detailed Register Map (continued)
CMD_A 0x14
BIT
7
6
5
4
3
0
2
0
1
0
0
0
BIT Name
Reset Value
RFU
RFU
0
RFU
0
SelA
0
0
SelA
00000 = Enable only SW01A (0x0001)
00001 = Enable only SW02A (0x0002)
00010 = Enable only SW03A (0x0004)
00011 = Enable only SW04A (0x0008)
00100 = Enable only SW05A (0x0010)
00101 = Enable only SW06A (0x0020)
00110 = Enable only SW07A (0x0040)
00111 = Enable only SW08A (0x0080)
01000 = Enable only SW09A (0x0100)
01001 = Enable only SW10A (0x0200)
01010 = Enable only SW11A (0x0400)
01011 = Enable only SW12A (0x0800)
01100 = Enable only SW13A (0x1000)
01101 = Enable only SW14A (0x2000)
01110 = Enable only SW15A (0x4000)
01111 = Enable only SW16A (0x8000)
10000 = Disable all bank A switches (0x0000)
Description
10001 = Copy A shadows registers (SHDW0 and SHDW1) to switches
10010 ..11111 = No change on bank A
CMD_B 0x15
BIT
7
6
5
4
3
0
2
0
1
0
0
0
BIT Name
Reset Value
RFU
0
RFU
0
RFU
0
SelB
0
SelB
00000 = Enable only SW01B (0x0001)
00001 = Enable only SW02B (0x0002)
00010 = Enable only SW03B (0x0004)
00011 = Enable only SW04B (0x0008)
00100 = Enable only SW05B (0x0010)
00101 = Enable only SW06B (0x0020)
00110 = Enable only SW07B (0x0040)
00111 = Enable only SW08B (0x0080)
01000 = Enable only SW09B (0x0100)
01001 = Enable only SW10B (0x0200)
01010 = Enable only SW11B (0x0400)
01011 = Enable only SW12B (0x0800)
01100 = Enable only SW13B (0x1000)
01101 = Enable only SW14B (0x2000)
01110 = Enable only SW15B (0x4000)
01111 = Enable only SW16B (0x8000)
10000 = Disable all bank B switches (0x0000)
RFU = Reserved
Description
10001 = Copy B shadows registers (SHDW2 and SHDW3) to switches
10010 .. 11111 = No change on bank B
Maxim Integrated
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Set Mux Command Registers
Detailed Description
The set mux command registers allow the user to easily
select any one single switch in a bank. The CMD_A regis-
ter allows the user to turn on one single switch in bank A,
to open the entire bank A switches, to copy SHDW0 and
SHDW1 registers to DIR0 and DIR1 registers, or to leave
bank A as it is (no changes). Similarly, the CMD_B reg-
ister allows the user to turn on one single switch in bank
B, to open the entire bank B switches, to copy SHDW2
and SHDW3 registers to DIR2 and DIR3 registers, or to
leave bank B as it is (no changes). The values apply to
the switches after both registers (CMD_A and CMD_B)
have been written. CMD_A and CMD_B are a single
16-bit register; therefore, CMD_A must be programmed
before CMD_B.
Low-Power Shutdown
The device includes an active-low shutdown pin (SD).
When this pin is low, all registers are cleared and all
switches are open. The serial interface is not functional
when in shutdown. All switch connections are open and
tolerant of the full ±5.5V specified signal range. In this
mode the part consumes minimal power.
SPI Output Supply
2
The SPI/I C pin has a dual purpose. In addition to select-
ing which serial protocol the part uses, it also functions as
the I/O voltage power pin for the SPI DOUT signal. This
allows the user to set the output voltage independent of
the device supply voltage.
Serial Addressing
When in I C mode, the MAX14661 operates as a slave
device that sends and receives data through an I C-
2
I C Serial Interface
2
2
Direct Access Registers
compatible 2-wire interface. The interface uses a serial-
data line (SDA) and a serial-clock line (SCL) to achieve
bidirectional communication between master(s) and
slave(s). A master (typically a microcontroller) initiates all
data transfers to and from the MAX14661 and generates
the SCL clock that synchronizes the data transfer. The
SDA line operates as both an input and an open-drain
output.ꢀAꢀpullupꢀresistorꢀisꢀrequiredꢀonꢀSDA.ꢀTheꢀSCLꢀlineꢀ
operatesꢀonlyꢀasꢀanꢀinput.ꢀAꢀpullupꢀresistorꢀisꢀrequiredꢀonꢀ
SCL if there are multiple masters on the 2-wire interface,
or if the master in a single-master system has an open-
drain SCL output. Each transmission consists of a START
condition sent by a master, followed by the MAX14661
7-bit slave address plus R/W bit, a register address byte,
one or more data bytes, and finally a STOP condition
(Figure 4).
The direct access registers (DIR0–DIR3) allow the user to
read or write the switches eight at a time. These register
addresses support automatic incrementing so they can
beꢀreadꢀorꢀwrittenꢀsequentially.ꢀTheꢀswitchesꢀareꢀupdatedꢀ
after the last bit of the byte clocked in.
Shadow Registers
The shadow registers (SHDW0–SHDW3) provide storage
for switch values to allow for simultaneous updates of the
switches. Unlike the direct access registers, these regis-
ters have no immediate effect until the copy command is
issued. The copy command has to be written in CMD_A
and CMD_B registers. Simply write to the four registers
with the desired state of each switch, and then write the
appropriate command to registers CMD_A and CMD_B to
simultaneously apply the values to the switches.
t
R
SDA
t
BUF
t
t
SU:STA
SU:DAT
t
HD:STA
t
LOW
t
SU:STO
t
HD:DAT
t
SCL
HIGH
t
HD:STA
t
R
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
2
Figure 4. I C Interface Timing Details
Maxim Integrated
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse. The SDA line is stable low during the high period
of the clock pulse. When the master is transmitting to the
MAX14661, it generates the acknowledge bit because the
device is the recipient. When the device is transmitting
to the master, the master generates the acknowledge bit
because the master is the recipient. If the device did not
pull SDA low, a not acknowledge is indicated.
Start and Stop Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (Figure 5). When the master has
finished communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission.
Bit Transfer
Slave Address
The MAX14661 features a 7-bit slave address, configured
by the A0 and A1 inputs. To select the slave address, con-
One data bit is transferred during each clock pulse
(Figure 6). The data on SDA must remain stable while
SCL is high.
nect A0 and A1 to GND or V , as indicated in Table 3.
CC
Acknowledge
The IC has four possible addresses, allowing up to four
MAX14661 devices to share the same interface bus. The
bit following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
The acknowledge bit is a clocked 9th bit (Figure 7), which
the recipient uses to handshake receipt of each byte of
data.ꢀ Thus,ꢀ eachꢀ byteꢀ transferredꢀ effectivelyꢀ requiresꢀ 9ꢀ
SDA
SCL
SDA
SCL
S
P
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
START
CONDITION
STOP
CONDITION
Figure 6. Bit Transfer
Figure 5. Start and Stop Conditions
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
CONDITION
SCL
1
2
8
9
SDA BY
TRANSMITTER
SDA BY
RECEIVER
S
Figure 7. Acknowledge
Table 3. Slave Address Configuration
2
I C SLAVE ADDRESS
LOGIC INPUTS
READ
ADD
WRITE
ADD
A1
A0
A6
A5
A4
A3
A2
A1
A0
R/W
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1/0
1/0
1/0
1/0
0X99
0X9B
0X9D
0X9F
0X98
0X9A
0X9C
0X9E
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
dataꢀbytesꢀgoꢀintoꢀsubsequentꢀregistersꢀ(Figure 8). If mul-
tiple data bytes are transmitted before a STOP condition,
theseꢀbytesꢀareꢀstoredꢀinꢀsubsequentꢀregistersꢀbecauseꢀ
the register addresses autoincrement (Figure 9).
Bus Reset
2
The MAX14661 resets the bus with the I C start condi-
tion for reads. When the R/W bit is set to 1, the device
transmits data to the master, thus the master is reading
from the device.
Format for Reading
The MAX14661 is read using the internally stored register
address as an address pointer, the same way the stored
register address is used as an address pointer for a write.
The pointer autoincrements after each data byte is read
using the same rules as for a write. Thus, a read is initiat-
ed by first configuring the register address by performing
a write (Figure 10). The master can now read consecutive
bytes from the device, with the first data byte being read
from the register addressed pointed by the previously
written register address (Figure 11). Once the master
sounds a NACK, the MAX14661 stops sending valid data.
Format for Writing
A write to the MAX14661 comprises the transmission of
the slave address with the R/W bit set to zero, followed
by at least 1 byte of information. The first byte of informa-
tion is the register address or command byte. The register
address determines which register of the device is to be
written by the next byte, if received. If a STOP (P) condi-
tion is detected after the register address is received,
then the device takes no further action beyond storing
the register address. Any bytes received after the register
address are data bytes. The first data byte goes into the
registerꢀselectedꢀbyꢀtheꢀregisterꢀaddressꢀandꢀsubsequentꢀ
ADDRESS = 0x98
REGISTER ADDRESS = 0x01
0 = WRITE
S
1
0
0
1
1
0
0
0
A
P
0
0
0
0
0
0
0
1
A
REGISTER 0x01 WRITE DATA
S = START BIT
P = STOP BIT
A = ACK
d7
d6
d5
d4
d3
d2
d1
d0
A
N = NACK
d_ = DATA BIT
2
Figure 8. Format for I C Write
ADDRESS = 0x98
REGISTER ADDRESS = 0x01
0 = WRITE
S
1
0
0
1
1
0
0
0
A
0
0
0
0
0
0
0
1
A
REGISTER 0x02 WRITE DATA
REGISTER 0x01 WRITE DATA
d7
d6
d5
d4
d3
d2
d1
d0
A
A/N
d7
d6
d5
d4
d3
d2
d1
d0
P
Figure 9. Format for Writing to Multiple Registers
Maxim Integrated
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
0 = WRITE
REGISTER ADDRESS = 0x01
ADDRESS = 0x98
A
S
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
A/N
1 = READ
ADDRESS = 0x99
REGISTER 0x01 READ DATA
A
Sr
1
1
1
d7
d6
d5
d4
d3
d2
d1
d0
A/N
P
Figure 10. Format for Reads (Repeated Start)
0 = WRITE
REGISTER ADDRESS = 0x01
ADDRESS = 0x98
A
A
S
Sr
d7
1
1
0
0
0
0
1
1
0
0
0
0
0
0
d7
d7
0
d6
d6
0
0
0
0
0
d1
d1
1
d0
d0
A/N
1 = READ
ADDRESS = 0x99
REGISTER 0x01 READ DATA
1
1
1
d5
d4
d3
d2
A
REGISTER 0x02 READ DATA
REGISTER 0x03 READ DATA
A
d6
d5
d4
d3
d2
d1
d0
d5
d4
d3
d2
A/N
P
Figure 11. Format for Reading Multiple Registers
Maxim Integrated
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
by the SPI interface. The first 32 bits out of DOUT after
the falling edge of CS are the contents of the shift register
prior to CS falling, followed by the data being clocked into
DIN. The bits in the shift register are all zero when power
is applied or after shutdown is released.
SPI Interface
In SPI mode, the device operates a shift register designed
to work with common serial interfaces. The bits are shifted
through so that a large serial chain can be made to
minimize pins needed for a system with multiple devices.
(See Figure 12.) This shift register is also designed to
be compatible with common microcontroller SPI-type
interfaces. The switches in the MAX14661 are all tran-
sitioned simultaneously. To update the switches in SPI
mode, the user must shift in a bit with the desired state of
each switch according to the data format listed in Table 4.
The switches are updated at the rising edge of CS with
the last 32 bits of data shifted in only if the number of
bits clocked in is greater than or equal to the number
of switches (32). The DOUT pin is the serial output of
the shift register. This outputs the data loaded into DIN,
delayed by 32 clocks, and is intended for creating a serial
daisyꢀchainꢀtoꢀminimizeꢀtheꢀnumberꢀselectꢀlinesꢀrequiredꢀ
Note that the data in the shift register may not be the same
as the state of the switches. The DOUT pin is intended
for daisy chain applications and not for switch readback.
Note for V
less than 2.7V, the DOUT propagation
CC
delayꢀ canꢀ limitꢀ theꢀ maximumꢀ SPIꢀ operatingꢀ frequency.ꢀ
See Figures 12 and 13 for the SPI timing diagrams. The
voltage level driven out by the DOUT buffer is set by the
2
voltage applied to SPI/I C. This allows the voltage to be
independent from the supply voltage. While we expect the
2
voltage at SPI/I CꢀtoꢀbeꢀlessꢀthanꢀorꢀequalꢀtoꢀVCC in most
applications, it can be higher than VCC as long as it does
not exceed VCC before VCC has reached at least 1.8V.
Table 4. SPI Data Format
BYTE
First
BIT7
SW16B
SW08B
SW16A
SW08A
BIT6
SW15B
SW07B
SW15A
SW07A
BIT5
SW14B
SW06B
SW14A
SW06A
BIT4
SW13B
SW05B
SW13A
SW05A
BIT3
SW12B
SW04B
SW12A
SW04A
BIT2
SW11B
SW03B
SW11A
SW03A
BIT1
SW10B
SW02B
SW10A
SW02A
BIT0
SW09B
SW01B
SW09A
SW01A
Second
Third
Fourth
CS
t
CH
t
t
CSS
CSH
t
CL
SCLK
t
DS
t
DH
MOSI
MISO
t
DO
Figure 12. SPI Timing Details
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
CS
SCLK
DIN
X
d0
d1
SW16B
SW14B'
SW15B
SW13B'
SW14B
SW12B'
SW13B
SW11B'
SW04A
SW02A'
SW03A
SW01A'
SW02A
d0
SW01A
X
DOUT
SW16B'
SW15B'
d1
‘ REPRESENTS PREVIOUS DATA IN SHIFT REGISTER
D0 AND D1 CAN BE ANY DATA. BITS. THEY ARE THERE SIMPLY TO DEMONSTRATE
THAT THE DEVICE USES THE LAST N BITS RECEIVED TO UPDATE THE SWITCHES.
Figure 13. SPI Timing Diagram
troller, as many devices as desired can be loaded by con-
necting all the CS and SCK pins in parallel and chaining
the DOUT pin from one device to the DIN pin on the next.
It is also acceptable to provide a separate CS pin for each
device so that they can be individually addressed and
loaded. Alternatively a separate data line can be used for
eachꢀ deviceꢀ toꢀ reduceꢀ theꢀ timeꢀ requiredꢀ toꢀ loadꢀ allꢀ theꢀ
devices. Some of the options and tradeoffs are listed in
Table 5, as well as example application diagrams in the
Typical Application Circuit.
Applications Information
Serial Bus Configurations
The MAX14661 was designed to support a wide variety
of multiplexing applications. Multiple devices can be used
in a system to expand the number of ports being multi-
plexed. With the two address-select pins provided in I C
mode, four devices can be attached to the same I C bus
simultaneously using only two pins. There are also sev-
eral options for addressing multiple devices when using
the SPI interface. Using only three pins on the microcon-
2
2
Table 5. Benefits and Limitations of Different Serial-Bus Configurations
SERIAL BUS
PINS
BENEFITS
LIMITATIONS
Maximum four devices per bus, slow protocol, no
simultaneous updates across all devices
I2C (Figure 16)
2
Fewest Pins
SPI Daisy
Chain
(Figure 19)
Faster than I2C with only one additional pin,
simultaneous updates across all devices in chain
3
nꢀxꢀ32ꢀclocksꢀrequiredꢀtoꢀloadꢀallꢀdevices
nꢀxꢀ32ꢀclocksꢀrequiredꢀtoꢀloadꢀallꢀdevices,ꢀ
requiresꢀanꢀadditionalꢀpinꢀperꢀdevice,ꢀnoꢀ
simultaneous updates across all devices
SPI Separate
CS (Figure 17)
CommonꢀSPIꢀimplementation,ꢀquickꢀforꢀsingleꢀ
device updates
n+2
n+2
SPI Separate
Data
(Figure 18)
Fastest loading for multiple devices,
simultaneous updates across all devices
Requiresꢀanꢀadditionalꢀpinꢀperꢀdevice,ꢀꢀmayꢀnotꢀ
be supported by SPI controller
Maxim Integrated
│ 20
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Extended ESD
ESD Test Conditions
ESD protection structures are incorporated on all pins
to protect against electrostatic discharges up to ±2kV
(HBM) encountered during handling and assembly. AB_
and COM_ are further protected against ESD up to ±10kV
(HBM) without damage. The ESD structures withstand
high ESD both in normal operation and when the device
is powered down. After an ESD event, the MAX14661
continues to function without latchup.
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Human Body Model
Figure 14 shows the Human Body Model. Figure 15
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest
thatꢀisꢀthenꢀdischargedꢀintoꢀtheꢀdeviceꢀthroughꢀaꢀ1.5kΩꢀ
resistor.
R
R
D
1.5kΩ
C
1MΩ
I
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
P
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPERES
36.8%
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
STORAGE
CAPACITOR
S
100pF
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 14. Human Body ESD Test Model
Figure 15. Human Body Current Waveform
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Typical Application Circuit
2V5
V
CC
COMB
COMB
SD
SCL
COMA
COMA
SDA
SCL
A1
µCONTROLLER
SDA
MAX14661
A0
AB1–AB16
AB0–AB15
2
SPI/I C
GND
2V5
2V5
2V5
V
CC
COMB
COMA
COMB
COMA
SD
SDA
SCL
A1
MAX14661
A0
AB1–AB16
AB16–AB31
2
SPI/I C
GND
V
CC
COMB
COMA
COMB
COMA
SD
SDA
SCL
A1
MAX14661
A0
AB1–AB16
AB32–AB47
2
SPI/I C
GND
V
CC
COMB
COMA
1V8
COMB
COMA
SD
SDA
MAX14661
SCL
A1
A0
AB1–AB16
AB48–AB63
2
SPI/I C
GND
2
Figure 16. I C Controlled 64:2 MUX
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Typical Application Circuit (continued)
1V8 3V3
V
CC
COMD
COMB
SD
2
MOSO
MOSI
SCK
SPI/I C
COMC
COMA
MAX14661
DIN
µCONTROLLER
SCLK
CS
CS1
AB1–AB16
AB0–AB15
CS0
DOUT
GND
1V8 3V3
V
CC
COMB
COMA
SD
COMB
COMA
2
SPI/I C
MAX14661
DIN
SCLK
CS
AB1–AB16
AB0–AB15
DOUT
GND
Figure 17. SPI Separate CS 16:4
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MAX14661
Beyond-the-Rails 16:2 Multiplexer
Typical Application Circuit (continued)
3V3
3V3
V
V
CC
CC
B15
B14
B7
B6
COMB
COMB
2
2
SPI/I C
SD
SPI/I C
SD
COMA
MAX14661
AB1–AB16
COMA
MAX14661
AB1–AB16
DIN
DIN
SCLK
CS
SCLK
CS
A0–A15
A0–A15
DOUT
GND
DOUT
GND
3V3
3V3
V
V
CC
CC
B13
B12
B5
B4
COMB
COMB
2
2
SPI/I C
SD
SPI/I C
SD
COMA
MAX14661
AB1–AB16
COMA
MAX14661
AB1–AB16
DIN
DIN
SCLK
CS
SCLK
CS
A0–A15
A0–A15
DOUT
GND
DOUT
GND
3V3
3V3
V
V
CC
CC
B11
B10
B3
B2
COMB
COMB
2
2
SPI/I C
SD
SPI/I C
SD
COMA
MAX14661
AB1–AB16
COMA
MAX14661
AB1–AB16
DIN
DIN
SCLK
CS
SCLK
CS
A0–A15
A0–A15
DOUT
GND
DOUT
GND
3V3
3V3
V
V
CC
CC
B9
B8
B1
B0
COMB
COMB
2
2
SPI/I C
SD
SPI/I C
SD
COMA
MAX14661
AB1–AB16
COMA
MAX14661
AB1–AB16
DIN
DIN
SCLK
CS
SCLK
CS
D7
D6
A0–A15
A0–A15
DOUT
GND
DOUT
GND
D5
D4
D3
D2
D1
D0
SCK
CS
Figure 18. SPI Separate Data 16:16 MUX
Maxim Integrated
│ 24
www.maximintegrated.com
MAX14661
Beyond-the-Rails 16:2 Multiplexer
Typical Application Circuit (continued)
2V5
V
CC
COMB
COMB
2
SPI/I C
SD
COMA
COMA
MISO
MOSI
MAX14661
DIN
SCLK
CS
SCK
CS
AB1–AB16
AB0–AB15
DOUT
GND
2V5
2V5
2V5
V
CC
COMB
COMA
COMB
COMA
2
SPI/I C
SD
MAX14661
DIN
SCLK
CS
AB1–AB16
AB1–AB15
DOUT
GND
V
CC
COMB
COMA
COMB
COMA
2
SPI/I C
SD
DIN
SCLK
CS
MAX14661
AB1–AB16
AB1–AB15
DOUT
GND
V
CC
COMB
COMA
COMB
COMA
2
SPI/I C
SD
MAX14661
DIN
SCLK
CS
AB1–AB16
AB1–AB15
DOUT
GND
Figure 19. SPI Daisy Chain 256:2 MUX
Maxim Integrated
│ 25
www.maximintegrated.com
MAX14661
Beyond-the-Rails 16:2 Multiplexer
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
PIN-PACKAGE
28 TQFN
4mm x 4mm
MAX14661ETI+
-40°C to +85°C
-40°C to +85°C
28 TQFN
4mm x 4mm
MAX14661ETI+T
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
+Denotes lead(Pb)-free/RoHS-compliant package.
T = Tape and reel
28 TQFN-EP
T2844+1
21-0139
90-0035
*EP = Exposed Pad.
Chip Information
PROCESS: BiCMOS
Maxim Integrated
│ 26
www.maximintegrated.com
MAX14661
Beyond-the-Rails 16:2 Multiplexer
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
2
6/13
1/14
1/15
Initial release
—
26
1
Added MAX14661ETI+
Updated page 1 content
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
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