MAX149BEAP-TG071 [MAXIM]
D/A Converter, 10-Bit, 1 Func, 8 Channel, Serial Access, CMOS, PDSO20, SSOP-20;
| 型号： | MAX149BEAP-TG071 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 10-Bit, 1 Func, 8 Channel, Serial Access, CMOS, PDSO20, SSOP-20 光电二极管 |
| 文件： | 总23页 (文件大小：1916K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+3V
V
DD
CH0
V
DD
0.1FF
O TO
+2.5V
ANALOG
INPUTS
DGND
MAX149
AGND
COM
CH7
CPU
VREF
4.7FF
CS
SCLK
DIN
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
READJ
DOUT
0.01FF
SSTRB
SHDN
V
SS
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
DD
AGND to DGND ...................................................-0.3V to +0.3V
CH0–CH7, COM to AGND, DGND........... -0.3V to (V
VREF, REFADJ to AGND...........................-0.3V to (V
Digital Inputs to DGND ...........................................-0.3V to +6V
Digital Outputs to DGND.......................... -0.3V to (V + 0.3V)
Digital Output Sink Current ................................................25mA
V
to AGND, DGND..............................................-0.3V to +6V
SSOP (derate 8.00mW/NC above +70NC)....................640mW
CERDIP (derate 11.11mW/NC above +70NC) ..............889mW
Operating Temperature Ranges
MAX148_C_P/MAX149_C_P .............................. 0NC to +70NC
MAX148_E_P/MAX149_E_P............................ -40NC to +85NC
MAX148_MJP/MAX149_MJP ........................ -55NC to +125NC
MAX149BMAP............................................... -55NC to +125NC
Storage Temperature Range............................ -60NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
+ 0.3V)
+ 0.3V)
DD
DD
DD
Continuous Power Dissipation (T = +70NC)
A
Plastic DIP (derate 11.11mW/NC above +70NC)..........889mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +5.25V; COM = 0; f
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
DD
SCLK
MAX149—4.7FF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; T = T
to T
, unless
MAX
A
MIN
otherwise noted.)
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
Bits
LSB
LSB
LSB
MAX14_A
MAX14_B
0.5
1.0
1
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
DNL
No missing codes over temperature
MAX14_A
MAX14_B
MAX14_A
MAX14_B
0.15
0.15
1
2
1
Gain Error (Note 3)
LSB
2
Gain Temperature Coefficient
0.25
0.05
ppm/°C
Channel-to-Channel Offset
Matching
LSB
DYNAMIC SPECIFICATIONS (10kHz Sine-Wave Input, 0 to 2.500V , 133ksps, 2.0MHz External Clock, Bipolar Input Mode)
P-P
Signal-to-Noise + Distortion
Noise
SINAD
66
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
Full-Power Bandwidth
THD
Up to the 5th harmonic
-70
70
dB
dB
SFDR
65kHz, 2.500V
-3dB rolloff
(Note 4)
-75
2.25
1.0
dB
P-P
MHz
MHz
CONVERSION RATE
5.5
35
7.5
65
Internal clock, SHDN = unconnected
Internal clock, SHDN = V
DD
Conversion Time (Note 5)
t
μs
CONV
External clock = 2MHz, 12 clocks/
conversion
6
Track/Hold Acquisition Time
Aperture Delay
t
1.5
μs
ns
ps
ACQ
30
Aperture Jitter
< 50
2
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +5.25V; COM = 0; f
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
DD
SCLK
MAX149—4.7FF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; T = T
to T
, unless
MAX
A
MIN
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE (continued)
1.8
SHDN = unconnected
SHDN = V
Internal Clock Frequency
MHz
MHz
0.225
DD
0.1
1
2.0
2.0
External Clock Frequency
Data transfer only
ANALOG/COM INPUTS
Unipolar, COM = 0
0 to VREF
VREF/2
1
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
Bipolar, COM = VREF/2
On/off leakage current, V
Multiplexer Leakage Current
Input Capacitance
= 0 or V
0.01
16
μA
pF
CH_
DD
INTERNAL REFERENCE (MAX149 Only, Reference Buffer Enabled)
VREF Output Voltage
2.470
2.500
2.530
30
V
T
= +25°C (Note 7)
A
VREF Short-Circuit Current
VREF Temperature Coefficient
Load Regulation (Note 8)
mA
MAX149
30
ppm/°C
mV
0 to 0.2mA output load
0.35
Internal compensation mode
External compensation mode
0
Capacitive Bypass at VREF
μF
4.7
0.01
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
μF
%
1.5
EXTERNAL REFERENCE AT VREF (Buffer Disabled)
V
+
VREF Input Voltage Range
(Note 9)
DD
1.0
18
V
50mV
VREF Input Current
VREF = 2.500V
100
25
150
μA
kΩ
μA
VREF Input Resistance
Shutdown VREF Input Current
0.01
10
V
0.5
-
DD
REFADJ Buffer-Disable Threshold
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at VREF
V
Internal compensation mode
External compensation mode
MAX149
0
μF
V/V
μA
4.7
2.06
2.00
Reference Buffer Gain
REFADJ Input Current
MAX148
MAX149
50
10
MAX148
_______________________________________________________________________________________
3
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +5.25V; COM = 0; f
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
DD
SCLK
MAX149—4.7FF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; T = T
to T
, unless
MAX
A
MIN
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
V
V
≤ 3.6V
> 3.6V
2.0
3.0
DD
V
V
DIN, SCLK, CS Input High Voltage
IH
DD
V
0.8
V
V
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
IL
V
0.2
HYST
I
V
= 0 or V
DD
0.01
1
μA
pF
IN
IN
C
IN
(Note 10)
15
V
-
DD
0.4
V
V
V
SHDN Input High Voltage
SHDN Input Mid Voltage
SH
V
-
DD
V
1.1
SM
1.1
V
0.4
V
μA
V
SHDN Input Low Voltage
SHDN Input Current
SL
I
4.0
SHDN = 0 or V
S
DD
V
FLT
V /2
DD
SHDN Voltage, Unconnected
SHDN = unconnected
SHDN Maximum Allowed
Leakage, Mid Input
100
nA
SHDN = unconnected
DIGITAL OUTPUTS (DOUT, SSTRB)
I
I
= 5mA
0.4
0.8
SINK
Output-Voltage Low
V
V
V
OL
= 16mA
SINK
V
DD
0.5
-
Output-Voltage High
V
I
= 0.5mA
OH
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
I
0.01
10
15
μA
pF
CS = V
CS = V
L
DD
C
(Note 10)
OUT
DD
V
DD
2.70
5.25
3.0
2.0
15
V
V
DD
V
DD
V
DD
V
DD
= 5.25V
= 3.6V
= 5.25V
= 3.6V
1.6
1.2
3.5
1.2
30
Operating mode, full-scale
input (Note 11)
mA
Positive Supply Current
I
DD
Full power-down
10
μA
Fast power-down (MAX149)
70
Full-scale input, external reference =
2.500V, V = 2.7V to 5.25V
Supply Rejection (Note 12)
PSR
0.3
mV
DD
4
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
TIMING CHARACTERISTICS
(V
= +2.7V to +5.25V, T = T
A
to T , unless otherwise noted.)
MAX
DD
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1.5
100
0
TYP
MAX
UNITS
μs
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
t
ACQ
t
ns
DS
DH
t
ns
MAX14_ _C/E
MAX14_ _M
20
200
240
240
240
SCLK Fall to Output Data Valid
t
Figure 1
ns
DO
20
t
Figure 1
Figure 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
DV
t
TR
t
100
0
CSS
CSH
t
t
200
200
CH
t
CL
t
Figure 1
240
240
240
SSTRB
t
External clock mode only, Figure 1
External clock mode only, Figure 2
Internal clock mode only (Note 7)
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
SDV
t
STR
t
0
SCK
Note 1: Tested at V
= 2.7V; COM = 0; unipolar single-ended input mode.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (V
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
= +2.500V), offset nulled.
REF
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V
Note 7: Sample tested to 0.1% AQL.
.
DD
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300FV
Note 10: Guaranteed by design. Not subject to production testing.
.
P-P
Note 11: The MAX148 typically draws 400FA less than the values shown.
Note 12: Measured as |V (2.7V) - V (5.25V)|.
FS
FS
_______________________________________________________________________________________
5
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Typical Operating Characteristics
(V
DD
= 3.0V, VREF = 2.500V, f
= 2.0MHz, C
= 20pF, T = +25NC, unless otherwise noted.)
SCLK
LOAD
A
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. CODE
0.125
0.125
0.100
0.075
0.050
0.025
0
V
= 2.7V
DD
0.10
0.100
0.075
0.050
0.025
0
0.05
0
MAX149
MAX148
MAX149
MAX148
-0.05
-0.10
0
256
512
768
1024
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
-60
-20
20
60
100
140
CODE
TEMPERATURE (NC)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX149 INTERNAL REFERENCE
VOLTAGE vs. SUPPLY VOLTAGE
2.00
1.75
1.50
1.25
1.00
0.75
0.50
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5020
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
RL = J
CODE = 1010101000
FULL POWER-DOWN
C
= 50pF
LOAD
MAX149
C
= 20pF
LOAD
MAX148
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX149 INTERNAL REFERENCE
VOLTAGE vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
1.3
1.2
1.1
1.0
0.9
0.8
2.0
1.6
1.2
0.8
0.4
0
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.494
V
= 5.25V
DD
MAX149
V
DD
= 3.6V
V
= 2.7V
DD
MAX148
R
= J
L0AD
CODE = 1010101000
-20 20
TEMPERATURE (NC)
-60
60
100
140
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (NC)
TEMPERATURE (NC)
6
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Pin Description
PIN
NAME
CH0–CH7 Sampling Analog Inputs
FUNCTION
1–8
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to 0.5 LSB.
9
COM
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they
are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation
mode. Leaving SHDN unconnected puts the reference-buffer amplifier in external compensation
mode.
10
SHDN
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
11
VREF
REFADJ to V
.
DD
12
13
14
15
REFADJ
AGND
DGND
DOUT
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
.
DD
Analog Ground
Digital Ground
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin
the A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high
(external clock mode).
16
SSTRB
17
18
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
CS
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed (duty cycle must be 40% to 60%).
19
20
SCLK
V
Positive Supply Voltage
DD
V
DD
V
DD
6kI
6kI
DOUT
6kI
DOUT
DOUT
DOUT
C
50pF
C
50pF
LOAD
LOAD
C
50pF
C
LOAD
50pF
LOAD
6kI
DGND
DGND
DGND
HIGH-Z
DGND
a) HIGH-Z TO V AND V TO V
a) V
b) V
OL TO
HIGH-Z
b) HIGH-Z TO V AND V TO V
OL
OH TO
OH
OL
OH
OL
OH
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________________________________________________________________________________
7
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
control word has been entered. At the end of the acquisi-
tion interval, the T/H switch opens, retaining charge on
as a sample of the signal at IN+.
Detailed Description
The MAX148/MAX149 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible
serial interface provides easy interface to microproces-
sors (FPs). Figure 3 is a block diagram of the MAX148/
MAX149.
C
HOLD
The conversion interval begins with the input multiplexer
switching C from the positive input (IN+) to the
HOLD
negative input (IN-). In single-ended mode, IN- is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0 within
the limits of 10-bit resolution. This action is equivalent to
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit (Figure
4). In single-ended mode, IN+ is internally switched to
CH0–CH7, and IN- is switched to COM. In differential
mode, IN+ and IN- are selected from the following
pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7.
Configure the channels with Tables 2 and 3.
transferring a 16pF x [(V ) - (V )] charge from C
IN+
IN-
HOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-| is sampled. At the end of the
conversion, the positive input connects back to IN+, and
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain stable
within Q0.5 LSB (Q0.1 LSB for best results) with respect
to AGND during a conversion. To accomplish this, con-
nect a 0.1FF capacitor from IN- (the selected analog
input) to AGND.
C
HOLD
charges to the input signal.
During the acquisition interval, the channel selected as
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
the positive input (IN+) charges capacitor C
. The
HOLD
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
18
CS
19
SCLK
CAPACITIVE DAC
VREF
INPUT
SHIFT
INT
CLOCK
17
10
DIN
CONTROL
LOGIC
REGISTER
COMPARATOR
INPUT
MUX
SHDN
C
-
HOLD
ZERO
1
2
3
4
5
6
7
8
9
15
16
+
OUTPUT
SHIFT
REGISTER
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DOUT
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
16pF
SSTRB
R
IN
ANALOG
INPUT
MUX
T/H
C
SWITCH
CLOCK
9kΩ
10+2-BIT
SAR
ADC
IN
HOLD
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
TRACK
T/H
SWITCH
OUT
REF
20
14
13
A ≈ 2.06*
V
DD
20kΩ
+1.21V
REFERENCE
(MAX149)
DGND
AGND
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
REFADJ
VREF
12
11
MAX148
MAX149
+2.500V
*A ≈ 2.00 (MAX148)
Figure 3. Block Diagram
Figure 4. Equivalent Input Circuit
8
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
OSCILLOSCOPE
V
+3V
DD
0.1µF
DGND
AGND
COM
CS
SCLK
MAX148
MAX149
0 TO
+2.500V
ANALOG
INPUT
SSTRB
DOUT*
CH7
0.01µF
SCLK
DIN
+3V
2MHz
OSCILLATOR
REFADJ
VREF
+3V
2.5V
+3V
CH1
CH2
CH3
CH4
V
OUT
DOUT
SSTRB
C1
0.1µF
1000pF
MAX872
COMP
SHDN
N.C.
OPTIONAL FOR MAX149,
REQUIRED FOR MAX148
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
Figure 5. Quick-Look Circuit
allowed between conversions. The acquisition time,
, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
Analog Input Protection
Internal protection diodes, which clamp the analog
input to V and AGND, allow the channel input pins to
t
ACQ
DD
swing from AGND - 0.3V to V
+ 0.3V without damage.
DD
However, for accurate conversions near full scale, the
inputs must not exceed V by more than 50mV or be
DD
t
= 7 x (R + R ) x 16pF
S IN
ACQ
lower than AGND by 50mV.
where R = 9kI, R = the source impedance of the
IN
S
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of off
channels over 2mA.
input signal, and t
is never less than 1.5Fs. Note that
ACQ
source impedances below 4kIdo not significantly affect
the ADC’s AC performance.
Higher source impedances can be used if a 0.01FF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with
the input source impedance, limiting the ADC’s signal
bandwidth.
Quick Look
To quickly evaluate the MAX148/MAX149’s analog per-
formance, use the circuit of Figure 5. The MAX148/
MAX149 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in
control bytes of $FF (HEX), which trigger single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In external
clock mode, the SSTRB output pulses high for one clock
period before the most significant bit of the conversion
result is shifted out of DOUT. Varying the analog input to
CH7 will alter the sequence of bits from DOUT. A total of
15 clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate
by using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
_______________________________________________________________________________________
9
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Table 1. Control-Byte Format
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
START
SEL2
SEL1
SEL0
PD1
PD0
UNI/BIP
SGL//DIF
BIT
NAME
DESCRIPTION
The first logic “1” bit after CS goes low defines the beginning of the control byte.
7(MSB)
START
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion (Tables 2 and 3)
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0 to VREF can be converted; in bipolar mode, the signal can range from
-VREF/2 to +VREF/2.
3
UNI/BIP
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
2
1
SGL/DIF
PD1
Selects clock and power-down modes.
PD1
0
PD0
0
Mode
Full power-down
0(LSB)
PD0
0
1
Fast power-down (MAX149 only)
Internal clock mode
External clock mode
1
0
1
1
Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
polarity and sampling edge in the SPI control registers:
set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and
QSPI all transmit a byte and receive a byte at the same
time. Using the Typical Operating Circuit, the simplest
software interface requires only three 8-bit transfers to
perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
conversion result). See Figure 20 for MAX148/ MAX149
QSPI connections.
How to Start a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX148/MAX149’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX148/MAX149 are compatible with SPI/QSPI and
MICROWIRE devices. For SPI, select the correct clock
10 _____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Table 3. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
-
+
-
+
-
+
-
-
-
+
-
+
-
+
+
CS
SCLK
DIN
t
ACQ
1
4
8
12
16
20
24
UNI/
BIP
SGL/
DIF
SEL2 SEL1 SEL0
PD1 PD0
START
SSTRB
DOUT
RB1
RB2
B6
RB3
S0
FILLED WITH
ZEROS
B9
MSB
B0
LSB
B8
B7
B5
B4
B3
B2
B1
S1
ACQUISITION
A/D STATE
1.5Fs
IDLE
CONVERSION
IDLE
(f
= 2MHz)
SCLK
Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f
SCLK
P2MHz)
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero, two sub-LSB bits, and three
trailing zeros. The total conversion time is a function of
the serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120Fs.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is twos
complement (Figure 18). Data is clocked out at the fall-
ing edge of SCLK in MSB-first format.
2) Use a general-purpose I/O line on the CPU to pull CS
low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB2.
Clock Modes
The MAX148/MAX149 may use either an external serial
clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the exter-
nal clock shifts data in and out of the MAX148/MAX149.
5) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB3.
6) Pull CS high.
______________________________________________________________________________________ 11
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
CS
t
t
CSH
t
CSS
CH
t
t
CL
CSH
SCLK
t
DS
t
DH
DIN
t
DV
t
DO
t
TR
DOUT
Figure 7. Detailed Serial-Interface Timing
CS
t
t
STR
SDV
SSRTB
SCLK
t
t
SSTRB
SSTRB
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
The T/H acquires the input signal as the last three bits of
the control byte are clocked into DIN. Bits PD1 and PD0
of the control byte program the clock mode. Figures 7–10
show the timing characteristics common to both modes.
and DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic-low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time, or
droop on the sample-and-hold capacitors may degrade
conversion results. Use internal clock mode if the serial-
clock frequency is less than 100kHz, or if serial-clock
interruptions could cause the conversion interval to
exceed 120Fs.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive- approxi-
mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (Figure 6). SSTRB
12 _____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
CS
1
2
3
4
5
6
7
8
9
10 11 12
18 19 20 21 22 23 24
SCLK
UNI/ SGL/
BIP DIF
SEL2 SEL1 SEL0
PD1 PD0
DIN
START
SSTRB
t
CONV
FILLED WITH
ZEROS
B9
MSB
B0
LSB
DOUT
B8 B7
S1 S0
ACQUISITION
CONVERSION
1.5Fs
7.5Fs MAX
AD STATE
IDLE
IDLE
(f
= 2MHz)(SHDN = UNCONNECTED)
SCLK
Figure 9. Internal Clock Mode Timing
CS
t
CONV
t
CSS
t
t
SCK
CSH
SSTRB
SCLK
t
SSTRB
t
D0
PD0 CLOCK IN
DOUT
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
Internal Clock
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX148/MAX149 and three-states DOUT, but it
does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CS goes high.
In internal clock mode, the MAX148/MAX149 generate
their own conversion clocks internally. This frees the FP
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at
the processor’s convenience, at any clock rate from 0
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5Fs (SHDN = uncon-
nected), during which time SCLK should remain low for
best noise performance.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX148/MAX149 at clock rates exceeding 2.0MHz if
the minimum acquisition time (t ) is kept above 1.5Fs.
ACQ
An internal register stores data when the conversion
is in progress. SCLK clocks the data out of this regis-
ter at any time after the conversion is complete. After
SSTRB goes high, the next falling clock edge produces
the MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9). CS does
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on SCLK’s falling edge, after the eighth bit of
______________________________________________________________________________________ 13
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Table 4. Typical Power-Up Delay Times
REFERENCE-
VREF
CAPACITOR
(µF)
MAXIMUM
SAMPLING RATE
(ksps)
REFERENCE
BUFFER
BUFFER
COMPENSATION
MODE
POWER-DOWN POWER-UP DELAY
MODE
(µs)
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Internal
Internal
External
External
—
—
—
Fast
Full
5
26
300
26
4.7
4.7
—
Fast
Full
See Figure 14c
133
133
133
133
See Figure 14c
Fast
Full
2
2
—
—
Reference-Buffer Compensation
the control byte (the PD0 bit) is clocked into DIN. The
start bit is defined as follows:
In addition to its shutdown function, SHDN selects inter-
nal or external compensation. The compensation affects
both power-up time and maximum conversion speed.
The 100kHz minimum clock rate is limited by droop on
the sample-and-hold and is independent of the compen-
sation used.
The first high bit clocked into DIN with CS low any time
the converter is idle; e.g., after V
is applied.
DD
OR
The first high bit clocked into DIN after bit 3 of a con-
version in progress is clocked onto the DOUT pin.
Unconnect SHDN to select external compensation. The
Typical Operating Circuit uses a 4.7FF capacitor at VREF.
A 4.7FF value ensures reference-buffer stability and
allows converter operation at the 2MHz full clock speed.
External compensation increases power-up time (see the
Choosing Power-Down Mode section and Table 4).
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized
as a start bit; the current conversion is terminated, and
a new one is started.
The fastest the MAX148/MAX149 can run with CS held
low between conversions is 15 clocks per conversion.
Figure 11a shows the serial-interface timing necessary
to perform a conversion every 15 SCLK cycles in exter-
nal clock mode. If CS is tied low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
Pull SHDN high to select internal compensation. Internal
compensation requires no external capacitor at VREF
and allows for the shortest power-up times. The maxi-
mum clock rate is 2MHz in internal clock mode and
400kHz in external clock mode.
Most microcontrollers (FCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a FC can drive the
MAX148/MAX149. Figure 11b shows the serialinterface
timing necessary to perform a conversion every 16 SCLK
cycles in external clock mode.
Choosing Power-Down Mode
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down mode or fast power-down mode via bits 1
and 0 of the DIN control byte with SHDN high or uncon-
nected (Tables 1 and 5). In both software power-down
modes, the serial interface remains operational, but the
ADC does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX148/MAX149 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies stabi-
lize, the internal reset time is 10Fs, and no conversions
should be performed during this phase. SSTRB is high
on power-up and, if CS is low, the first logical 1 on DIN is
interpreted as a start bit. Until a conversion takes place,
DOUT shifts out zeros. Also see Table 4.
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current to
2FA (typ). Fast power-down mode turns off all circuitry
except the bandgap reference. With fast power-down
mode, the supply current is 30FA. Power-up time can be
shortened to 5Fs in internal compensation mode.
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
14 _____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
CS
1
8
15
1
8
15
1
SCLK
DIN
S
CONTROL BYTE 0
S
CONTROL BYTE 1
S
CONTROL BYTE 2
DOUT
SSTRB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS
1
8
16
1
8
16
SCLK
DIN
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6
DOUT
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
CLOCK
MODE
EXTERNAL
EXTERNAL
SHDN
SETS SOFTWARE
POWER-DOWN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
S X X X X X 1 1
S X X X X X 0 0
S X X X X X 1 1
DIN
10 + 2 DATA BITS
10 + 2 DATA BITS
VALID
DATA
INVALID
DATA
DOUT
HARDWARE
POWER-DOWN
POWERED UP
POWERED UP
POWERED UP
MODE
SOFTWARE
POWER-DOWN
Figure 12a. Timing Diagram Power-Down Modes, External Clock
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7FF com-
pensation capacitor when the capacitor is initially fully
discharged. From fast power-down, startup time can be
eliminated by using low-leakage capacitors that do not
discharge more than ½ LSB while shut down. In power-
down, leakage currents at VREF cause droop on the
reference bypass capacitor. Figures 12a and 12b show
the various power-down sequences in both external and
internal clock modes.
______________________________________________________________________________________ 15
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
CLOCK
MODE
INTERNAL
SETS INTERNAL
CLOCK MODE
SETS
POWER-DOWN
5 X X X X X 0 0
S
S X X X X X 1 0
DIN
DATA VALID
DATA VALID
DOUT
SSTRB
CONVERSION
CONVERSION
MODE
POWER-DOWN
POWERED OFF
POWERED UP
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
Table 5. Software Power-Down and Clock
Mode
Table 6. Hard-Wired Power-Down and
Internal Clock Frequency
PD1
PD0
DEVICE MODE
Full Power-Down
Fast Power-Down
Internal Clock
REFERENCE
BUFFER
COMPENSATION FREQUENCY
INTERNAL
CLOCK
DEVICE
MODE
SHDN
STATE
0
0
1
1
0
1
0
1
1
Enabled
Internal
External
225kHz
1.8MHz
External Clock
Unconnected Enabled
Power-
Down
0
—
—
AVERAGE SUPPLY CURRENT vs. CONVERSION
RATE WITH EXTERNAL REFERENCE
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE (USING FULLPD)
10,000
100
10
1
R
= ∞
LOAD
VREF = V = 3.0V
DD
CODE = 1010101000
R
LOAD
= ∞
1000
100
10
CODE = 1010101000
8 CHANNELS
8 CHANNELS
1 CHANNEL
1 CHANNEL
1
0.1
0.1
1
10 100 1k
10k 100k 1M
0.01
0.1
1
10
100
1k
CONVERSION RATE (Hz)
CONVERSION RATE (Hz)
Figure 13. Average Supply Current vs. Conversion Rate with
External Reference
Figure 14a. MAX149 Supply Current vs. Conversion Rate,
FULLPD
16 _____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
The first logical 1 on DIN is interpreted as a start bit and
powers up the MAX148/MAX149. Following the start bit, the
data input word or control byte also determines clock mode
and power-down states. For example, if the DIN word con-
tains PD1 = 1, then the chip remains powered up. If PD0
= PD1 = 0, a power-down resumes after one conversion.
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE (USING FASTPD)
10,000
1000
100
0
R
= ∞
LOAD
CODE = 1010101000
8 CHANNELS
Hardware Power-Down
Pulling SHDN low places the converter in hardware pow-
er-down (Table 6). Unlike software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN being brought low. SHDN also controls the clock
frequency in internal clock mode. Leaving SHDN uncon-
nected sets the internal clock frequency to 1.8MHz. When
returning to normal operation with SHDN unconnected,
1 CHANNEL
1
0.1
1
10 100 1k
10k 100k 1M
there is a t delay of approximately 2MI x C , where C
RC
L
L
CONVERSION RATE (Hz)
is the capacitive loading on the SHDN pin. Pulling SHDN
high sets internal clock frequency to 225kHz. This feature
eases the settling-time requirement for the reference volt-
age. With an external reference, the MAX148/MAX149
can be considered fully powered up within 2Fs of actively
pulling SHDN high.
Figure 14b. MAX149 Supply Current vs. Conversion Rate,
FASTPD
TYPICAL REFERENCE-BUFFER POWER-UP
DELAY vs. TIME IN SHUTDOWN
Power-Down Sequencing
The MAX148/MAX149 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 13, 14a, and 14b show
the average supply current as a function of the sampling
rate. The following discussion illustrates the various
power-down sequences.
2.0
1.5
1.0
0.5
0
Lowest Power at Up to 500
Conversions/Channel/Second
The following examples show two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (s)
Figure 14a depicts the MAX149 power consumption for
one or eight channel conversions utilizing full power-
down mode and internal-reference compensation. A
0.01FF bypass capacitor at REFADJ forms an RC filter
with the internal 20kI reference resistor with a 0.2ms
time constant. To achieve full 10-bit accuracy, 8 time
constants or 1.6ms are required after power-up. Waiting
this 1.6ms in FASTPD mode instead of in full power-up
can reduce power consumption by a factor of 10 or
more. This is achieved by using the sequence shown in
Figure 15.
Figure 14c. Typical Reference-Buffer Power-Up Delay vs.
Time in Shutdown
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 5, PD1 and
PD0 also specify the clock mode. When software shut-
down is asserted, the ADC operates in the last specified
clock mode until the conversion is complete. Then the
ADC powers down into a low quiescent-current state.
In internal clock mode, the interface remains active
and conversion results may be clocked out after the
MAX148/MAX149 enter a software power-down.
______________________________________________________________________________________ 17
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
COMPLETE CONVERSION SEQUENCE
1.6ms WAIT
0 1
(ZEROS)
CH1
CH7
(ZEROS)
DIN
1
0 0
1
1
1 1
1
0 0
1
0 1
FULLPD
FASTPD
FULLPD
NOPD
FASTPD
1.21V
0
REFADJ
VREF
H= RC = 20kIx C
REFADJ
2.50V
0
t
75Fs
BUFFEN =
Figure 15. MAX149 FULLPD/FASTPD Power-Up Sequence
+3.3V
OUTPUT CODE
24kI
FULL-SCALE
TRANSITION
TRANSITION
11...111
MAX149
510kI
11...110
11...101
REFADJ
100kI
12
0.01µF
FS = VREF + COM
ZS = COM
VREF
1 LSB =
Figure 16. MAX149 Reference-Adjust Circuit
1024
00...011
00...010
00...001
00...000
Lowest Power at Higher Throughputs
Figure 14b shows the power consumption with external-
reference compensation in fast power-down, with one
and eight channels converted. The external 4.7FF com-
pensation requires a 75Fs wait after power-up with one
dummy conversion. This graph shows fast multichannel
conversion with the lowest power consumption possible.
Full power-down mode may provide increased power
savings in applications where the MAX148/MAX149 are
inactive for long periods of time, but where intermittent
bursts of high-speed conversions are required.
0
1
2
3
FS
(COM)
INPUT VOLTAGE (LSB)
FS - 3/2 LSB
Figure 17. Unipolar Transfer Function, Full Scale (FS) = VREF
+ COM, Zero Scale (ZS) = COM
Internal Reference (MAX149)
The MAX149’s full-scale range with the internal refer-
ence is 2.5V with unipolar inputs and Q1.25V with bipolar
inputs. The internal reference voltage is adjustable to
Q1.5% with the circuit in Figure 16.
Internal and External References
The MAX149 can be used with an internal or external
reference voltage, whereas an external reference is
required for the MAX148. An external reference can be
connected directly at VREF or at the REFADJ pin.
External Reference
With both the MAX149 and MAX148, an external refer-
ence can be placed at either the input (REFADJ) or the
output (VREF) of the internal reference-buffer amplifier.
The REFADJ input impedance is typically 20kI for the
MAX149, and higher than 100kI for the MAX148. At
VREF, the DC input resistance is a minimum of 18kI.
During conversion, an external reference at VREF must
An internal buffer is designed to provide 2.5V at VREF
for both the MAX149 and the MAX148. The MAX149’s
internally trimmed 1.21V reference is buffered with a
2.06 gain. The MAX148’s REFADJ pin is also buffered
with a 2.00 gain to scale an external 1.25V reference at
REFADJ to 2.5V at VREF.
18 _____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Table 7. Full Scale and Zero Scale
UNIPOLAR MODE
BIPOLAR MODE
Zero Scale
COM
Full Scale
Zero Scale
COM
Positive Full Scale
VREF/2 + COM
Negative Full Scale
-VREF/2 + COM
VREF + COM
OUTPUT CODE
VREF
2
FS
=
+ COM
+ COM
011 . . . 111
011 . . . 110
SUPPLIES
ZS = COM
+3V
+3V
GND
-VREF
2
-FS =
000 . . . 010
000 . . . 001
000 . . . 000
VREF
1024
1LSB =
R* = 10Ω
111 . . . 111
111 . . . 110
111 . . . 101
V
DD
AGND
COM
DGND
+3V
DGND
DIGITAL
CIRCUITRY
100 . . . 001
100 . . . 000
MAX148
MAX149
COM*
- FS
+FS - 1LSB
*OPTIONAL
INPUT VOLTAGE (LSB)
*COM ≥ VREF/2
Figure 19. Power-Supply Grounding Connection
Figure 18. Bipolar Transfer Function, Full Scale (FS) = VREF/2
+ COM, Zero Scale (ZS) = COM
deliver up to 350FA DC load current and have 10I or
less output impedance. If the reference has a higher out-
put impedance or is noisy, bypass it close to the VREF
pin with a 4.7FF capacitor.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
The external reference must have a temperature coef-
ficient of 20ppm/NC or less to achieve accuracy to within
1 LSB over the 0NC to +70NC commercial temperature
range.
Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct VREF input,
disable the internal buffer by tying REFADJ to V
.
DD
In power-down, the input bias current to REFADJ is
Figure 17 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 18 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive-integer LSB values. Output
coding is binary, with 1 LSB = 2.44mV (2.500V/1024)
for unipolar operation, and 1 LSB = 2.44mV [(2.500V/2 -
-2.500V/2)/1024] for bipolar operation.
typically 25FA (MAX149) with REFADJ tied to V . Pull
DD
REFADJ to AGND to minimize the input bias current in
power-down.
______________________________________________________________________________________ 19
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
+3V
+3V
0.1µF
1µF
(POWER SUPPLIES)
1
2
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
V
DD
SCK
SCLK
CS
PCS0
3
MAX148
MAX149
4
MOSI
DIN
ANALOG
INPUTS
5
SSTRB
DOUT
DGND
AGND
REFADJ
VREF
MC683XX
MISO
6
7
8
9
(GND)
10
0.1µF
+2.5V
Figure 20. MAX148/MAX149 QSPI Connections, External Reference
Layout, Grounding, and Bypassing
For best performance, use PCBs. Wire-wrap boards
are not recommended. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the ADC package.
XF
CLKX
CLKR
DX
CS
SCLK
TMS320LC3x
MAX148
MAX149
Figure 19 shows the recommended system ground con-
nections. Establish a single-point analog ground (star
ground point) at AGND, separate from the logic ground.
Connect all other analog grounds and DGND to the star
ground. No other digital system ground should be con-
nected to this ground. For lowest-noise operation, the
ground return to the star ground’s power supply should
be low impedance and as short as possible.
DIN
DR
DOUT
SSTRB
FSR
High-frequency noise in the V
power supply may
DD
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1FF and 1FF capaci-
tors close to pin 20 of the MAX148/MAX149. Minimize
capacitor lead lengths for best supply-noise rejection.
If the power supply is very noisy, a 10I resistor can be
connected as a lowpass filter (Figure 19).
Figure 21. MAX148/MAX149-to-TMS320 Serial Interface
20 _____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
HIGH
IMPEDANCE
DOUT
MSB
B8
S1
S0
Figure 22. TMS320 Serial-Interface Timing Diagram
2) The MAX148/MAX149’s CS pin is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX148/MAX149’s DIN.
High-Speed Digital Interfacing with QSPI
The MAX148/MAX149 can interface with QSPI using the
circuit in Figure 20 (f
= 2.0MHz, CPOL = 0, CPHA =
SCLK
0). This QSPI circuit can be programmed to do a conver-
sion on each of the eight channels. The result is stored
in memory without taxing the CPU, since QSPI incorpo-
rates its own microsequencer.
3) An 8-bit word (1XXXXX11) should be written to the
MAX148/MAX149 to initiate a conversion and place
the device into external clock mode. See Table 1 to
select the proper XXXXX bit values for your specific
application.
The MAX148/MAX149 are QSPI compatible up to the
maximum external clock frequency of 2MHz.
4) The MAX148/MAX149’s SSTRB output is monitored
through the TMS320’s FSR input. A falling edge on
the SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX148/MAX149.
TMS320LC3x Interface
Figure 21 shows an application circuit to interface the
MAX148/MAX149 to the TMS320 in external clock mode.
The timing diagram for this interface circuit is shown in
Figure 22.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 10 + 2-bit conversion result followed by 4
trailing bits, which should be ignored.
Use the following steps to initiate a conversion in the
MAX148/MAX149 and to read the results:
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input
clock. CLKX and CLKR on the TMS320 are tied
together with the MAX148/MAX149’s SCLK input.
6) Pull CS high to disable the MAX148/MAX149 until
the next conversion is initiated.
______________________________________________________________________________________ 21
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Ordering Information (continued)
Pin Configuration
PIN-
INL
PART†
TEMP RANGE
PACKAGE (LSB)
TOP VIEW
MAX148AEPP
MAX148BEPP
MAX148AEAP
MAX148BEAP
MAX148AMJP
MAX148BMJP
MAX149ACPP
MAX149BCPP
MAX149ACAP
MAX149BCAP
MAX149AEPP
MAX149BEPP
MAX149AEAP
MAX149BEAP
MAX149AMJP
MAX149BMAP/PR
MAX149BMAP/PR2
MAX149BMAP/PR3
MAX149BMJP
-40°C to +85°C 20PlasticDIP
-40°C to +85°C 20PlasticDIP
1/2
1
1
2
20
19
18
17
16
15
14
13
12
11
CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
V
DD
-40°C to +85°C
-40°C to +85°C
20 SSOP
20 SSOP
1/2
1
SCLK
CS
3
-55°C to +125°C 20 CERDIP*
-55°C to +125°C 20 CERDIP*
1/2
1
MAX148
MAX149
4
DIN
5
SSTRB
DOUT
DGND
AGND
REFADJ
VREF
0°C to +70°C
0°C to +70°C
0°C to +70°C
20PlasticDIP
20PlasticDIP
20 SSOP
1/2
1
6
7
1/2
1
8
0°C to +70°C 20PlasticDIP
-40°C to +85°C 20PlasticDIP
-40°C to +85°C 20PlasticDIP
9
1/2
1
10
-40°C to +85°C
-40°C to +85°C
20 SSOP
20 SSOP
1/2
1
DIP/SSOP
-55°C to +125°C 20 CERDIP*
1/2
1
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
20 SSOP
20 SSOP
20 SSOP
1
1
-55°C to +125°C 20 CERDIP*
1
Package Information
†
Contact factory for availability of alternate surface-mount
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
package. Specify lead-free by placing + by the part number
when ordering.
*Contact factory for availability of CERDIP package, and for
processing to MIL-STD-883B. Not available in lead-free.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
20 Plastic Dip
20 SSOP
P20-4
A20-1
J20-2
21-0043
21-0056
21-0045
20 CERDIP
22 _____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
Revised Ordering Information, Electrical Characteristics table, Pin
Description, Figure 9, added ruggedized plastic information.
1–4, 7, 13, 14, 16, 17,
22–23
3
4
5/09
1/10
Revised Ordering Information.
22
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
23
©
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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