MAX15041 [MAXIM]
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM Step-Down DC-DC Regulator with Internal; 低成本， 3A ， 4.5V至28V输入，在350kHz ， PWM降压型DC -DC稳压器，内置
| 型号： | MAX15041 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM Step-Down DC-DC Regulator with Internal |
| 文件： | 总18页 (文件大小：1441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4815; Rev 3; 3/11
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
MAX5041
General Description
Features
o Up to 3A of Continuous Output Current
The MAX15041 low-cost, synchronous DC-DC convert-
er with internal switches delivers an output current up to
3A. The MAX15041 operates from an input voltage of
4.5V to 28V and provides an adjustable output voltage
o ±±1 Output Aꢀꢀurꢁꢀc Oꢂer ꢃeꢄperꢁture
o 4.5V to 28V Input Voltꢁge Rꢁnge
o Adjustꢁble Output Voltꢁge Rꢁnge froꢄ 0.606V to
from 0.6V to 90% of V , set with two external resistors.
IN
0.9 x V
IN
The MAX15041 is ideal for distributed power systems,
preregulation, set-top boxes, television, and other con-
sumer applications.
o Internꢁl ±70ꢄΩ R
High-Side ꢁnd ±05ꢄΩ
DS-ON
R
Low-Side Power Switꢀhes
DS-ON
o Fixed 350kHz Switꢀhing Frequenꢀc
o Up to 931 Effiꢀienꢀc
o Ccꢀle-Bc-Ccꢀle Oꢂerꢀurrent Proteꢀtion
o Progrꢁꢄꢄꢁble Soft-Stꢁrt
o Stꢁble with Low-ESR Cerꢁꢄiꢀ Output Cꢁpꢁꢀitors
o Sꢁfe Stꢁrtup into Prebiꢁsed Output
o Enꢁble Input ꢁnd Power-Good Output
The MAX15041 features a peak-current-mode PWM con-
troller with internally fixed 350kHz switching frequency
and a 90% maximum duty cycle. The current-mode con-
trol architecture simplifies compensation design, and
ensures a cycle-by-cycle current limit and fast response
to line and load transients. A high-gain transconductance
error amplifier allows flexibility in setting the external com-
pensation by using a type II compensation scheme,
thereby allowing the use of all ceramic capacitors.
o Fullc Proteꢀted Agꢁinst Oꢂerꢀurrent ꢁnd
Oꢂerteꢄperꢁture
This synchronous buck regulator features internal
MOSFETs that provide better efficiency than asynchro-
nous solutions, while simplifying the design relative to
discrete controller solutions. In addition to simplifying
the design, the integrated MOSFETs minimize EMI,
reduce board space, and provide higher reliability by
minimizing the number of external components.
o V
LDO Underꢂoltꢁge Loꢀkout
DD
o Spꢁꢀe-Sꢁꢂing, ꢃherꢄꢁllc Enhꢁnꢀed, 3ꢄꢄ x 3ꢄꢄ
Pꢁꢀkꢁge
Ordering Information
The MAX15041 also features thermal shutdown and
overcurrent protection (high-side sourcing and low-side
sinking), and an internal 5V LDO with undervoltage
lockout. In addition, this device ensures safe startup
when powering into a prebiased output.
PIN-
PACKAGE
ꢃOP
MARK
PARꢃ
ꢃEMP RANGE
MAX15041ETE+ -40°C to +85°C 16 TQFN-EP*
AGV
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Other features include an externally adjustable soft-start
that gradually ramps up the output voltage and reduces
inrush current. Independent enable control and power-
good signals allow for flexible power sequencing.
Typical Operating Circuit
INPUT
12V
The MAX15041 is available in a space-saving, high-
power, 3mm x 3mm, 16-pin TQFN-EP package and is
fully specified from -40°C to +85°C.
IN
BST
OUTPUT
EN
1.8V AT 3A
Applications
MAX15041 LX
Distributed Power Systems
Wall Adapters
V
DD
PGND
Preregulators
Set-Top Boxes
PGOOD
SS
FB
Televisions
PGOOD
COMP
xDSL Modems
SGND
Consumer Products
________________________________________________________________ Mꢁxiꢄ Integrꢁted Produꢀts
±
For priꢀing, deliꢂerc, ꢁnd ordering inforꢄꢁtion, pleꢁse ꢀontꢁꢀt Mꢁxiꢄ Direꢀt ꢁt ±-888-629-4642,
or ꢂisit Mꢁxiꢄ’s website ꢁt www.ꢄꢁxiꢄ-iꢀ.ꢀoꢄ.
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
ABSOLUꢃE MAXIMUM RAꢃINGS
IN to SGND.............................................................-0.3V to +30V
LX Current (Note 1) ....................................................-5A to +8A
Converter Output Short-Circuit Duration ...................Continuous
EN to SGND.................................................-0.3V to (V + 0.3V)
IN
LX to PGND ................................-0.3V to min (+30V, V + 0.3V)
Continuous Power Dissipation (T = +70°C)
16-Pin TQFN (derate 14.7mW/°C above +70°C)
IN
A
LX to PGND .....................-1V to min (+30V, V + 0.3V) for 50ns
IN
PGOOD to SGND .....................................................-0.3V to +6V
Multilayer Board .........................................................1666mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
V
to SGND............................................................-0.3V to +6V
DD
COMP, FB, SS to SGND..............-0.3V to min (+6V, V
+ 0.3V)
DD
BST to LX .................................................................-0.3V to +6V
BST to SGND .........................................................-0.3V to +36V
SGND to PGND ....................................................-0.3V to +0.3V
MAX5041
Note ±: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE ꢃHERMAL CHARACꢃERISꢃICS (Note 2)
16 TQFN-EP
Junction-to-Ambient Thermal Resistance (θJA).........+48°C/W
Junction-to-Case Thermal Resistance (θJC) ...............+7°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.ꢄꢁxiꢄ-iꢀ.ꢀoꢄ/therꢄꢁl-tutoriꢁl.
ELECꢃRICAL CHARACꢃERISꢃICS
(V = 12V, C
= 1µF, C = 22µF, T = T = -40°C to +85°C, typical values are at T = +25°C, unless otherwise noted.) (Note 3)
IN
VDD
IN
A
J
A
PARAMEꢃER
SYMBOL
CONDIꢃIONS
MIN
ꢃYP
MAX
UNIꢃS
SꢃEP-DOWN CONVERꢃER
Input-Voltage Range
Quiescent Current
V
4.5
28
4
V
IN
I
Not switching
= 0V, V regulated by internal
LDO
2.1
2
mA
IN
V
EN
DD
12
28
Shutdown Input Supply Current
µA
V
V
V
V
V
= 0V, V = V = 5V
18
EN
EN
IN
DD
ENABLE INPUꢃ
EN Shutdown Threshold Voltage
EN Shutdown Voltage Hysteresis
V
rising
rising
= 2.9V
rising
1.4
100
1.95
100
5.3
V
EN_SHDN
V
mV
V
EN_HYST
V
1.7
2
2.15
9
EN_LOCK
EN
EN Lockout Threshold Voltage
V
mV
µA
EN_LOCK_HYST
EN Input Current
I
EN
EN
POWER-GOOD OUꢃPUꢃ
PGOOD Threshold
V
540
560
15
584
100
mV
mV
mV
nA
PGOOD_TH
FB
PGOOD Threshold Hysteresis
PGOOD Output Low Voltage
PGOOD Leakage Current
ERROR AMPLIFIER
V
PGOOD_HYST
V
I
= 5mA, V = 0.5V
35
PGOOD_OL
PGOOD
FB
I
V
= 5V, V = 0.7V
10
PGOOD
PGOOD
FB
Error Amplifier
Transconductance
g
1.6
mS
MV
Error Amplifier Voltage Gain
FB Set-Point Accuracy
A
90
dB
VEA
V
600
606
612
mV
FB
2
_______________________________________________________________________________________
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
MAX5041
ELECꢃRICAL CHARACꢃERISꢃICS (ꢀontinued)
(V = 12V, C
= 1µF, C = 22µF, T = T = -40°C to +85°C, typical values are at T = +25°C, unless otherwise noted.) (Note 3)
IN A J A
IN
VDD
PARAMEꢃER
FB Input Bias Current
SS Current
SYMBOL
CONDIꢃIONS
MIN
-100
-100
4.5
ꢃYP
MAX
+100
+100
5.5
UNIꢃS
V
V
V
= 0.5V
= 0.7V
FB
FB
SS
I
I
nA
µA
Ω
FB
SS
= 0.45V, sourcing
5
6
SS Discharge Resistance
R
I
= 10mA, sinking, V = 1.6V
SS EN
SS
SS Prebiased Mode Stop Voltage
0.65
9
V
Current Sense to COMP
Transconductance
G
S
MOD
COMP Clamp Low
V
= 0.7V
0.68
830
V
FB
PWM Compensation Ramp Valley
PWM CLOCK
mV
Switching Frequency
f
315
350
90
385
5.5
kHz
%
SW
D
Maximum Duty Cycle
Minimum Controllable On-Time
150
ns
INꢃERNAL LDO OUꢃPUꢃ (V
)
DD
V
V
Output Voltage
V
I
= 1mA to 25mA, V = 6.5V
IN
4.75
30
5.1
80
V
DD
DD
DD
VDD
Short-Circuit Current
V
= 6.5V
mA
mV
IN
LDO Dropout Voltage
I
= 25mA, V
rising
DD
drops by -2%
DD
250
600
VDD
V
Undervoltage Lockout
DD
V
V
4
4.25
V
UVLO_TH
Threshold
V
Undervoltage Lockout
DD
V
150
mV
UVLO_HYST
Hysteresis
POWER SWIꢃCH
High-side switch, I = 1A
170
105
305
175
LX
LX On-Resistance
mΩ
A
Low-side switch, I = 1A
LX
High-Side Switch Source
Current-Limit Threshold
5
6
7.2
Low-Side Switch Sink
Current-Limit Threshold
-3
A
V
V
V
= 33V, V = V = 28V
10
10
10
BST
BST
BST
IN
LX
LX Leakage Current
nA
nA
= 5V, V = 28V, V = 0V
IN
LX
BST Leakage Current
= 33V, V = V = 28V
IN LX
ꢃHERMAL SHUꢃDOWN
Thermal-Shutdown Threshold
Rising
+155
20
°C
°C
Thermal-Shutdown Hysteresis
HICCUP PROꢃECꢃION
16 x Soft-
Start Time
Blanking Time
Note 3: Specifications are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by
A
design and characterization.
_______________________________________________________________________________________
3
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
Typical Operating Characteristics
(V = 12V, V
= 3.3V, C
= 1µF, C = 22µF, T = +25°C, circuit of Figure 3 (see Table 1 for values), unless otherwise specified.)
IN
OUT
VDD IN A
OUTPUT-VOLTAGE REGULATION
vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
0.2
0
V
= 12V
V
= 5V
IN
IN
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
MAX5041
V
V
= 5.0V
= 3.3V
OUT
OUT
V
V
= 3.3V
= 2.5V
OUT
OUT
V
= 2.5V
OUT
V
V
= 1.8V
= 1.2V
OUT
OUT
V
V
= 1.8V
= 1.2V
OUT
OUT
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
NORMALIZED OUTPUT VOLTAGE
vs. TEMPERATURE
NORMALIZED OUTPUT VOLTAGE
vs. TEMPERATURE
LOAD-TRANSIENT WAVEFORMS
MAX15041 toc04
1.004
1.002
1.000
0.998
0.996
0.994
0.992
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
I
= 2A
I
= 0A
LOAD
LOAD
I
LOAD
2A/div
V
OUT
AC-COUPLED
200mV/div
V
PGOOD
5V/div
-40
-15
10
35
60
85
-40
-15
10
35
60
85
200µs/div
TEMPERATURE (NC)
TEMPERATURE (NC)
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
FB SET POINT vs.TEMPERATURE
610
608
606
604
602
600
385
375
365
355
345
335
325
315
T
T
= +85NC
= +25NC
= -40NC
A
A
T
A
-40
-15
10
35
60
85
0
5
10
15
20
25
TEMPERATURE (NC)
INPUT VOLTAGE (V)
4
_______________________________________________________________________________________
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
MAX5041
Typical Operating Characteristics (continued)
(V = 12V, V
IN
= 3.3V, C
= 1µF, C = 22µF, T = +25°C, circuit of Figure 3 (see Table 1 for values), unless otherwise specified.)
OUT
VDD IN A
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
SHUTDOWN CURRENT
vs. INPUT VOLTAGE
SHUTDOWN CURRENT
vs. TEMPERATURE
16
10
9
8
7
6
5
4
3
2
1
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
L = 4.7FH
= 0A
I
LOAD
15
14
13
12
11
10
0
5
10
15
20
25
0
5
10
15
20
25
-40
-15
10
35
60
85
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TEMPERATURE (NC)
SHUTDOWN WAVEFORMS
OUTPUT SHORT-CIRCUIT WAVEFORMS
MAX15041 toc12
MAX15041 toc13
V
EN
V
OUT
2V/div
5V/div
I
IN
V
OUT
5A/div
2V/div
I
L
I
L
5A/div
2A/div
V
V
SS
PGOOD
5V/div
2V/div
100µs/div
10ms/div
SOFT-START WAVEFORMS
SWITCHING WAVEFORMS
MAX15041 toc15
MAX15041 toc14
V
V
EN
LX
5V/div
10V/div
V
OUT
2V/div
I
L
2A/div
I
L
2A/div
V
OUT
AC-COUPLED
50mV/div
V
PGOOD
5V/div
400µs/div
1µs/div
_______________________________________________________________________________________
5
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
Typical Operating Characteristics (continued)
(V = 12V, V
= 3.3V, C
= 1µF, C = 22µF, T = +25°C, circuit of Figure 3 (see Table 1 for values), unless otherwise specified.)
IN
OUT
VDD
IN
A
SOFT-START TIME
vs. CAPACITANCE
STARTUP INTO PREBIASED OUTPUT
MAX15041 toc17
1000
100
10
V
EN
5V/div
MAX5041
V
OUT
2V/div
I
L
2A/div
1
I
OUT
2A/div
0.1
400µs/div
1
10
100
1000
C
SS
(nF)
MAXIMUM LOAD CURRENT
vs. AMBIENT TEMPERATURE
STARTUP INTO PREBIASED OUTPUT
MAX15041 toc18
3.2
3.0
2.8
2.6
2.4
2.2
2.0
V
J
= 5V
T P +150NC
IN
V
EN
5V/div
V
OUT
2V/div
V
V
= 3.3V
= 2.5V
OUT
OUT
I
L
5A/div
V
V
= 1.8V
= 1.2V
OUT
OUT
I
OUT
5A/div
5
15 25 35 45 55 65 75 85
400µs/div
AMBIENT TEMPERATURE (NC)
6
_______________________________________________________________________________________
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
MAX5041
Typical Operating Characteristics (continued)
(V = 12V, V
= 3.3V, C
= 1µF, C = 22µF, T = +25°C, circuit of Figure 3 (see Table 1 for values), unless otherwise specified.)
IN
OUT
VDD
IN
A
MAXIMUM LOAD CURRENT
vs. AMBIENT TEMPERATURE
MAXIMUM LOAD CURRENT
vs. AMBIENT TEMPERATURE
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.2
3.0
2.8
2.6
2.4
2.2
2.0
V
J
= 28V
T P +150NC
V
J
= 12V
T P +150NC
IN
IN
V
= 3.3V
OUT
V
V
OUT
V
OUT
V
OUT
= 1.2V
= 3.3V
= 2.5V
= 2.5V
OUT
V
= 1.8V
OUT
V
= 1.2V
OUT
V
OUT
= 1.8V
5
15 25 35 45 55 65 75 85
5
15 25 35 45 55 65 75 85
AMBIENT TEMPERATURE (NC)
AMBIENT TEMPERATURE (NC)
DEVICE POWER DISSIPATION
vs. LOAD CURRENT
DEVICE POWER DISSIPATION
vs. LOAD CURRENT
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
V
= 12V
V
IN
= 5V
IN
2.5
2.0
1.5
1.0
0.5
0
V
OUT
= 3.3V
V
= 3.3V
OUT
V
= 2.5V
OUT
V
= 2.5V
OUT
V
OUT
= 1.8V
V
= 1.8V
OUT
V
OUT
= 1.2V
V
= 1.2V
OUT
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
LOAD CURRENT (A)
_______________________________________________________________________________________
7
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
Pin Configuration
TOP VIEW
12
11
10
9
I.C.
8
7
6
5
PGND 13
PGND 14
IN 15
SGND
SS
MAX5041
MAX15041
*EP
16
FB
IN
+
1
2
3
4
ꢃQFN
*EXPOSED PAD, CONNECT TO SGND.
Pin Description
PIN
1
NAME
FUNCꢃION
Internal LDO 5V Output. Supply input for the internal analog core. Bypass with a ceramic capacitor of at
least 1µF to SGND. See Figure 3.
V
DD
2
PGOOD Power-Good Open-Drain Output. PGOOD goes low if FB is below 545mV.
Enable Input. EN is a digital input that turns the regulator on and off. Drive EN high to turn on the regulator.
Connect to IN for always-on operations.
3
EN
4
COMP
FB
Voltage Error-Amplifier Output. Connect the necessary compensation network from COMP to SGND.
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to SGND to set
5
the output voltage from 0.606V to 90% of V
.
IN
Soft-Start Input. Connect a capacitor from SS to SGND to set the soft-start time (see the Setting the Soft-
Start Time section).
6
SS
7
8
SGND
I.C.
Analog Ground. Connect to PGND plane at one point near the input bypass capacitor return terminal.
Internally Connected. Connect to SGND.
High-Side MOSFET Driver Supply. Bypass BST to LX with a 10nF capacitor. Connect an external diode
9
10, 11, 12
13, 14
15, 16
—
BST
LX
(see the Diode Selection section) from V
to BST.
DD
Inductor Connection. Connect the LX pin to the switched side of the inductor. LX is high impedance when
the IC is in shutdown mode, thermal shutdown mode, or V is below the UVLO threshold.
DD
Power Ground. Connect to the SGND PCB copper plane at one point near the input bypass capacitor
return terminal.
PGND
IN
Input Power Supply. Input supply range is from 4.5V to 28V. Bypass with a ceramic capacitor of at least
22µF to PGND.
Exposed Pad. Connect to SGND externally. Solder the exposed pad to a large contiguous copper plane to
maximize thermal performance.
EP
8
_______________________________________________________________________________________
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
MAX5041
Simplified Block Diagram
ENABLE CONTROL
AND THERMAL
SHUTDOWN
EN
5V LDO
VDD
UVLO
COMPARATOR
4V
MAX15041
VDD
BIAS
GENERATOR
BST
IN
CURRENT-SENSE/CURRENT-LIMIT
AMPLIFIER
LX
VOLTAGE
REFERENCE
N
CONTROL
LOGIC AND
SINK LIMIT
0.65V
LX
VDD
STRONG PREBIAS
COMPARATOR
5µA
0.606V
N
PWM
COMPARATOR
PGND
SS
FB
ERROR
AMPLIFIER
Σ
OSCILLATOR
COMP
SGND
PGOOD
N
0.560V RISING,
0.545V FALLING
POWER-GOOD
COMPARATOR
_______________________________________________________________________________________
9
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
2) The high-side MOSFET current limit is reached.
Detailed Description
3) The maximum duty cycle of 90% is reached.
The MAX15041 is a high-efficiency, peak-current-
mode, step-down DC-DC converter with integrated
high-side (170mΩ, typ) and low-side (105mΩ, typ)
power switches. The output voltage is set from 0.606V
Then, the low-side MOSFET turns on; the low-side
MOSFET turns off when the clock period ends.
Starting into a Prebiased Output
The MAX15041 is capable of safely soft-starting into a
prebiased output without discharging the output
capacitor. Starting up into a prebiased condition, both
low-side and high-side MOSFETs remain off to avoid
discharging the prebiased output. PWM operation
starts only when the SS voltage crosses the FB voltage.
The MAX15041 is also capable of soft-starting into an
output prebiased above the OUT nominal set point. In
this case, forced PWM operation starts when SS volt-
age reaches 0.65V (typ).
to 0.9 x V by using an adjustable, external resistive
IN
divider and can deliver up to 3A load current. The 4.5V
to 28V input voltage range makes the device ideal for
distributed power systems, notebook computers, and
preregulation applications.
MAX5041
The MAX15041 features a PWM, internally fixed 350kHz
switching frequency with a 90% maximum duty cycle.
PWM current-mode control allows for an all-ceramic
capacitor solution. The MAX15041 comes with a high-
gain transconductance error amplifier. The current-
mode control architecture simplifies compensation
design and ensures a cycle-by-cycle current limit and
fast reaction to line and load transients. The low
In case of a prebiased output, below or above the OUT
nominal set point, if the low-side MOSFET sink current
reaches the sink current limit (-3A, typ), the low-side
MOSFET turns off before the end of the clock period
and the high-side MOSFET turns on until one of the fol-
lowing conditions happens:
R
, on-chip, MOSFET switches ensure high effi-
ciency at heavy loads and minimize critical induc-
tances, reducing layout sensitivity.
DS-ON
The MAX15041 also features thermal shutdown and
overcurrent protection (high-side sourcing and low-side
sinking), and an internal 5V, LDO with undervoltage
lockout. An externally adjustable voltage soft-start
gradually ramps up the output voltage and reduces
inrush current. Independent enable control and power-
good signals allow for flexible power sequencing. The
MAX15041 also provides the ability to start up into a
prebiased output, below or above the set point.
1) High-side MOSFET source current hits the reduced
high-side MOSFET current limit (0.75A, typ); in this
case, the high-side MOSFET is turned off for the
remaining clock period.
2) The clock period ends.
Enable Input and Power-Good Output
The MAX15041 features independent device enable
control and power-good signals that allow for flexible
power sequencing. The enable input (EN) is an input
with a 1.95V (typ) threshold that controls the regulator.
Assert a voltage exceeding the threshold on EN to
enable the regulator, or connect EN to IN for always-on
operations. Power-good (PGOOD) is an open-drain
Controller Function—PWM Logic
The MAX15041 operates at a constant 350kHz switch-
ing frequency. When EN is high, after a brief settling
time, PWM operation starts when V crosses the FB
SS
voltage, at the beginning of soft-start.
output that deasserts (goes high impedance) when V
FB
The first operation is always a high-side MOSFET turn-
on, at the beginning of the clock cycle. The high-side
MOSFET is turned off when:
is above 560mV (typ), and asserts low if V is below
FB
545mV (typ).
When the EN voltage is higher than 1.4V (typ) and
lower than 1.95V (typ), most of the internal blocks are
disabled, only an internal coarse preregulator, includ-
ing the EN accurate comparator, is kept on.
1) COMP voltage crosses the internal current-mode
ramp waveform, which is the sum of the compensa-
tion ramp and the current-mode ramp derived from
the inductor current waveform (current-sense block).
±0 ______________________________________________________________________________________
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
MAX5041
capacitor, C for a fixed period of time (∆T = 70ns,
Programmable Soft-Start (SS)
The MAX15041 utilizes a soft-start feature to slowly ramp
up the regulated output voltage to reduce input inrush
current during startup. Connect a capacitor from SS to
SGND to set the startup time (see the Setting the Soft-
Start Time section for capacitor selection details).
SS
0
typ). If the overcurrent condition persists, SS is pulled
below 0.606V and a hiccup event is triggered.
During a hiccup event, high-side and low-side
MOSFETs are kept off, and COMP is pulled low for a
period equal to 16 times the nominal soft-start time
(blanking time). This is obtained by charging SS from 0
to 0.606V with a 5µA (typ) current, and then slowly dis-
charging it back to 0V with a 333nA (typ) current. After
the blanking time has elapsed, the device attempts to
restart. If the overcurrent fault has cleared, the device
resumes normal operation, otherwise a new hiccup
event is triggered (see the Output Short-Circuit
Waveforms in the Typical Operating Characteristics).
Internal LDO (V
)
DD
DD
The MAX15041 has an internal 5.1V (typ) LDO. V
is
externally compensated with a minimum 1µF, low-ESR
ceramic capacitor. The V voltage is used to supply
DD
the low-side MOSFET driver, and to supply the internal
control logic. When the input supply (IN) is below 4.5V,
V
is 50mV (typ) lower than IN. The V
output cur-
DD
DD
rent limit is 80mA (typ) and an UVLO circuit inhibits
switching when V falls below 3.85V (typ).
DD
Thermal-Shutdown Protection
The MAX15041 contains an internal thermal sensor that
limits the total power dissipation in the device and pro-
tects it in the event of an extended thermal fault condi-
tion. When the die temperature exceeds +155°C (typ),
the thermal sensor shuts down the device, turning off
the DC-DC converter and the LDO regulator to allow
the die to cool. After the die temperature falls by 20°C
(typ), the device restarts, using the soft-start sequence.
Error Amplifier
A high-gain error amplifier provides accuracy for the volt-
age feedback loop regulation. Connect the necessary
compensation network between COMP and SGND (see
the Compensation Design Guidelines section). The error-
amplifier transconductance is 1.6mS (typ). COMP clamp
low is set to 0.68V (typ), just below the PWM ramp com-
pensation valley, helping COMP to rapidly return to cor-
rect set point during load and line transients.
Applications Information
PWM Comparator
The PWM comparator compares COMP voltage to the
current-derived ramp waveform (LX current to COMP volt-
age transconductance value is 9A/V, typ.). To avoid insta-
bility due to subharmonic oscillations when the duty cycle
is around 50% or higher, a compensation ramp is added
to the current-derived ramp waveform. The compensation
ramp slope (0.45V x 350kHz) is equivalent to half of the
inductor current down slope in the worst case (load 3A,
current ripple 30% and maximum duty cycle operation of
90%). Compensation ramp valley is set at 0.83V (typ).
Setting the Output Voltage
Connect a resistive divider (R and R , see Figures 1
1
2
and 3) from OUT to FB to SGND to set the DC-DC con-
verter output voltage. Choose R and R so that the DC
1
2
errors due to the FB input bias current do not affect the
output-voltage precision. With lower value resistors, the
DC error is reduced, but the amount of power consumed
in the resistive divider increases. A typical tradeoff value
for R is 10kΩ, but values between 5kΩ and 50kΩ are
2
acceptable. Once R is chosen, calculate R using:
2
1
⎛
⎜
⎝
⎞
⎠
V
OUT
R = R ×
− 1
Overcurrent Protection
and Hiccup Mode
1
2
⎟
V
FB
When the converter output is shorted or the device is
overloaded, the high-side MOSFET current-limit event
(6A, typ) turns off the high-side MOSFET and turns on
the low-side MOSFET. In addition, it discharges the SS
where the feedback threshold voltage V = 0.606V
FB
(typ).
______________________________________________________________________________________ ±±
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
For ceramic capacitors, ESR contribution is negligible:
1
Inductor Selection
A larger inductor value results in reduced inductor ripple
current, leading to a reduced output ripple voltage.
However, a larger inductor value results in either a larger
physical size or a higher series resistance (DCR) and a
lower saturation current rating. Typically, inductor value
is chosen to have current ripple equal to 30% of load
current. Choose the inductor with the following formula:
R
<<
ESR _ COUT
8 × f
× C
OUT
SW
For tantalum or electrolytic capacitors, ESR contribution
is dominant:
1
R
>>
ESR _ COUT
⎛
⎞
⎟
⎠
V
V
OUT
8 × f
× C
OUT
OUT
SW
L =
× 1−
⎜
⎝
f
× ∆I
V
IN
0
SW
L
Compensation Design Guidelines
The MAX15041 uses a fixed-frequency, peak-current-
mode control scheme to provide easy compensation
and fast transient response. The inductor peak current is
monitored on a cycle-by-cycle basis and compared to
the COMP voltage (output of the voltage error amplifier).
The regulator’s duty-cycle is modulated based on the
inductor’s peak current value. This cycle-by-cycle con-
trol of the inductor current emulates a controlled current
source. As a result, the inductor’s pole frequency is
shifted beyond the gain-bandwidth of the regulator.
where f
is the internally fixed 350kHz switching fre-
SW
quency, and ∆I is the estimated inductor ripple current
L
(typically set to 0.3 x I
inductor current, I
). In addition, the peak
LOAD
must always be below both the
L_PK,
minimum high-side MOSFET current-limit value,
(5A, typ), and the inductor saturation current
I
HSCL_MIN
rating, I
. Ensure that the following relationship is
L_SAT
satisfied:
1
2
I
= I
+
× ∆I < min(I
,I
)
L _PK
LOAD
L
HSCL _MIN L _ SAT
System stability is provided with the addition of a sim-
ple series capacitor-resistor from COMP to SGND. This
pole-zero combination serves to tailor the desired
response of the closed-loop system.
Diode Selection
The MAX15041 requires an external bootstrap steering
diode. Connect the diode between V and BST. The
diode should have a reverse voltage rating, higher than
the converter input voltage and a 150mA minimum cur-
rent rating. Typically, a fast switching or Schottky diode
is used in this application, such as a 1N4148 diode.
DD
The basic regulator loop consists of a power modulator
(comprising the regulator’s pulse-width modulator,
compensation ramp, control circuitry, MOSFETs, and
inductor), the capacitive output filter and load, an out-
put feedback divider, and a voltage-loop error amplifier
with its associated compensation circuitry. See Figure 1
for a graphical representation.
Input Capacitor Selection
For a step-down converter, input capacitor C helps to
IN
keep the DC input voltage steady, in spite of discontin-
uous input AC current. Low-ESR capacitors are pre-
ferred to minimize the voltage ripple due to ESR.
The average current through the inductor is expressed as:
I = G
× V
COMP
Size C using the following formula:
IN
L
MOD
I
V
OUT
V
IN
LOAD
where I is the average inductor current and G
the power modulator’s transconductance. For a buck
converter:
is
L
MOD
C
=
×
IN
f
× ∆V
SW
IN_RIPPLE
Output-Capacitor Selection
V
= R
× I
LOAD L
OUT
Low-ESR capacitors are recommended to minimize the
voltage ripple due to ESR. Total output-voltage peak-to-
peak ripple is estimated by the following formula:
where R
is the equivalent load resistor value.
LOAD
Combining the two previous equations, the power mod-
ulator’s transfer function in terms of V with respect
OUT
⎛
⎞
⎟
⎠
⎛
⎞
⎟
V
V
OUT
1
OUT
to V
is:
COMP
∆V
=
× 1−
× R
+
OUT
ESR _ COUT
⎜
⎝
⎜
⎝
f
× L
V
8 × f
× C
⎠
SW
IN
SW OUT
V
R
× I
OUT
LOAD L
=
= R
× G
LOAD MOD
V
⎛
⎞
⎟
I
COMP
L
⎜
G
⎝
⎠
MOD
±2 ______________________________________________________________________________________
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
MAX5041
POWER MODULATOR
OUTPUT FILTER
AND LOAD
ERROR AMPLIFIER
FEEDBACK
DIVIDER
COMPENSATION
RAMP
V
OUT
V
IN
g
MC
Σ
FB
R
R
1
2
COMP
Q
Q
HS
V
OUT
L0
DCR
CONTROL
LOGIC
I
L
PWM
COMPARATOR
LS
ESR
R
LOAD
R
C
R
OUT
*C
CC
g
MV
C
OUT
C
C
V
V
OUT
COMP
G
MOD
I
L
R
OUT
= A /g
VEA MV
NOTE: THE G
STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF
MOD
THE INDUCTOR INJECTED INTO THE OUTPUT LOAD. THIS REPRESENTS A
SIMPLIFICATION FOR THE POWER MODULATOR STAGE DRAWN ABOVE.
*C IS OPTIONAL.
CC
REF
Figure 1. Peak Current-Mode Regulator Transfer Model
Having defined the power modulator’s transfer function
gain, the total system loop gain can be written as fol-
lows (see Figure 1):
The dominate poles and zeros of the transfer loop gain
is shown below:
g
1
MV
f
=
f
=
P1
P2
A
dB /20
[
]
R
× sC R + 1
C C
(
)
2π × C
ESR + R
VEA
(
)
OUT
OUT
LOAD
2π × 10
× C
C
α =
⎡
⎤
⎡
⎤
+ 1
⎦
s C + C
R
+ R
OUT
+ 1 × s C || C
R
|| R
OUT
(
)(
)
(
)(
)
C
CC
C
C
CC
C
⎣
⎦
⎣
1
1
f
=
f
=
P3
Z1
sC
ESR + 1
(
)
2π × C
R
2π × C R
C C
OUT
ESR + R
CC
C
β = G
× R ×
LOAD
MOD
⎡
⎤
+ 1
⎦
sC
(
)
1
OUT
LOAD
⎣
f
=
Z2
2π × C
ESR
R
A
OUT
2
VEA
Gain =
×
× α × β
R
+ R
R
OUT
1
2
The order of pole-zero occurrence is:
< f < f < f ≤ f
P3
where R
is the quotient of the error amplifier’s DC
f
OUT
P1 P2
Z1 Z2
gain, A
, divided by the error amplifier’s transcon-
VEA
ductance, g ; R
much larger than C
is much larger than R and C is
C C
.
MV OUT
Note under heavy load, f , may approach f
.
P2
Z1
CC
A graphical representation of the asymptotic system
closed-loop response, including the dominant pole and
zero locations is shown in Figure 2.
Rewriting:
sC R + 1
(
)
V
C C
FB
Gain =
A
×
VEA
V
⎡
⎤
⎛
⎜
⎝
⎞
⎟
⎠
A
g
OUT
VEA
sC
+ 1 × sC
R + 1
(
)
⎢
⎣
⎥
C
CC C
MV
⎦
sC
ESR + 1
(
)
OUT
× G
R
×
MOD LOAD
⎡
⎤
sC
ESR + R
(
+ 1
)
OUT
LOAD
⎣
⎦
______________________________________________________________________________________ ±3
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
1ST ASYMPTOTE
A
[dB]/20
x V -1 x 10
x G
x R
MOD LOAD
VEA
V
GAIN
FB
OUT
2ND ASYMPTOTE
V
FB
x V -1 x g x (C )-1 x G
x R
MOD LOAD
OUT
MV
C
3RD ASYMPTOTE
x V -1 x g x (C )-1 x G
V
x R
x( C (ESR + R
))-1
LOAD
FB
OUT
MV
C
MOD
LOAD
OUT
MAX5041
4TH ASYMPTOTE
x V
-1 x g x R x G
V
x R
LOAD
x (C (ESR + R
))-1
LOAD
FB
OUT
MV
C
MOD
OUT
3RD POLE
(C R )-1
CC
C
2ND ZERO
(C ESR)-1
OUT
UNITY
RAD/S
1ST POLE
x (10
1ST ZERO
(C R )-1
A
[dB]/20
C )-1
C
CO
VEA
g
MV
C
C
2ND POLE
(C (ESR + R
))-1
OUT
LOAD
5TH ASYMPTOTE
x (ESR || R
V
FB
x V -1 x g x R x G
)
LOAD
OUT
MV
C
MOD
6TH ASYMPTOTE
x (ESR || R
-1
V
FB
x V -1 x g x( C
)
x G
MOD
)
LOAD
OUT
MV
CC
Figure 2. Asymptotic Loop Response of Peak Current-Mode Regulator
If C
is large, or exhibits a lossy equivalent series
the desired closed-loop frequency response and phase
margin as outlined in the Closing the Loop: Designing
the Compensation Circuitry section.
OUT
resistance (large ESR), the circuit’s second zero may
come into play around the crossover frequency (f
=
CO
ω
/2π). In this case, a third pole may be induced by a
CO
Closing the Loop: Designing the
Coꢄpensꢁtion Cirꢀuitrc
second (optional) small compensation capacitor (C ),
CC
connected from COMP to SGND.
1) Select the desired crossover frequency. Choose f
CO
The loop response’s fourth asymptote (in bold, Figure
2) is the one of interest in establishing the desired
crossover frequency (and determining the compensa-
tion component values). A lower crossover frequency
provides for stable closed-loop operation at the
expense of a slower load and line transient response.
Increasing the crossover frequency improves the tran-
sient response at the (potential) cost of system instabili-
ty. A standard rule of thumb sets the crossover
frequency ≤ 1/10 of the switching frequency (for the
MAX15041, this is approximately 35kHz for the 350kHz
fixed switching frequency).
equal to 1/10th of f , or f
≈ 35kHz.
CO
SW
2) Select R using the transfer-loop’s fourth asymptote
C
gain (assuming f
the overall loop gain to unity) as follows:
> f , f , and f and setting
P1 P2 Z1
CO
V
FB
1=
× g
× R × G
× R
MV
C
MOD LOAD
V
OUT
1
×
2π × f
× C
× ESR+ R
(
)
CO
OUT LOAD
therefore:
First, select the passive and active power components
that meet the application’s requirements. Then, choose
the small-signal compensation components to achieve
2π × f
× C
× ESR + R
V
(
)
CO
OUT
LOAD
× R
MOD LOAD
OUT
R
=
×
C
V
g
× G
FB
MV
±4 ______________________________________________________________________________________
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
MAX5041
For R
much greater than ESR, the equation can be
this third-pole placement is well beyond the desired
crossover frequency, minimizing its interaction with the
LOAD
further simplified as follows:
system loop response at crossover. If C
is smaller than
CC
V
2π × f
× C
OUT
× G
OUT
CO
10pF, it can be neglected in these calculations.
R
=
×
C
V
g
FB
MV MOD
Setting the Soft-Start Time
The soft-start feature ramps up the output voltage slow-
ly, reducing input inrush current during startup. Size the
where V is equal to 0.606V.
FB
3) Select C . C is determined by selecting the
C
capacitor to achieve the desired soft-start time t
SS
C
C
SS
using:
desired first system zero, f , based on the desired
Z1
phase margin. Typically, setting f below 1/5th of
Z1
I
× t
SS
f
provides sufficient phase margin.
CO
SS
C
=
SS
V
FB
f
1
CO
5
f
=
≤
Z1
2π × C R
I
SS
, the soft-start current, is 5µA (typ) and V , the out-
FB
C C
put feedback voltage threshold, is 0.606V (typ). When
using large C capacitance values, the high-side
therefore:
OUT
current limit may trigger during the soft-start period. To
ensure the correct soft-start time, t , choose C large
5
SS
SS
C
≥
C
enough to satisfy:
2π × f
× R
CO
C
V
× I
OUT SS
4) If the ESR output zero is located at less than one-half
the switching frequency use the (optional) sec-
C
>> C ×
OUT
SS
(I
− I
) × V
FB
HSCL _MIN
OUT
ondary compensation capacitor, C , to cancel it,
CC
as follows:
I
is the minimum high-side switch, current-
HSCL_MIN
limit value.
1
1
= f = f
=
P3
Z2
Power Dissipation
2π × C
R
2π × C
ESR
CC C
OUT
The MAX15041 is available in a thermally enhanced
TQFN package and can dissipate up to 1.666W at T =
A
therefore:
+70°C. The exposed pad should be connected to
SGND externally, preferably soldered to a large ground
plane to maximize thermal performance. When the die
temperature exceeds +155°C, The thermal-shutdown
protection is activated (see the Thermal-Shutdown
Protection section).
C
× ESR
OUT
C
=
CC
R
C
If the ESR zero exceeds 1/2 the switching frequency,
use the following equation:
Layout Procedure
Careful PCB layout is critical to achieve clean and sta-
ble operation. It is highly recommended to duplicate
the MAX15041 evaluation kit layout for optimum perfor-
mance. If deviation is necessary, follow these guide-
lines for good PCB layout:
f
1
SW
2
f
=
=
P3
2π × C
R
CC C
therefore:
2
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the
signal ground plane.
C
=
CC
2π × f
× R
SW
C
The downside of C
is that it detracts from the overall
CC
system phase margin. Care should be taken to guarantee
______________________________________________________________________________________ ±5
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
2) Place capacitors on V , IN, and SS as close as
DD
4) Connect IN, LX, and PGND separately to a large
copper area to help cool the IC to further improve
efficiency.
possible to the IC and the corresponding pin using
direct traces. Keep the power ground plane (con-
nected to PGND) and signal ground plane (connect-
ed to SGND) separate. PGND and SGND connect at
only one common point near the input bypass
capacitor return terminal.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors and compensa-
tion components as close as possible to the IC.
6) Route high-speed switching nodes (such as LX and
BST) away from sensitive analog areas (such as FB
and COMP).
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output
capacitors, and the input capacitors.
MAX5041
D
INPUT
4.5V TO 28V
R
BST
47Ω
IN
BST
CIN
CBST
10nF
47µF
MAX15041
EN
V
L
4.7µH
OUTPUT = 3.3V
LX
DD
COUT
22µF
CVDD
1µF
RPU
R1
10kΩ
45.3kΩ
1%
PGND
PGOOD
FB
PGOOD
SS
COMP
R2
10.0kΩ
1%
RC
1.8kΩ
I.C.
SGND
CCC
100pF
CSS
CC
0.01µF
12nF
Figure 3. Typical Operating Circuit (4.5V to 28V Input Buck Converter)
ꢃꢁble ±. ꢃcpiꢀꢁl Coꢄponent Vꢁlues for Coꢄꢄon Output-Voltꢁge Settings
V
(V)
L (µH)
4.7
C
(nF)
R
(kΩ)
R ꢁnd R
± 2
OUꢃ
5.0
3.3
2.5
1.8
1.2
C
C
8
2.70
1.80
1.50
1.00
0.68
Select R so that:
2
4.7
12
22
33
47
5kΩ ≤ R ≤ 50kΩ
2
3.3
Calculate R using the equation in the
1
Setting the Output Voltage section.
2.2
2.2
±6 ______________________________________________________________________________________
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
MAX5041
Package Information
Chip Information
For the latest package outline information and land patterns
(footprints), go to www.ꢄꢁxiꢄ-iꢀ.ꢀoꢄ/pꢁꢀkꢁges. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
LAND
PAꢃꢃERN NO.
PACKAGE
ꢃYPE
PACKAGE
CODE
OUꢃLINE NO.
2±-0±36
90-003±
16 TQFN-EP
T1633+4
______________________________________________________________________________________ ±7
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
Revision History
REVISION
NUMBER
REVISION
DAꢃE
PAGES
CHANGED
DESCRIPꢃION
0
7/09
Initial release
—
Revised General Description, Absolute Maximum Ratings, Electrical
Characteristics, Applications Information, Figures 2 and 3.
1, 2, 3, 8, 11–14,
16, 17
1
3/10
2
3
9/10
3/11
Update Electrical Characteristics and Package Information
2, 17, 18
15
Recommended new diode for boost
MAX5041
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
±8 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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