MAX1537AETX [MAXIM]
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers; 高效率， 5路输出，主电源控制器，用于笔记本电脑
| 型号： | MAX1537AETX |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers |
| 文件： | 总38页 (文件大小：1409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4023; Rev 0; 4/06
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
General Description
Features
The MAX1533A/MAX1537A are dual step-down, switch-
mode power-supply (SMPS) controllers with synchro-
nous rectification, intended for main 5V/3.3V power
generation in battery-powered systems. Fixed-frequen-
cy operation with optimal interleaving minimizes input
ripple current from the lowest input voltages up to the
26V maximum input. Optimal 40/60 interleaving allows
the input voltage to go down to 8.3V before duty-cycle
overlap occurs, compared to 180° out-of-phase regula-
tors where the duty-cycle overlap occurs when the
input drops below 10V. Output current sensing pro-
vides accurate current limit using a sense resistor.
Alternatively, power dissipation can be reduced using
lossless inductor current sensing.
♦ Fixed-Frequency, Current-Mode Control
♦ 40/60 Optimal Interleaving
♦ Accurate Differential Current-Sense Inputs
♦ Internal 5V and 3.3V Linear Regulators with
100mA Load Capability
♦ Auxiliary 12V or Adjustable 150mA Linear
Regulator (MAX1537A Only)
♦ Dual Mode™ Feedback—3.3V/5V Fixed or
Adjustable Output (Dual Mode) Voltages
♦ 200kHz/300kHz/500kHz Switching Frequency
♦ Versatile Power-Up Sequencing
Internal 5V and 3.3V linear regulators power the
MAX1533A/MAX1537A and their gate drivers, as well as
external keep-alive loads, up to a total of 100mA. When
the main PWM regulators are in regulation, automatic
bootstrap switches bypass the internal linear regulators,
providing currents up to 200mA from each linear output.
An additional 5V to 23V adjustable internal 150mA linear
regulator is typically used with a secondary winding to
provide a 12V supply.
♦ Adjustable Overvoltage and Undervoltage
Protection
♦ 6V to 26V Input Range
♦ 2V 0.75ꢀ Reference Output
♦ Power-Good Output
♦ Soft-Shutdown
The MAX1533A/MAX1537A include on-board power-up
sequencing, a power-good (PGOOD) output, digital
soft-start, and internal soft-shutdown output discharge
that prevents negative voltages on shutdown. The
MAX1533A is available in a 32-pin 5mm x 5mm thin
QFN package, and the MAX1537A is available in a 36-
pin 6mm x 6mm thin QFN package. The exposed back-
side pad improves thermal characteristics for
demanding linear keep-alive applications.
♦ 5µA (typ) Shutdown Current
Pin Configurations
TOP VIEW
32
31
30
29
28
27
26
25
ON5
ON3
1
2
3
4
5
6
7
8
24 FB5
Applications
23
22
LDO5
DL5
2 to 4 Li+ Cells Battery-Powered Devices
Notebook and Subnotebook Computers
PDAs and Mobile Communicators
FSEL
ILIM3
ILIM5
REF
21 PGND
20 DL3
MAX1533A
Ordering Information
19
18 FB3
17
LDO3
GND
PART
TEMP RANGE PIN-PACKAGE
V
CSL3
CC
MAX1533AETJ
MAX1533AETJ+
-40°C to +85°C 32 Thin QFN 5mm x 5mm
-40°C to +85°C 32 Thin QFN 5mm x 5mm
-40°C to +85°C 36 Thin QFN 6mm x 6mm
-40°C to +85°C 36 Thin QFN 6mm x 6mm
9
10 11 12 13 14 15 16
MAX1537AETX
MAX1537AETX+
THIN QFN
5mm x 5mm
+Denotes lead-free package.
Pin Configurations continued at end of data sheet.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
ABSOLUTE MAXIMUM RATINGS
IN, SHDN, INA, LDOA to GND ...............................-0.3V to +30V
GND to PGND .......................................................-0.3V to +0.3V
LX5 to BST5..............................................................-6V to +0.3V
DH5 to LX5 ..............................................-0.3V to (V + 0.3V)
BST5
LDO3, LDO5 Short Circuit to GND.............................Momentary
REF Short Circuit to GND ...........................................Momentary
INA Shunt Current.............................................................+15mA
LDO5, LDO3, V
to GND .......................................-0.3V to +6V
CC
ILIM3, ILIM5, PGDLY to GND...................................-0.3V to +6V
CSL3, CSH3, CSL5, CSH5 to GND ..........................-0.3V to +6V
ON3, ON5, FB3, FB5 to GND ..................................-0.3V to +6V
SKIP, OVP, UVP to GND...........................................-0.3V to +6V
PGOOD, FSEL, ADJA, ONA to GND........................-0.3V to +6V
REF to GND................................................-0.3V to (V
DL3, DL5 to PGND..................................-0.3V to (V
Continuous Power Dissipation (T = +70°C)
A
32-Pin TQFN (derate 21.3mW/°C above +70°C) .......1702mW
36-Pin TQFN (derate 26.3mW/°C above +70°C) .......2105mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V)
+ 0.3V)
CC
LDO5
BST3, BST5 to PGND .............................................-0.3V to +36V
LX3 to BST3..............................................................-6V to +0.3V
DH3 to LX3 ..............................................-0.3V to (V
+ 0.3V)
BST3
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, both SMPS enabled, V
= 5V, FSEL = REF, SKIP = GND, V
= V
, V
= 15V, V
= 12V,
LDOA
IN
CC
ILIM_
LDO5 INA
I
= I
= I = no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
LDOA A A
LDO5
LDO3
PARAMETER
INPUT SUPPLIES (Note 1)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LDO5 in regulation
IN = LDO5, V
6
26
5.5
35
V
V
V
V
Input Voltage Range
V
V
IN
IN
IN
IN
IN
< 4.43V
4.5
OUT5
Operating Supply Current
Standby Supply Current
Shutdown Supply Current
I
LDO5 switched over to CSL5
15
100
5
µA
µA
µA
IN
V
= 6V to 26V, both SMPS off,
IN
I
170
17
IN(STBY)
includes I
SHDN
I
V
= 6V to 26V, SHDN = GND
IN
IN(SHDN)
Both SMPS on, FB3 = FB5 = SKIP = GND,
Quiescent Power Consumption
P
V
= 3.5V, V
= 5.3V, V = 15V,
INA
3.5
1.1
4.5
2.1
mW
mA
Q
CSL3
CSL5
I
= 0, P + P
+ P + P
CSL5 INA
LDOA
IN
CSL3
Both SMPS on, FB3 = FB5 = GND,
V
V
Quiescent Supply Current
I
CC
CC
= 3.5V, V
= 5.3V
CSL3
CSL5
MAIN SMPS CONTROLLERS
3.3V Output Voltage in Fixed
Mode
V
V
V
= 6V to 26V, SKIP = V
= 6V to 26V, SKIP = V
(Note 2)
3.280
4.975
0.990
3.33
5.05
3.380
5.125
1.020
V
V
V
OUT3
OUT5
IN
CC
CC
5V Output Voltage in Fixed Mode
V
V
(Note 2)
IN
IN
Feedback Voltage in Adjustable
Mode
= 6V to 26V, FB3 or FB5,
V
1.005
FB_
duty factor = 20% to 80% (Note 2)
Output-Voltage Adjust Range
FB3, FB5 Dual-Mode Threshold
Feedback Input Leakage Current
Either SMPS
1.0
0.1
5.5
0.2
V
V
V
= V
= 1.1V
FB5
-0.1
+0.1
µA
FB3
Either SMPS, SKIP = V
,
CC
DC Load Regulation
-0.1
%
I
= 0 to full load
LOAD
2
_______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, V
= 5V, FSEL = REF, SKIP = GND, V
= V
, V
= 15V, V
= 12V,
LDOA
IN
CC
ILIM_
LDO5 INA
I
= I
= I = no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
LDOA A A
LDO5
LDO3
PARAMETER
SYMBOL
CONDITIONS
Either SMPS, duty cycle = 10% to 90%
FSEL = GND
MIN
TYP
1
MAX
UNITS
Line-Regulation Error
%
170
270
425
91
200
300
500
93
230
330
575
Operating Frequency (Note 1)
f
kHz
FSEL = REF
OSC
FSEL = V
CC
FSEL = GND
FSEL = REF
Maximum Duty Factor (Note 1)
D
91
93
%
MAX
FSEL = V
(Note 3)
91
93
CC
Minimum On-Time
t
200
ns
%
ON(MIN)
40
SMPS3 to SMPS5 Phase Shift
SMPS5 starts after SMPS3
CSH_, CSL_
144
Deg
CURRENT LIMIT
ILIM_ Adjustment Range
Current-Sense Input Range
0.5
0
V
V
V
REF
5.5
Current-Sense Input Leakage
Current
CSH_, V
_ = 5.5V
CSH
-1
+1
µA
Current-Limit Threshold (Fixed)
V
_
_
V
V
_ - V
_, ILIM_ = V
CC
70
170
91
75
200
100
50
80
230
109
58
mV
LIMIT
LIMIT
CSH
CSL
CSL
V
V
V
_ = 2.00V
_ = 1.00V
_ = 0.50V
ILIM
ILIM
ILIM
Current-Limit Threshold
(Adjustable)
V
_ - V
CSH
_
mV
%
42
Current-Limit Threshold
(Negative)
V
- V
, SKIP = V , percent of
CSH_
CSL_ CC
V
-120
NEG
current limit
Current-Limit Threshold (Zero
Crossing)
V
V
V
- V _, SKIP = GND, ILIM_ = V
CC
3
mV
mV
%
ZX
PGND
LX
ILIM_ = V
10
16
20
22
CC
Idle-Mode™ Threshold
V
_ - V
_
CSL
IDLE
CSH
With respect to current-
limit threshold (V
)
LIMIT
ILIM_ Leakage Current
Soft-Start Ramp Time
ILIM3 = ILIM5 = GND or V
-0.1
+0.1
µA
s
CC
Measured from the rising edge of ON_ to
full scale
512 /
t
SS
f
OSC
INTERNAL FIXED LINEAR REGULATORS
ON3 = ON5 = GND, 6V < V < 26V,
IN
LDO5 Output Voltage
V
4.80
4.95
4.0
5.10
V
LDO5
0 < I
< 100mA
LDO5
LDO5 Undervoltage-Lockout Fault
Threshold
Rising edge, hysteresis = 1%
3.75
4.41
4.25
4.75
3
V
V
LDO5 Bootstrap Switch Threshold
Rising edge of CSL5, hysteresis = 1%
LDO5 Bootstrap Switch
Resistance
LDO5 to CSL5, V
= 5V,
CSL5
0.75
Ω
I
= 50mA
LDO5
Idle Mode is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
3
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, V
= 5V, FSEL = REF, SKIP = GND, V
= V
, V
= 15V, V = 12V,
LDOA
IN
CC
ILIM_
LDO5 INA
I
= I
= I
= no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
LDO5
LDO3
LDOA
A
A
PARAMETER
SYMBOL
CONDITIONS
Standby mode, 6V < V < 26V,
MIN
TYP
MAX
3.42
3.10
3
UNITS
IN
LDO3 Output Voltage
V
3.20
2.83
3.35
V
V
LDO3
0 < I
< 100mA
LOAD
LDO3 Bootstrap Switch Threshold
Rising edge of CSL3, hysteresis = 1%
LDO3 Bootstrap Switch
Resistance
LDO3 to CSL3, V = 3.2V,
CSL3
1
Ω
I
= 50mA
LDO3
LDO3 = LDO5 = GND,
CSL3 = CSL5 = GND
Short-Circuit Current
150
220
mA
mA
Short-Circuit Current (Switched
Over to CSL_)
LDO3 = LDO5 = GND, V
> 3.1V,
CSL3
250
V
> 4.7V
CSL5
AUXILIARY LINEAR REGULATOR (MAX1537A ONLY)
LDOA Voltage Range
INA Voltage Range
V
5
6
23
24
V
V
LDOA
V
INA
LDOA Regulation Threshold,
Internal Feedback
ADJA = GND, 0 < I
< 120mA,
LDOA
11.4
1.94
12.0
12.4
2.06
V
V
V
> 13V
INA
ADJA Regulation Threshold,
External Feedback
0 < I
< 120mA, V
> 5.0V and
LDOA
LDOA
V
2.00
0.15
ADJA
V
> V
+ 1V
LDOA
INA
ADJA Dual-Mode Threshold
ADJA Leakage Current
0.1
0.2
V
V
= 2.1V
-0.1
+0.1
µA
ADJA
LDOA
V
V
forced to V
> 6V
- 1V, V
= 1.9V,
INA
ADJA
LDOA Current Limit
150
mA
V
INA
INA
INA
Secondary Feedback Regulation
Threshold
V
- V
0.65
0.8
0.95
LDOA
V
- V
< 0.7V, pulse width with
LDOA
DL Duty Factor
33
50
%
respect to switching period
INA Quiescent Current
INA Shunt Sink Current
INA Leakage Current
REFERENCE (REF)
Reference Voltage
I
V
V
V
= 24V, I
= no load
LDOA
165
30
µA
mA
µA
INA
INA
INA
INA
= 28V
10
I
= 5V, LDOA disabled
INA(SHDN)
V
V
= 4.5V to 5.5V, I = 0
REF
1.985
1.980
2.00
1.95
2.015
2.020
V
V
V
REF
CC
Reference Load Regulation
REF Lockout Voltage
FAULT DETECTION
I
= -10µA to +100µA
REF
V
Rising edge, hysteresis = 350mV
REF(UVLO)
Output Overvoltage Trip
Threshold
OVP = GND, with respect to error-
comparator threshold
8
11
10
15
%
Output Overvoltage Fault-
Propagation Delay
t
50mV overdrive
µs
OVP
4
_______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, V
= 5V, FSEL = REF, SKIP = GND, V
= V
, V
= 15V, V = 12V,
LDOA
IN
CC
ILIM_
LDO5 INA
I
= I
= I
= no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
LDO5
LDO3
LDOA
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Undervoltage-Protection
Trip Threshold
With respect to error-comparator threshold
65
70
75
%
Output Undervoltage Fault-
Propagation Delay
t
50mV overdrive
10
µs
s
UVP
Output Undervoltage-Protection
Blanking Time
6144 /
t
From rising edge of ON_
BLANK
f
OSC
-10
10
With respect to error-comparator
threshold, hysteresis = 1%
PGOOD Lower Trip Threshold
-14
-7.5
%
PGOOD Propagation Delay
PGOOD Output Low Voltage
PGOOD Leakage Current
PGDLY Pullup Current
t
I
_
_
Falling edge, 50mV overdrive
µs
V
PGOOD
I
= 4mA
0.4
1
SINK
High state, PGOOD forced to 5.5V
PGDLY = GND
µA
µA
Ω
PGOOD
4
5
6
PGDLY Pulldown Resistance
10
25
REF-
0.2
REF+
0.2
PGDLY Trip Threshold
REF
V
Thermal-Shutdown Threshold
GATE DRIVERS
T
Hysteresis = 15°C
+160
°C
SHDN
DH_ Gate-Driver On-Resistance
R
BST_ - LX_ forced to 5V
DL_, high state
1.5
1.7
0.6
5
5
3
Ω
Ω
DH
DL_ Gate-Driver On-Resistance
R
DL
DL_, low state
DH_ Gate-Driver Source/Sink
Current
DH_ forced to 2.5V,
BST_ - LX_ forced to 5V
I
2
A
DH
I
DL_ Gate-Driver Source Current
DL_ Gate-Driver Sink Current
DL_ forced to 2.5V
DL_ forced to 2.5V
DL_ rising
1.7
3.3
35
A
A
DL
I
DL (SINK)
Dead Time
t
ns
DEAD
DH_ rising
26
LX_, BST_ Leakage Current
V
_ = V _ = 26V
<2
20
µA
BST
LX
INPUTS AND OUTPUTS
High
Low
2.4
Logic Input Voltage
SKIP, hysteresis = 600mV
OVP, UVP, ONA
V
V
0.8
0.7 x
High
Low
V
Fault Enable Logic Input Voltage
CC
0.4
+1
Logic Input Current
OVP, UVP, SKIP, ONA
Rising trip level
-1
µA
V
1.10
0.96
1.6
1
2.20
1.04
0.8
SHDN Input Trip Level
Falling trip level
Clear fault level/SMPS off level
Delay start level (REF)
SMPS on level
ON_ Input Voltage
1.9
2.4
2.1
V
_______________________________________________________________________________________
5
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, V
= 5V, FSEL = REF, SKIP = GND, V
= V
, V
= 15V, V
= 12V,
LDOA
IN
CC
ILIM_
LDO5 INA
I
= I
= I
= no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
LDO5
LDO3
LDOA
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
High
REF
V
- 0.2
CC
FSEL Three-Level Input Logic
Input Leakage Current
1.7
2.3
0.4
V
GND
OVP, UVP, SKIP, ONA, ON3, ON5 = GND
or V
-1
+1
CC
µA
SHDN, 0V or 26V
-1
-3
+1
+3
FSEL = GND or V
CC
CSL_ Discharge-Mode
On-Resistance
R
10
25
Ω
DISCHARGE
CSL_ Synchronous-Rectifier
Discharge-Mode Turn-On Level
0.2
0.3
0.4
V
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, both SMPS enabled, V
= 5V, FSEL = REF, SKIP = GND, V
= V
, V
= 15V, V
= 12V,
LDOA
IN
CC
ILIM_
LDO5 INA
I
= I
= I = no load, T = -40°C to +85°C, unless otherwise noted.) (Note 4)
LDOA A
LDO5
LDO3
PARAMETER
INPUT SUPPLIES (Note 1)
SYMBOL
CONDITIONS
MIN
MAX
UNITS
LDO5 in regulation
IN = LDO5, V
6
26
V
V
Input Voltage Range
V
V
IN
IN
IN
< 4.4V
4.5
5.5
OUT5
LDO5 switched over to CSL5,
either SMPS on
Operating Supply Current
I
35
µA
IN
V
= 6V to 26V, both SMPS off,
IN
V
V
Standby Supply Current
Shutdown Supply Current
I
170
17
µA
µA
IN
IN
IN(STBY)
includes I
SHDN
I
V
= 6V to 26V
IN
IN(SHDN)
Both SMPS on, FB3 = FB5 = SKIP = GND,
V
= 3.5V, V
= 5.3V, V
= 15V,
+ P
Quiescent Power Consumption
P
Q
4.5
2.5
mW
mA
CSL3
CSL5
INA
I
= 0, P + P
+ P
LDOA
IN
CSL3
CSL5 INA
Both SMPS on, FB3 = FB5 = GND,
V
V
Quiescent Supply Current
I
CC
CC
= 3.5V, V
= 5.3V
CSL3
CSL5
MAIN SMPS CONTROLLERS
3.3V Output Voltage in
Fixed Mode
V
V
V
= 6V to 26V, SKIP = V
= 6V to 26V, SKIP = V
(Note 2)
3.28
3.38
5.125
1.018
5.5
V
V
V
V
V
OUT3
OUT5
IN
CC
CC
5V Output Voltage in Fixed Mode
V
V
(Note 2)
4.975
0.982
1.0
IN
IN
Feedback Voltage in
Adjustable Mode
= 6V to 26V, FB3 or FB5,
V
, V
FB3 FB5
duty factor = 20% to 80% (Note 2)
Output-Voltage Adjust Range
Either SMPS
FB3, FB5 Adjustable-Mode
Threshold Voltage
Dual-mode comparator
0.1
0.2
6
_______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, V
= 5V, FSEL = REF, SKIP = GND, V
= V
, V
= 15V, V = 12V,
LDOA
IN
CC
ILIM_
LDO5 INA
I
= I
= I = no load, T = -40°C to +85°C, unless otherwise noted.) (Note 4)
LDOA A
LDO5
LDO3
PARAMETER
SYMBOL
CONDITIONS
MIN
170
240
375
91
MAX
230
330
575
UNITS
FSEL = GND
FSEL = REF
Operating Frequency (Note 1)
Maximum Duty Factor (Note 1)
f
kHz
OSC
FSEL = V
CC
FSEL = GND
FSEL = REF
D
%
91
MAX
FSEL = V
91
CC
Minimum On-Time
t
250
ns
ON(MIN)
CURRENT LIMIT
ILIM_ Adjustment Range
Current-Limit Threshold (Fixed)
0.5
67
V
V
REF
V
_
_
V
V
_ - V
_, ILIM_ = V
CC
83
230
110
60
mV
LIMIT
LIMIT
CSH
CSL
CSL
V
V
V
_ = 2.00V
_ = 1.00V
_ = 0.50V
170
90
ILIM
ILIM
ILIM
Current-Limit Threshold
(Adjustable)
V
_ - V
CSH
_
mV
40
INTERNAL FIXED LINEAR REGULATORS
ON3 = ON5 = GND, 6V < V < 26V,
IN
LDO5 Output Voltage
V
V
4.8
5.1
V
V
V
LDO5
0 < I
< 100mA
LDO5
LDO5 Undervoltage-Lockout
Fault Threshold
Rising edge, hysteresis = 1%
3.75
3.20
4.30
3.43
Standby mode, 6V < V < 28V,
IN
LDO3 Output Voltage
LDO3
0 < I
< 100mA
LOAD
AUXILIARY LINEAR REGULATOR (MAX1537A ONLY)
LDOA Voltage Range
INA Voltage Range
V
5
6
23
24
V
V
LODA
V
INA
LDOA Regulation Threshold,
Internal Feedback
ADJA = GND, 0 < I
< 120mA,
LDOA
11.40
12.55
V
V
> 13V
INA
ADJA Regulation Threshold,
External Feedback
0 < I
< 120mA, V
> 5.0V and
LDOA
LDOA
> V
V
1.94
0.10
0.63
2.08
0.25
0.97
165
V
V
ADJA
V
+ 1V
INA
LDOA
ADJA Dual-Mode Threshold
ADJA
Secondary Feedback
Regulation Threshold
V
V
- V
V
INA
INA
LDOA
INA Quiescent Current
REFERENCE (REF)
Reference Voltage
I
= 24V, I
= no load
µA
INA
LDOA
V
V
= 4.5V to 5.5V, I = 0
REF
1.97
2.03
V
REF
CC
_______________________________________________________________________________________
7
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, V
= 5V, FSEL = REF, SKIP = GND, V
= V
, V
= 15V, V
= 12V,
LDOA
IN
CC
ILIM_
LDO5 INA
I
= I
= I = no load, T = -40°C to +85°C, unless otherwise noted.) (Note 4)
LDOA A
LDO5
LDO3
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
FAULT DETECTION
Output Overvoltage Trip
Threshold
OVP = GND, with respect to error-
comparator threshold
+8
+15
+75
-7.0
%
%
%
Output Undervoltage-Protection
Trip Threshold
With respect to error-comparator threshold
+65
-14.0
With respect to error-comparator threshold,
hysteresis = 1%
PGOOD Lower Trip Threshold
PGOOD Output Low Voltage
PGDLY Pulldown Resistance
I
= 4mA
0.4
25
V
SINK
Ω
REF-
0.2
REF+
0.2
PGDLY Trip Threshold
V
GATE DRIVERS
DH_ Gate-Driver On-Resistance
R
BST_ - LX_ forced to 5V
DL_, high state
5
5
3
Ω
Ω
DH
DL_ Gate-Driver On-Resistance
INPUTS AND OUTPUTS
Logic Input Voltage
R
DL
DL_, low state
High
Low
2.4
SKIP, hysteresis = 600mV
OVP, UVP, ONA
V
V
V
0.8
0.7 x
High
Low
V
Fault Enable Logic Input Voltage
CC
0.4
2.2
1.05
0.8
1.6
2.1
Rising trip level
Falling trip level
Clear fault level
SMPS off level
Delay start level (REF)
SMPS on level
High
1.1
SHDN Input Trip Level
0.95
ON_ Input Voltage
V
V
1.9
2.4
V
- 0.2
CC
FSEL Three-Level Input Logic
REF
1.7
2.3
0.4
GND
Note 1: The MAX1533A/MAX1537A cannot operate over all combinations of frequency, input voltage (V ), and output voltage. For
IN
large input-to-output differentials and high-switching frequency settings, the required on-time may be too short to maintain
the regulation specifications. Under these conditions, a lower operating frequency must be selected. The minimum on-time
must be greater than 150ns, regardless of the selected switching frequency. On-time and off-time specifications are mea-
sured from 50% point to 50% point at the DH_ pin with LX_ = GND, V
= 5V, and a 250pF capacitor connected from DH_
BST_
to LX_. Actual in-circuit times may differ due to MOSFET switching speeds.
Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error-comparator
threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regula-
tion level higher than the trip level by approximately 1% due to slope compensation.
Note 3: Specifications are guaranteed by design, not production tested.
Note 4: Specifications to -40°C are guaranteed by design, not production tested.
8
_______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Typical Operating Characteristics
(MAX1537A circuit of Figure 1, V = 12V, LDO5 = V
IN
= 5V, SKIP = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
A
CC
PWM5 EFFICIENCY vs. LOAD CURRENT
5V OUTPUT VOLTAGE (OUT5)
vs. LOAD CURRENT
5V OUTPUT VOLTAGE (OUT5)
vs. INPUT VOLTAGE
(V
= 5.0V)
OUT5
100
90
80
70
60
50
5.12
5.08
5.04
5.00
4.96
4.92
4.88
5.12
5.08
5.04
5.00
4.96
4.92
4.88
NO LOAD
SKIP = GND
SKIP = V
CC
V
= 7V
IN
V
= 12V
= 20V
IN
V
IN
SKIP = GND
SKIP = V
SKIP = GND
SKIP = V
CC
CC
0.01
0.1
1
10
0
1
2
3
4
5
6
5
5
0
10
15
20
25
30
30
30
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
PWM3 EFFICIENCY vs. LOAD CURRENT
3.3V OUTPUT VOLTAGE (OUT3)
vs. LOAD CURRENT
3.3V OUTPUT VOLTAGE (OUT3)
vs. INPUT VOLTAGE
(V
= 3.3V)
OUT3
100
90
80
70
60
50
3.39
3.36
3.33
3.30
3.27
3.24
3.21
3.39
3.36
3.33
3.30
3.27
3.24
3.21
NO LOAD
SKIP = GND
SKIP = V
CC
V
= 5V
IN
V
= 12V
IN
V
= 20V
IN
SKIP = GND
SKIP = V
SKIP = GND
SKIP = V
CC
CC
0.01
0.1
1
10
0
1
2
3
4
5
6
10
15
20
25
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
NO-LOAD SUPPLY CURRENT
NO-LOAD SUPPLY CURRENT
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
vs. INPUT VOLTAGE (FULLY ENABLED)
vs. INPUT VOLTAGE (STANDBY MODE)
32
28
24
20
16
12
8
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
8
ON3 = ON5 = V
ON3 = ON5 = GND
CC
SHDN = GND
6
SKIP = GND
SKIP = V
CC
4
2
4
0.22mA (V = 12V)
IN
0
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
5
10
15
20
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(MAX1537A circuit of Figure 1, V = 12V, LDO5 = V
IN
= 5V, SKIP = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
CC
A
IDLE-MODE CURRENT
vs. INPUT VOLTAGE
LINEAR-REGULATOR
LOAD REGULATION
2.0V REFERENCE LOAD REGULATION
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.02
2.01
2.00
1.99
1.98
50
0
DUTY CYCLE
LIMITED
LDO3
LDO5
-50
-100
-150
-200
V
= 6V
IN
5V OUTPUT
25
ON3 = ON5 = GND
0
5
10
15
20
30
-20
0
20
40
60
80
100
0
20
40
60
80 100 120 140
INPUT VOLTAGE (V)
REF LOAD CURRENT (μA)
LDO LOAD CURRENT (mA)
LINEAR-REGULATOR
AUXILIARY LINEAR-REGULATOR
LOAD REGULATION
STARTUP WAVEFORMS
INTERLEAVED OPERATION
MAX1533/37 toc15
MAX1533/37 toc14
12.1
12.0
11.9
11.8
11.7
5V
12V
A
B
A
0
4V
0
B
5V
2V
C
0
0
2V
12V
C
D
D
0
2V
0
3.3V
0
E
F
0
400μs/div
2.0μs/div
0
40
80
120
160
200
A. SHDN, 5V/div
B. LDO5, 2V/div
C. LDO3, 2V/div
D. REF, 2V/div
A. LX5, 10V/div
B. 5V OUTPUT, 100mV/div
C. PWM5 INDUCTOR CURRENT, 5A/div
D. LX3, 10V/div
LDOA LOAD CURRENT (mA)
100Ω LOAD ON LDO5 AND LDO3
E. 3.3V OUTPUT, 100mV/div
F. PWM3 INDUCTOR CURRENT, 5A/div
10 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(MAX1537A circuit of Figure 1, V = 12V, LDO5 = V
IN
= 5V, SKIP = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
A
CC
DELAYED STARTUP WAVEFORM
STARTUP WAVEFORM (HEAVY LOAD)
(LIGHT LOAD)
SHUTDOWN WAVEFORM (NO LOAD)
MAX1533/37 toc17
MAX1533/37 toc16
MAX1533/37 toc18
3.3V
0
3.3V
2V
0
5V
A
A
B
A
B
0
5V
4V
2V
0
5V
B
C
D
0
2.5A
0
0
0
3.3V
0
3.3V
C
C
D
5V
0
0
D
E
5V
0
E
F
0
0
400μs/div
2ms/div
2ms/div
A. ON5, 5V/div
A. ON5, 5V/div
B. 5V OUTPUT, 2V/div
C. 3.3V OUPUT, 2V/div
D. PGOOD, 2V/div
A. SHDN, 5V/div
B. 5V OUTPUT, 5V/div
C. DL5, 5V/div
D. 3.3V OUTPUT, 5V/div
E. DL3, 5V/div
F. PGOOD, 5V/div
B. 5V OUTPUT, 2V/div
C. INDUCTOR CURRENT, 5A/div
D. LDO5, 1V/div
E. DL5, 5V/div
1.0Ω LOAD
ON3 = ON5 = V , OVP = GND
CC
100Ω LOAD ON OUT5 AND OUT3, ON3 = REF
5V OUTPUT LOAD TRANSIENT
3.3V OUTPUT LOAD TRANSIENT
(FORCED-PWM)
SHUTDOWN WAVEFORM (1Ω LOAD)
(FORCED-PWM)
MAX1533/37 toc19
MAX1533/37 toc20
MAX1533/37 toc21
4A
0
4A
0
2V
0
5V
5V
A
A
A
B
B
B
5V
4A
3.3V
C
D
4A
0
5A
C
D
C
D
0
0
12V
12V
0
5V
E
0
0
100μs/div
40μs/div
40μs/div
A. SHDN, 5V/div
B. LDO5, 2V/div
A. I
B. V
= 0.2A TO 4A, 5A/div
= 5.0V, 100mV/div
A. I
B. V
= 0.2A TO 4A, 5A/div
= 3.3V, 100mV/div
OUT5
OUT3
OUT5
OUT3
C. 5V OUTPUT, 2V/div
D. INDUCTOR CURRENT, 5A/div
E. DL5, 5V/div
C. INDUCTOR CURRENT, 5A/div
D. LX5, 10V/div
C. INDUCTOR CURRENT, 5A/div
D. LX3, 10V/div
SKIP = V
SKIP = V
CC
CC
ON3 = ON5 = V , OVP = GND
CC
______________________________________________________________________________________ 11
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(MAX1537A circuit of Figure 1, V = 12V, LDO5 = V
IN
= 5V, SKIP = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
CC
A
OUTPUT OVERLOAD
(UVP ENABLED)
3.3V OUTPUT LOAD TRANSIENT
LDO5 LOAD TRANSIENT
MAX1533/37 toc24
(PULSE SKIPPING)
MAX1533/37 toc23
MAX1533/37 toc22
4A
5V
A
B
A
B
0
5V
0
0
3.3V
A
B
3.3V
0
100mA
0
30A
4A
0
C
C
D
0
7A
D
E
0
5.0V
12V
0
C
12V
0
4.95V
4μs/div
20μs/div
40μs/div
A. PGOOD2, 5V/div
B. 3.3V OUTPUT, 3.3V/div
C. LOAD (0 TO 30A), 20A/div
D. INDUCTOR CURRENT, 10A/div
E. LX3, 20V/div
A. CONTROL SIGNAL, 5V/div
A. I
B. V
= 0.2A TO 4A, 5A/div
= 3.3V, 100mV/div
OUT3
B. I
= 1mA TO 100mA, 100mA/div
LDO5
OUT3
C. LDO5, 50m/div
ON3 = ON5 = GND
C. INDUCTOR CURRENT, 5A/div
D. LX3, 10V/div
SKIP = GND
AUXILIARY LINEAR-REGULATOR
LOAD TRANSIENT
LDO5 LINE TRANSIENT
MAX1533/37 toc25
MAX1533/37 toc26
20V
15V
10V
5V
120mA
10mA
A
A
B
14V
13V
B
5.05V
5.00V
4.95V
11.96V
11.90V
C
20μs/div
100μs/div
A. INPUT VOLTAGE (V = 7V TO 20V), 5V/div
IN
A. I
= 10mA TO 100mA, 100mA/div
LDOA
B. LDO5 OUTPUT VOLTAGE, 50mV/div
B. INA, 1V/div
ON3 = ON5 = GND, I
= 20mA
C. LDOA, 50mV/div
LDO5
INA = VOLTAGE GENERATED BY SECONDARY
TRANSFORMER WINDING
12 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Pin Description
PIN
NAME
FUNCTION
MAX1533A MAX1537A
Auxiliary Feedback Input. Connect a resistive voltage-divider from LDOA to analog
ground to adjust the auxiliary linear-regulator output voltage. ADJA regulates at 2V.
Connect ADJA to GND for nominal 12V output using internal feedback.
—
1
1
2
ADJA
5V SMPS Enable Input. The 5V SMPS is enabled if ON5 is greater than the SMPS on
level and disabled if ON5 is less than the SMPS off level. If ON5 is connected to REF,
the 5V SMPS starts after the 3.3V SMPS reaches regulation (delay start). Drive ON5
below the clear fault level to reset the fault latches.
ON5
3.3V SMPS Enable Input. The 3.3V SMPS is enabled if ON3 is greater than the SMPS
on level and disabled if ON3 is less than the SMPS off level. If ON3 is connected to
REF, the 3.3V SMPS starts after the 5V SMPS reaches regulation (delay start). Drive
ON3 below the clear fault level to reset the fault latches.
2
—
3
3
4
5
ON3
ONA
FSEL
LDOA Enable Input. When ONA is low, LDOA is high impedance and the secondary
winding control is off. When ONA is high, LDOA is on. Connect to LDO3, LDO5,
CSL3, CSL5, or other output for desired automatic startup sequencing.
Frequency-Select Input. This three-level logic input sets the controller’s switching
frequency. Connect to GND, REF, or V
frequencies:
to select the following typical switching
CC
V
= 500kHz, REF = 300kHz, GND = 200kHz
CC
3.3V SMPS Peak Current-Limit Threshold Adjustment. The current-limit threshold
defaults to 75mV if ILIM3 is connected to V . In adjustable mode, the current-limit
CC
4
6
ILIM3
ILIM5
threshold across CSH3 and CSL3 is precisely 1/10 the voltage seen at ILIM3 over a
500mV to 2.0V range. The logic threshold for switchover to the 75mV default value is
approximately V
- 1V.
CC
5V SMPS Peak Current-Limit Threshold. The current-limit threshold defaults to 75mV if
ILIM5 is connected to V . In adjustable mode, the current-limit threshold across CSH5
CC
and CSL5 is precisely 1/10th the voltage seen at ILIM5 over a 500mV to 2.0V range. The
logic threshold for switchover to the 75mV default value is approximately V - 1V.
CC
5
6
7
8
2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1µF or greater
ceramic capacitor. The reference can source up to 100µA for external loads. Loading
REF degrades output-voltage accuracy according to the REF load-regulation error.
The reference shuts down when SHDN is low.
REF
7
8
9
GND
Analog Ground. Connect the backside pad to GND.
Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through
a series 20Ω resistor. Bypass V
to analog ground with a 1µF or greater ceramic
10
V
CC
CC
capacitor.
Power-Good One-Shot Delay. Place a timing capacitor on PGDLY to delay PGOOD
going high. PGDLY has a 5µA pullup current and a 10Ω pulldown. The pulldown is
activated when power is not good. When power is good, the pulldown is shut off and
the 5µA pullup is activated. When PGDLY crosses REF, PGOOD is enabled.
9
11
PGDLY
______________________________________________________________________________________ 13
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1533A MAX1537A
Open-Drain Power-Good Output. PGOOD is low if either output is more than 10%
(typ) below the normal regulation point, during soft-start, and in shutdown. PGOOD is
delayed on the rising edge by the PGDLY one-shot timer. PGOOD becomes high
impedance when both SMPS outputs are in regulation.
10
12
PGOOD
Undervoltage Fault-Protection Control. Connect UVP to GND to select the default
overvoltage threshold of 70% of nominal. Connect to V to disable undervoltage
CC
protection and clear the undervoltage fault latch.
11
12
13
13
14
15
UVP
DH3
BST3
High-Side Gate-Driver Output for 3.3V SMPS. DH3 swings from LX3 to BST3.
Boost Flying-Capacitor Connection for 3.3V SMPS. Connect to an external capacitor
and diode as shown in Figure 6. An optional resistor in series with BST3 allows the
DH3 pullup current to be adjusted.
Inductor Connection for 3.3V SMPS. Connect LX3 to the switched side of the
inductor. LX3 serves as the lower supply rail for the DH3 high-side gate driver.
14
15
16
17
18
16
17
18
19
20
LX3
OVP
Overvoltage Fault-Protection Control. Connect OVP to GND to select the default
overvoltage threshold of +11% above nominal. Connect to V
overvoltage protection and clear the overvoltage fault latch.
to disable
CC
Positive Current-Sense Input for 3.3V SMPS. Connect to the positive terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
CSH3
CSL3
FB3
Negative Current-Sense Input for 3.3V SMPS. Connect to the negative terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
CSL3 also serves as the bootstrap input for LDO3.
Feedback Input for 3.3V SMPS. Connect to GND for fixed 3.3V output. In adjustable
mode, FB3 regulates to 1V.
3.3V Internal Linear-Regulator Output. Bypass with 2.2µF (min) (1µF/20mA). Provides
100mA (min). Power is taken from LDO5. If CSL3 is greater than 3V, the linear
regulator shuts down and LDO3 connects to CSL3 through a 1Ω switch rated for
loads up to 200mA.
19
21
LDO3
20
21
22
22
23
24
DL3
PGND
DL5
Low-Side Gate-Driver Output for 3.3V SMPS. DL3 swings from PGND to LDO5.
Power Ground
Low-Side Gate-Driver Output for 5V SMPS. DL5 swings from PGND to LDO5.
5V Internal Linear-Regulator Output. Bypass with 2.2µF (min) (1µF/20mA). Provides
power for the DL_ low-side gate drivers, the DH_ high-side drivers through the BST
diodes, the PWM controller, logic, and reference through the V
pin, as well as the
CC
23
24
25
26
LDO5
FB5
LDO3 internal 3.3V linear regulator. Provides 100mA (min) for external loads (+25mA
for gate drivers). If CSL5 is greater than 4.5V, the linear regulator shuts down and
LDO5 connects to CSL5 through a 0.75Ω switch rated for loads up to 200mA.
Feedback Input for 5V SMPS. Connect to GND for fixed 5V output. In adjustable
mode, FB5 regulates to 1V.
14 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1533A MAX1537A
Negative Current-Sense Input for 5V SMPS. Connect to the negative terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
CSL5 also serves as the bootstrap input for LDO5.
25
27
CSL5
Positive Current-Sense Input for 5V SMPS. Connect to the positive terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
26
27
28
28
29
30
CSH5
IN
Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to
PGND with 0.22µF close to the IC.
Inductor Connection for 5V SMPS. Connect LX5 to the switched side of the inductor.
LX5 serves as the lower supply rail for the DH5 high-side gate driver.
LX5
Boost Flying-Capacitor Connection for 5V SMPS. Connect to an external capacitor
and diode as shown in Figure 6. An optional resistor in series with BST5 allows the
DH5 pullup current to be adjusted.
29
31
BST5
30
31
32
33
DH5
High-Side Gate-Driver Output for 5V SMPS. DH5 swings from LX5 to BST5.
Pulse-Skipping Control Input. Connect to V
for low-noise forced-PWM mode.
CC
SKIP
Connect to GND for high-efficiency pulse-skipping mode at light loads.
Shutdown Control Input. The device enters its 5µA supply-current shutdown mode if
V
V
is less than the SHDN input falling-edge trip level and does not restart until
SHDN
is greater than the SHDN input rising-edge trip level. Connect SHDN to V for
SHDN IN
32
—
—
34
35
36
SHDN
INA
automatic startup. SHDN can be connected to V through a resistive voltage-divider
to implement a programmable undervoltage lockout.
IN
Supply Voltage Input for the Auxiliary LDOA Linear Regulator. INA is clamped with an
internal shunt to 26V.
Adjustable (12V Nominal) 150mA Auxiliary Linear-Regulator Output. Input supply
comes from INA. Bypass LDOA to GND with 2.2µF (min) (1µF/20mA). Secondary
feedback threshold is set at INA - LDOA = 0.8V, and triggers the DL5 on the 5V
SMPS only. ONA high enables regulator output and secondary regulation. PGOOD is
not affected by the state of LDOA.
LDOA
______________________________________________________________________________________ 15
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Table 1. Component Selection for Standard Applications
COMPONENT
5A/300kHz
= 7V to 24V
5A/500kHz
V = 7V to 24V
IN
Input Voltage
V
IN
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
C
, Input Capacitor
, Output Capacitor
, Output Capacitor
IN_
150µF, 6.3V, 40mΩ, low-ESR capacitor
Sanyo 6TPB150ML
150µF, 6.3V, 40mΩ, low-ESR capacitor
Sanyo 6TPB150ML
C
C
OUT5
OUT3
220µF, 4V, 40mΩ, low-ESR capacitor
Sanyo 4TPB220ML
220µF, 4V, 40mΩ, low-ESR capacitor
Sanyo 4TPB220ML
Fairchild Semiconductor FDS6612A
International Rectifier IRF7807V
Fairchild Semiconductor FDS6612A
International Rectifier IRF7807V
N
High-Side MOSFET
Low-Side MOSFET
H_
Fairchild Semiconductor FDS6670S
International Rectifier IRF7807VD1
Fairchild Semiconductor FDS6670S
International Rectifier IRF7807VD1
N
L_
D
Schottky Rectifier
(if needed)
2A, 30V, 0.45V
Nihon EC21QS03L
2A, 30V, 0.45V
f
Nihon EC21QS03L
L_
f
T1 = 6.8µH, 1:2 turns Sumida 4749-T132
L1 = 5.8µH, 8.6A Sumida CDRH127-5R8NC
3.9µH
Inductor/Transformer
Sumida CDRH124-3R9NC
10mΩ 1%, 0.5W resistor
IRC LR2010-01-R010F or
Dale WSL-2010-R010F
10mΩ 1%, 0.5W resistor
IRC LR2010-01-R010F or
Dale WSL-2010-R010F
R
CS
Table 2. Component Suppliers
SUPPLIER
WEBSITE
SUPPLIER
Panasonic
WEBSITE
AVX
www.avx.com
www.panasonic.com/industrial
www.secc.co.jp
Central Semiconductor
Coilcraft
www.centralsemi.com
www.coilcraft.com
www.coiltronics.com
Sanyo
Sumida
www.sumida.com
Coiltronics
Taiyo Yuden
TDK
www.t-yuden.com
Fairchild Semiconductor www.fairchildsemi.com
www.component.tdk.com
www.tokoam.com
International Rectifier
Kemet
www.irf.com
TOKO
www.kemet.com
Vishay (Dale, Siliconix)
www.vishay.com
Fixed Linear Regulators (LDO5 and LDO3)
Two internal linear regulators produce preset 5V (LDO5)
and 3.3V (LDO3) low-power outputs. LDO5 powers
LDO3, the gate drivers for the external MOSFETs, and
Detailed Description
The MAX1533A/MAX1537A standard application circuit
(Figure 1) generates the 5V/5A and 3.3V/5A typical of the
main supplies in a notebook computer. The input supply
range is 7V to 24V. See Table 1 for component selections
and Table 2 for component manufacturers.
provides the bias supply (V ) required for the SMPS
CC
analog control, reference, and logic blocks. LDO5
supplies at least 100mA for external and internal loads,
including the MOSFET gate drive, which typically varies
from 5mA to 50mA, depending on the switching frequen-
cy and external MOSFETs selected. LDO3 also supplies
at least 100mA for external loads. Bypass LDO5 and
LDO3 with a 2.2µF or greater output capacitor, using an
additional 1.0µF per 20mA of internal and external load.
The MAX1533A/MAX1537A contain two interleaved
fixed-frequency step-down controllers designed for low-
voltage power supplies. The optimal interleaved archi-
tecture guarantees out-of-phase operation, reducing the
input capacitor ripple. Two internal LDOs generate
the keep-alive 5V and 3.3V power. The MAX1537A has
an auxiliary LDO that can be configured to the preset
12V output or an adjustable output.
16 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
INPUT (V )
IN
5V LDO
C
IN
OUTPUT
C1
(2) 10μF
10μF
IN
LDO5
D
BST
D
BST
C5
N
H1
22μF
N
H2
DH3
DH5
MAX1533A
MAX1537A
SECONDARY
OUTPUT
BST5
BST3
C
BST
C
BST
0.1μF
0.1μF
D1
T1
1:2 TURNS
LP = 6.8μH
LX3
DL3
LX5
DL5
D
L2
D
L1
L1
N
L2
5.8μH
N
L1
PGND
GND
R
CS1
10mΩ
R
CS2
CSH5
CSL5
CSH3
CSL3
FB3
10mΩ
5V PWM
OUTPUT
3.3V PWM
OUTPUT
C
C
OUT2
OUT1
FB5
150μF
40mΩ
220μF
40mΩ
OVP
REF
UVP
C
REF
0.22μF
SKIP
R2
100kΩ
FSEL
VCC
REF (300kHz)
R3
60.4kΩ
ILIM3
CONNECT
TO LDO5
R1
C2
R4
100kΩ
R8
100kΩ
20Ω
1μF
R5
60.4kΩ
ILIM5
SHDN
ON3
PGOOD
PGDLY
POWER-GOOD
ON OFF
3.3V LDO
OUTPUT
LDO3
ON OFF
C3
ON5
10μF
MAX1537A ONLY
SECONDARY
OUTPUT
12V LDO
OUTPUT
LDOA
ADJA
INA
C4
10μF
R6
OPEN
ON OFF
ONA
R7
0Ω
POWER GROUND
ANALOG GROUND
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS
Figure 1. MAX1533A/MAX1537A Standard Application Circuit
______________________________________________________________________________________ 17
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
SMPS to LDO Bootstrap Switchover
When the 5V main output voltage is above the LDO5
bootstrap-switchover threshold, an internal 0.75Ω (typ)
p-channel MOSFET shorts CSL5 to LDO5 while simulta-
neously shutting down the LDO5 linear regulator.
Similarly, when the 3.3V main output voltage is above
the LDO3 bootstrap-switchover threshold, an internal
1Ω (typ) p-channel MOSFET shorts CSL3 to LDO3 while
simultaneously shutting down the LDO3 linear regula-
tor. These actions bootstrap the device, powering the
internal circuitry and external loads from the output
SMPS voltages, rather than through linear regulators
from the battery. Bootstrapping reduces power dissipa-
tion due to gate charge and quiescent losses by pro-
viding power from a 90%-efficient switch-mode source,
rather than from a much-less-efficient linear regulator.
The output current limit increases to 200mA when the
LDO_ outputs are switched over.
System Enable/Shutdown (SHDN)
Drive SHDN below the precise SHDN input falling-edge
trip level to place the MAX1533A/MAX1537A in their
low-power shutdown state. The MAX1533A/MAX1537A
consume only 5µA of quiescent current while in shut-
down mode. When shutdown mode activates, the refer-
ence turns off, making the threshold to exit shutdown
less accurate. To guarantee startup, drive SHDN above
2.2V (SHDN input rising-edge trip level). For automatic
shutdown and startup, connect SHDN to V . The accu-
IN
rate 1V falling-edge threshold on SHDN can be used to
detect a specific input-voltage level and shut the
device down. Once in shutdown, the 1.6V rising-edge
threshold activates, providing sufficient hysteresis for
most applications.
SMPS Detailed
Description
SMPS 5V Bias Supply (LDO5 and V
)
CC
SMPS POR, UVLO, and Soft-Start
The A switch-mode power supplies (SMPS) require a
5V bias supply in addition to the high-power input sup-
ply (battery or AC adapter). This 5V bias supply is gen-
erated by the MAX1533A/MAX1537As’ internal 5V linear
regulator (LDO5). This bootstrapped LDO allows the
MAX1533A/MAX1537A to power-up independently. The
gate-driver input supply is connected to the fixed 5V
linear-regulator output (LDO5). Therefore, the 5V LDO
Power-on reset (POR) occurs when V
rises above
CC
approximately 1V, resetting the undervoltage, overvolt-
age, and thermal-shutdown fault latches. The POR cir-
cuit also ensures that the low-side drivers are pulled
low if OVP is disabled (OVP = V ), or driven high if
CC
OVP is enabled (OVP = GND) until the SMPS con-
trollers are activated.
The V
input undervoltage-lockout (UVLO) circuitry
CC
supply must provide V
(PWM controller) and the
CC
inhibits switching if the 5V bias supply (LDO5) is below
the 4V input UVLO threshold. Once the 5V bias supply
(LDO5) rises above this input UVLO threshold and the
controllers are enabled, the SMPS controllers start
switching and the output voltages begin to ramp up
using soft-start.
gate-drive power, so the maximum supply current
required is:
I
= I
+ f
(Q
+ Q
)
BIAS
CC
SW
G(LOW)
G(HIGH)
= 5mA to 50mA (typ)
where I
and Q
is 1mA (typ), f
is the switching frequency,
CC
G(LOW)
SW
The internal digital soft-start gradually increases the
internal current-limit level during startup to reduce the
input surge currents. The MAX1533A/MAX1537A divide
the soft-start period into five phases. During the first
phase, each controller limits its current limit to only 20%
of its full current limit. If the output does not reach regu-
and Q
are the MOSFET data
G(HIGH)
sheet’s total gate-charge specification limits at V = 5V.
GS
Reference (REF)
The 2V reference is accurate to 1% over temperature
and load, making REF useful as a precision system ref-
erence. Bypass REF to GND with a 0.22µF or greater
ceramic capacitor. The reference sources up to 100µA
and sinks 10µA to support external loads. If highly
accurate specifications ( 0.5%) are required for the
main SMPS output voltages, the reference should not
be loaded. Loading the reference reduces the LDO5,
LDO3, OUT5, and OUT3 output voltages slightly
because of the reference load-regulation error.
lation within 128 clock cycles (1 / f ), soft-start enters
OSC
the second phase and the current limit is increased by
another 20%. This process repeats until the maximum
current limit is reached after 512 clock cycles (1 / f
)
OSC
or when the output reaches the nominal regulation volt-
age, whichever occurs first (see the startup waveforms
in the Typical Operating Characteristics).
18 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
LDO3
SHDN
FSEL
IN
5V LINEAR
REGULATOR
3.3V LINEAR
REGULATOR
LDO5
LDO BYPASS
CIRCUITRY
LDO BYPASS
CIRCUITRY
OSC
SKIP
ILIM5
CSH5
ILIM3
CSH3
CSL5
BST5
CSL3
BST3
PWM5
CONTROLLER
(FIGURE 3)
DH5
LX5
PWM3
CONTROLLER
(FIGURE 3)
DH3
LX3
LDO5
LDO5
DL5
DL3
PGND
FB DECODE
(FIGURE 5)
FB5
FB
DECODE
(FIGURE 5)
FB3
INTERNAL
FB
ON5
ON3
REF
R
V
CC
2.0V
REF
GND
R
OVP
UVP
POWER-GOOD AND
FAULT PROTECTION
(FIGURE 7)
MAX1537A
AUXILIARY
LINEAR
REGULATOR
(FIGURE 8)
INA
PGDLY
PGOOD
LDOA
ADJA
ONA
MAX1533A/MAX1537A
Figure 2. MAX1533A/MAX1537A Functional Diagram
______________________________________________________________________________________ 19
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Table 3. Operating Modes
INPUTS*
ON5
OUTPUTS
5V SMPS
MODE
SHDN
LOW
ON3
X
LDO5
OFF
ON
LDO3
OFF
ON
3V SMPS
OFF
Shutdown Mode
Standby Mode
X
OFF
OFF
ON
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
HIGH
LOW
OFF
Normal Operation
3.3V SMPS Active
5V SMPS Active
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
OFF
ON
Normal Operation
(Delayed 5V SMPS
Startup)
Power-up after
3.3V SMPS is in
regulation
HIGH
HIGH
REF
HIGH
REF
ON
ON
ON
ON
ON
ON
Normal Operation
(Delayed 3.3V
SMPS Startup)
Power-up after
5V SMPS is in
regulation
HIGH
ON
*SHDN is an accurate, low-voltage logic input with 1V falling-edge threshold voltage and 1.6V rising-edge threshold voltage. ON3
and ON5 are 3-level CMOS logic inputs, a logic-low voltage is less than 0.8V, a logic-high voltage is greater than 2.4V, and the mid-
dle logic level is between 1.9V and 2.1V (see the Electrical Characteristics table).
0.3V, its low-side driver (DL_) is forced high, clamping
the respective SMPS output to GND. The reference
remains active to provide an accurate threshold and to
provide overvoltage protection. Both SMPS controllers
contain separate soft-shutdown circuits.
SMPS Enable Controls (ON3, ON5)
ON3 and ON5 control SMPS power-up sequencing.
ON3 or ON5 rising above 2.4V enables the respective
outputs. ON3 or ON5 falling below 1.6V disables the
respective outputs. Driving ON_ below 0.8V clears the
overvoltage, undervoltage, and thermal fault latches.
When output discharge is disabled (OVP = V ), the low-
CC
side drivers (DL_) and high-side drivers (DH_) are both
pulled low, forcing LX into a high-impedance state. Since
the outputs are not actively discharged by the SMPS con-
trollers, the output-voltage discharge rate is determined
only by the output capacitance and load current.
SMPS Power-Up Sequencing
Connecting ON3 or ON5 to REF forces the respective
outputs off while the other output is below regulation
and starts after that output regulates. The second SMPS
remains on until the first SMPS turns off, the device
shuts down, a fault occurs, or LDO5 goes into undervolt-
age lockout. Both supplies begin their power-down
sequence immediately when the first supply turns off.
Fixed-Frequency, Current-Mode
PWM Controller
The heart of each current-mode PWM controller is a multi-
input, open-loop comparator that sums two signals: the
output-voltage error signal with respect to the reference
voltage and the slope-compensation ramp (Figure 3).
The MAX1533A/MAX1537A use a direct-summing con-
figuration, approaching ideal cycle-to-cycle control over
the output voltage without a traditional error amplifier and
the phase shift associated with it. The MAX1533A/
MAX1537A use a relatively low loop gain, allowing the
use of low-cost output capacitors. The low loop gain
results in the -0.1% typical load-regulation error and
helps reduce the output capacitor size and cost by
shifting the unity-gain crossover frequency to a lower
level.
Output Discharge (Soft-Shutdown)
When output discharge is enabled (OVP pulled low)
and the switching regulators are disabled—by transi-
tions into standby or shutdown mode, or when an
output undervoltage fault occurs—the controller dis-
charges both outputs through internal 12Ω switches,
until the output voltages decrease to 0.3V. This slowly
discharges the output capacitance, providing a soft-
damped shutdown response. This eliminates the slight-
ly negative output voltages caused by quickly
discharging the output through the inductor and low-
side MOSFET. When an SMPS output discharges to
20 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
FROM FB
CSH
CSL
(SEE FIGURE 5)
REF / 2
SLOPE COMP
AGND
0.2 x V
LIMIT
R
S
Q
IDLE-
MODE
DH DRIVER
CURRENT
SKIP
SOFT-START
COUNTER
CURRENT
LIMIT
DAC
ON
OSC
-1.2 x V
LIMIT
S
R
Q
DL DRIVER
LX
PGND
MAX1537A ONLY
0.8V
ONE-SHOT
SECONDARY
FEEDBACK
Figure 3: PWM-Controller Functional Diagram
______________________________________________________________________________________ 21
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Idle-Mode Current-Sense Threshold
The on-time of the step-down controller terminates
when the output voltage exceeds the feedback thresh-
old and when the current-sense voltage exceeds the
idle-mode current-sense threshold. Under light-load
conditions, the on-time duration depends solely on the
idle-mode current-sense threshold, which is approxi-
mately 20% of the full-load current-limit threshold set by
ILIM_. This forces the controller to source a minimum
amount of power with each cycle. To avoid overcharg-
ing the output, another on-time cannot begin until the
output voltage drops below the feedback threshold.
Since the zero-crossing comparator prevents the
switching regulator from sinking current, the controller
must skip pulses. Therefore, the controller regulates the
valley of the output ripple under light-load conditions.
Frequency Selection (FSEL)
The FSEL input selects the PWM-mode switching fre-
quency. Table 4 shows the switching frequency based
on FSEL connection. High-frequency (500kHz) operation
optimizes the application for the smallest component
size, trading off efficiency due to higher switching losses.
This may be acceptable in ultra-portable devices where
the load currents are lower. Low-frequency (200kHz)
operation offers the best overall efficiency at the expense
of component size and board space.
Forced-PWM Mode
The low-noise forced-PWM mode disables the zero-
crossing comparator, which controls the low-side switch
on-time. This forces the low-side gate-drive waveform to
constantly be the complement of the high-side gate-
drive waveform, so the inductor current reverses at light
Automatic Pulse-Skipping Crossover
In skip mode, an inherent automatic switchover to PFM
takes place at light loads (Figure 4). This switchover is
affected by a comparator that truncates the low-side
switch on-time at the inductor current’s zero crossing.
The zero-crossing comparator senses the inductor cur-
rent across the low-side MOSFET (PGND to LX_). Once
loads while DH_ maintains a duty factor of V
/ V .
IN
OUT
The benefit of forced-PWM mode is to keep the switch-
ing frequency fairly constant. However, forced-PWM
operation comes at a cost: the no-load 5V supply current
remains between 15mA and 50mA, depending on the
external MOSFETs and switching frequency.
Forced-PWM mode is most useful for avoiding audio-
frequency noise and improving load-transient
response. Since forced-PWM operation disables the
zero-crossing comparator, the inductor current revers-
es under light loads.
V
- V _ drops below the 3mV zero-crossing cur-
LX
PGND
rent-sense threshold, the comparator forces DL_ low
(Figure 3). This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between con-
tinuous and discontinuous inductor-current operation
(also known as the “critical conduction” point). The
load-current level at which PFM/PWM crossover
Light-Load Operation Control (SKIP)
The MAX1533A/MAX1537A include a light-load operat-
ing-mode control input (SKIP) used to independently
enable or disable the zero-crossing comparator for
both controllers. When the zero-crossing comparator is
enabled, the controller forces DL_ low when the cur-
rent-sense inputs detect zero inductor current. This
keeps the inductor from discharging the output capaci-
tors and forces the controller to skip pulses under light-
load conditions to avoid overcharging the output. When
the zero-crossing comparator is disabled, the controller
is forced to maintain PWM operation under light-load
conditions (forced-PWM).
occurs, I , is given by:
LOAD(SKIP)
V
(V − V )
OUT IN OUT
I
=
LOAD(SKIP)
2 × V × f
× L
IN
SW
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
Table 4. FSEL Configuration Table
FSEL
SWITCHING FREQUENCY
V
500kHz
300kHz
200kHz
CC
REF
GND
22 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
TO ERROR
AMPLIFIER
ADJUSTABLE
OUTPUT
FB
REF
(2.0V)
I
L
IDLE
t
≥
ON(SKIP)
V
IN
- V
OUT
12R
R
I
LOAD(SKIP)
FIXED OUTPUT
FB = GND
CSL
0
TIME
ON-TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
Figure 5. Dual-Mode Feedback Decoder
Output Voltage
⎛
⎜
⎞
f
1
SW
DC output accuracy specifications in the Electrical
Characteristics table refer to the error-comparator’s
threshold. When the inductor continuously conducts,
the MAX1533A/MAX1537A regulate the peak of the out-
put ripple, so the actual DC output voltage is lower than
the slope-compensated trip level by 50% of the output
ripple voltage. For PWM operation (continuous conduc-
tion), the output voltage is accurately defined by the fol-
lowing equation:
V
= V
+
I
× ESR
OUT(PFM)
NOM
IDLE
⎟
2 f
⎝
⎠
OSC
where V
is the nominal output voltage, f
is the
NOM
OSC
maximum switching frequency set by the internal oscil-
lator, f
is the actual switching frequency, and I
is
SW
IDLE
the idle-mode inductor current when pulse skipping.
Adjustable/Fixed Output Voltages
(Dual-Mode Feedback)
Connect FB3 and FB5 to GND to enable the fixed
SMPS output voltages (3.3V and 5V, respectively), set
by a preset, internal resistive voltage-divider connected
between CSL_ and analog ground. Connect a resistive
voltage-divider at FB_ between CSL_ and GND to
adjust the respective output voltage between 1V and
5.5V (Figure 5). Choose R2 (resistance from FB to
GND) to be about 10kΩ and solve for R1 (resistance
from OUT to FB) using the equation:
⎛
⎞
A
V
V
RIPPLE
⎛
⎞
SLOPE NOM
V
= V
1 -
-
⎜
⎝
⎟
⎠
OUT(PWM)
NOM
⎜
⎟
V
2
⎝
⎠
IN
where V
is the nominal output voltage, A
SLOPE
NOM
equals 1%, and V
is the output ripple voltage
RIPPLE
(V
= ESR x ΔI
as described in the
RIPPLE
INDUCTOR
Output Capacitor Selection section).
In discontinuous conduction (I
< I
), the
LOAD(SKIP)
OUT
MAX1533A/MAX1537A regulate the valley of the output
ripple, so the output voltage has a DC regulation level
higher than the error-comparator threshold. For PFM
operation (discontinuous conduction), the output volt-
age is approximately defined by the following equation:
⎛
⎞
V
OUT_
R1 = R2
− 1
⎜
⎟
V
⎝
⎠
FB _
where V
= 1V nominal.
FB_
______________________________________________________________________________________ 23
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
When adjusting both output voltages, set the 3.3V
SMPS lower than the 5V SMPS. LDO5 connects to the
5V output (CSL5) through an internal switch only when
CSL5 is above the LDO5 bootstrap threshold (4.56V).
Similarly, LDO3 connects to the 3.3V output (CSL3)
through an internal switch only when CSL3 is above the
LDO3 bootstrap threshold (2.91V). Bootstrapping works
most effectively when the fixed output voltages are
used. Once LDO_ is bootstrapped from CSL_, the inter-
nal linear regulator turns off. This reduces internal
power dissipation and improves efficiency at higher
input voltage.
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V
-
IN
V
differential exists. The high-side gate drivers
OUT
(DH_) source and sink 2A, and the low-side gate dri-
vers (DL_) source 1.7A and sink 3.3A. This ensures
robust gate drive for high-current applications. The
DH_ floating high-side MOSFET drivers are powered by
diode-capacitor charge pumps at BST_ (Figure 6) while
the DL_ synchronous-rectifier drivers are powered
directly by the fixed 5V linear regulator (LDO5).
Current-Limit Protection (ILIM_)
The current-limit circuit uses differential current-sense
inputs (CSH_ and CSL_) to limit the peak inductor cur-
rent. If the magnitude of the current-sense signal
exceeds the current-limit threshold, the PWM controller
turns off the high-side MOSFET (Figure 3). At the next
rising edge of the internal oscillator, the PWM controller
does not initiate a new cycle unless the current-sense
signal drops below the current-limit threshold. The
actual maximum load current is less than the peak cur-
rent-limit threshold by an amount equal to half of the
inductor ripple current. Therefore, the maximum load
capability is a function of the current-sense resistance,
inductor value, switching frequency, and duty cycle
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL_ and DH_ drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly;
otherwise, the sense circuitry in the MAX1533A/
MAX1537A interprets the MOSFET gates as “off” while
charge actually remains. Use very short, wide traces (50
to 100 mils wide if the MOSFET is 1 inch from the driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω (typ) on-resistance. This helps pre-
vent DL_ from being pulled up due to capacitive cou-
pling from the drain to the gate of the low-side
MOSFETs when the inductor node (LX_) quickly switch-
(V
/ V ).
IN
OUT
In forced-PWM mode, the MAX1533A/MAX1537A also
implement a negative current limit to prevent excessive
reverse inductor currents when V
is sinking current.
OUT
es from ground to V . Applications with high input volt-
IN
The negative current-limit threshold is set to approxi-
mately 120% of the positive current limit and tracks the
positive current limit when ILIM_ is adjusted.
ages and long inductive driver traces may require
additional gate-to-source capacitance to ensure fast-
rising LX_ edges do not pull up the low-side MOSFETs’
gate, causing shoot-through currents. The capacitive
coupling between LX_ and DL_ created by the
Connect ILIM_ to V
for the 75mV default threshold, or
CC
adjust the current-limit threshold with an external resis-
tor-divider at ILIM_. Use a 2µA to 20µA divider current
for accuracy and noise immunity. The current-limit
threshold adjustment range is from 50mV to 200mV. In
the adjustable mode, the current-limit threshold voltage
equals precisely 1/10th the voltage seen at ILIM_. The
logic threshold for switchover to the 75mV default value
MOSFET’s gate-to-drain capacitance (C
), gate-to-
RSS
source capacitance (C
- C
), and additional
ISS
RSS
board parasitics should not exceed the following
minimum threshold:
⎛
⎞
C
C
RSS
V
> V
IN
is approximately V
- 1V.
GS(TH)
CC
⎜
⎟
⎝
⎠
ISS
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the dif-
ferential current-sense signals seen by CSH_ and
CSL_. Place the IC close to the sense resistor with
short, direct traces, making a Kelvin-sense connection
to the current-sense resistor.
Lot-to-lot variation of the threshold voltage may cause
problems in marginal designs. Alternatively, adding a
resistor less than 10Ω in series with BST_ may remedy
the problem by increasing the turn-on time of the high-
side MOSFET without degrading the turn-off time
(Figure 6).
24 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Power-Good Output (PGOOD)
PGOOD is the open-drain output of a comparator that
continuously monitors both SMPS output voltages for
C
BYP
undervoltage conditions. PGOOD is actively held low in
shutdown (SHDN or ON3 or ON5 = GND), soft-start,
and soft-shutdown. Once the digital soft-start termi-
nates, PGOOD becomes high impedance as long as
both outputs are above 90% of the nominal regulation
voltage set by FB_. PGOOD goes low once either
SMPS output drops 10% below its nominal regulation
point, an output overvoltage fault occurs, or either
SMPS controller is shut down. For a logic-level PGOOD
output voltage, connect an external pullup resistor
LDO5
BST
MAX1533A
MAX1537A
D
BST
(R )*
BST
INPUT (V )
IN
C
BST
DH
LX
N
H
L
between PGOOD and V . A 100kΩ pullup resistor
CC
LDO5
works well in most applications.
DL
N
L
PGOOD is independent of the fault protection states
OVP and UVP.
(C )*
NL
GND
Fault Protection
Output Overvoltage Protection (OVP)
If the output voltage of either SMPS rises above 111%
of its nominal regulation voltage and the OVP protection
is enabled (OVP = GND), the controller sets the fault
latch, pulls PGOOD low, shuts down both SMPS con-
trollers, and immediately pulls DH_ low and forces DL_
(R )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
BST
THE SWITCHING-NODE RISE TIME.
(C )* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
NL
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 6. Optional Gate-Driver Circuitry
FAULT
PROTECTION
POWER-GOOD
0.9 x
INT REF_
0.7 x
INT REF_
1.11 x
INT REF_
INTERNAL FB
ENABLE OVP
ENABLE UVP
BLANK
(POWER-UP)
FAULT
LATCH
FAULT
TIMER
POR
POWER-
GOOD
Figure 7. Power-Good and Fault Protection
______________________________________________________________________________________ 25
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
high. This turns on the synchronous-rectifier MOSFETs
with 100% duty, rapidly discharging the output capaci-
tors and clamping both outputs to ground. However,
immediately latching DL_ high typically causes slightly
negative output voltages due to the energy stored in
the output LC at the instant the OVP occurs. If the load
cannot tolerate a negative voltage, place a power
Schottky diode across the output to act as a reverse-
polarity clamp. If the condition that caused the overvolt-
age persists (such as a shorted high-side MOSFET),
Output Undervoltage Protection (UVP)
Each SMPS controller includes an output UVP protec-
tion circuit that begins to monitor the output 6144 clock
cycles (1 / f
) after that output is enabled (ON_
OSC
pulled high). If either SMPS output voltage drops below
70% of its nominal regulation voltage and the UVP pro-
tection is enabled (UVP = GND), the UVP circuit sets
the fault latch, pulls PGOOD low, and shuts down both
controllers using discharge mode (see the Output
Discharge (Soft-Shutdown) section). When an SMPS
output voltage drops to 0.3V, its synchronous rectifier
turns on, clamping the discharged output to GND.
the battery fuse blows. Cycle V
below 1V or toggle
CC
either ON3, ON5, or SHDN to clear the fault latch and
restart the SMPS controllers.
Cycle V
below 1V or toggle either ON3, ON5, or
CC
SHDN to clear the fault latch and restart the SMPS
Connect OVP to V
to disable the output overvoltage
CC
controllers.
protection.
Connect UVP to V
to disable the output undervoltage
CC
protection.
Table 5. Operating Modes Truth Table
MODE
Power-Up
Run
CONDITION
COMMENTS
Transitions to discharge mode after V POR and after REF
IN
becomes valid. LDO5, LDO3, REF remain active. DL_ is active
LDO5 < UVLO threshold.
if OVP is low.
SHDN = high, ON3 or ON5 enabled.
Normal operation.
Output Overvoltage
Protection (OVP)
Either output > 111% of nominal level,
OVP = low.
Exited by POR or cycling SHDN, ON3, or ON5.
Either output < 70% of nominal level, UVP
Output Undervoltage
Protection (UVP)
Exited by POR or cycling SHDN, ON3, or ON5. If OVP is not
high, DL3 and DL5 go high after discharge.
is enabled 6144 clock cycles (1 / f
)
OSC
after the output is enabled and UVP = low.
Discharge switch (10Ω) connects CSL_ to PGND. This is a
temporary state entered when LDO5 is undervoltage or on the
way to output UVLO, standby, shutdown, or thermal-shutdown
states. One SMPS can be in discharge mode while the other is
in run mode. If both outputs are discharged to 0.3V (on CSL_),
discharge mode transitions to the appropriate state.
OVP is low and either SMPS output is still
high in either standby mode or shutdown
mode.
Discharge
ON5 and ON3 < startup threshold,
SHDN = high.
Standby
Shutdown
DL_ stays high if OVP is low. LDO3, LDO5 active.
SHDN = low.
All circuitry off.
Exited by POR or cycling SHDN, ON3, or ON5.
If OVP is not high, DL3 and DL5 go high before LDO5 turns off.
Thermal Shutdown
T > +160°C.
J
Excessive current on LDO3 or LDO5
switchover transistors.
Exited by POR or cycling SHDN, ON3, or ON5.
If OVP is not high, DL3 and DL5 go high before LDO5 turns off.
Switchover Fault
26 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Thermal Fault Protection
The MAX1533A/MAX1537A feature a thermal fault-pro-
tection circuit. When the junction temperature rises
SECONDARY
FEEDBACK
above +160°C, a thermal sensor activates the fault
latch, pulls PGOOD low, and shuts down both SMPS
controllers using discharge mode (see the Output
Discharge (Soft-Shutdown) section). When an SMPS
INA
LDOA
output voltage drops to 0.3V, its synchronous rectifier
turns on, clamping the discharged output to GND.
Cycle V
below 1V or toggle either ON3, ON5, or
CC
SHDN to clear the fault latch and restart the controllers
after the junction temperature cools by 15°C.
FIXED 12V
5R
ONA
Auxiliary LDO Detailed
Description (MAX1537A Only)
REF (2.0V)
The MAX1537A includes an auxiliary linear regulator
that delivers up to 150mA of load current. The output
(LDOA) can be preset to 12V, ideal for PCMCIA power
requirements, and for biasing the gates of load switch-
es in a portable device. In adjustable mode, LDOA can
be set to anywhere from 5V to 23V. The auxiliary regu-
lator has an independent ON/OFF control, allowing it to
be shut down when not needed, reducing power con-
sumption when the system is in a low-power state.
R
ADJA
0.15V
A flyback-winding control loop regulates a secondary
winding output, improving cross-regulation when the pri-
mary output is lightly loaded or when there is a low
Figure 8. Linear-Regulator Functional Diagram
input-output differential voltage. If V
- V
falls
LDOA
INA
100kΩ and solve for R1 (resistance from LDOA to
ADJA) using the following equation:
below 0.8V, the low-side switch is turned on for a time
equal to 33% of the switching period. This reverses the
inductor (primary) current, pulling current from the out-
put filter capacitor and causing the flyback transformer
to operate in forward mode. The low impedance pre-
sented by the transformer secondary in forward mode
dumps current into the secondary output, charging up
⎛
⎞
V
LDOA
R1 = R2
- 1
⎜
⎟
V
⎝
⎠
ADJA
where V
= 2V nominal.
ADJA
the secondary capacitor and bringing V
- V
LDOA
INA
Design Procedure
back into regulation. The secondary feedback loop does
not improve secondary output accuracy in normal fly-
back mode, where the main (primary) output is heavily
loaded. In this condition, secondary output accuracy is
determined by the secondary rectifier drop, transformer
turns ratio, and accuracy of the main output voltage.
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
Adjustable LDOA Voltage
(Dual-Mode Feedback)
Connect ADJA to GND to enable the fixed, preset 12V
auxiliary output. Connect a resistive voltage-divider at
ADJA between LDOA and GND to adjust the respective
output voltage between 5V and 23V (Figure 8). Choose
R2 (resistance from ADJA to GND) to be approximately
• Input Voltage Range. The maximum value
(V
) must accommodate the worst-case, high
IN(MAX)
AC-adapter voltage. The minimum value (V
)
IN(MIN)
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery-selector
switches. If there is a choice at all, lower input volt-
ages result in better efficiency.
______________________________________________________________________________________ 27
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
• Maximum Load Current. There are two values to
consider. The peak load current (I ) deter-
look for nonstandard values, which can provide a better
compromise in LIR across the input voltage range. If
using a swinging inductor (where the no-load induc-
tance decreases linearly with increasing current), evalu-
ate the LIR with properly scaled inductance values. For
the selected inductance value, the actual peak-to-peak
LOAD(MAX)
mines the instantaneous component stresses and fil-
tering requirements and thus drives output-capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load cur-
rent (I
) determines the thermal stresses and
inductor ripple current (ΔI
) is defined by:
LOAD
INDUCTOR
thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents.
V
V
- V
)
(
OUT
IN
OUT
ΔI
=
INDUCTOR
V
f
L
IN OSC
• Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are
Ferrite cores are often the best choice, although pow-
dered iron is inexpensive and can work well at 200kHz.
The core must be large enough not to saturate at the
proportional to frequency and V 2. The optimum fre-
peak inductor current (I
):
IN
PEAK
quency is also a moving target, due to rapid improve-
ments in MOSFET technology that are making higher
frequencies more practical.
ΔI
INDUCTOR
I
=I
+
PEAK LOAD(MAX)
2
• Inductor Operating Point. This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher
output ripple due to increased ripple currents. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc-
tion (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction bene-
fit. The optimum operating point is usually found
between 20% and 50% ripple current. When pulse
skipping (SKIP low and light loads), the inductor
value also determines the load-current value at
which PFM/PWM switchover occurs.
Transformer Design
(For the MAX1537A Auxiliary Output)
A coupled inductor or transformer can be substituted
for the inductor in the 5V SMPS to create an auxiliary
output (Figure 1). The MAX1537A is particularly well
suited for such applications because the secondary
feedback threshold automatically triggers DL5 even if
the 5V output is lightly loaded.
The power requirements of the auxiliary supply must be
considered in the design of the main output. The trans-
former must be designed to deliver the required current
in both the primary and the secondary outputs with the
proper turns ratio and inductance. The power ratings of
the synchronous-rectifier MOSFETs and the current limit
in the MAX1537A must also be adjusted accordingly.
Extremes of low input-output differentials, widely different
output loading levels, and high turns ratios can further
complicate the design due to parasitic transformer para-
meters such as interwinding capacitance, secondary
resistance, and leakage inductance. Power from the
main and secondary outputs is combined to get an
equivalent current referred to the main output. Use this
total current to determine the current limit (see the
Setting the Current Limit section):
Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
V
V
- V
(
)
OUT
IN OUT
L =
V
f
I
LIR
IN OSC LOAD(MAX)
For example: I
OSC
= 5A, V = 12V, V
= 5V,
OUT
LOAD(MAX)
= 300kHz, 30% ripple current or LIR = 0.3.
IN
f
I
= P
/ V
LOAD(MAX)
TOTAL OUT5
5V × 12V- 5V
(
)
where PTOTAL is the sum of the main and secondary
outputs and ILOAD(MAX) is the maximum output cur-
rent used to determine the primary inductance (see the
Inductor Selection section).
L =
= 6.50μH
12V × 300kHz × 5A × 0.3
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Most
inductor manufacturers provide inductors in standard
values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also
28 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
The transformer turns ratio (N) is determined by:
where D
is the maximum duty factor (see the
MAX
Electrical Characteristics table), T is the switching period
(1 / f ), and ΔT equals V / V x T when in PWM
OSC
OUT
IN
OUT
V
+ V
FWD
SEC
mode, or L x 0.2 x I
/ (V - V
) when in skip
MAX
IN
N=
V
+ V
+ V
mode. The amount of overshoot during a full-load to no-
load transient due to stored inductor energy can be
calculated as:
OUT5
RECT SENSE
where V
is the minimum required rectified sec-
SEC
2
ondary voltage, V
is the forward drop across the
FWD
ΔI
L
(
)
LOAD(MAX)
secondary rectifier, V
of the main output voltage, and V
voltage drop across the synchronous-rectifier MOSFET.
The transformer secondary return is often connected to
the main output voltage instead of ground to reduce
the necessary turns ratio. In this case, subtract V
from the secondary voltage (V
is the minimum value
RECT
OUT5(MIN)
V
=
SOAR
is the on-state
2C
V
OUT OUT
Setting the Current Limit
OUT5
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The
peak inductor current occurs at I
the ripple current; therefore:
- V
) in the
OUT5
SEC
transformer turns-ratio equation above. The secondary
diode in coupled-inductor applications must withstand
flyback voltages greater than 60V. Common silicon rec-
tifiers, such as the 1N4001, are also prohibited
because they are too slow. Fast silicon rectifiers such
as the MURS120 are the only choice. The flyback volt-
plus half
LOAD(MAX)
ΔI
⎛
⎞
⎠
INDUCTOR
2
I
> I
+
⎜
⎝
⎟
LIMIT
LOAD(MAX)
age across the rectifier is related to the V - V
dif-
IN
OUT
ference, according to the transformer turns ratio:
= V + (V - V ) x N
V
FLYBACK
SEC
IN
OUT5
where I
equals the minimum current-limit threshold
LIMIT
where N is the transformer turns ratio (secondary wind-
ings/primary windings), and V is the maximum sec-
voltage divided by the current-sense resistance
(R ). For the default setting, the minimum current-
SEC
SENSE
ondary DC output voltage. If the secondary winding is
returned to V instead of ground, subtract V
limit threshold is 70mV.
OUT5
OUT5
Connect ILIM_ to V
for the default current-limit
CC
from V
in the equation above. The diode’s
FLYBACK
threshold. In adjustable mode, the current-limit thresh-
old is precisely 1/10th the voltage seen at ILIM_. For an
adjustable threshold, connect a resistive divider from
REF to analog ground (GND) with ILIM_ connected to
the center tap. The external 500mV to 2V adjustment
range corresponds to a 50mV to 200mV current-limit
threshold. When adjusting the current limit, use 1% tol-
erance resistors and a divider current of approximately
10µA to prevent significant inaccuracy in the current-
limit tolerance.
reverse-breakdown voltage rating must also accommo-
date any ringing due to leakage inductance. The
diode’s current rating should be at least twice the DC
load current on the secondary output.
Transient Response
The inductor ripple current also impacts transient-
response performance, especially at low V - V
dif-
OUT
IN
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The total output voltage sag is the sum of the voltage
sag while the inductor is ramping up, and the voltage
sag before the next pulse can occur.
The current-sense method (Figure 9) and magnitude
determine the achievable current-limit accuracy and
power loss. Typically, higher current-sense limits pro-
vide tighter accuracy, but also dissipate more power.
Most applications employ a current-limit threshold
(V ) of 50mV to 100mV, so the sense resistor can
LIMIT
be determined by:
2
L ΔI
(
)
LOAD(MAX)
V
=
+
SAG
2C
V
× D
- V
(
)
OUT
IN
MAX
OUT
R
= V
/ I
SENSE
LIMIT LIM
ΔI
T - ΔT
(
)
LOAD(MAX)
For the best current-sense accuracy and overcurrent
protection, use a 1% tolerance current-sense resistor
between the inductor and output as shown in Figure
C
OUT
______________________________________________________________________________________ 29
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
9a. This configuration constantly monitors the inductor
current, allowing accurate current-limit protection.
where R is the inductor’s series DC resistance. In this
L
configuration, the current-sense resistance equals the
inductor’s DC resistance (R
= R ). Use the worst-
L
SENSE
Alternatively, high-power applications that do not
require highly accurate current-limit protection may
reduce the overall power dissipation by connecting a
series RC circuit across the inductor (Figure 9b) with an
equivalent time constant:
case inductance and R values provided by the induc-
L
tor manufacturer, adding some margin for the
inductance drop over temperature and load.
Output Capacitor Selection
The output filter capacitor must have low enough equiv-
alent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements. The output capaci-
tance must be high enough to absorb the inductor
L
= C
× R
EQ
EQ
R
L
INPUT (V )
IN
C
D
IN
N
H
DH_
LX_
DL_
GND
R
SENSE
L
C
OUT
MAX1533A
MAX1537A
L
N
L
CSH_
CSL_
a) OUTPUT SERIES RESISTOR SENSING
INPUT (V )
IN
C
IN
N
H
INDUCTOR
DH_
LX_
C
OUT
DL_
MAX1533A
MAX1537A
D
L
N
L
R
EQ
C
EQ
GND
CSH_
CSL_
b) LOSSLESS INDUCTOR SENSING
Figure 9. Current-Sense Configurations
30 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
energy while transitioning from full-load to no-load con-
ditions without tripping the overvoltage fault protection.
When using high-capacitance, low-ESR capacitors (see
the Output-Capacitor Stability Considerations section),
the filter capacitor’s ESR dominates the output voltage
ripple. So the output capacitor’s size depends on the
maximum ESR required to meet the output voltage rip-
selection, the ESR needed to support 25mV
ripple is
P-P
25mV / 1.5A = 16.7mΩ. One 220µF/4V Sanyo polymer
(TPE) capacitor provides 15mΩ (max) ESR. This results
in a zero at 48kHz, well within the bounds of stability.
For low-input-voltage applications where the duty cycle
exceeds 50% (V
age should not be greater than twice the internal slope-
compensation voltage:
/ V ≥ 50%), the output ripple volt-
IN
OUT
ple (V
) specifications:
RIPPLE(P-P)
V
≤ 0.02 x V
RIPPLE
OUT
x R
V
= R
I
LIR
RIPPLE(P−P)
ESR LOAD(MAX)
where V
equals ΔI
. The worst-
ESR
RIPPLE
INDUCTOR
In idle mode, the inductor current becomes discontinu-
ous, with peak currents set by the idle-mode current-
sense threshold (V
no-load output ripple can be determined as follows:
case ESR limit occurs when V = 2 x V
, so the
OUT
IN
above equation can be simplified to provide the follow-
ing boundary condition:
= 0.2V
). In idle mode, the
LIMIT
IDLE
R
ESR
≤ 0.04 x L x f
OSC
Do not put high-value ceramic capacitors directly
across the feedback sense point without taking precau-
tions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
V
R
IDLE ESR
R
V
=
RIPPLE(P−P)
SENSE
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, polymers, and other electrolytics).
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
Unstable operation manifests itself in two related but
distinctly different ways: short/long pulses or cycle skip-
ping resulting in a lower switching frequency. Instability
occurs due to noise on the output or because the ESR
is so low that there is not enough voltage ramp in the
output voltage signal. This “fools” the error comparator
into triggering too early or skipping a cycle. Cycle skip-
ping is more annoying than harmful, resulting in nothing
worse than increased output ripple. However, it can
indicate the possible presence of loop instability due to
insufficient ESR. Loop instability can result in oscilla-
tions at the output after line or load steps. Such pertur-
bations are usually damped, but can cause the output
voltage to rise above or fall below the tolerance limits.
capacity needed to prevent V
and V
from
SOAR
SAG
causing problems during load transients. Generally,
once enough capacitance is added to meet the over-
shoot requirement, undershoot at the rising load edge
is no longer a problem (see the V
and V
equa-
SOAR
SAG
tions in the Transient Response section). However, low-
capacity filter capacitors typically have high-ESR zeros
that may affect the overall stability (see the Output-
Capacitor Stability Considerations).
Output-Capacitor Stability Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The boundary of insta-
bility is given by the following equation:
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output-voltage-ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC-current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
f
OSC
π
f
≤
ESR
1
where f
=
ESR
Input Capacitor Selection
2π R
C
ESR OUT
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents.
RMS
For a typical 300kHz application, the ESR zero frequency
must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use at
the time of publication have typical ESR zero frequen-
cies of 25kHz. In the design example used for inductor
For an out-of-phase regulator, the total RMS current in
the input capacitor is a function of the load currents, the
input currents, the duty cycles, and the amount of over-
lap as defined in Figure 10.
______________________________________________________________________________________ 31
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
The 40/60 optimal interleaved architecture of the
MAX1533A/MAX1537A allows the input voltage to go
as low as 8.3V before the duty cycles begin to overlap.
V
and V
. Ideally, the losses at V
IN(MAX) IN(MIN)
IN(MIN)
should be roughly equal to the losses at V
, with
IN(MAX)
IN(MIN)
lower losses in between. If the losses at V
are
significantly higher, consider increasing the size of N .
H
This offers improved efficiency over a regular 180° out-
of-phase architecture where the duty cycles begin to
overlap below 10V. Figure 10 shows the input-capacitor
RMS current vs. input voltage for an application that
requires 5V/5A and 3.3V/5A. This shows the improve-
ment of the 40/60 optimal interleaving over 50/50 inter-
leaving and in-phase operation.
Conversely, if the losses at V
are significantly
IN(MAX)
higher, consider reducing the size of N . If V does
H
IN
not vary over a wide range, maximum efficiency is
achieved by selecting a high-side MOSFET (N ) that
H
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (N ) that has the lowest
possible on-resistance (R
L
), comes in a moder-
DS(ON)
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to power-up surge currents typical of sys-
tems with a mechanical switch or connector in series
with the input. Choose a capacitor that has less than
10°C temperature rise at the RMS input current for opti-
mal reliability and lifetime.
ate-sized package (i.e., SO-8, DPAK, or D2PAK), and is
reasonably priced. Ensure that the MAX1533A/
MAX1537A DL_ gate driver can supply sufficient cur-
rent to support the gate charge and the current injected
into the parasitic drain-to-gate capacitor caused by the
high-side MOSFET turning on; otherwise, cross-
conduction problems may occur. Switching losses are
not an issue for the low-side MOSFET since it is a zero-
voltage switched device when used in the step-down
topology.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N ), the worst-
H
case power dissipation due to resistance occurs at
minimum input voltage:
The high-side MOSFET (N ) must be able to dissipate
H
the resistive losses plus the switching losses at both
INPUT CAPACITOR RMS CURRENT
vs. INPUT VOLTAGE
5.0
⎛
⎞
V
V
2
OUT
PD (N Resistive) =
I
(
R
DS(ON)
)
H
LOAD
⎜
⎟
4.5
⎝
⎠
IN
4.0
IN PHASE
3.5
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
DS(ON)
3.0
2.5
2.0
1.5
1.0
0.5
0
50/50 INTERLEAVING
R
required to stay within package power-dissi-
pation limits often limits how small the MOSFET can be.
The optimum occurs when the switching losses equal
the conduction (R
) losses. High-side switching
DS(ON)
40/60 OPTIMAL
INTERLEAVING
losses do not become an issue until the input is greater
than approximately 15V.
5V/5A AND 3.3V/5A
Calculating the power dissipation in high-side
MOSFETs (N ) due to switching losses is difficult, since
H
6
8
10
12
V
14
(V)
16
18
20
it must allow for difficult-to-quantify factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board
layout characteristics. The following switching loss cal-
culation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably includ-
IN
INPUT RMS CURRENT FOR INTERLEAVED OPERATION
I
=
RMS
2
2
(I
(I
- I
+ I
)
(D - D ) + (I
- I
)
(D - D ) +
OUT5 IN
LX5
OL
OUT3 IN
LX3
OL
2
- I )2 D + I (1 - D - D + D
)
OL
OUT5 OUT3 IN
OL IN
LX5
LX3
V
V
V
OUT3
V
IN
OUT5
D
= DUTY-CYCLE OVERLAP FRACTION
OL
D
=
D
LX3
=
LX5
IN
INPUT RMS CURRENT FOR SINGLE-PHASE OPERATION
ing verification using a thermocouple mounted on N :
H
I
= I
V
(V - V
)
RMS LOAD
OUT IN
OUT
(
)
2
V
IN
V
C
I
f I
RSS SW LOAD
(
)
IN(MAX)
PD (N Switching) =
H
Figure 10. Input RMS Current
GATE
32 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
where C
and I
is the reverse transfer capacitance of N ,
H
RSS
Q
200mV
is the peak gate-drive source/sink current
GATE
GATE
(1A typ).
C
=
BST
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC-adapter voltages
are applied, due to the squared term in the switching-
loss equation (C x V 2 x f ). If the high-side MOSFET
where Q
is the total gate charge specified in the
GATE
high-side MOSFET’s data sheet. For example, assume
the FDS6612A n-channel MOSFET is used on the high
side. According to the manufacturer’s data sheet, a sin-
gle FDS6612A has a maximum gate charge of 13nC
IN
SW
chosen for adequate R
at low battery voltages
DS(ON)
becomes extraordinarily hot when subjected to
(V
= 5V). Using the above equation, the required
V
, consider choosing another MOSFET with
GS
IN(MAX)
lower parasitic capacitance.
boost capacitance is:
For the low-side MOSFET (N ), the worst-case power
L
dissipation always occurs at maximum battery voltage:
13nC
200mV
C
=
= 0.065μF
BST
⎡
⎤
⎥
⎛
⎞
V
2
OUT
⎢
Selecting the closest standard value. This example
requires a 0.1µF ceramic capacitor.
PD (N Resistive) = 1 -
I
(
R
DS(ON)
)
⎜
⎟
L
LOAD
V
⎢
⎣
⎥
⎦
IN(MAX)
⎝
⎠
Applications Information
The absolute worst case for MOSFET power dissipation
occurs under heavy-overload conditions that are
Duty-Cycle Limits
greater than I
but are not high enough to
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by the maximum duty-cycle specification
(see the Electrical Characteristics table). However,
keep in mind that the transient performance gets worse
as the step-down regulators approach the dropout volt-
age, so bulk output capacitance must be added (see
the voltage sag and soar equations in the Design
Procedure section). The absolute point of dropout
occurs when the inductor current ramps down during
LOAD(MAX)
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the cir-
cuit to tolerate:
ΔI
⎛
⎞
INDUCTOR
I
= I
-
⎜
⎝
⎟
⎠
LOAD
LIMIT
2
where I
is the peak current allowed by the current-
LIMIT
limit circuit, including threshold tolerance and sense-
resistance variation. The MOSFETs must have a
relatively large heatsink to handle the overload power
dissipation.
the off-time (ΔI
) as much as it ramps up during
DOWN
the on-time (ΔI ). This results in a minimum operating
UP
voltage defined by the following equation:
Choose a Schottky diode (D ) with a forward-voltage
L
⎛
⎞
1
V
= V
+ V
+ h
- 1 V
+ V
(
)
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3rd the load current. This diode is optional
and can be removed if efficiency is not critical.
IN(MIN)
OUT
CHG
OUT DIS
⎜
⎟
D
⎝
⎠
MAX
where V
and V
are the parasitic voltage drops in
DIS
CHG
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
Boost Capacitors
) must be selected large
The boost capacitors (C
BST
Maximum Input Voltage
The MAX1533A/MAX1537A controllers include a mini-
mum on-time specification, which determines the maxi-
mum input operating voltage that maintains the
selected switching frequency (see the Electrical
Characteristics table). Operation above this maximum
input voltage results in pulse-skipping operation,
regardless of the operating mode selected by SKIP. At
the beginning of each cycle, if the output voltage is still
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
______________________________________________________________________________________ 33
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
above the feedback-threshold voltage, the controller
does not trigger an on-time pulse, effectively skipping a
cycle. This allows the controller to maintain regulation
above the maximum input voltage, but forces the con-
troller to effectively operate with a lower switching fre-
quency. This results in an input threshold voltage at
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
which the controller begins to skip pulses (V
):
IN(SKIP)
• Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (REF,
FB_, CSH_, CSL_).
⎛
⎞
1
V
= V
OUT
⎜
⎟
IN(SKIP)
f
t
OSC ON(MIN)
⎝
⎠
Layout Procedure
where f
is the switching frequency selected by FSEL.
OSC
1) Place the power components first, with ground termi-
nals adjacent (N _ source, C , C
_, and D _
L
L
IN
OUT
PC Board Layout Guidelines
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 11). If possible, mount all of the power compo-
nents on the top side of the board, with their ground
terminals flush against one another. Follow these guide-
lines for good PC board layout:
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite N
L_
and N to keep LX_, GND, DH_, and the DL_ gate-
H_
drive lines short and wide. The DL_ and DH_ gate
traces must be short and wide (50 to 100 mils wide if
the MOSFET is 1 inch from the controller IC) to keep
the driver impedance low and for proper adaptive
dead-time sensing.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
3) Group the gate-drive components (BST_ diode and
capacitor, LDO5 bypass capacitor) together near
the controller IC.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance caus-
es a measurable efficiency penalty.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 11. This diagram can be
viewed as having two separate ground planes:
power ground, where all the high-power compo-
nents go; and an analog ground plane for sensitive
analog components. The analog ground plane and
power ground plane must meet only at a single point
directly at the IC.
• Minimize current-sensing errors by connecting CSH_
and CSL_ directly across the current-sense resistor
(R
).
SENSE_
5) Connect the output power planes directly to the out-
put-filter-capacitor positive and negative terminals
with multiple vias. Place the entire DC-DC converter
circuit as close to the load as is practical.
34 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
CONNECT GND AND PGND TO THE
CONTROLLER AT ONE POINT
ONLY AS SHOWN
CONNECT THE
EXPOSED PAD TO
ANALOG GND
VIA TO POWER
GROUND
VIA TO REF
BYPASS CAPACITOR
VIA TO REF PIN
VIA TO V
CC
BYPASS CAPACITOR
VIA TO V PIN
CC
MAX1533A
BOTTOM LAYER
MAX1533A
TOP LAYER
KELVIN-SENSE VIAS
UNDER THE SENSE
RESISTOR
(SEE THE EVALUATION KIT)
DUAL
n-CHANNEL
MOSFET
INDUCTOR
SINGLE
n-CHANNEL
MOSFETS
INDUCTOR
DH
LX
DL
COUT
COUT
INPUT
OUTPUT
COUT
OUTPUT
GROUND
INPUT
GROUND
HIGH-POWER LAYOUT
LOW-POWER LAYOUT
Figure 11. PC Board Layout
______________________________________________________________________________________ 35
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Pin Configurations (continued)
Chip Information
TRANSISTOR COUNT: 6890
PROCESS: BiCMOS
TOP VIEW
ADJA
ON5
1
2
3
4
5
6
7
8
9
27 CSL5
26 FB5
ON3
25 LDO5
24 DL5
23 PGND
22 DL3
21 LDO3
ONA
FSEL
ILIM3
ILIM5
REF
MAX1537A
FB3
20
GND
19 CSL3
THIN QFN
6mm x 6mm
36 ______________________________________________________________________________________
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 37
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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