MAX154ACWG-T [MAXIM]
Analog Circuit, 1 Func, CMOS, PDSO24, SOIC-24;
| 型号： | MAX154ACWG-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO24, SOIC-24 光电二极管 |
| 文件： | 总17页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0892; Rev 3; 12/96
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
4/MAX158
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ One-Chip Data Acquisition System
♦ Four or Eight Analog Input Channels
♦ 2.5µs per Channel Conversion Time
♦ Internal 2.5V Reference
The MAX154/MAX158 are high-speed multi-channel
analog-to-digital converters (ADCs). The MAX154 has
four analog input channels while the MAX158 has eight
channels. Conversion time for both devices is 2.5µs.
The MAX154/MAX158 also feature a 2.5V on-chip refer-
ence, forming a complete high-speed data acquisition
system.
♦ Built-In Track/Hold Function
1
♦ / LSB Error Specification
2
Both converters include a built-in track/hold, eliminating
the need for an external track/hold. The analog input
range is 0V to +5V, although the ADC operates from a
single +5V supply.
♦ Single +5V Supply Operation
♦ No External Clock
♦ New Space-Saving SSOP Package
Microprocessor interfaces are simplified by the ADC’s
ability to appear as a memory location or I/O port without
the need for external logic. The data outputs use latched,
three-state buffer circuitry to allow direct connection to a
microprocessor data bus or system input port.
______________Ord e rin g In fo rm a t io n
ERROR
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
24 Narrow
0°C to +70°C
1
MAX154ACNG
±
/
2
Plastic DIP
________________________Ap p lic a t io n s
Digital Signal Processing
24 Narrow
0°C to +70°C
MAX154BCNG
MAX154BC/D
±1
1
Plastic DIP
0°C to +70°C
Dice
±
/
/
2
High-Speed Data Acquisition
Telecommunications
1
±
MAX154ACWG 0°C to +70°C
MAX154BCWG 0°C to +70°C
24 Wide SO
24 Wide SO
24 SSOP
24 SSOP
2
±1
1
MAX154ACAG
MAX154BCAG
0°C to +70°C
0°C to +70°C
±
/
High-Speed Servo Control
2
±1
Audio Instrumentation
Ordering Information continued at end of data sheet.
__________________________________________________________P in Co n fig u ra t io n s
TOP VIEW
AIN6
AIN5
AIN4
AIN3
AIN7
AIN8
V
1
2
28
27
AIN4
AIN3
AIN2
AIN1
V
1
2
24 DD
3
26 DD
N.C.
23
A0
25
4
A0
22
3
MAX158
AIN2
AIN1
A1
5
24
A1
21
4
23 A2
6
MAX154
REF OUT
DB0
DB7
DB6
DB5
DB4
CS
5
20
19
18
17
16
15
14
13
REF OUT
DB0
DB7
7
22
6
21 DB6
8
DB1
7
DB1
DB2
DB3
RD
DB5
DB4
CS
9
20
19
18
17
DB2
8
10
11
12
13
14
DB3
RD
9
RDY
10
11
12
RDY
INT
V
REF
+
INT
V
+
16
15
REF
GND
V
REF
-
GND
V
-
REF
DIP/SO/SSOP
DIP/SO/SSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V to GND.........................................0V, +10V
Operating Temperature Ranges
DD
Voltage at Any Other Pins ........................GND -0.3V, V +0.3V
MAX15_ _C_ _.....................................................0°C to +70°C
MAX15_ _E_ _..................................................-40°C to +85°C
MAX15_ _M_ _ ...............................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
Output Current (REF OUT)..................................................30mA
Power Dissipation (any package) to +75°C ....................450mW
Derate above +25°C by ..............................................6mW/°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +5V, V
= +5V, V
= GND, Mode 0, T = T
A
to T , unless otherwise noted).
MAX
DD
REF+
REF-
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
8
Bits
4/MAX158
MAX15_A
MAX15_B
±1/2
±1
Total Unadjusted Error (Note 1)
LSB
No-Missing-Codes Resolution
Channel-to-Channel Mismatch
REFERENCE INPUT
8
Bits
±1/4
LSB
Reference Resistance
1
4
kΩ
V
V
+ Input Voltage Range
V
-
V
DD
REF
REF
V - Input Voltage Range
REF
GND
V +
REF
V
REFERENCE OUTPUT (Note 2)
Output Voltage
REF OUT
T
= +25°C
2.47
2.50
-6
2.53
-10
±3
V
A
Load Regulation
I = 0mA to 10mA, T = +25°C
L
mV
mV
A
Power-Supply Sensitivity
V
±5%, T = +25°C
±1
40
DD
A
MAX15_ _C
MAX15_ _E
MAX15_ _M
70
Temperature Drift (Note 3)
40
70
ppm/°C
60
100
Output Noise
e
200
µV/rms
µF
N
Capacitive Load
0.01
ANALOG INPUT
Analog Input Voltage Range
Analog Input Capacitance
Analog Input Current
A
V
REF
-
V
+
V
pF
INR
REF
C
45
AIN
I
Any channel, AIN = 0V to 5V
±3
µA
AIN
Slew Rate, Tracking
SR
0.7
0.157
V/µs
–—– –—–
LOGIC INPUTS (RD, CS, A0, A1, A2)
Input High Voltage
Input Low Voltage
V
2.4
V
V
INH
V
INL
0.8
1
Input High Current
Input Low Current
I
µA
µA
pF
INH
I
-1
8
INL
Input Capacitance (Note 4)
C
5
IN
2
_______________________________________________________________________________________
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
4/MAX158
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V, V
= +5V, V
= GND, MODE 0, T = T
A
to T , unless otherwise noted).
MAX
DD
REF+
REF-
MIN
PARAMETER
LOGIC OUTPUTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
DB0-DB7, INT; I
= -360µA
4.0
V
V
OH
OUT
I
= 1.6mA
= 2.6mA
0.4
0.4
±3
8
OUT
Output Low Voltage
V
OL
DB0-DB7, INT; RDY
DB0-DB7, RDY; V
I
OUT
Three-State Output Current
= 0V to V
µA
pF
OUT
DD
Output Capacitance (Note 4)
POWER-SUPPLY
Supply Voltage
C
5
OUT
V
DD
5V ±5% for specified performance
CS = RD = 2.4V
4.75
5.25
15
V
Supply Current
I
DD
mA
mW
LSB
Power Dissipation
25
75
Power-Supply Sensitivity
PSS
V
DD
= ±5%
±1/16
±1/4
Note 1: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 2: Specified with no external load unless otherwise noted.
Note 3: Temperature drift is defined as change in output voltage from +25°C to T
Note 4: Guaranteed by design.
or T
divided by (25 - T
) or (T - 25).
MAX
MIN
MAX
MIN
TIMING CHARACTERISTICS (Note 5)
(V = +5V, V
= +5V, V
= GND, MODE 0, T = T
to T , unless otherwise noted).
MAX
DD
REF+
REF-
A
MIN
T
= +25°C
MAX15_C/E
MAX15_M
MIN MAX
A
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN TYP MAX
MIN
MAX
CS to RD Setup Time
CS to RD Hold Time
t
0
0
0
0
0
0
ns
ns
CSS
t
CSH
Multiplexer Address
Setup Time
t
0
0
0
ns
ns
AS
Multiplexer Address
Hold Time
t
30
35
40
AH
CS to RDY Delay
t
C
= 50pF, R = 5kΩ
30
40
2.0
85
60
2.4
110
60
ns
µs
ns
RDY
L
L
Conversion Time (Mode 0)
Data Access Time After RD
t
1.6
2.8
CRD
t
(Note 6)
(Note 6)
120
ACC1
Data Access Time
After INT, Mode 0
t
20
40
50
60
70
ns
ACC2
RD to INT Delay (Mode 1)
Data Hold Time
t
C
= 50pF
L
75
60
100
70
100
70
ns
ns
INTH
t
(Note 7)
DH
Delay Time
Between Conversions
t
500
60
500
80
600
80
ns
ns
P
RD Pulse Width (Mode 1)
t
600
500
400
RD
Note 5: All input control signals are specified with t = t = 20ns (10% to 90% of +5V) and timed from a 1.6V voltage level.
R
F
Note 6: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
_______________________________________________________________________________________
3
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
OUTPUT CURRENT
vs. TEMPERATURE
ACCURACY
vs. DELAY BETWEEN CONVERSIONS (tp)
REFERENCE TEMPERATURE DRIFT
20
16
2.520
2.0
1.5
V
DD
= 5V
V
V
REF
= 5V
= 5V
DD
2.510
2.500
I
V
= 2.4V
SOURCE OUT
12
8
1.0
I
V
= 0.4V
SINK OUT
2.490
2.480
0.5
0
4
4/MAX158
0
-100
-50
0
50
100
150
-50
0
50
100
150
300 400 500
600 700
t (ns)
p
800 900
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
ACCURACY vs. V
POWER-SUPPLY CURRENT vs. TEMPERATURE
(NOT INCLUDING REFERENCE LADDER)
REF
[V = V (+) - V (-)]
REF
REF
REF
2.0
1.5
8
V
DD
= 5V
7
V
DD
= 5.25V
6
5
1.0
0.5
V
= 5V
DD
4
V
DD
= 4.75V
3
2
0
0
1
2
3
4
5
-100
-50
0
50
100
150
V
REF
(V)
AMBIENT TEMPERATURE (°C)
+5V
+5V
3k
3k
DBN
DBN
DBN
DBN
3k
10pF
3k
10pF
100pF
100pF
DGND
DGND
DGND
DGND
a. High-Z to V
b. High-Z to V
a. High-Z to V
b. High-Z to V
OL
OH
OL
OH
Figure 2. Load Circuits for Data-Hold Time Test
Figure 1. Load Circuits for Data-Access Time Test
4
_______________________________________________________________________________________
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
4/MAX158
_____________________________________________________________P in De s c rip t io n s
PIN
MAX154
PIN
MAX158
NAME
FUNCTION
NAME
FUNCTION
1
2
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
REF OUT
DB0
Analog Input Channel 6
1
2
3
4
5
6
7
8
9
AIN4
AIN3
AIN2
AIN1
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 5
3
Analog Input Channel 4
4
Analog Input Channel 3
5
Analog Input Channel 2
REF OUT Reference Output (2.5V) for MAX154
6
Analog Input Channel 1
DBO
DB1
DB2
DB3
Three-State Data Output, bit 0 (LSB)
Three-State Data Output, bit 1
Three-State Data Output, bit 2
Three-State Data Output, bit 3
7
Reference Output (2.5V) for MAX158
Three-State Data Output, bit 0 (LSB)
Three-State Data Output, bit 1
Three-State Data Output, bit 2
Three-State Data Output, bit 3
8
9
DB1
10
11
DB2
Read Input. RD controls conversions and
data access. See Digital Interface section.
DB3
10
11
RD
Read Input. RD controls conversions
and data access.
See Digital Interface section.
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See Digital Interface section.
12
13
RD
INT
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See Digital Interface section.
12
13
GND
Ground
INT
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to V +.
REF
V
REF
-
14
15
GND
Ground
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to V +.
REF
Upper Limit of Reference Span. Sets
the full-scale input voltage.
V
-
REF
14
V +
REF
Range: V - to V
.
REF
DD
Upper Limit of Reference Span. Sets
the full-scale input voltage.
16
V
+
Ready Output. Open-drain output with
no active pull-up device. Goes low
when CS goes low and high imped-
ance at the end of a conversion.
REF
Range: V - to V
.
REF
DD
15
16
RDY
CS
Ready Output. Open-drain output with
no active pull-up device. Goes low
when CS goes low and high imped-
ance at the end of a conversion.
17
18
RDY
CS
Chip-Select Input. CS must be low for
the device to be selected.
–
17
18
19
20
21
22
23
24
DB4
DB5
DB6
DB7
A1
Three-State Data Output, bit 4
Three-State Data Output, bit 5
Three-State Data Output, bit 6
Three-State Data Output, bit 7 (MSB)
Channel Address 1 Input
Channel Address 0 Input
No Connect
Chip-Select input. CS must be low for
the device to be selected.
Three-State Data Output, bit 4
Three-State Data Output, bit 5
Three-State Data Output, bit 6
Three-State Data Output, bit 7 (MSB)
Channel Address 2 Input
Channel Address 1 Input
Channel Address 0 Input
Power-Supply Voltage, +5V
Analog Input Channel 8
19
20
21
22
23
24
25
26
27
28
DB4
DB5
DB6
DB7
A2
A0
NC
A1
V
DD
Power-Supply Voltage, +5V
A0
V
DD
AIN8
AIN7
Analog Input Channel 7
_______________________________________________________________________________________
5
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
_______________De t a ile d De s c rip t io n
___________________Dig it a l In t e rfa c e
The MAX154/MAX158 use only Chip Select (CS) and
Read (RD) as control inputs. A READ operation, taking
CS and RD low, latches the multiplexer address inputs
and starts a conversion (Table 1).
Co n ve rt e r Op e ra t io n s
The MAX154/MAX158 use what is commonly called a
"half-flash" conversion technique (Figure 3). Two 4-bit
flash ADC converter sections are used to achieve an 8-
bit result. Using 15 comparators, the upper 4-bit MS
(most significant) flash ADC compares the unknown
input voltage to the reference ladder and provides the
upper four data bits.
Table 1. Truth Table for Input Channel
Selection
MAX154/MX7824
MAX158/MX7828
SELECTED
CHANNEL
A1
A0
A2
A1
A0
An internal DAC uses the MS bits to generate an analog
signal from the first flash conversion. A residue voltage
representing the difference between the unknown input
and the DAC voltage is then compared to the reference
ladder by 15 LS (least significant) flash comparators to
obtain the lower four output bits.
0
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
0
1
1
4/MAX158
Op e ra t in g S e q u e n c e
The operating sequence is shown in Figure 4. A conver-
sion is initiated by a falling edge of RD and CS. The
comparator inputs track the analog input voltage for
approximately 1µs. After this first cycle, the MS flash
result is latched into the output buffers and the LS con-
version begins. INT goes low approximately 600ns later,
indicating the end of the conversion, and that the lower
four bits are latched into the output buffers. The data
can then be accessed using the CS and RD inputs.
There are two interface modes, which are determined
by the length of the RD input. Mode 0, implemented by
keeping RD low until the conversion ends, is designed
for microprocessors that can be forced into a WAIT
state. In this mode, a conversion is started with a READ
operation (taking CS and RD low), and data is read
when the conversion ends. Mode 1, on the other hand,
does not require microprocessor WAIT states. A READ
operation simultaneously initiates a conversion and
reads the previous conversion result.
DB7
V
+
REF
4-BIT
FLASH
ADC
(4MSB)
DB6
V
REF
-
DB5
DB4
AIN1
AIN4
THREE-
STATE
DRIVERS
4-BIT
DAC
MUX*
V
+
REF
DB3
DB2
DB1
AIN8
4-BIT
FLASH
ADC
16
(4LSB)
DB0
ADDRESS
LATCH
DECODE
REF OUT
2.5V
REF
TIMING AND CONTROL
CIRCUITRY
INT
A0 A1 A2
RDY
CS
RD
*MAX154 – 4-Channel Mux
MAX158 – 8-Channel Mux
Figure 3. Functional Diagram
6
_______________________________________________________________________________________
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
4/MAX158
device), is connected to the processor’s READY/WAIT
input. RDY goes low on the falling edge of CS and goes
high impedance at the end of the conversion, when the
INT GOING LOW INDICATES
THAT CONVERSION IS
COMPLETE AND THAT
DATA CAN BE READ
RD
conversion result appears on the data outputs. If the
600ns
500ns
1000ns
RDY output is not required, its external pull-up resistor
can be omitted. INT goes low when the conversion is
complete and returns high on the rising edge of CS or
RD.
SETUP TIME REQUIRED
BY THE INTERNAL
COMPARATORS PRIOR TO
STARTING CONVERSION
V IS SAMPLED
AND THE FOUR MSBs
ARE LATCHED
IN
In t e rfa c e Mo d e 1
Mode 1 is designed for applications where the micro-
processor is not forced into a WAIT state. Taking CS
and RD low latches the multiplexer address and starts
a c onve rs ion (Fig ure 6). Da ta from the p re vious
c onve rs ion is imme d ia te ly re a d from the outp uts
(DB0–DB7).
V IS TRACKED
BY INTERNAL
COMPARATORS
IN
Figure 4. Operating Sequence
In t e rfa c e Mo d e 0
Figure 5 shows the timing diagram for Mode 0 opera-
tion. This is used with microprocessors that have WAIT
state capability, whereby a READ instruction is extend-
ed to accommodate slow-memory devices. Taking CS
and RD low latches the analog multiplexer address and
starts a conversion. Data outputs DB0–DB7 remain in
the high-impedance condition until the conversion is
complete.
INT goes high at the rising edge of CS or RD and goes
low at the end of the conversion. A second READ oper-
ation is required to read the result of this conversion.
The second READ latches a new multiplexer address
and starts another conversion. A delay of 2.5µs must
be allowed between READ operations. RDY goes low
on the falling edge of CS and goes high impedance at
the rising edge of CS. If RDY is not needed, its external
pull-up resistor can be omitted.
There are two status outputs: Interrupt (INT) and Ready
(RDY). RDY, an open-drain output (no internal pull-up
CS
t
t
t
CSH
CSS
CSS
RD
t
P
t
AS
t
AS
ANALOG
CHANNEL
ADDRESS
ADDR
VALID
ADDR
VALID
t
AH
RDY
INT
t
RDY
t
INTH
t
CRD
t
t
DH
ACC2
HIGH IMPEDANCE
DATA
VALID
DATA
Figure 5. Mode 0 Timing Diagram
_______________________________________________________________________________________
7
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
CS
t
t
RD
t
t
CSS
t
t
RD
CSH
CSH
CSS
RD
t
P
t
AS
t
AS
ANALOG
CHANNEL
ADDRESS
ADDR
VALID
ADDR
VALID
t
AH
t
AH
RDY
t
t
RDY
RDY
t
CRD
4/MAX158
t
t
INTH
INTH
INT
t
t
DH
t
DH
t
ACCI
ACCI
OLD
DATA
NEW
DATA
DATA
Figure 6. Mode 1 Timing Diagram
_____________An a lo g Co n s id e ra t io n s
OUTPUT
CODE
FULL-SCALE
TRANSITION
Re fe re n c e a n d In p u t
The V + and V - inputs of the converter define the
REF
REF
zero and the full-scale of the ADC. In other words, the
11111111
11111110
11111101
voltage at V - is equal to the input voltage that pro-
REF
duces an output code of all zeros, and the voltage at
V + is equal to input voltage that produces an output
REF
code of all ones (Figure 7).
Figure 8 shows some possible reference configura-
tions. A 0.01µF bypass capacitor to GND should be
used to reduce the high-frequency output impedance
of the internal reference. Larger capacitors should not
be used, as this degrades the stability of the reference
buffer. The 2.5V reference output is with respect to the
GND pin.
1LSB = F8 = V + - V
-
REF
REF
256
256
00000011
00000010
V
+
REF
00000001
00000000
Byp a s s in g
A 47µF electrolytic and 0.1µF ceramic capacitor should
1
2
3
FS
FS–1LSB
be used to bypass the V pin to GND. These capaci-
DD
V
-
REF
AIN INPUT VOLTAGE
(IN TERMS OF LSBs)
tors must have minimum lead length, since excess lead
length may contribute to conversion errors and insta-
bility. If the reference inputs are driven by long lines,
they should be bypassed to GND with 0.1µF capac-
itors at the reference input pins.
Figure 7. Transfer Function
8
_______________________________________________________________________________________
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
4/MAX158
In p u t Cu rre n t
The converters’ analog inputs behave somewhat differ-
ently from conventional ADCs. The sampled data com-
AIN (+)
x
V
IN
parators take varying amounts of current from the input,
depending on the cycle they are in. The equivalent cir-
AIN (-)
x
GND
cuit of the converter is shown in Figure 9a. When the
conversion starts, AIN(n) is connected to the MS and
LS comparators. Thus, AIN(n) is connected to thirty-one
1pF capacitors.
MAX154
MAX158
+5V
V
DD
REFOUT
0.1µF
47µF
To acquire the input signal in approximately 1µs, the input
capacitors must charge to the input voltage through the
on-resistance of the multiplexer (about 600Ω) and the
comparator’s analog switches (2kΩ to 5kΩ per compara-
tor). In addition, about 12pF of stray capacitance must be
charged. The input can be modeled as an equivalent RC
V
+
REF
0.01µF
V
REF
-
network shown in Figure 9b. As R (source impedance)
increases, the capacitors take longer to charge.
S
Figure 8a. Internal Reference
Since the length of the input acquisition time is internal-
ly set, large source resistances (greater than 100Ω) will
cause settling errors. The output impedance of an op-
amp is its open-loop output impedance divided by the
loop gain at the frequency of interest. It is important
that the amplifier driving the converter input have suffi-
cient loop gain at approximately 1MHz to maintain low
output impedance.
AIN (+)
x
V
IN
GND
AIN (-)
x
MAX154
MAX158
V
DD
+5V
In p u t Filt e rin g
The transients in the analog input caused by the sam-
pled data comparators do not degrade the converter’s
performance, since the ADC does not “look” at the
input when these transients occur. The comparator’s
outputs track the input during the first 1µs of the con-
version, and are then latched. Therefore, at least 1µs
will be provided to charge the ADC’s input capaci-
tance. It is not necessary to filter these transients with
an external capacitor on the AIN terminals.
V
+
0.1µF
REF
47µF
V
REF
-
Figure 8b. Power Supply as Reference
* Current path must
still exist from
S in u s o id a l In p u t s
The MAX154/MAX158 can measure input signals with
slew rates as high as 157mV/µs to the rated specifications.
This means that the analog input frequency can be as
high as 10kHz without the aid of an external track/hold.
The maximum sampling rate is limited by the conversion
V
IN(-)
to Ground
AIN (+)
x
V
IN
GND
+5V
0.1µF
V
DD
MAX154
MAX158
time (typical t
= 2µs) plus the time required between
CRD
conversions (t = 500ns). It is calculated as:
p
V
REF
+
47µF
f
1
1
400kHz
=
MAX
=
=
2.5V
*
t
+ t
(2.0 + 0.5) µs
CRD
p
V
-
AIN (-)
x
REF
f
permits a maximum sampling rate of 50kHz per
MAX
c ha nne l whe n us ing the MAX158 a nd 100kHz p e r
channel when using the MAX154. These rates are well
above the Nyquist requirement of 20kHz sampling rate
for a 10kHz input bandwidth.
Figure 8c. Inputs Not Referenced to GND
_______________________________________________________________________________________
9
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
Bip o la r In p u t Op e ra t io n
The circuit in Figure 10a can be used for bipolar input
operation. The input voltage is scaled by an amplifier
so tha t only positive volta g e s a p pe a r a t the ADC’s
inputs. The analog input range is ±4V and the output
c od e is c omp le me nta ry offs e t b ina ry. The id e a l
FS = 8V
1LSB = FS / 256
11111111
11111110
input/output characteristic is shown in Figure 10b.
11111101
10000010
C
S
2pF
10000001
+FS
2
R
S
R
MUX
R
ON
AIN1
10000000
01111111
-FS
2
+ 1LSB
1pF
V
IN
C
S
1pF
•
•
•
TO LS
LADDER
01111110
00000010
00000001
00000000
12pF
15 LSB COMPARATORS
4/MAX158
R
ON
0V
AIN INPUT VOLTAGE (LSBs)
1pF
1pF
•
•
•
TO MS
LADDER
16 MSB COMPARATORS
Figure 9a. Equivalent Input Circuit
Figure 10b. Transfer Function for ±4V Input Operation
R
350Ω
B MUX
600Ω
ON
R
S
AIN1
C
2pF
C
2pF
S2
S1
32pF
V
IN
A15
ADDRESS BUS
A0
Figure 9b. RC Network Model
3.57k
ADDRESS
DECODE
A0
A1
A2*
EN
5V
MREQ
11.5Ω
V
IN
ZBO
CS
AIN1
MAX154
MAX158
10.0k
CS
5k
RDY
MAX154
MAX158
WAIT
RD
RDY
RD
0.01µF
16.2k
RD
DATA BUS
DB0-DB7
D0-D7
V
+
INT
REF
0.01µF
REFOUT
+5V
V
DD
DB0-DB7
V
-
REF
0.1µF
47µF
*A2 ON MAX158.
GND
ONLY CHANNEL 1 SHOWN
Figure 11. Simple Mode 0 Interface
Figure 10a. Bipolar ±4V Input Operation
10 ______________________________________________________________________________________
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
4/MAX158
_Ord e rin g In fo rm a t io n (c o n t in u e d )
+5V
26
ERROR
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
V
DD
1
± /
MAX154AENG -40°C to +85°C
MAX154BENG -40°C to +85°C
MAX154AEWG -40°C to +85°C
MAX154BEWG -40°C to +85°C
MAX154AEAG -40°C to +85°C
MAX154BEAG -40°C to +85°C
24 Plastic DIP
24 Plastic DIP
24 Wide SO
24 Wide SO
24 SSOP
2
BANDPASS
FILTER 1
6
5
18
12
AIN1
AIN2
CS
RD
±1
1
±
/
2
BANDPASS
FILTER 2
±1
1
±
/
2
MAX158
24 SSOP
±1
1
SPEECH
INPUT
MAX154AMRG -55°C to +125°C 24 CERDIP
MAX154BMRG -55°C to +125°C 24 CERDIP
±
/
AMP
2
DATA
DB0-DB7
±1
1
MAX158ACPI
MAX158BCPI
MAX158BC/D
MAX158ACWI
MAX158BCWI
MAX158ACAI
MAX158BCAI
MAX158AEPI
MAX158BEPI
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +70°C
-40°C to +85°C
28 Plastic DIP
28 Plastic DIP
Dice
±
/
2
BANDPASS
FILTER 7
28
±1
1
AIN7
23
24
±
/
/
A2
A1
2
1
±
28 Wide SO
28 Wide SO
28 SSOP
BANDPASS
FILTER 8
27
16
2
AIN8
V
±1
25
1
± /
+5V
A0
REF+
V
2
28 SSOP
±1
GND
14
REF-
15
1
± /
28 Plastic DIP
28 Plastic DIP
28 Wide SO
28 Wide SO
28 SSOP
2
±1
1
± /
MAX158AEWI -40°C to +85°C
MAX158BEWI -40°C to +85°C
MAX158AEAI -40°C to +85°C
MAX158BEAI -40°C to +85°C
2
±1
1
± /
2
Figure 12. Speech Analysis Using Real-Time Filtering
28 SSOP
±1
1
MAX158AMJI -55°C to +125°C 28 CERDIP
MAX158BMJI -55°C to +125°C 28 CERDIP
± /
2
±1
SAMPLE
PULSE
+5V
+5V
18
24
16
CS
10
RD
+5V
V
DD
V
DD
4
2
4
3
V
REF
AIN1
15
WR
11
AIN2
V
A
B
C
D
INT
OUT
1
2
1
V
AIN3
AIN4
V
OUT
MAX506
MAX154
20
19
6
V
OUT
DB0-DB7
DB0-DB7
14
13
12
V
REF+
OUT
16
17
21
22
V
REF-
A1
A0
A1
A0
DGND
AGND
5
GND
V
SS
3
A0
A1
Figure 13. 4-Channel Fast Sample and Infinite Hold
______________________________________________________________________________________ 11
CMOS Hig h -S p e e d 8 -Bit ADCs w it h
Mu lt ip le x e r a n d Re fe re n c e
___________________Ch ip To p o g ra p h y
AIN4 AIN6 AIN8
(N.C.) (AIN2) (AIN4)
AIN3 AIN5 AIN7
VDD A0
(N.C.) (AIN1) (AIN3)
A1
A2 (N.C.)
AIN2 (N.C.)
AIN1 (N.C.)
0.127"
(3.228mm)
TP (REF OUT)
DB7
DB6
DB0
DB1
DB5
DB2
DB3
4/MAX158
DB4
CS
A0
GND
INT
V
REF
+
ADY
REF
V
-
0.124"
(3.150mm)
( ) ARE FOR MAX154/MX7824
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
MIN
0.068
MAX
0.078
0.008
0.015
0.008
MIN
1.73
0.05
0.25
0.09
MAX
1.99
0.21
0.38
0.20
A
A1 0.002
B
C
D
E
e
0.010
0.004
SEE VARIATIONS
α
0.205
0.209
5.20
5.38
E
H
0.0256 BSC
0.65 BSC
H
L
0.301
0.311
0.037
8˚
7.65
0.63
0˚
7.90
0.95
8˚
0.025
0˚
C
α
L
INCHES
MILLIMETERS
DIM PINS
MAX
6.33
MIN MAX MIN
0.239 0.249 6.07
0.239 0.249 6.07
0.278 0.289 7.07
0.317 0.328 8.07
0.397 0.407 10.07
e
D
D
D
D
D
14
16
20
24
28
6.33
SSOP
7.33
SHRINK
A
8.33
SMALL-OUTLINE
PACKAGE
10.33
21-0056A
B
A1
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
ENG LIS H • ? ? ? ? • ? ? ? • ? ?
WH AT' S N EW
PRO DU CT S
S OL UT IO NS
D ESIGN
A PPNOTES
SU PPORT
B U Y
CO MPA N Y
M EMB ERS
M a x i m > P r o d u c t s > A n a l o g - t o - D i g i t a l C o n v e r t e r s
M A X 1 5 4 , M A X 1 5 8
C M O S H i g h - S p e e d , 8 - B i t A D C s w i t h M u l t i p l e x e r a n d R e f e r e n c e
Q
u
i
c
k
V
i
e
w
T e c h n i c a l D o c u m e n t s
O
r
d
e
r
i
n
g
I
n
f
o
M
o
r
e
I
n
f
o
r
m
a
t
i
o
n
A l l
O r d e r i n g I n f o r m a t i o n
N o t e s :
1 . O t h e r o p t i o n s a n d l i n k s f o r p u r c h a s i n g p a r t s a r e l i s t e d a t : h t t p : / / w w w . m a x i m - i c . c o m / s a l e s .
2 . D i d n ' t F i n d W h a t Y o u N e e d ? A s k o u r a p p l i c a t i o n s e n g i n e e r s . E x p e r t a s s i s t a n c e i n f i n d i n g p a r t s , u s u a l l y w i t h i n o n e
b u s i n e s s d a y .
3 . P a r t n u m b e r s u f f i x e s : T o r T & R = t a p e a n d r e e l ; + = R o H S / l e a d - f r e e ; # = R o H S / l e a d - e x e m p t . M o r e : S e e F u l l D a t a
S h e e t o r P a r t N a m i n g C o n v e n t i o n s .
4 . * S o m e p a c k a g e s h a v e v a r i a t i o n s , l i s t e d o n t h e d r a w i n g . " P k g C o d e / V a r i a t i o n " t e l l s w h i c h v a r i a t i o n t h e p r o d u c t u s e s .
D e v i c e s : 1 - 9 3 o f 9 3
M
A
X
1
5
4
F
r
e
e
B uy
T
e
m
p
R o H S/ L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P
a
c
k
a
g
e
:
T
Y
P
E
P
I
N
S
F
O
O
T
P
R
I
N
T
S
a
m
p
l
e
D RA WI NG C OD E/ VA R *
M
A
X
1
5
4
B
E
A
G
+
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e
- 5 5 C t o + 1 2 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e
M A X 1 5 4 A M R G +
M A X 1 5 4 B M R G
C e r a m i c D I P ; 2 4 p i n ; 2 5 6 m m
D w g : 2 1 - 0 0 4 5 A ( P D F )
- 5 5 C t o + 1 2 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : R 2 4 - 4 *
M A X 1 5 4 A M R G
C e r a m i c D I P ; 2 4 p i n ; 2 5 6 m m
D w g : 2 1 - 0 0 4 5 A ( P D F )
- 5 5 C t o + 1 2 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U
s
e
p
k
g
c
o
d
e
/
v
a
r
i
a
t
i
o
n
:
R
2
4
-
4
*
M A X 1 5 4 A M R G / 8 8 3 B
M A X 1 5 4 B M R G / 8 8 3 B
M A X 1 5 4 B C / D
C e r a m i c D I P ; 2 4 p i n ; 2 5 6 m m
D w g : 2 1 - 0 0 4 5 A ( P D F )
U s e p k g c o d e / v a r i a t i o n : R 2 4 - 4 *
- 5 5 C t o + 1 2 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
C e r a m i c D I P ; 2 4 p i n ; 2 5 6 m m
D w g : 2 1 - 0 0 4 5 A ( P D F )
U s e p k g c o d e / v a r i a t i o n : R 2 4 - 4 *
- 5 5 C t o + 1 2 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
R o H S / L e a d - F r e e : S e e d a t a s h e e
M A X 1 5 4 B C N G
P D I P ; 2 4 p i n ; 2 6 5 m m
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : N 2 4 - 1 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 5 4 B C N G +
M A X 1 5 4 A C N G
P D I P ; 2 4 p i n ; 2 6 5 m m
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : N 2 4 + 1 *
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
P D I P ; 2 4 p i n ; 2 6 5 m m
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : N 2 4 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 5 4 A C N G +
M A X 1 5 4 A E N G +
M A X 1 5 4 B E N G +
P D I P ; 2 4 p i n ; 2 6 5 m m
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : N 2 4 + 1 *
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
P D I P ; 2 4 p i n ; 2 6 5 m m
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : N 2 4 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
P D I P ; 2 4 p i n ; 2 6 5 m m
D w g : 2 1 - 0 0 4 3 D ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : N 2 4 + 1 *
M A X 1 5 4 A E N G
P D I P ; 2 4 p i n ; 2 6 5 m m
D w g : 2 1 - 0 0 4 3 D ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : N 2 4 - 1 *
M A X 1 5 4 B E N G
P D I P ; 2 4 p i n ; 2 6 5 m m
D w g : 2 1 - 0 0 4 3 D ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : N 2 4 - 1 *
M A X 1 5 4 A C W G + T
M A X 1 5 4 B C W G + T
M A X 1 5 4 A C W G +
M A X 1 5 4 B C W G +
M A X 1 5 4 A C W G
M A X 1 5 4 B C W G - T
M A X 1 5 4 A C W G - T
M A X 1 5 4 B C W G
M A X 1 5 4 B E W G - T
M A X 1 5 4 A E W G
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 + 1 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 + 1 *
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 + 1 *
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 + 1 *
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : W 2 4 - 1 *
M A X 1 5 4 A E W G + T
M A X 1 5 4 B E W G + T
M A X 1 5 4 B E W G +
M A X 1 5 4 A E W G +
M A X 1 5 4 B E W G
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : W 2 4 - 1 *
M A X 1 5 4 A E W G - T
M A X 1 5 4 B C A G + T
M A X 1 5 4 A C A G - T
M A X 1 5 4 B C A G +
M A X 1 5 4 A C A G + T
M A X 1 5 4 A C A G +
S O I C ; 2 4 p i n ; 1 6 6 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 4 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 + 2 *
0 C t o + 7 0 C
0 C t o + 7 0 C
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R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 - 2 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 + 2 *
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 + 2 *
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : A 2 4 + 2 *
M A X 1 5 4 B C A G
M A X 1 5 4 B C A G - T
M A X 1 5 4 A C A G
M A X 1 5 4 A E A G +
M A X 1 5 4 B E A G - T
M A X 1 5 4 A E A G
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 - 2 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 - 2 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 - 2 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 + 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 - 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : A 2 4 - 2 *
M A X 1 5 4 B E A G + T
M A X 1 5 4 A E A G - T
M A X 1 5 4 B E A G
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 4 - 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : A 2 4 - 2 *
M A X 1 5 4 A E A G + T
S S O P ; 2 4 p i n ; 6 6 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : A 2 4 + 2 *
M A X 1 5 8
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C e r a m i c D I P ; 2 8 p i n ; 6 0 6 m m
D w g : 2 1 - 0 0 4 6 A ( P D F )
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C e r a m i c D I P ; 2 8 p i n ; 6 0 6 m m
D w g : 2 1 - 0 0 4 6 A ( P D F )
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- 5 5 C t o + 1 2 5 C R o H S / L e a d - F r e e : N o
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C e r a m i c D I P ; 2 8 p i n ; 6 0 6 m m
D w g : 2 1 - 0 0 4 6 A ( P D F )
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U s e p k g c o d e / v a r i a t i o n : P 2 8 + 1 *
0 C t o + 7 0 C
0 C t o + 7 0 C
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R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
P D I P ; 2 8 p i n ; 5 9 3 m m
D w g : 2 1 - 0 0 4 4 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 2 8 - 1 *
R o H S / L e a d - F r e e : N o
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P D I P ; 2 8 p i n ; 5 9 3 m m
D w g : 2 1 - 0 0 4 4 B ( P D F )
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P D I P ; 2 8 p i n ; 5 9 3 m m
D w g : 2 1 - 0 0 4 4 B ( P D F )
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R o H S / L e a d - F r e e : N o
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P D I P ; 2 8 p i n ; 5 9 3 m m
D w g : 2 1 - 0 0 4 4 B ( P D F )
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P D I P ; 2 8 p i n ; 5 9 3 m m
D w g : 2 1 - 0 0 4 4 B ( P D F )
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D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 8 + 1 *
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 8 + 1 *
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 8 + 1 *
R o H S / L e a d - F r e e : L e a d F r e e
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 8 + 1 *
R o H S / L e a d - F r e e : L e a d F r e e
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
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D w g : 2 1 - 0 0 4 2 B ( P D F )
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
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S O I C ; 2 8 p i n ; 1 9 3 m m
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S O I C ; 2 8 p i n ; 1 9 3 m m
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 8 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : W 2 8 - 1 *
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 8 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 8 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
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S O I C ; 2 8 p i n ; 1 9 3 m m
D w g : 2 1 - 0 0 4 2 B ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
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U s e p k g c o d e / v a r i a t i o n : W 2 8 - 1 *
M A X 1 5 8 B C A I +
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S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 + 1 *
0 C t o + 7 0 C
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S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 - 1 *
R o H S / L e a d - F r e e : N o
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S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 + 1 *
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S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : A 2 8 - 1 *
M A X 1 5 8 B C A I
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M A X 1 5 8 A C A I +
M A X 1 5 8 B E A I +
M A X 1 5 8 B E A I + T
M A X 1 5 8 B E A I - T
M A X 1 5 8 B E A I
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 - 1 *
0 C t o + 7 0 C
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R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 + 1 *
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S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 + 1 *
R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
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S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : A 2 8 - 1 *
M A X 1 5 8 A E A I +
M A X 1 5 8 A E A I - T
M A X 1 5 8 A E A I
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 8 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : A 2 8 - 1 *
M A X 1 5 8 A E A I + T
S S O P ; 2 8 p i n ; 8 2 m m
D w g : 2 1 - 0 0 5 6 C ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : A 2 8 + 1 *
D i d n ' t F i n d W h a t Y o u N e e d ?
N e x t D a y P r o d u c t S e l e c t i o n A s s i s t a n c e f r o m A p p l i c a t i o n s E n g i n e e r s
P a r a m e t r i c S e a r c h
A p p l i c a t i o n s H e l p
Q u i c k V i e w
T e c h n i c a l D o c u m e n t s
O r d e r i n g I n f o
M o r e I n f o r m a t i o n
D e s c r i p t i o n
D a t a S h e e t
A p p l i c a t i o n N o t e s
D e s i g n G u i d e s
E n g i n e e r i n g J o u r n a l s
R e l i a b i l i t y R e p o r t s
S o f t w a r e / M o d e l s
E v a l u a t i o n K i t s
P r i c e a n d A v a i l a b i l i t y
S a m p l e s
B u y O n l i n e
P a c k a g e I n f o r m a t i o n
L e a d - F r e e I n f o r m a t i o n
R e l a t e d P r o d u c t s
N o t e s a n d C o m m e n t s
E v a l u a t i o n K i t s
K e y F e a t u r e s
A p p l i c a t i o n s / U s e s
K e y S p e c i f i c a t i o n s
D i a g r a m
D o c u m e n t R e f . : 1 9 - 0 8 9 2 ; R e v 3 ; 1 9 9 6 - 1 2 - 0 1
T h i s p a g e l a s t m o d i f i e d : 2 0 0 7 - 0 5 - 2 9
C O N T A C T U S : S E N D U S A N E M A I L
C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s S e m i c o n d u c t o r • L e g a l N o t i c e s • P r i v a c y P o l i c y
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