MAX156BEWI+ [MAXIM]
ADC, Successive Approximation, 8-Bit, 1 Func, 4 Channel, Parallel, 8 Bits Access, PDSO28, 0.300 INCH, SOIC-28;
| 型号： | MAX156BEWI+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 8-Bit, 1 Func, 4 Channel, Parallel, 8 Bits Access, PDSO28, 0.300 INCH, SOIC-28 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：970K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
General Description
Features
The MAX155/MAX156 are high-speed, 8-bit, multichan-
nel analog-to-digital converters (ADCs) with simultaneous
track/holds (T/Hs) to eliminate timing differences between
input channel samples. The MAX155 has 8 analog input
channels and the MAX156 has 4 analog input channels.
Each channel has its own T/H, and all T/Hs sample at the
same instant. The ADC converts a channel in 3.6µs and
stores the result in an internal 8x8 RAM. The MAX155/
MAX156 also feature a 2.5V internal reference and
power-down capability, providing a complete, sampling
data-acquisition system.
● 8 Simultaneously Sampling Track/Hold Inputs
● 3.6µs Conversion Time Per Channel
● Unipolar or Bipolar Input Range
● Single-Ended or Differential Inputs
● Mixed Input Configurations Possible
● 2.5V Internal Reference
● Single +5V or Dual ±5V Supply Operation
Applications
● Phase-Sensitive Data Acquisition
● Vibration and Waveform Analysis
● DSP Analog Input
● AC Power Meters
● Portable Data Loggers
When operating from a single +5V supply, the MAX155/
MAX156 perform either unipolar or bipolar, single-ended
or differential conversions. For applications requiring
wider dynamic range or bipolar conversions around
ground, the VSS supply pin may be connected to -5V.
Conversions are initiated with a pulse to the WR pin, and data
is accessed from the ADC’s RAM with a pulse to the RD pin.
A bidirectional interface updates the channel configuration
and provides output data. The ADC may also be wired for
output-only operation.The MAX155 comes in 28-pin PDIP
and wide SO packages, and the MAX156 comes in 24-pin
narrow PDIP and 28-pin wide SO packages.
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX155.related.
Functional Diagram
MAX155
AIN0
T/H
CLK
AIN1
T/H
8-BIT
A/D
3.6µs
REFIN
AIN2
T/H
REFOUT
2.5V
AIN3
T/H
V
REF
8
8-BIT
DATA
BUS
AIN4
T/H
THREE-
STATE
BUFFER
8
8
8
8 x 8
RAM
AIN5
T/H
AIN6
T/H
AIN7
T/H
CS
RD
CONTROL
LOGIC
8
WR
MODE
19-2949; Rev 2; 1/12
MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Absolute Maximum Ratings
V
to AGND ............................................................. -0.3V, +6V
Continuous Power Dissipation (T = +70°C)
A
DD
V
to DGND............................................................. -0.3V, +6V
24-Pin PDIP (derate 8.7mW/°C above +70°C)............696mW
28-Pin PDIP (derate 9.09mW/°C above +70°C)..........727mW
28-Pin Wide SO (derate 12.5mW/°C above +70°C)..1000mW
Operating Temperature Ranges:
DD
AGND to DGND ...........................................-0.3V, (V
+ 0.3V)
DD
V
V
to AGND.............................................................. +0.3V, -6V
to DGND............................................................. +0.3V, -6V
SS
SS
CS, WR, RD, CLK, MODE to DGND ...........-0.3V, (V
BUSY, D0–D7 to DGND...............................-0.3V, (V
REFOUT to AGND .......................................-0.3V, (V
REFIN to AGND ...........................................-0.3V, (V
+ 0 3V)
+ 0 3V)
+ 0 3V)
+ 0 3V)
+ 0 3V)
MAX155/MAX156_C_ _......................................0°C to +70°C
MAX155/MAX156_E_ _.................................. -40°C to +85°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
DD
DD
DD
DD
DD
AIN to AGND....................................(V - 0.3V), (V
SS
Output Current (REFOUT) .................................................30mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
= +5V, V
= +2.5V. External Reference, V
= V
= 0V, V
= 0V or -5V, f
= 5MHz external, Unipolar range
DD
REFIN
AGND
DGND
SS
CLK
single-ended mode, T = T
A
to T
, unless otherwise noted.)
MAX
MIN
PARAMETER
ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
8
Bits
LSB
Bits
LSB
MAX15_A
MAX15_B
±½
±1
Integral Linearity Error
No Missing Codes Resolution
Offset Error (Unipolar)
Guaranteed monotonic
MAX15_A
8
±½
±1
±1
±2
±1
±1
±1
±2
MAX15_B
MAX15_A
Offset Error (Bipolar)
Gain Error
LSB
LSB
LSB
dB
MAX15_B
MAX15_A
Unipolar
Bipolar
MAX15_B
MAX15_A
MAX15_B
MAX15_A
MAX15_B
±½
±1
Channel-to-Channel Matching
DYNAMIC PERFORMANCE (V = 50kHz, 2.5V
IN
sine wave sampled at 220ksps)
MAX15_A
P-P
48
47
-60
-62
4
Signal-to-Noise and Distortion
Ratio
SINAD
MAX15_B
Total Harmonic Distortion
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Aperture Delay
THD
dB
dB
SFDR
MHz
ns
20
Aperture Delay Matching (Note 2)
4
ns
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Electrical Characteristics (continued)
(V
= +5V, V
= +2.5V. External Reference, V
= V
= 0V, V
= 0V or -5V, f
= 5MHz external, Unipolar range
DD
REFIN
AGND
DGND
SS
CLK
single-ended mode, T = T
A
to T
, unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Voltage Range, Unipolar, Single-
Ended
AIN_(+) to AGND
0
0
V
REF
Unipolar Differential
Bipolar, Single-Ended
Bipolar, Differential
AIN_(+) to AIN_(-)
AIN_(+) to AGND
AIN_(+) to AIN_(-)
Differential mode
V
V
V
REF
REF
REF
V
-V
REF
REF
-V
Common-Mode Range
DC Input Impedance
REFERENCE INPUT
V
V
DD
SS
AIN = V
10
MΩ
DD
REFIN Range (For Specified
Performance) (Note 2)
2.375
2.500
2.625
1
V
I
V
= 2.5V
mA
REF
REFIN
REFERENCE OUTPUT (C = 4.7µF)
L
T
= +25°C
2.44
2.38
2.50
2.50
2.56
2.62
A
Output Voltage
I = 0mA
V
T
T
= T
to
MIN
L
A
MAX
Load Regulation
T
T
= +25°C, I
= 0 to 10mA
= 5V ±5%
-10
±3
mV
mV
A
OUT
Power-Supply Sensitivity
Temperature Drift
= +25°C, V
±1
A
DD
±100
ppm/°C
LOGIC INPUTS (Mode = Open Circuit)
CS, RD, WR, CLK, D0–D7 (When
Inputs) Input Low Voltage
V
0.8
V
IL
Input High Voltage
Input Current
V
2.4
V
IH
I
±10
15
µA
pF
IN
Input Capacitance (Note 2)
MODE
C
IN
Input Low Voltage
V
0.5
V
V
IL
V
0.5
-
DD
Input High Voltage
V
IH
V
- 0.5
/2
V
+ 0.5
/2
DD
DD
Input Midlevel Voltage
V
V
MID
Input Floating Voltage
Input Current
V
V
/2
DD
V
FLT
I
±50
±100
µA
IN
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Electrical Characteristics (continued)
(V
= +5V, V
= +2.5V. External Reference, V
= V
= 0V, V
= 0V or -5V, f
= 5MHz external, Unipolar range
DD
REFIN
AGND
DGND
SS
CLK
single-ended mode, T = T
A
to T
, unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC OUTPUTS
BUSY, D0–D7 Output Low Voltage
Output High Voltage
V
I
I
= 1.6mA
0.4
V
V
OL
OUT
OUT
V
= -360µA
4
OH
D0–D7 Floating State Leakage
±10
15
µA
Floating State Output Capacitance
(Note 2)
C
pF
µs
OUT
Conversion Time
f
= 5MHz, single channel
MAX155
3.6
3.8
CLK
POWER REQUIREMENTS
Positive Power-Supply Voltage
V
4.75
5.25
24
V
DD
18
9
PD = 0
mA
MAX156
12
CLK, CS, WR,
Positive Power-Supply Current
I
I
DD
RD = 0V or V
;
DD
PD = 1
25
100
µA
D
V
= 0V or
OUT
DD
Negative Power-Supply Voltage
Negative Power-Supply Current
V
0
-5
50
V
SS
PD = 0
PD = 1
2
µA
SS
2
50
V
V
= 5V ±5%, V = 0V
±0.1
±0.1
±0.25
Power-Supply Rejection (Change
in Full-Scale Error)
DD
DD
SS
LSB
= 5V, V = -5V ±5%
SS
TIMING CHARACTERISTICS (Note 3, Figures 1–7)
(V
= +5V, V
= +2.5V. External Reference, V
= V
= 0V, V = 0V or -5V, T = T
to T
, unless otherwise noted.)
MAX
DD
REFIN
AGND
DGND
SS
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
ns
CS to WR Setup Time
CS to WR Hold Time
t
CWS
t
0
ns
CWH
CS to RD Setup Time
t
0
ns
CRS
CS to RD Hold Time (Note 2)
WR Low Pulse Width
t
0
ns
CRH
t
MAX15_C/E
MAX15_C/E
MAX15_C/E
MAX15_C/E
MAX15_C/E
100
100
180
280
2000
220
ns
WR
RD Low Pulse Width
t
ns
RDL
RD High Pulse Width (Note 2)
WR to RD Delay (Note 2)
WR to BUSY Low Delay
t
ns
RDH
t
ns
WRD
t
ns
WBD
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
TIMING CHARACTERISTICS (Note 3, Figures 1-7) (continued)
(V
= +5V, V
= +2.5V. External Reference, V
= V
= 0V, V = 0V or -5V, T = T
to T
, unless otherwise noted.)
MAX
DD
REFIN
AGND
DGND
SS
A
MIN
MIN
50
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
UNITS
BUSY High to WR Delay (to update
configuration register) (Notes 2, 3)
t
ns
BWD
CLK to WR Delay (Acquisition Time)
(Note 2)
t
800
ns
ACQ
BUSY High to RD Delay (Notes 2, 3)
Address-Setup Time
t
50
120
0
ns
ns
BRD
t
AS
AH
DV
Address-Hold Time
t
t
ns
RD to Data Valid (Note 4)
RD to Data Three-State Output (Note 5)
CLK to BUSY Delay (Note 2)
CLK Frequency
MAX15_C/E
MAX15_C/E
100
80
ns
t
t
ns
TR
100
300
5.0
ns
CB
0.5
MHz
Note 1:
V
= +5V, V
= +2.5V, V = 0V. Performance at ±5% power-supply tolerance is guaranteed by Power-Supply
DD
REFIN SS
Rejection test.
Note 2: Guaranteed by design, not production tested.
Note 3: All input control signals are specified with t = t = 20ns (10% to 90% of +5V) and timed from a +1.6V voltage level. Output
r
f
signals are timed from V
and V
.
OH
OL
Note 4:
Note 5:
t
t
is the time required for an output to cross +0.8V or +2.4V measured with load circuit of Figure 1.
is the time required for the data lines to change 0.5V, measured with load circuits of Figure 2.
DV
TR
+5V
+5V
3kΩ
3kΩ
DN
3kΩ
DN
DN
3kΩ
DN
100pF
100pF
DGND
10pF
10pF
HIGH-Z TO V
OL
V
TO HIGH-Z
OL
DGND
HIGH-Z TO V
V
TO HIGH-Z
OH
OH
Figure 1. Load Circuits for Data-Access Timing
Figure 2. Load Circuits for Three-State Output Timing
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
t
CRS
t
t
t
t
t
t
CRH
CWS
CWH
CRS
CRH
CRS
CS
WR
t
t
WR
WRD
t
t
t
RDL
RDH
RDL
RD
t
BRD
t
t
CONV
WBD
t
BWD
BUSY
t
t
t
t
tR
DV
tR
DV
DATA IN
DATA OUT
DATA OUT
D0–D7
t
t
ACQ
AH
t
AS
Figure 3. Write and Read Timing
Pin Configuration
TOP VIEW
+
AIN1
+
+
N.C
AIN1
N.C.
AIN0
1
2
28 AIN2
27 N.C.
26 AIN3
25 N.C.
24 VDD
1
2
AIN2 24
1
2
3
4
5
6
7
8
9
AIN3
AIN2
AIN1
AIN0
MODE
VSS
AIN4 28
AIN5 27
AIN0
AIN3 23
VDD 22
3
3
MODE
AIN6 26
MAX156
4
4
VSS
AGND 21
REFIN 20
REFOUT 19
D0/A0 18
D1/A1 17
D2 16
AIN7 25
MAX156
MODE
VSS
5
5
CS
VDD 24
MAX155
6
23 AGND
6
RD
AGND 23
REFIN 22
REFOUT 21
D0/A0 20
D1/A1 19
D2/A2 18
D3/PD 17
CS
7
22
21
20
19
18
17
16
15
REFIN
REFOUT
D0/A0
D1/A1
D2
7
WR
CS
8
RD
8
BUSY
CLK
RD
9
WR
9
WR
10
11
12
13
14
BUSY
CLK
10
11
12
D7/ALL
D6/DIFF
DGND
D3/PD 15
D4/INH 14
D5/BIP 13
10 BUSY
11 CLK
D7/ALL
D6/DIFF
DGND
D3/PD
D4/INH
D5/BIP
12 D7/ALL
D6/DIFF
DGND
13
14
16
15
D4/INH
D5/BIP
PDIP
WIDE SO
PDIP/SO
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Pin Description
PIN
MAX155
PDIP/SO
1
MAX156
PDIP
NAME
FUNCTION
SO
26
28
2
23
24
1
AIN3
AIN2
Sampling Analog Input, Channel 3
2
3
4
5
6
7
8
Sampling Analog Input, Channel 2
AIN1
Sampling Analog Input, Channel 1
2
4
AIN0
Sampling Analog Input, Channel 0
3
5
MODE
Mode configures multiplexer and converter. See Table 4.
4
6
V
Negative Supply. Power V with -5V for extended input range.
SS
SS
5
7
CS
RD
CHIP SELECT Input must be low for the ADC to recognize RD, or WR
READ Input reads data sequentially from RAM
6
8
WRITE Input’s rising edge initiates conversion and updates channel configuration
register. Falling edge samples inputs.
9
7
9
WR
10
11
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
—
BUSY
CLK
BUSY Output low when conversion is in progress
External Clock Input
9
12
10
11
12
13
14
15
16
17
18
19
20
21
22
—
D7/ALL
D6/DIFF
DGND
D5/BIP
D4/INH
D3/PD
D2/A2
D1/A1
D0/A0
Three-State Data Output Bit 7 (MSB)/Sequential or Specific Conversion
Three-State Data Output Bit 6/Single-Ended/Differential Select
Digital Ground
13
14
15
Three-State Data Output Bit 5/Unipolar/Bipolar Conversion
Three-State Data Output Bit 4/Inhibit Conversion Input
Three-State Data Output Bit 3/Power-Down Input
Three-State Data Output Bit 2/RAM Address Bit A2 (MAX155 Only)
Three-State Data Output Bit 1/RAM Address Bit A1
Three-State Data Output Bit 0/RAM Address Bit A0
16
17
18
19
20
21
REFOUT Reference Output, +2.5V
22
REFIN
AGND
Reference Input, +2.5 Normally
Analog Ground
23
24
V
Power-Supply Voltage, +5V Normally
Sampling Analog Input, Channels 7–4
DD
25–28
AIN7–4
N.C.
1, 3,
25, 27
—
—
No Connection. No internal connection—pin unconnected.
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
figuration register. This register also selects single-ended/
differential, unipolar/bipolar (Figure 9), power-down, and
other functions. Each channel selection requires a sepa-
rate write operation (i.e. 8 writes for 8 channels), but only
after power-up. Once the desired channel arrangement
is loaded, each subsequent write converts all selected
channels without reconfiguring the multiplexer (mux). I/O
mode requires more write operations, but provides more
flexibility than hard-wired mode.
Detailed Description
ADC Operation
The MAX155/MAX156 contain a 3.6µs successive approx-
imation ADC and 8/4 track-and-hold (T/H) inputs. When a
conversion is started, all AIN inputs are simultaneously
sampled. All channels sample whether or not they are
selected for the conversion. Either a single-channel or
multichannel conversion may be requested and channel
configurations may be mixed, ADC results are then stored
in an internal RAM.
To access conversion results, successive RD pulses auto-
matically sence through RAM, beginning with channel 0.
Each RD pulse increments the RAM address counter,
which resets to 0 when WR goes low in multi channel
conversions. An arbitrary RAM location may also be read
by writing a 1 to INH while loading the RAM address (A0–
A2), and then performing a read operation.
In hard-wired mode (see the Multiplexer and AID
Configurations section) multichannel conversions are
initiated with one write operation. In input/output (I/O)
mode, multichannel configurations are set up prior to the
conversion by loading channel selections into the con-
Table 1. Multiplexer Configurations
PIN
NAME
FUNCTION
D0/A0
D1/A1
D2/A2
A0–A2 select a multiple channel for the configurations described below, or select a RAM address
for reading with a subsequent RD.
1 or 0
0
1
0
1
Normal ADC operation
D3/PD
Power-down reduces the power-supply current. Configuration data may be loaded and is
maintained during power-down.
A conversion starts when WR goes high
D4/INH
Inhibits the conversion when WR goes high. Allows mux configuration to be loaded and RAM
locations to be accessed without starting a conversion.
0
1
0
1
Unipolar conversion (Figure 9a) for the channel specified by A0–A2. Input range = 0V to V
.
REF
D5/BIP**
Bipolar conversion (Figure 9b) for the channel specified by A0–A2. Input range = ±V
.
REF
Single-ended configuration for the channel specified by A0–A2 as described in Table 2
Differential contiguration for the channel specified by A0–A2 as described in Table 2
D6/DIFF**
All previously configured channels are converted. Data is read with consecutive RD pulses,
beginning with the lowest configured channel.
0
1
D7/ALL
Only the channel specified by A2–A0 is converted. A single RD pulse reads the result of that
conversion.
•Configuration inputs are shared with data outputs D0-D7. The functions of D0-D7 are not described in this table.
••DIFF and BIP are not implemented on the current conversion, but go into effect on the.following conversion.
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
select from 4 mux configurations as listed inTable 4 (see the
Hard-Wired Mode section).
Multiplexer and A/D Configuration
A conversion is started with a WR pulse. All channels
sample on WR’s falling edge. Mux configuration data is
loaded on WR’s rising edge. In I/O mode (MODE = Open
Circuit), selections for channel number, single or multi-
channel conversion, unipolar or bipolar input, and single-
ended or differential input are made with A0-A2, ALL, BIP,
and DIFF (Table 1). These input pins are also shared with
the RAM data outputs D0–D7. An alternate, simpler inter-
face is provided by the hard-wired mode, which selects
some general mux configurations without requiring ADC
On the rising edge of WR, the mux configuration register
is updated; falling edge initiates sampling of all inputs.
A channel selection can be implemented on the current
conversion, but changes from unipolar to bipolar (with
BIP) or from singleended to differential operation (with
DIFF) do not go into effect until the following WR. This can
be overcome by writing to the configuration register while
inhibiting the conversion (INH = 1), or by changing DIFF
and BIP one conversion early, i.e. on the previous write.
programming. Hard-wired connections of MODE and V
SS
Table 2. Single-Ended Channel Selection (MODE = Open Circuit)
MUX ADDRESS
SINGLE-ENDED CHANNEL SELECTION
A0
0
A1
0
A2
0
DIFF
0
1
2
3
4
5
6
7
AGND
0
0
0
0
0
0
0
0
+
-
-
-
-
-
-
-
-
1
0
0
+
0
1
0
+
1
1
0
+
0
0
1
+
1
0
1
+
0
1
1
+
1
1
1
+
Note: Shaded areas represent MAX156 operation.
Table 3. Differential Channel Selection (MODE = Open Circuit)
MUX ADDRESS
DIFFERENTIAL CHANNEL SELECTION
A0
0
A1
0
A2
0
DIFF
0
1
2
3
4
5
6
7
-
1
1
1
1
1
1
1
1
+
-
0
1
0
+
-
0
0
1
+
-
0
1
1
+
-
1
0
0
-
+
1
1
0
-
+
1
0
1
-
+
1
1
1
+
Note: Shaded areas represent MAX156 operation.
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
The configuration data determines which RAM locations
are sequentially read by consecutive RD pulses, so new
data should be placed in the configuration register only
after a full RD operation. It is not necessary to update the
configuration register for every conversion. A new conver-
sion is initiated with a WR pulse (when INH = 0), regard-
less of the number of channe ls that have been read.
Interface Timing
Input/Output Mode, Multichannel Conversion
Timing
I/O mode is selected when the MODE input is open
circuit. In I/O mode, the mux configuration register deter-
mines the conversion type. The register is updated on the
rising edge of WR.
Figure 4a shows the MAX155 timing for an 8-channel
unipolar configuration. 8 channels are configured and
8 consecutive RD pulses access data. Figure 4b illus-
trates 4-channel differential conversion timing involving
4 sampled channels and 4 RD pulses. In cases where
conflicting differential configurations are loaded, the last
channel selected with DIFF = 1 will be the positive input
of the differential channel.
Table 1 lists all conversion options. For example, at
D6/DIFF, a logic 0 or 1 selects a single-ended or differen-
tial conversion. Data is loaded into addressed locations
in the configuration register with a series of WR pulses.
If INH is high while writing, no conversion takes place. A
conversion is started by writing INH = 0 to the configura-
tion register. When a change is made to the contents of
the configuration register, a “dummy” conversion may be
necessary. This is due to a built-in latency of one full con-
version for unipolar/bipolar and single-ended/differential
selections.
Input/Output Mode, Single-Channel Conver-
sion Timing
Figure 5a shows timing for a single-channel (ALL = 1),
single-ended conversion; Figure 5b shows a differential
conversion. With MODE floating, the configuration reg-
ister is updated on the rising edge of WR. BUSY goes
low at the beginning of the conversion and returns high
when the channel designated by the configuration reg-
ister has been converted. All channels are sampled on
the falling edge of WR even if only a single channel has
been requested. At conversion end, the µP can read the
result for the selected channel with a single RD pulse.
Subsequent RD pulses will access old conversion results
remaining in other RAM locations. The next conversion
is initiated with a WR pulse, regardless of the number of
channels that have been read.
It is not necessary to update the configuration register
before every conversion. A particular mux configuration
must be loaded only once after power-up (but the con-
figuration may require several writes to be loaded). A
mux configuration is retained for successive conversions
and during power-down (PD = 1) so that reconfiguring is
unnecessary when the ADC returns to normal operation
(PD = 0). Configuration and RAM data is lost only when
power is removed from the ADC at V
.
DD
When updating the configuration register, INH should be
high for all except the last WR so the conversion is not
started until the mux is set. On WR’s falling edge, all input
channels sample simultaneously. BUSY goes low at the
beginning of the conversion, and channels are converted
sequentially starting with the lowest selected channel.
When BUSY goes high, conversion results are stored
in RAM. At conversion end, a microprocessor (µP) can
access the RAM contents with consecutive RD pulses.
The first accessed data is the lowest channel’s result.
INH and A0–A2, in the configuration register, access loca-
tions in RAM. INH = 1 allows the RAM address pointer to
be updated without starting a conversion. A READ pulse
then reads the contents of the addressed location.
Subsequent RD pulses access conversion results for the
remaining channels.
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
CS
WR
RD
t
CONV
BUSY
D0-D7
DATA IN
CH0
CH1
CH2
CH3
UPDATE CONFIGURATION
REGISTER AND BEGIN NEW
CONVERSION
THE FIRST RAM
LOCATION READ
IS CH 0
CONSECUTIVE RAM LOCATIONS ARE
CONVERSION END
OF ALL 8 CHANNELS
ACCESSED BY CONSECUTIVE RD PULSES
ALL 8 CHANNELS ARE SAMPLED HERE
NOTE: After power-up, and prior to the above
timing sequence, all single-ended channels must
be set up by writing the following data into the
configuration register. 8 WRs (see Figure 3) are
needed for 8 channels:
Once the above data is loaded, all channels are
converted with a single WR to any address
(this is where the above timing diagram begins).
With INH = 0, and ALL = 0:
A0 A1 A2
PD INH BIP DIFF ALL
A0 A1 A2 PD INH BIP DIFF ALL
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S
S
S
S
S
S
S
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S
0
0
S = May be selected
Figure 4a. Input/Output Mode Timing–Eight Single-Ended Conversions
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
CS
WR
RD
t
CONV
BUSY
D0-D7
DATA IN
0,1
2,3
4,5
6,7
UPDATE CONFIGURATION
REGISTER AND BEGIN NEW
CONVERSION
THE FIRST RAM
LOCATION READ
IS CH 0,1
CONSECUTIVE RAM LOCATIONS ARE
ACCESSED BY CONSECUTIVE RD PULSES
CONVERSION END
OF ALL 4 DIFFERENTIAL CHANNELS
ALL 4 DIFFERENTIAL CHANNELS
ARE SAMPLED HERE
NOTE: After power-up, and prior to the above
timing sequence, all differential channels must
be set up by writing to the configuration register.
(AIN0, 2, 4, 6 are +, and AIN1, 3, 5, 7 are - for
this example). 4 WRs (see Figure 3) are needed
for 8 channels:
Once the above data is loaded, all channels
are converted with a single WR to any address
(this is where the above timing diagram begins).
With INH = 0, and ALL = 0:
A0 A1 A2 PD INH BIP DIFF ALL
0
0
0
0
0
S
0
0
A0 A1 A2 PD INH BIP DIFF ALL
0
1
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1
S
S
S
S
0
0
0
0
0
0
0
0
S = May be selected
Figure 4b. Input/Output Mode Timing–Four Differential Conversions
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
CS
WR
RD
t
CONV
BUSY
D0-D7
DATA IN
DATA OUT
READ DATA INDICATED
BY ADDRESS
UPDATE CONFIGURATION
REGISTER AND BEGIN NEW
CONVERSION
END OF CONVERSION
CHANNEL IS SAMPLED HERE
NOTE: A single-ended channel is converted by writing
the following data into the configuration register
(see Figure 3) The BIP and DIFF bits are not implemented
until the next WR
A0 A1 A2
PD INH BIP DIFF ALL
S
S
S
0
0
S
0
1
S = May be selected
Figure 5a. Input/Output Mode Timing–Single-Channel, Single-Ended Conversion
CS
WR
RD
t
CONV
BUSY
D0-D7
DATA IN
DATA OUT
READ DATA INDICATED
BY ADDRESS
UPDATE CONFIGURATION
REGISTER AND BEGIN NEW
CONVERSION
END OF CONVERSION
CHANNEL IS SAMPLED HERE
NOTE: A differential channel is converted by writing
the following data into the configuration register
(see Figure 3) The BIP and DIFF bits are not
implemented until the next WR
A0
A1
A2
PD INH BIP DIFF ALL
S
S
S
0
0
S
1
1
S = May be selected
Figure 5b. Input/Output Mode Timing–Single-Channel, Differential Conversion
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
CS
WR
RD
t
CONV
BUSY
INH = 0
DATA IN
INH = 1
DATA OUT
INH = 0
DATA IN
DATA OUT
DATA OUT
D0-D7
READ DATA
AT ADDRESS
END OF
CONVERSION
UPDATE CONFIGURATION REGISTER
AND BEGIN NEW CONVERSION
READ DATA INDICATED
BY ADDRESS
UPDATE CONFIGURATION
REGISTER WITH NEW
ADDRESS
UPDATE
CONFIGURATION
REGISTER BEGIN
CONVERSION
ALL CHANNELS ARE
SAMPLED HERE
NOTE: A RAM location is read by writing the following
data into the configuration register and when performing
a RD. If INH = 0, a conversion will begin.
A0 A1 A2 PD INH BIP DIFF ALL
S
S
S
0
1
X
X
1
S = May be selected
X = Don’t Care for this WR if INH = 0, but may effect next conversion.
Figure 6. Input/Output Mode Timing–Reading Arbitrary RAM Locations
Hard-Wired Mode
For simpler applications, the MODE and V pins can be
Table 4. Hard-Wired Mode—Multiplexer
Selections
SS
hard-wired to specify the type of conversion as outlined
in Table 4. In this mode, the configuration register is not
used, so input data on DO-D7 is ignored. For example,
with MODE tied low, an 8-channel, single-ended conver
sion begins with WR With MODE tied high, a 4-channel,
differential conversion is init iated with WR. Again, the
configuration register is not affected by the data present
on 00-07. These conversions are otherwise identical to
those shown in Figure 4.
MODE
V
CONVERSION TYPE
SS
Multiplexer configuration register
determines conversion type. Not
hard-wired.
OPEN
CIRCUIT
X
8-Channel, Single-Ended, Unipolar
Conversion
0
1
0
1
AGND
AGND
-5V
4-Channel, Differential, Unipolar
Conversion
8-Channel, Single-Ended, Bipolar
Conversion
Analog Considerations
lntemal Reference
4-Channel, Differential, Bipolar
Conversion
-5V
The internal 2.5V reference (REFOUT) must be bypassed
to AGND (Figure 8a) with a 4.7µF electrolytic and a 0.1µF
ceramic capacitor to ensure stability.
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
CS
WR
RD
t
CONV
BUSY
D0-D7
CH0
CH1
CH6
CH7
THE FIRST RAM
LOCATION
READ IS CH 0
CONSECUTIVE RAM LOCATIONS ARE
ALL 8 CHANNELS ARE
SAMPLED HERE
END OF CONVERSION
OF 8 CHANNELS
ACCESSED BY CONSECUTIVE RD PULSES
MODE = 0
Figure 7a. Hard-Wired Mode Timing—Eight Single-Ended Conversions
CS
WR
RD
t
CONV
BUSY
0, 1
2, 3
4, 5
6, 7
D0–D7
THE FIRST RAM
LOCATION
READ IS CH 0, 1
CONSECUTIVE RAM LOCATIONS ARE
END OF CONVERSION
OF 4 DIFFERENTIAL
CHANNELS
ALL 4 DIFFERENTIAL CHANNELS
SAMPLED HERE
ACCESSED BY CONSECUTIVE RD PULSES
MODE = 1
Figure 7b. Hard-Wired Mode Timing—Eight Single-Ended Conversions
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
AINx (+)
AINx (-)
AINx
AINx (+)
AINx (-)
AINx
MAX155
MAX156
MAX155
MAX156
+5V
V
DD
+5V
V
47µF
0.1µF
DD
MAX584
+2.5V
47µF
0.1µF
REFOUT
REFIN
REFIN
AGND
4.7µF
0.1µF
4.7µF
0.1µF
V
SS
AGND
REFOUT
4.7µF
V
SS
Figure 8a. Internal Reference
Figure 8b. External Reference, +2.5V Full Scale
Extemal Reference
Bypassing
If an external voltage reference is used at REFIN,
REFOUT must either be bypassed (Figure 8b) or dis-
abled to prevent its output from oscillating and generating
unwanted conversion noise elsewhere in the ADC. If com-
ponent count is critical when using an external reference,
A 47µF electrolytic and a 0.1µF ceramic capacitor should
bypass V to AGND. If input signals below ground are
DD
expected, a negative supply is necessary. In that case,
should be bypassed to AGND with a 4.7µF and
V
SS
0.1µF combination.
REFOUT may be disabled by connecting it to V . In
this case, the unused internal reference does not need a
DD
The internal reference requires a 4.7µF and 0.1µF com-
bination. If an external voltage reference is used, bypass
REFIN to AGND with a 4.7µF capacitor close to the chip.
When an external reference is used, REFOUT must still
bypass cap. A disadvantage of tying REFOUT to V
is
DD
that power-down current will be increased by about 250µA
above the specification limits.
be either bypassed or connected to V
.
DD
Power-Down Mode
Track/Hold Amplifiers
The MAX155/MAX156 may be placed in a powered-down
state by writing a 1 to the PD location in the configuration
register (Table 1). The register may be updated while in
this state (to change mux configurations or exit power-
down mode) and all register contents are retained; how-
ever no data can be read from RAM and no conversions
can be started. The power-down command is implement-
ed on WR’s rising edge.
The MAX155/MAX156 T/H amplifiers’ high input imped-
ance usually requires no input buffering. All T/Hs sample
simultaneously. For best results, the analog inputs should
not exceed the power-supply rails (V , V ) by more
DD
SS
than 50mV.
The time required for the T/H to acquire an input signal
for one channel is a function of how quickly the channel
input capacitance is charged. If the source impedance of
the input signal is high, acquisition takes longer, and more
time must be allowed between conversions. Acquisition
time is calculated by:
To minimize current drain, the MAX155/MAX156 inter-
nal reference is turned off during power-down. When
returning to normal operation (PD = 0), up to 5ms may
be needed to allow the reference to recharge its 4.7µF
bypass capacitor before a conversion is performed. If an
external reference is used, and remains on during power-
down, a conversion can be started within 50µs after load-
ing PD with a 0.
t
= 8(R + R ) x 4pF (but never less than 800ns)
S IN
ACQ
where R = 15kΩ, and R = source impedance of the
IN
S
ADC’s input signal.
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Applications Information
OUTPUT
CODE
9-Bit A/D Conversion
In I/O mode, a 9th bit of resolution can be created by per-
forming two unipolar differential conversions with opposite
input polarities (i.e., first with AIN0[+] and AIN1[-], then with
AINO[-] and AIN1[+]). Only the A0 bit must be changed to
reverse input channel polarity (Table 3). The sign reversal
also occurs on the current write without a one conversion
delay. For a differential input signal, one of the two conver-
sions will read 0 while the other will contain an 8-bit result.
The input polarity that provides the 8-bit result indicates
the 9th (sign) bit. 4 channels can be measured this way. A
major drawback of this technique is that many of the sam-
pling features of the MAX155/MAX156 are defeated since
two separate samples are needed
(FS - 3/2 LSB)
1111 1111
1111 1110
1111 1101
FS = V
REF
FS
1 LSB =
256
0000 0011
0000 0010
0000 0001
0000 0000
01 LSB 3 LSBs
2 LSBs
AIN
FS - 1 LSB
FS
AIN, INPUT VOLTAGE (LSB)
If only two 9-bit channels are needed, then two separate
differential channels with reversed input polarities can be
connected so that both input pairs sample at the same
time. This way the simultaneoussampling advantages of
the MAX155/MAX156 are retained.
Figure 9a. Transfer Function—Unipolar Operation
OUTPUT
CODE
Typical I/O Mode Application
0111 1111
0111 1110
The MAX155/MAX156 address and configuration inputs
for this example were determined by selecting the desired
channel configurations in Tables 2 and 3. Figure 10 illus-
trates the configuration outlined in Table 5.
0000 0010
0000 0001
-1/2 LSB
Table 5. Typical Multiplexer Configuration
AIN
0000 0000
+FS - 1 LSB
+1/2 LSB
1111 1111
A2 A1 A0
DIFF
BIP
FUNCTION
FS = 2V
1 LSB =
REF
FS
1111 1110
Channel (1, 0) Differential
Bipolar
256
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1000 0001
1000 0000
Channel 2 Single-Ended,
Unipolar
0
0
0
0
1
0
1
1
0
0
Channel 3 Single-Ended,
Bipolar
Channel 4 Single-Ended,
Bipolar
Figure 9b. Transfer Function—Bipolar Operation
Conversion Time
Conversion time is calculated by:
Channel 5 Single-Ended,
Unipolar
t
= (9 x N x 2)/f
CLK
Channel (6. 7)
Differential, Unipolar
CONV
where N is the number of channels converted. This
includes one clock cycle of uncertainty. For a single
channel and 5MHz clock, the conversion time is (9 x 1 x
2)/5MHz = 3.6µs. For the MAX155, the maximum conver-
sion time for 8 channels is (9 x 8 x 2)/5MHz = 28.8µs. In
the application example (Figure 10), six conversions are
configured, and the conversion time is (9 x 6 x 2}/5MHz
= 21.6µs.
An A/D conversion in I/O mode involves the following
steps:
1) Configure the mux by loading data into the con-
figuration register based on selections from Table 2
and/or 3 (with INH = 1 and MODE = open circuit).
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
For this example, 6 write operations (with each
address and data setting in Table 5 above) load the
mux after power-up.
When the conversion starts, BUSY goes low while all
selected channels are sequentially converted. Conversion
results are stored in RAM and are ready to read when
BUSY returns high.
2) Sample all selected channels with a WR pulse (and
INH = 0), and update or rewrite any one location of
the configuration register.
3) Data is read from RAM with INH = L and consecutive
RD strobes. Note that in the 6 channel configurations
described in this example (Figure 10), 6 RD pulses
access all available data, start with the differential
channel (1, 0). Additional RD pulses loop around,
accessing the lowest channel data again.
This write operation may be skipped by loading INH with a
0 on the last WR of the above step. The conversion then
starts on the 6th WR. DIFF and SIP cannot be changed
on the 6th WR in the conversion is started at that time.
4) To start a new conversion cycle with the same mux
configuration, repeat steps 2 and 3.
+5V
+24
0.1µF
0.1µF
47µF
47µF
V
DD
AIN
(-) 3
(1)
21
22
DIFFERENTIAL
BIPOLAR
REFOUT
REFIN
(+) 4
2
(0)
(2) BIPOLAR
MAX155
11
5
CLK
MODE
CS
CLOCK
1
(3) BIPOLAR
(4) BIPOLAR
7
28
8
RD
27
9
SENSOR
(5) BIPOLAR
(6)
WR
10
BUSY
(+) 26
20...15, 13, 12
8
DIFFERENTIAL
UNIPOLAR
2.5V
D0–D7
DATA I/0 LINES
(-) 25
(7)
-1.75V
AGND
23
DGND
14
V
SS
6
-5V
47µF
0.1µF
Figure 10. MAX155/MAX156 Typical Operating Circuit
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PIN-
PACKAGE
ERROR
(LSBs)
PART
TEMP RANGE
MAX155ACPI+
MAX155BCPI+
MAX155ACWI+
MAX155BCWI+
MAX155BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
28 PDIP
28 PDIP
±½
±1
LAND
PATTERN
NO.
28 Wide SO
28 Wide SO
Dice*
±½
±1
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
±1
24 PDIP
28 PDIP
N24+8
P28+7
W28+3
21-0043
21-0044
21-0042
—
—
MAX155AEPI+
MAX155BEPI+
MAX155AEWI+
MAX155BEWI+
MAX156ACNG+
MAX156BCNG+
MAX156ACWI+
MAX156BCWI+
MAX156BC/D
-40°C to +85°C 28 PDIP
-40°C to +85°C 28 PDIP
-40°C to +85°C 28 Wide SO
-40°C to +85°C 28 Wide SO
±½
±1
28 Wide SO
90-0109
±½
±1
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
24 PDIP
24 PDIP
±½
±1
Chip Information
PROCESS: BiCMOS
28 Wide SO
28 Wide SO
Dice*
±½
±1
±1
MAX156AENG+
MAX156BENG+
MAX156AEWI+
MAX156BEWI+
-40°C to +85°C 24 PDIP
-40°C to +85°C 24 PDIP
-40°C to +85°C 28 Wide SO
-40°C to +85°C 28 Wide SO
±½
±1
±½
±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Contact factory for dice specifications.
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MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
2
11/91
6/94
1/12
Initial release
—
16
Revised Figure 9a
Removed military grade packages and updated stylistic changes
1–5, 18–20
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2012 Maxim Integrated Products, Inc.
│ 20
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