MAX1586CETM [MAXIM]
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones; 高效率，低IQ PMIC，带有动态内核，用于PDA和智能电话
| 型号： | MAX1586CETM |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones |
| 文件： | 总30页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3089; Rev 4; 4/09
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
General Description
Features
The MAX1586/MAX1587 power-management ICs are
optimized for devices using Intel XScale® microproces-
sors, including Smart Phones, PDAs, internet appli-
ances, and other portable devices requiring substantial
computing and multimedia capability at low power.
♦ Six Regulators in One Package
Step-Down DC-DC for I/O at 1.3A
Step-Down DC-DC for Memory at 0.9A
Step-Down Serial-Programmed DC-DC for CORE
Up to 0.9A
The ICs integrate seven high-performance, low-operating-
current power supplies along with supervisory and
management functions. Included are three step-down
DC-DC outputs, three linear regulators, and a seventh
always-on output. DC-DC converters power I/O, DRAM,
and the CPU core. The I/O supply can be preset to
3.3V or adjusted to other values. The DRAM supply on
the A and C devices is preset for 1.8V or 2.5V, while the
MAX1586B DRAM supply is preset for 3.3V or 2.5V. The
DRAM supply on all parts can also be adjusted with
external resistors. The CPU core supply is serial pro-
grammed for dynamic voltage management and, on C
devices, can supply up to 0.9A. Linear-regulated out-
puts are provided for SRAM, PLL, and USIM supplies.
Three LDO Outputs for SRAM, PLL, and USIM
Always-On Output for VCC_BATT
♦ Low Operating Current
60µA in Sleep Mode (Sleep LDOs On)
130µA with DC-DCs On (Core Off)
200µA All Regulators On, No Load
5µA Shutdown Current
♦ Optimized for XScale Processors
♦ Backup-Battery Input
♦ 1MHz PWM Switching Allows Small External
Components
♦ Tiny 6mm x 6mm, 40-Pin and 7mm x 7mm, 48-Pin
To minimize quiescent current, critical power supplies
have bypass “sleep” LDOs that can be activated when
output current is very low. Other functions include sep-
arate on/off control for all DC-DC converters, low-bat-
tery and dead-battery detection, a reset and power-OK
output, a backup-battery input, and a two-wire serial
interface.
Thin QFN Packages
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1586AETM -40°C to +85°C 48 Thin QFN 7mm x 7mm
MAX1586BETM -40°C to +85°C 48 Thin QFN 7mm x 7mm
MAX1586CETM -40°C to +85°C 48 Thin QFN 7mm x 7mm
MAX1587AETL -40°C to +85°C 40 Thin QFN 6mm x 6mm
MAX1587CETL -40°C to +85°C 40 Thin QFN 6mm x 6mm
All DC-DC outputs use fast, 1MHz PWM switching and
small external components. They operate with fixed-fre-
quency PWM control and automatically switch from
PWM to skip-mode operation at light loads to reduce
operating current and extend battery life. The core out-
put can be forced into PWM mode at all loads to mini-
mize noise. A 2.6V to 5.5V input voltage range allows
1-cell lithium-ion (Li+), 3-cell NiMH, or a regulated 5V
input. The MAX1587 is available in a tiny 6mm x 6mm,
40-pin thin QFN package. The MAX1586 features an
additional linear regulator (V6) for VCC_USIM and low-
battery and dead- battery comparators. The MAX1586
is available in a 7mm x 7mm, 48-pin thin QFN package.
Pin Configurations and Selector Guide appear at end of
data sheet.
Simplified Functional Diagram
MAIN BATTERY
IN MAX1586
MAX1587
BACKUP
BATTERY
VCC_IO 3.3V
V1
V2
V3
BKBT
Applications
VCC_MEM 2.5V
PDA, Palmtop, and Wireless Handhelds
Third-Generation Smart Cell Phones
Internet Appliances and Web-Books
VCC_CORE
0.8V TO 1.3V
MR
VCC_PLL 1.3V
V4
V5
RSO
nRESET
nVCC_FAULT
nBATT_FAULT
SYS_EN
POK
DBO
VCC_SRAM 1.1V
VCC_USIM
0V, 1.8V, 3.0V
V6
V7
ON1-2
ON3-6
PWR_EN
VCC_BATT
Intel XScale is a registered trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
ABSOLUTE MAXIMUM RATINGS
LX3 Continuous Current........................................-0.9A to +0.9A
PG1, PG2, PG3 to GND.........................................-0.3V to +0.3V
V1, V2, V4, V5, V6 Output Short-Circuit Duration.......Continuous
IN, IN45, IN6, MR, LBO, DBO, RSO, POK, SCL, SDA,
BKBT, V7, SLP, SRAD, PWM3 to GND...............-0.3V to +6V
REF, CC_, ON_, FB_, DBI, LBI, V1, V2, RAMP, BYP,
Continuous Power Dissipation (T = +70°C)
MR to GND ...........................................-0.3V to (V + 0.3V)
PV1, PV2, PV3, SLPIN to IN...................................-0.3V to +0.3V
A
IN
6mm x 6mm 40-Pin Thin QFN
(derate 26.3mW/°C above +70°C)...........................2105mW
7mm x 7mm 48-Pin Thin QFN
V4, V5 to GND ..........................................-0.3V to (V
V6 to GND ..................................................-0.3V to (V
+ 0.3V)
+ 0.3V)
IN45
IN6
(derate 26.3mW/°C above +70°C)...........................2105mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PV1 to PG1 ............................................................-0.3V to +6.0V
PV2 to PG2 ............................................................-0.3V to +6.0V
PV3 to PG3 ............................................................-0.3V to +6.0V
LX1 Continuous Current....................................-1.30A to +1.30A
LX2 Continuous Current........................................-0.9A to +0.9A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 3.6V, V
= 3.0V, V
= 1.1V, V
= 1.35V, circuit of Figure 5, T = 0°C to +85°C, unless otherwise noted. Typical values
DBI A
IN
BKBT
LBI
are at T = +25°C.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
PV1, PV2, PV3, SLPIN, IN Supply
Voltage Range
PV1, PV2, PV3, IN, and SLPIN must connect together
externally
2.6
5.5
V
V
V
IN45, IN6 Supply Voltage Range
2.4
2.25
2.200
5.5
2.55
2.525
V
V
rising
falling
2.40
2.35
32
IN
IN
IN Undervoltage-Lockout (UVLO)
Threshold
MAX1586
MAX1587
MAX1586
MAX1587
MAX1586
MAX1587
MAX1586
MAX1587
Only V7 on, V below
DBI threshold V = 3.0V
IN
IN
5
130
130
60
REG1 and REG2 on in
switch mode, REG3 off
No load (I
+
+ I
IN
+
PV1
I
I
I
+ I
+ I
+
PV2
SLPIN
PV3
Quiescent Current
µA
IN45
REG1 and REG2 on in
sleep mode, REG3 off
)
IN6
60
225
200
4
All REGs on
ON1 = 0
ON1 = IN
0 to 10µA load
BKBT Input Current
µA
V
0.8
REF Output Voltage
1.2375 1.25 1.2625
SYNCHRONOUS-BUCK PWM REG1
REG1 Voltage Accuracy
FB1 = GND, 3.6V ≤ V
≤ 5.5V, load = 0 to 1300mA
3.25
3.3
3.35
1.269
100
V
V
PV1
FB1 used with external resistors, 3.6V ≤ V
load = 0 to 1300mA
≤ 5.5V,
PV1
FB1 Voltage Accuracy
1.231
1.25
FB1 Input Current
FB1 used with external resistors
Referred to FB
nA
µS
Error-Amplifier Transconductance
87
Load = 800mA
180
293
280
450
Dropout Voltage (Note 1)
mV
Load = 1300mA
B6/MAX1587C
2
_______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.6V, V
= 3.0V, V
= 1.1V, V
= 1.35V, circuit of Figure 5, T = 0°C to +85°C, unless otherwise noted. Typical values
DBI A
IN
BKBT
LBI
are at T = +25°C.)
A
PARAMETER
CONDITIONS
MIN
TYP
0.18
0.21
0.13
0.15
0.5
MAX UNITS
I
I
I
I
= -180mA
0.3
Ω
LX1
LX1
LX1
LX1
p-Channel On-Resistance
n-Channel On-Resistance
= -180mA, V
= 180mA
= 2.6V
0.35
PV1
0.225
Ω
= 180mA, V
= 2.6V
0.25
PV1
Current-Sense Transresistance
V/A
p-Channel Current-Limit Threshold
-1.55 -1.80 -2.10
A
PWM Skip-Mode Transition Load
Current
Decreasing load current (Note 2)
2.6V ≤ V ≤ 5.5V (Note 3)
30
mA
OUT1 Maximum Output Current
LX1 Leakage Current
1.3
A
PV1
V
= 5.5V, LX1 = GND or PV1, V
= 0V
-20
+0.1
+20
µA
PV1
ON1
SYNCHRONOUS-BUCK PWM REG2
FB2 = GND, 3.6V ≤ V
≤ 5.5V, load = 0 to 900mA
2.463
1.773
2.5
1.8
2.537
1.827
PV2
MAX1586A, MAX1587A, FB2 = IN, 3.6V ≤ V
load = 0 to 900mA
≤ 5.5V,
PV2
REG2 Voltage Accuracy
V
V
MAX1586B, FB2 = IN, 3.6V ≤ V
load = 0 to 900mA
≤ 5.5V,
PV2
3.25
3.3
3.35
FB2 used with external resistors, 3.6V ≤ V
load = 0 to 900mA
≤ 5.5V,
PV2
FB2 Voltage Accuracy
1.231
1.25
1.269
100
FB2 Input Current
FB2 used with external resistors, V
Referred to FB
= 1.25V
nA
µS
FB2
Error-Amplifier Transconductance
Dropout Voltage
87
Load = 900mA (Note 1)
243
380
mV
I
I
I
I
= -180mA
= -180mA, V
= 180mA
0.225 0.375
LX2
LX2
LX2
LX2
p-Channel On-Resistance
n-Channel On-Resistance
Ω
Ω
= 2.6V
0.26
0.15
0.17
0.7
0.425
0.25
PV2
= 180mA, V
= 2.6V
0.275
PV2
Current-Sense Transresistance
V/A
A
p-Channel Current-Limit Threshold
-1.1 -1.275 -1.50
PWM Skip-Mode Transition Load
Current
Decreasing load current (Note 2)
2.6V ≤ V ≤ 5.5V (Note 3)
30
mA
OUT2 Maximum Output Current
LX2 Leakage Current
0.9
A
PV2
V
= 5.5V, LX2 = GND or PV2, V
= 0V
-10
+0.1
+10
µA
PV2
ON2
SYNCHRONOUS-BUCK PWM REG3
MAX1586A, MAX1586B, MAX1587A,
load = 0 to 500mA
-1.5
-1.5
+1.5
+1.5
REG3 from 0.7V to
1.475V, 2.6V ≤
REG3 Output Voltage Accuracy
Error-Amplifier Transconductance
%
MAX1586C, MAX1587C,
load = 0 to 900mA
V
≤ 5.5V
PV3
68
µS
_______________________________________________________________________________________
3
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.6V, V
= 3.0V, V
= 1.1V, V
= 1.35V, circuit of Figure 5, T = 0°C to +85°C, unless otherwise noted. Typical values
DBI A
IN
BKBT
LBI
are at T = +25°C.)
A
PARAMETER
CONDITIONS
= 2.6V
MIN
TYP
MAX UNITS
I
I
I
I
= -180mA
0.225 0.375
LX3
LX2
LX3
LX3
p-Channel On-Resistance
n-Channel On-Resistance
Ω
Ω
= -180mA, V
= 180mA
0.26
0.15
0.17
1.1
0.425
0.25
PV3
= 180mA, V
= 2.6V
0.275
PV3
MAX1586A, MAX1586B, MAX1587A
MAX1586C, MAX1587C
Current-Sense Transresistance
V/A
A
0.55
-0.7
MAX1586A, MAX1586B, MAX1587A
MAX1586C, MAX1587C
-0.60
-0.85
p-Channel Current-Limit Threshold
-1.125 -1.35 -1.700
PWM Skip-Mode Transition Load
Current
Decreasing load current (Note 2)
30
mA
MAX1586A, MAX1586B, MAX1587A
MAX 1586C, MAX1587C
0.5
0.9
2.6V ≤ V
(Note 3)
≤ 5.5V
PV3
OUT3 Maximum Output Current
LX3 Leakage Current
A
V
= 5.5V, LX3 = GND or PV2, V
= 0V
ON3
-10
+0.1
+10
µA
PV3
LDOS V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT
V4, V5, V6, V1 SLEEP, V2 SLEEP
Output Current
35
mA
V7 Output Current
30
mA
REG4 Output Voltage
REG4 Noise
Load = 0.1mA to 35mA
With 1µF C and 0.01µF C
1.261
1.3
15
1.339
V
µVRMS
OUT
BYP
REG5 Output Voltage
IN45, IN6 Input Voltage Range
Load = 0.1mA to 35mA
1.067
2.4
1.1
1.133
5.5
V
V
0V setting (either ON6 low or serial programmed)
1.8V setting, load = 0.1mA to 35mA
2.5V setting, load = 0.1mA to 35mA
3.0V setting, load = 0.1mA to 35mA
0
1.746
2.425
2.91
1.8
2.5
3.0
1.854
2.575
3.09
REG6 Output Voltage (POR Default
to 0V, Set by Serial Input)
MAX1586
V
V1 on and in regulation
V1 off
V
V1
V7 Output Voltage
V
V
BKBT
V1 and V2 SLEEP Output Voltage
Accuracy
Set to same output voltage as REG1 and REG2
-3.0
+3.0
%
V1 and V2 SLEEP Dropout Voltage
V6 Dropout Voltage
LOAD = 20mA
75
110
100
90
150
200
200
mV
mV
mV
mA
µA
MAX1586 3V mode, load = 30mA, 2.5V mode, load = 30mA
V7 Switch Voltage Drop
V4, V5, V6 Output Current Limit
BKBT Leakage
LOAD = 20mA, V
= V = 3.0V
BKBT V1
40
1
OSCILLATOR
PWM Switching Frequency
0.93
1
1.07
MHz
%
SUPERVISORY/MANAGEMENT FUNCTIONS
Rising
POK Trip Threshold (Note 4)
Falling
92
94.75
90.5
97
88.5
92.5
B6/MAX1587C
4
_______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.6V, V
= 3.0V, V
= 1.1V, V
= 1.35V, circuit of Figure 5, T = 0°C to +85°C, unless otherwise noted. Typical values
DBI A
IN
BKBT
LBI
are at T = +25°C.)
A
PARAMETER
CONDITIONS
LBI = IN (for preset)
MIN
3.51
TYP
3.6
MAX UNITS
3.69
V
MAX1586 hysteresis is
5% (typ)
LBI Threshold (Falling)
DBI Threshold (Falling)
With resistors at LBI
DBI = IN (for preset)
With resistors at LBI
0.98
1.00
3.15
1.02
3.024
3.276
V
MAX1586 hysteresis is
5% (typ)
1.208 1.232 1.256
RSO Threshold (Falling)
RSO Deassert Delay
LBI Input Bias Current
DBI Input Bias Current
Voltage on REG7, hysteresis is 5% (typ)
2.25
61
2.41
65.5
-5
2.56
70
V
ms
nA
nA
°C
°C
MAX1586
MAX1586
-50
15
50
Thermal-Shutdown Temperature
Thermal-Shutdown Hysteresis
LOGIC INPUTS AND OUTPUTS
T rising
J
+160
15
LBO, DBO, POK, RSO, SDA Output
Low Level
2.6V ≤ V7 ≤ 5.5V, sinking 1mA
V7 = 1V, sinking 100µA
Pin = 5.5V
0.4
0.4
0.2
V
V
LBO, DBO, POK, RSO Output Low
Level
LBO, DBO, POK, RSO Output-High
Leakage Current
µA
V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input High Level
2.6V ≤ V ≤ 5.5V
1.6
-1
IN
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Low Level
2.6V ≤ V ≤ 5.5V
0.4
+1
V
IN
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Leakage Current
Pin = GND, 5.5V
µA
SERIAL INTERFACE
Clock Frequency
400
kHz
µs
Bus-Free Time Between START and
STOP
1.3
Hold Time Repeated START Condition
CLK Low Period
0.6
1.3
0.6
0.6
0
µs
µs
µs
µs
µs
ns
CLK High Period
Setup Time Repeated START Condition
DATA Hold Time
DATA Setup Time
100
Maximum Pulse Width of Spikes that
Must be Suppressed by the Input
Filter of Both DATA and CLK Signals
50
ns
µs
Setup Time for STOP Condition
0.6
_______________________________________________________________________________________
5
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
ELECTRICAL CHARACTERISTICS
(V = 3.6V, V
IN
= 3.0V, V
= 1.1V, V
= 1.35V, circuit of Figure 5, T = -40°C to +85°C, unless otherwise noted.) (Note 5)
DBI A
BKBT
LBI
PARAMETER
CONDITIONS
MIN
MAX UNITS
PV1, PV2, PV3, SLPIN, IN Supply
Voltage Range
PV1, PV2, PV3, IN, and SLPIN must connect together
externally
2.6
5.5
V
V
V
IN45, IN6 Supply Voltage Range
2.4
2.25
2.200
5.5
2.55
2.525
V
V
rising
falling
IN
IN
IN Undervoltage-Lockout (UVLO)
Threshold
SYNCHRONOUS-BUCK PWM REG1
FB1 = GND, 3.6V ≤ V
≤ 5.5V, load = 0 to 1300mA
3.25
3.35
PV1
REG1 Voltage Accuracy
V
FB1 = IN, 3.6V ≤ V
≤ 5.5V, load = 0 to 1300mA
2.955
3.045
PV1
FB1 used with external resistors, 3.6V ≤ V
load = 0 to 1300mA
≤ 5.5V,
PV1
FB1 Voltage Accuracy
FB1 Input Current
Dropout Voltage
1.231
1.269
V
FB1 used with external resistors
Load = 800mA (Note 1)
100
280
nA
mV
Load = 1300mA (Note 1)
450
I
I
I
I
= -180mA
= -180mA, V
= 180mA
0.3
LX1
LX1
LX1
LX1
p-Channel On-Resistance
n-Channel On-Resistance
Ω
Ω
= 2.6V
0.35
0.225
0.25
-2.10
PV1
PV1
= 180mA, V
= 2.6V
p-Channel Current-Limit Threshold
OUT1 Maximum Output Current
LX1 Leakage Current
-1.55
1.30
-10
A
A
2.6V ≤ V
≤ 5.5V (Note 3)
PV1
V
= 5.5V, LX1 = GND or PV1, V
= 0V
+10
µA
PV1
ON1
SYNCHRONOUS-BUCK PWM REG2
FB2 = GND, 3.6V ≤ V
≤ 5.5V, load = 0 to 900mA
2.463
1.773
2.537
1.827
PV2
MAX1586A, MAX1587A, FB2 = IN, 3.6V ≤ V
load = 0 to 900mA
≤ 5.5V,
PV2
REG2 Voltage Accuracy
V
V
MAX1586B, FB2 = IN, 3.6V ≤ V
load = 0 to 900mA
≤ 5.5V,
PV2
3.25
3.35
FB2 used with external resistors, 3.6V ≤ V
load = 0 to 900mA
≤ 5.5V,
PV2
FB2 Voltage Accuracy
1.231
1.269
FB2 Input Current
Dropout Voltage
FB2 used with external resistors, V
Load = 900mA (Note 1)
= 1.25V
100
380
nA
FB2
mV
I
I
I
I
= -180mA
0.375
0.425
0.25
LX2
LX2
LX2
LX2
p-Channel On-Resistance
n-Channel On-Resistance
Ω
Ω
= -180mA, V
= -180mA
= 2.6V
= 2.6V
PV2
= -180mA, V
0.275
-1.50
PV2
p-Channel Current-Limit Threshold
OUT2 Maximum Output Current
LX2 Leakage Current
-1.1
0.9
-10
A
A
2.6V ≤ V
≤ 5.5V (Note 3)
PV2
V
= 5.5V, LX2 = GND or PV2, V
= 0V
+10
µA
PV2
ON2
B6/MAX1587C
6
_______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.6V, V
IN
= 3.0V, V
= 1.1V, V
= 1.35V, circuit of Figure 5, T = -40°C to +85°C, unless otherwise noted.) (Note 5)
DBI A
BKBT
LBI
PARAMETER
CONDITIONS
MIN
MAX UNITS
SYNCHRONOUS-BUCK PWM REG3
MAX1586A, MAX1586B, MAX1587A,
load = 0 to 500mA
-1.5
-1.5
+1.5
%
REG3 from 0.7V to
1.475V, 2.6V ≤
REG3 Output Voltage Accuracy
MAX1586C, MAX1587C,
load = 0 to 900mA
V
≤ 5.5V
PV3
+1.5
I
I
I
I
= -180mA
= -180mA, V
= 180mA
0.375
Ω
LX3
LX2
LX3
LX3
p-Channel On-Resistance
= 2.6V
= 2.6V
0.425
PV3
0.25
Ω
n-Channel On-Resistance
= 180mA, V
0.275
PV3
MAX1586A, MAX1586B, MAX1587A
MAX1586C, MAX1587C
-0.60
-1.125
0.5
-0.85
A
p-Channel Current-Limit Threshold
-1.700
MAX1586A, MAX1586B, MAX1587A
MAX1586C, MAX1587C
2.6V ≤ V
(Note 3)
≤ 5.5V
PV3
OUT3 Maximum Output Current
LX3 Leakage Current
A
0.9
V
= 5.5V, LX3 = GND or PV2, V
= 0V
-10
+10
µA
PV3
ON3
LDOs V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT
V4, V5, V6, V1 SLEEP, V2 SLEEP
Output Current
35
mA
V7 Output Current
30
mA
V
REG4 Output Voltage
Load = 0.1mA to 35mA
Load = 0.1mA to 35mA
1.254
1.061
2.4
1.346
1.139
5.5
REG5 Output Voltage
V
IN45, IN6 Input Voltage Range
V
1.8V setting, load = 0.1mA to 35mA
2.5V setting, load = 0.1mA to 35mA
3.0V setting, load = 0.1mA to 35mA
1.737
2.412
2.895
1.863
2.588
3.105
REG6 Output Voltage (POR Default
to 0V, Set by Serial Input)
MAX1586
V
V1 and V2 SLEEP Output Voltage
Accuracy
Set to same output voltage as REG1 and REG2
-3.5
+3.5
%
V1 and V2 SLEEP Dropout Voltage
V6 Dropout Voltage
Load = 20mA
150
200
200
mV
mV
mV
mA
µA
MAX1586 3V mode, load = 30mA; 2.5V mode, load = 30mA
V7 Switch Voltage Drop
V4, V5, V6 Output Current Limit
BKBT Leakage
Load = 20mA, V
= V = 3.0V
BKBT V1
40
1
OSCILLATOR
PWM Switching Frequency
0.93
1.07
MHz
SUPERVISORY/MANAGEMENT FUNCTIONS
Rising
POK Trip Threshold (Note 4)
Falling
92
97
%
V
88.5
3.51
0.98
92.5
3.69
1.02
LBI = IN (for preset)
With resistors at LBI
MAX1586,
LBI Threshold (Falling)
hysteresis is 5% (typ)
_______________________________________________________________________________________
7
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
ELECTRICAL CHARACTERISTICS (continued)
(V = 3.6V, V
IN
= 3.0V, V
= 1.1V, V
= 1.35V, circuit of Figure 5, T = -40°C to +85°C, unless otherwise noted.) (Note 5)
DBI A
BKBT
LBI
PARAMETER
CONDITIONS
DBI = IN (for preset)
With resistors at LBI
MIN
2.993
1.208
2.25
62
MAX UNITS
3.307
V
MAX1586,
hysteresis is 5% (typ)
DBI Threshold (Falling)
1.256
RSO Threshold (Falling)
RSO Deassert Delay
LBI Input Bias Current
DBI Input Bias Current
Voltage on REG7, hysteresis is 5% (typ)
2.60
69
V
ms
nA
nA
MAX1586
MAX1586
-50
75
LOGIC INPUTS AND OUTPUTS
LBO, DBO, POK, RSO, SDA Output
Low Level
2.6V ≤ V7 ≤ 5.5V, sinking 1mA
V7 = 1V, sinking 100µA
Pin = 5.5V
0.4
0.4
0.2
V
V
LBO, DBO, POK, RSO, SDA Output
Low Level
LBO, DBO, POK, RSO Output-High
Leakage Current
µA
V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input High Level
2.6V ≤ V ≤ 5.5V
1.6
-1
IN
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Low Level
2.6V ≤ V ≤ 5.5V
0.4
+1
V
IN
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Leakage Current
Pin = GND, 5.5V
µA
SERIAL INTERFACE
Clock Frequency
400
kHz
µs
Bus-Free Time Between START and
STOP
1.3
0.6
Hold Time Repeated START
Condition
µs
CLK Low Period
CLK High Period
1.3
0.6
µs
µs
Setup Time Repeated START
Condition
0.6
µs
DATA Hold Time
0
µs
ns
µs
DATA Setup Time
100
0.6
Setup Time for STOP Condition
B6/MAX1587C
8
_______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
ELECTRICAL CHARACTERISTICS (continued)
Note 1: Dropout voltage is guaranteed by the P-channel switch resistance and assumes a maximum inductor resistance of 45mΩ.
Note 2: The PWM-skip-mode transition has approximately 10mA of hysteresis.
Note 3: The maximum output current is guaranteed by the following equation:
VOUT (1 − D)
2 x f x L
ILIM
−
IOUTmax
=
(1 − D)
2 x f x L
1 + (RN + RL)
where:
VOUT + IOUT(MAX) (RN + RL)
VIN + IOUT(MAX) (RN − RP)
D =
and
R = N-channel synchronous rectifier R
N DS(ON)
R = P-channel power switch R
P
DS(ON)
R = external inductor ESR
L
I
= maximum required load current
OUT(MAX)
f = operating frequency minimum
L = external inductor value
I
can be substituted for I
(desired) when solving for D. This assumes that the inductor ripple current is
LIM
OUT(MAX)
small relative to the absolute value.
Note 4: POK only indicates the status of supplies that are enabled (except V7). When a supply is turned off, POK does not trigger
low. When a supply is turned on, POK immediately goes low until that supply reaches regulation. POK is forced low when all
supplies (except V7) are disabled.
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
_______________________________________________________________________________________
9
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
Typical Operating Characteristics
(Circuit of Figure 6, V = 3.6V, T = +25°C, unless otherwise noted.)
IN
A
REG2 2.5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
REG3 1.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
REG1 3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
100
90
80
70
60
50
40
100
90
80
70
60
50
40
100
90
80
70
60
50
40
V
= 3.6V
IN
V
IN
= 3.6V
V
= 3.6V
IN
V
IN
= 4.0V
V
IN
= 4.0V
V
IN
= 5.0V
V
IN
= 5.0V
V
IN
= 4.0V
V = 5.0V
IN
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000 10,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
REG3 1.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
REG3 1.3V OUTPUT WITH FORCED-PWM
EFFICIENCY vs. LOAD CURRENT
REG3 1.3V OUTPUT WITH FORCED-PWM
EFFICIENCY vs. LOAD CURRENT
100
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
L3 = 4.7μH
C17 = 44μF
90
80
70
60
50
40
30
V
IN
= 3.6V
V
= 3.6V
IN
V
IN
= 3.6V
MAX1586C
MAX1587C
V
IN
= 5.0V
V
IN
= 5.0V
V
IN
= 5.0V
V
= 4.0V
IN
V
= 4.0V
IN
V
= 4.0V
IN
L3 = 4.7μH
C17 = 44μF
MAX1586C
MAX1587C
20
10
20
10
0.1
1
10
100
1000
0.1
1
10
LOAD CURRENT (mA)
100
1000
0.1
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
REG1 SLEEP LDO 3.3V OUTPUT
EFFICIENCY vs. LOAD CURRENT
REG2 SLEEP LDO 2.5V OUTPUT
EFFICIENCY vs. LOAD CURRENT
QUIESCENT CURRENT
vs. SUPPLY VOLTAGE
100
90
80
70
60
50
40
90
80
70
60
50
40
30
220
200
180
160
140
BKBT BIASED AT 3.6V
V
= 4.0V
IN
V
= 3.6V
IN
V1, V2, AND V3 ON
V1 AND V2 ON
V
= 3.6V
V = 4.0V
IN
IN
V
= 5.0V
IN
120
100
80
60
40
20
0
V1 ON
V1 AND V2 SLEEP
V1 SLEEP
V
= 5.0V
IN
ALL BUT V7 OFF
0.1
1
10
0.1
1
10
0
1
2
3
4
5
LOAD CURRENT (mA)
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
B6/MAX1587C
10 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
Typical Operating Characteristics (continued)
(Circuit of Figure 6, V = 3.6V, T = +25°C, unless otherwise noted.)
IN
A
DROPOUT VOLTAGE
vs. LOAD CURRENT
CHANGE IN OUTPUT VOLTAGE
vs. LOAD CURRENT
300
250
200
150
100
200
150
100
50
REG1 3.3V OUTPUT
REG2 2.5V OUTPUT
REG3 1.3V OUTPUT
0
REG1 3.3V OUTPUT
50
0
-50
V
IN
= 3.6V
-100
0
200
400
600
800 1000 1200
0
200
400
600
800 1000 1200
LOAD CURRENT (mA)
LOAD CURRENT (mA)
REFERENCE VOLTAGE
vs. TEMPERATURE
SWITCHING FREQUENCY
vs. SUPPLY VOLTAGE
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1040
1000
960
T
= +85°C
A
T
A
= +25°C
T
A
= -40°C
920
1.230
1.225
880
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
°
TEMPERATURE ( C)
INPUT VOLTAGE (V)
REG1 SWITCHING WAVEFORMS
WITH 10mA LOAD
REG1 SWITCHING WAVEFORMS
WITH 800mA LOAD
MAX1586A/86B/87A toc13
MAX1586A/86B/87A toc12
50mv/div
AC-COUPLED
10mv/div
AC-COUPLED
V1
V1
V
LX1
V
LX1
2V/div
0
2V/div
0
I
L1
500mA/div
0
500mA/div
0
I
L1
20μs/div
400ns/div
______________________________________________________________________________________ 11
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
Typical Operating Characteristics (continued)
(Circuit of Figure 6, V = 3.6V, T = +25°C, unless otherwise noted.)
IN
A
REG3 SWITCHING WAVEFORMS
WITH 250mA LOAD
REG3 PULSE-SKIP SWITCHING
WAVEFORMS WITH 10mA LOAD
MAX1586A/86B/87A toc14
MAX1586A/86B/87A toc15
10mv/div
AC-COUPLED
10mv/div
AC-COUPLED
V3
V3
2V/div
0
2V/div
0
V
LX3
V
LX3
500mA/div
0
500mA/div
0
I
L3
I
L3
400ns/div
10μs/div
V7 AND RSO
STARTUP WAVEFORMS
REG3 FORCED-PWM SWITCHING
WAVEFORMS WITH 10mA LOAD
MAX1586A/86B/87A toc17
MAX1586A/86B/87A toc16
10mv/div
AC-COUPLED
V3
2V/div
0V
V
IN
V
LX3
V7
2V/div
0V
2V/div
0V
2V/div
0V
500mA/div
0mA
RSO
I
L3
10ms/div
400ns/div
SYS_EN STARTUP WAVEFORMS
PWR_EN STARTUP WAVEFORMS
MAX1586A/86B/87A toc18
MAX1586A/86B/87A toc19
V
AND
EN3
V
AND
EN1
2V/div
2V/div
V
EN45
V
EN2
2V/div
2V/div
2V/div
2V/div
2V/div
V3
V4
V5
V1
V2
V
POK
2V/div
2V/div
V
POK
2ms/div
1ms/div
B6/MAX1587C
12 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
Typical Operating Characteristics (continued)
(Circuit of Figure 6, V = 3.6V, T = +25°C, unless otherwise noted.)
IN
A
REG1 LOAD-TRANSIENT RESPONSE
REG2 LOAD-TRANSIENT RESPONSE
MAX1586A/86B/87A toc20
MAX1586A/86B/87A toc21
V1
V2
100mV/div
AC-COUPLED
100mV/div
AC-COUPLED
I
LOAD1
I
LOAD2
200mA/div
200mA/div
0A
0A
200μs/div
200μs/div
REG3 LOAD-TRANSIENT RESPONSE
REG3 LOAD-TRANSIENT RESPONSE
MAX1586A/86B/87A toc22B
MAX1586A/86B/87A toc22
MAX1586C
MAX1587C
V3
V3
100mV/div
AC-COUPLED
100mV/div
I
LOAD3
I
850mA
50mA
LOAD3
200mA/div
500mA/div
0A
100μs/div
200μs/div
REG3 OUTPUT VOLTAGE CHANGING FROM
1.3V TO 1.0V WITH DIFFERENT VALUES OF C
RAMP
REG6 USIM TRANSITIONS
MAX1586A/86B/87A toc23
MAX1586A/86B/87A toc24
C
RAMP
= 2200pF
500mV/div
V6
2.5V TO 3.0V
V6
C
RAMP
= 1500pF
1.8V TO 2.5V
C
= 1000pF
= 330pF
RAMP
V6
0 TO 1.8V
0
C
RAMP
200μs/div
10μs/div
______________________________________________________________________________________ 13
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
Pin Description
PIN
NAME
FUNCTION
MAX MAX
1586 1587
Dual Mode™, Low-Battery Input. Connect to IN to set the low-battery threshold to 3.6V (no resistors
needed). Connect LBI to a resistor-divider for an adjustable LBI threshold. When IN is below the set
threshold, LBO output switches low. LBO is deactivated and forced low when IN is below the dead-battery
(DBI) threshold and when all REGs are disabled.
1
2
—
LBI
REG1 Compensation Node. Connect a series resistor and capacitor from CC1 to GND to compensate the
regulation loop. See the Compensation and Stability section.
40
CC1
FB1
REG1 Feedback Input. Connect FB1 to GND to set V1 to 3.3V. Connect FB1 to external feedback resistors
for other output voltages.
3
4
1
2
BKBT Input Connection for Backup Battery. This input can also accept the output of an external boost converter.
Also known as VCC_BATT. V7 is always active if main or backup power is present. It is the first regulator
that powers up. V7 has two states:
1) V7 tracks V1 if ON1 is high and V1 is in regulation.
5
3
V7
2) V7 tracks V
when ON1 is low or V1 is out of regulation.
BKBT
REG1 Voltage-Sense Input. Connect directly to the REG1 output voltage. The output voltage is set by FB1
to either 3.3V or adjustable with resistors.
6
7
8
4
5
6
V1
SLPIN Input to V1 and V2 Sleep Regulators. The input to the standby regulators at V1 and V2. Connect SLPIN to IN.
REG2 Voltage-Sense Input. Connect directly to the REG2 output voltage. The output voltage is set by FB2
to either 1.8V/2.5V (MAX1586A, MAX1587A), 3.3V/2.5V (MAX1586B), or adjustable with resistors.
V2
REG2 Feedback Input. Connect to GND to set V2 to 2.5V on all devices. Connect FB2 to IN to set V2 to
1.8V on the MAX1586A and MAX1587A. Connect FB2 to IN to set V2 to 3.3V on the MAX1586B. Connect
FB2 to external feedback resistors for other voltages.
9
7
8
FB2
REG2 Compensation Node. Connect a series resistor and capacitor from CC2 to GND to compensate the
regulation loop. See the Compensation and Stability section.
10
CC2
Power-OK Output. Open-drain output that is low when any of the V1–V6 outputs are below their regulation
threshold. When all activated outputs are in regulation, POK is high impedance. POK maintains a valid low
output with V7 as low as 1V. POK does not flag an out-of-regulation condition while REG3 is transitioning
between voltages set by serial programming. POK also does not flag for any REG channel that has been
turned off; however, if all REG channels are off (V1–V6), then POK is forced low. If IN < UVLO, then POK is
low. POK is expected to connect to nVCC_FAULT.
11
9
POK
12
13
10
11
SCL Serial Clock Input
Serial Data Input. Data is read on the rising edge of SCL. Serial data programs the REG3 (core) and REG6
(VCC_USIM) voltage. REG3 and REG6 can be programmed even when off, but at least one of the ON_ pins
SDA
must be logic-high to activate the serial interface. On power-up, REG3 defaults to 1.3V and REG6 defaults
to 0V.
Force V3 to PWM at All Loads. Connect PWM3 to GND for normal operation (skip mode at light loads). Drive
or connect high for forced-PWM operation at all loads for V3 only.
14
15
12
—
PWM3
LBO Low-Battery Output. Open-drain output that goes low when IN is below the threshold set by LBI.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
B6/MAX1587C
14 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
Pin Description (continued)
PIN
NAME
FUNCTION
MAX MAX
1586 1587
REG2 Power Input. Bypass to PG2 with a 4.7µF or greater low-ESR capacitor. PV1, PV2, PV3, and IN must
connect together externally.
16
17
18
19
20
13
14
15
16
17
PV2
LX2 REG2 Switching Node. Connects to REG2 inductor.
REG2 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close as possible to the IC.
PG2
IN
Main Battery Input. This input provides power to the IC.
V3 Ramp-Rate Control. A capacitor connected from RAMP to GND sets the rate-of-change when V3 is
RAMP
changed. The output impedance of RAMP is 100kΩ. FB3 regulates to 1.28 x V
.
RAMP
21
22
23
18
19
20
GND Analog Ground
REF Reference Output. Output of the 1.25V reference. Bypass to GND with a 0.1µF or greater capacitor.
BYP Low-Noise LDO Bypass. Low-noise bypass pin for V4 LDO. Connect a 0.01µF capacitor from BYP to GND.
Dead or Missing Battery Output. DBO is an open-drain output that goes low when IN is below the threshold
DBO set by DBI. DBO does not deactivate any MAX1586/MAX1587 regulator outputs. DBO is expected to
connect to nBATT_FAULT on Intel CPUs.
24
25
26
—
21
—
On/Off Input for REG2. Drive high to turn on. When enabled, the REG2 output soft-starts. ON2 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON1, ON2, and ON6 are connected to SYS_EN.
ON2
On/Off Input for REG4. Drive high to turn on. When enabled, the REG4 output activates. ON4 has hysteresis
ON4 so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that
ON4 is connected to PWR_EN.
27
28
29
23
24
25
V4
IN45
V5
Also Known as VCC_PLL. 1.3V, 35mA linear-regulator output for PLL. Regulator input is IN45.
Power Input to V4 and V5 LDOs. Typically connected to V2, but can also connect to IN or another voltage
from 2.5V to V
.
IN
Also Known as VCC_SRAM. 1.1V, 35mA linear-regulator output for CPU SRAM. Regulator input is IN45.
On/Off Input for REG5. Drive high to turn on. When enabled, the MAX1586/MAX1587 soft-starts the REG5
output. ON5 has hysteresis so an RC can be used to implement manual sequencing with respect to other
inputs. It is expected that ON5 is connected to PWR_EN.
30
—
ON5
REG3 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close as possible to the IC.
31
32
33
26
27
28
PG3
LX3 REG3 Switching Node. Connects to the REG3 inductor.
REG3 Power Input. Bypass to PG3 with a 4.7µF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and
IN must connect together externally.
PV3
On/Off Input for REG3 (Core). Drive high to turn on. When enabled, the REG3 output ramps up. ON3 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON3 is driven from CPU SYS_EN.
34
34
ON3
______________________________________________________________________________________ 15
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
Pin Description (continued)
PIN
NAME
FUNCTION
MAX MAX
1586 1587
Serial Address Bit. SRAD allows the serial address of the MAX1586/MAX1587 to be changed in case it
conflicts with another serial device. If SRAD = GND, A1 = 0. If SRAD = IN, A1 = 1.
35
36
37
38
39
29
30
31
32
33
SRAD
RSO
MR
Open-Drain Reset Output. Deasserts when V7 exceeds 2.55V (typ rising). Has 65ms delay before release.
RSO is expected to connect to nRESET on the CPU.
Manual Reset Input. A low input at MR causes the RSO output to go low and also resets the V3 output to its
default 1.3V setting. MR impacts no other MAX1586/MAX1587 functions.
REG 3 Compensation Node. Connect a series resistor and capacitor from CC3 to GND to compensate the
regulation loop. See the Compensation and Stability section.
CC3
FB3
REG3 Feedback-Sense Input. Connect directly to the REG3 output voltage. Output voltage is set by the
serial interface.
On/Off Input for REG6. Drive high to turn on. When enabled, the REG6 output activates. ON6 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that
ON1, ON2, and ON6 are connected to SYS_EN.
40
—
ON6
Also known as VCC_USIM. Linear-regulator output. This voltage is programmable through the I2C interface
to 0V, 1.8V, 2.5V, or 3.0V. The default voltage is 0V. REG6 is activated when ON6 is high.
41
42
43
44
45
—
—
36
37
38
V6
IN6
PG1
Power Input to the V6 LDO. Typically connected to V1, but can also connect to IN.
REG1 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close as possible to the IC.
LX1 REG1 Switching Node. Connects to the REG1 inductor.
REG1 Power Input. Bypass to PG2 with a 4.7µF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and
IN must connect together externally.
PV1
On/Off Input for REG1. Drive high to turn on REG1. When enabled, the REG1 output soft-starts. ON1 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON1, ON2, and ON6 connect to SYS_EN.
46
47
35
39
ON1
Sleep Input. SLP selects which regulators ON1 and ON2 turn on. SLP = high is normal operation (ON1 and
SLP ON2 are the enables for the V1 and V2 DC-DC converters). SLP = low is sleep operation (ON1 and ON2 are
the enables for the V1 and V2 LDOs).
Dual Mode, Dead-Battery Input. Connect DBI to IN to set the dead-battery falling threshold to 3.15V (no
resistors needed). Connect DBI to a resistor-divider for an adjustable DBI threshold.
48
—
—
22
EP
DBI
On/Off Input for REG4 and REG5. Drive high to turn on. When enabled, the REG4 and REG5 outputs
activate. ON45 has hysteresis so an RC can be used to implement manual sequencing with respect to
other inputs. It is expected that ON45 is connected to PWR_EN.
ON45
EP
Exposed Metal Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not
remove the requirement for proper ground connections to the appropriate ground pins.
EP
B6/MAX1587C
16 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
BATT
MAIN
BATT
IN SLPIN
DBI (3.15V OR ADJ)
UVLO
MAX1586
AND
BATT
MON
LBI (3.6V OR ADJ)
REF
PV1
LX1
PG1
STEP-DOWN
PWM
REG1
REF
1.25V
V1, VCC_IO
3.3V WITH FB1 = GND,
OR ADJ WITH RESISTORS
ON
LBO
DBO
OPEN-DRAIN LOW-BATT OUT
OPEN-DRAIN DEAD-BATT OUT
TO nBATT_FAULT
V1
SLEEP
LDO
FB1
ON1
ON2
FROM CPU
SYS_EN
PV2
LX2
PG2
TO BATT
ON
STEP-DOWN
PWM
REG2
SLP
RUN
SLEEP
TO V1
V2, VCC_MEM
2.5V WITH FB2 = GND,
1.8V WITH FB2 = IN (MAX1586A, MAX1587A)
3.3V WITH FB2 = IN (MAX1586B)
OR ADJ WITH RESISTORS
BKBT
Li+
BACKUP
BATTERY
REG1 OK
V7
V7, VCC_BATT
(1ST SUPPLY, ALWAYS ON)
V2
RSO
TO CPU
nRESET
V7
RESET
2.425V
SLEEP
LDO
FB2
PV3
LX3
TO BATT
65ms
STEP-DOWN
PWM
REG3
MR
RESET INPUT
V3, VCC_CORE
0.7V TO 1.475V
500mA (MAX1586A, MAX1586B, MAX1587A)
900mA (MAX1586C, MAX1587C)
PWM3
POK
FORCE REG3
TO PWM
TO CPU
PWM
ADJ
nVCC_FAULT
PG3
FB3
V1–V6
POWER-
OK
ON
ON3
IN45
FROM CPU
PWR_EN
TO V2
RAMP
V4
V4, VCC_PLL
1.3V, 35mA
BYP
100kΩ
LDO
REG
4
V3
DAC
ON4
ON5
LDO
REG
5
V5, VCC_SRAM
1.1V, 35mA
V5
CC1
CC2
CC3
IN6
V6
TO V2
VCC_USIM
0V, 1.8V, 3.0V (DEF = 0V)
2
I C
LDO
REG
6
SERIAL
ON6
FROM CPU
SYS_EN
GND
SRAD SCL SDA
Figure 1. MAX1586 Functional Diagram (The MAX1587 omits some features. See the Pin Description section.)
______________________________________________________________________________________ 17
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
V2 is also a 1MHz current-mode step-down converter.
Detailed Description
The V2 step-down DC-DC converter on the MAX1586A
and MAX1587A is preset for 1.8V or 2.5V, while the
MAX1586B V2 supply is preset for 3.3V or 2.5V. V2 can
also be adjusted with external resistors on all parts. V2
supplies loads up to 900mA.
The MAX1586/MAX1587 power-management ICs are
optimized for devices using Intel XScale microproces-
sors, including third-generation smart cell phones,
PDAs, internet appliances, and other portable devices
requiring substantial computing and multimedia
capability at low power. The MAX1586A/MAX1586B/
MAX1587A comply with Intel Processor Power
specifications.
Under moderate to heavy loading, the converters operate
in a low-noise PWM mode with constant frequency and
modulated pulse width. Switching harmonics generated
by fixed-frequency operation are consistent and easily fil-
tered. Efficiency is enhanced under light loading (< 30mA
typ), by assuming an Idle Mode™ during which the con-
verter switches only as needed to service the load.
The ICs integrate seven high-performance, low-operat-
ing-current power supplies along with supervisory and
management functions. Regulator outputs include three
step-down DC-DC outputs (V1, V2, and V3), three lin-
ear regulators (V4, V5, and V6), and one always-on out-
put, V7 (Intel VCC_BATT). The V1 step-down DC-DC
converter provides 3.3V or adjustable output voltage for
I/O and peripherals. The V2 step-down DC-DC convert-
er on the MAX1586A and MAX1587A is preset for 1.8V
or 2.5V, while the MAX1586B V2 supply is preset for
3.3V or 2.5V. V2 can also be adjusted with external
resistors on all parts. The V3 step-down DC-DC con-
verter provides a serial-programmed output for power-
ing microprocessor cores. The three linear regulators
(V4, V5, and V6) provide power for PLL, SRAM, and
USIM.
Synchronous Rectification
Internal n-channel synchronous rectifiers eliminate the
need for external Schottky diodes and improve efficien-
cy. The synchronous rectifier turns on during the sec-
ond half of each cycle (off-time). During this time, the
voltage across the inductor is reversed, and the induc-
tor current falls. In normal operation (not forced PWM),
the synchronous rectifier turns off at the end of the
cycle (at which time another on-time begins) or when
the inductor current approaches zero.
100% Duty-Cycle Operation
If the inductor current does not rise sufficiently to sup-
ply the load during the on-time, the switch remains on,
allowing operation up to 100% duty cycle. This allows
the output voltage to maintain regulation while the input
voltage approaches the regulation voltage. Dropout
voltage is approximately 180mV for an 800mA load on
V1 and 220mV for an 800mA load on V2. During
dropout, the high-side p-channel MOSFET turns on,
and the controller enters a low-current-consumption
mode. The device remains in this mode until the regula-
tor channel is no longer in dropout.
To minimize sleep-state quiescent current, V1 and V2
have bypass “sleep” LDOs that can be activated to
minimize battery drain when output current is very low.
Other functions include separate on/off control for all
DC-DC converters, low-battery and dead-battery
detection, a power-OK output, a backup-battery input,
and a two-wire serial interface.
All DC-DC outputs use fast, 1MHz PWM switching and
small external components. They operate with fixed-fre-
quency PWM control and automatically switch from
PWM to skip-mode operation at light loads to reduce
operating current and extend battery life. The V3 core
output is capable of forced-PWM operation at all loads.
The 2.6V to 5.5V input voltage range allows 1-cell Li+,
3-cell NiMH, or a regulated 5V input.
Sleep LDOs
In addition to the high-efficiency step-down converters,
V1 and V2 can also be supplied with low-quiescent cur-
rent, low-dropout (LDO) linear regulators that can be
used in sleep mode or at any time when the load current
is very low. The sleep LDOs can source up to 35mA. To
enable the sleep LDOs, drive SLP low. When SLP is high,
the switching step-down converters are active. The out-
put voltage of the sleep LDOs is set to be the same as
the switching step-down converters as described in the
Setting the Output Voltages section. SLPIN is the input to
the V1 and V2 sleep LDOs and must connect to IN.
The following power-supply descriptions include the
Intel terms for the various voltages in parenthesis. For
example, the MAX1586/MAX1587 V1 output is referred
to as VCC_IO in Intel documentation. See Figure 1.
V1 and V2 (VCC_IO, VCC_MEM)
Step-Down DC-DC Converters
V1 is a 1MHz current-mode step-down converter. The V1
output voltage can be preset to 3.3V or adjusted using a
resistor voltage-divider. V1 supplies loads up to 1300mA.
Idle Mode is a trademark of Maxim Integrated Products, Inc.
B6/MAX1587C
18 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
V4 and V5 linear regulators is IN45, which is typically
connected to V2. To enable V5 on the MAX1586, drive
ON5 high, or drive ON5 low for shutdown. On the
MAX1587, the enable pins for V4 and V5 are combined.
Drive ON45 high to enable V4 and V5, or drive ON45 low
for shutdown. V5 is intended to connect to VCC_SRAM.
V3 (VCC_CORE) Step-Down
DC-DC Converter
V3 is a 1MHz current-mode step-down converter. The
MAX1586A, MAX1586B, and MAX1587A supply loads
up to 500mA from V3 while the MAX1586C and
MAX1587C supply loads up to 1A.
The V3 output is set by the I2C serial interface to
between 0.7V and 1.475V in 25mV increments. The
default output voltage on power-up and after a reset is
1.3V. See the Serial Interface section for programming
details. See the Applications Information for instructions
on how to increase the V3 output voltage.
V6 (VCC_USIM—MAX1586 Only)
V6 is a linear regulator on the MAX1586 that supplies
loads up to 35mA. The V6 output voltage is pro-
grammed with the I2C serial interface to 0V, 1.8V, 2.5V,
or 3.0V. The power-up default for V6 is 0V. See the
Serial Interface section for details on changing the volt-
age. The power input for the V6 linear regulator is IN6,
which is typically connected to V1. To enable V6, drive
ON6 high, or drive ON6 low for shutdown. V6 is intend-
ed to connect to VCC_USIM.
Forced PWM on REG3
Under moderate to heavy loading, the V3 always operates
in a low-noise PWM mode with constant frequency and
modulated pulse width. Switching harmonics generated by
fixed-frequency operation are consistent and easily filtered.
V7 Always-On Output (VCC_BATT)
The V7 output is always active if V1 is enabled and in
regulation or if backup power is present. When ON1 is
high and V1 is in regulation, V7 is sourced from V1 by
an internal MOSFET switch. When ON1 is low or V1 is
out of regulation, V7 is sourced from BKBT by a second
on-chip MOSFET. V7 can supply loads up to 30mA. V7
is intended to connect to VCC_BATT on Intel CPUs.
With light loads (< 30mA) and PWM3 low, V3 operates
in an enhanced-efficiency Idle Mode during which the
converter switches only as needed to service the load.
With PWM3 high, V3 operates in low-noise forced-PWM
mode under all load conditions.
Linear Regulators (V4, V5, and V6)
V4 (VCC_PLL)
V4 is a linear regulator that provides a fixed 1.3V output
and supplies loads up to 35mA. The power input for the
V4 and V5 linear regulators is IN45, which is typically
connected to V2. To enable V4 on the MAX1586, drive
ON4 high, or drive ON4 low for shutdown. On the
MAX1587, the enable pins for V4 and V5 are combined.
Drive ON45 high to enable V4 and V5, or drive ON45 low
for shutdown. V4 is intended to connect to VCC_PLL.
Due to variations in system implementation, BKBT and
V7 can be utilized in different ways. See the Backup-
Battery and V7 Configurations section for information on
how to use BKBT and V7.
Quiescent Operating Current
in Various States
The MAX1586/MAX1587 are designed for optimum effi-
ciency and minimum operating current for all typical
operating modes, including sleep and deep sleep.
These states are outlined in Table 1.
V5 (VCC_SRAM)
V5 is a linear regulator that provides a fixed 1.1V output
and supplies loads up to 35mA. The power input for the
Table 1. Quiescent Operating Current in Various States
OPERATING
DESCRIPTION
POWER MODE
TYPICAL MAX1586/MAX1587
NO-LOAD OPERATING CURRENT
RUN
IDLE
All supplies on and running
All supplies on and running, peripherals on
All supplies on, minimal loading, peripherals monitored
All supplies on, minimal loading, peripherals not monitored
200µA MAX1587,
225µA MAX1586
SENSE
STANDBY
60µA if V1 and V2 SLEEP LDOs on;
130µA if V1, V2 step-down DC-DCs enabled
SLEEP
PWR_EN controlled voltages (V3, V4, V5) are off. V1 and V2 on.
5µA MAX1587 if IN > DBI threshold;
32µA MAX1586 if IN > DBI threshold;
4µA if IN < DBI threshold
DEEP SLEEP
All supplies off except V7. V7 biased from backup battery.
______________________________________________________________________________________ 19
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
Voltage Monitors, Reset, and
Undervoltage-Lockout Functions
IN
Undervoltage Lockout
100kΩ
When the input voltage is below 2.35V (typ), an under-
voltage-lockout (UVLO) circuit disables the IC. The
inputs remain high impedance while in UVLO, reducing
battery load under this condition. All serial registers are
maintained with the input voltage down to at least 2.35V.
MAX1586
MAX1587
MR
0.22μF
Reset Output (RSO) and MR Input
The reset output (RSO) is low when the MR input is low
or when V7 is below 2.425V. V7 is powered from V1
(when enabled) or the backup-battery input (BKBT).
RSO normally goes low:
Figure 2. An RC delay connected from IN to MR ensures that
the 65ms RSO release delay remains in effect for any
sequence of V and V7.
IN
1) When power is first applied in configurations with no
separate backup battery (external diode from IN to
BKBT).
MAIN BATTERY
IN
R1
MAX1586
438kΩ
2) When power is removed in configurations with no
separate backup battery (external diode from IN to
BKBT).
DBI (1.232V THRESHOLD)
LBI (1.00V THRESHOLD)
R2
62kΩ
3) If the backup battery falls below 2.425V when V1 is
off or out of regulation.
R3
200kΩ
4) When the manual reset button is pressed (MR goes
low).
If V is > 2.4V, an internal timer delays the release of
IN
RSO for 65ms after V7 rises above 2.3V. However, if V
IN
Figure 3. Setting the Low-Battery and Dead-Battery Thresholds
with One Resistor Chain. The values shown set a DBI threshold
of 3.3V and an LBI threshold of 3.5V (no resistors are needed
for the factory preset thresholds).
< 2.4V when V7 exceeds 2.3V, or if V and V7 rise at the
IN
same time, RSO deasserts immediately with no 65ms
delay. There is no delay in the second case because the
timer circuitry is deactivated to minimize operating cur-
rent during V undervoltage lockout.
IN
(V ) discharges to the dead-battery threshold. The
IN
factory-set 3.15V threshold is selected by connecting
DBI to IN, or the threshold can be programmed with a
resistor-divider at DBI. The low-battery comparator has
a factory-set 3.6V threshold that is selected by connect-
ing LBI to IN, or its threshold can be programmed with a
resistor-divider at LBI.
If it is desired to have a 65ms RSO release delay for any
sequence of V and V7, the circuit in Figure 2 may be
IN
used. An RC connected from IN to MR delays the rise of
MR until after V powers up. The 65ms timer is valid for
IN
either sequence of V7 and V and does not release until
IN
65ms after both are up. The only regulator output that
affects RSO is V7. RSO will not respond to V1–V6, which
are monitored by POK. Also, RSO is high impedance
and does not function if BKBT is not powered.
One three-resistor-divider can set both DBI and LBI
(R1, R2, and R3 in Figure 3) according to the following
equations:
MR is a manual reset input for hardware reset. A low
input at MR causes the RSO output to go low for at least
65ms and also resets the V3 output to its default 1.3V set-
ting. MR impacts no other MAX1586/MAX1587 functions.
1) Choose R3 to be less than 250kΩ.
⎛
⎞
V
V
DBITH
LB
2)
3)
R1= R3
1−
⎜
⎟
V
V
⎝
⎠
LBITH
DB
Dead-Battery and Low-Battery Comparators—
DBI, LBI (MAX1586 only)
The DBI and LBI inputs monitor input power (usually a
battery) and trigger the DBO and LBO outputs. The
dead-battery comparator triggers DBO when the battery
⎛
⎞
V
V
V
DBITH LB
R2 = R3 ×
−1
⎟
⎜
V
⎝
⎠
LBITH DB
B6/MAX1587C
20 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
Power-OK Output (POK)
POK is an open-drain output that goes low when any
activated regulator (V1–V6) is below its regulation
MAIN BATTERY
IN
threshold. POK does not monitor V7. When all active
output voltages are within 10% of regulation, POK is
high impedance. POK does not flag an out-of-regula-
tion condition while V3 is transitioning between voltages
set by serial programming or when any regulator chan-
nel has been turned off. POK momentarily goes low
when any regulator is turned on, but returns high when
that regulator reaches regulation. When all regulators
(V1–V6) are off, POK is forced low. If the input voltage
is below the UVLO threshold, POK is held low and
R4
334kΩ
R6
500kΩ
MAX1586
DBI (1.232V THRESHOLD)
LBI (1.00V THRESHOLD)
R5
200kΩ
R7
200kΩ
maintains a valid low output with V as low as 1V. If
IN
BKBT is not powered, POK does not function and is
high impedance.
Figure 4. Setting the Low-Battery and Dead-Battery Thresholds
with Separate Resistor-Dividers. The values shown set a DBI
threshold of 3.3V and an LBI threshold of 3.5V (no resistors are
needed for factory-preset thresholds).
Connection to Processor
and Power Sequencing
Typical processor connections have only power-control
pins, typically labeled PWR_EN and SYS_EN. The
MAX1586/MAX1587 provide numerous on/off control
pins for maximum flexibility. In a typical application,
many of these pins are connected together. ON1, ON2,
and ON6 typically connect to SYS_EN. ON3, ON4, and
ON5 typically connect to PWR_EN. V7 remains on as long
as the main or backup power is connected. Sequencing
is not performed internally on the MAX1586/MAX1587;
however, all ON_ inputs have hysteresis and can connect
to RC networks to set sequencing. For typical connec-
tions to Intel CPUs, no external sequencing is required.
where V is the desired low-battery detection voltage
LB
and V
is the desired dead-battery detection voltage.
DB
V
is the LBI threshold (1.0V typ) and V
is the
LBITH
DBITH
DBI threshold (1.232V typ).
Alternately, LBI and DBI can be set with separate two-
resistor-dividers. Choose the lower resistor of the divider
chain to be 250kΩ or less (R5 and R7 in Figure 4). The
equations for upper divider-resistors as a function of
each threshold are then:
⎛
⎞
V
DB
R4 = R5 ×
R6 = R7 ×
−1
⎜
⎟
V
Backup-Battery Input
The backup-battery input (BKBT) provides backup
power for V7 when V1 is disabled. Normally, a primary
or rechargeable backup battery is connected to this
pin. If a backup battery is not used, then BKBT should
connect to IN through a diode or external regulator. See
the Backup-Battery and V7 Configurations section for
information on how to use BKBT and V7.
⎝
⎠
DBITH
⎛
⎞
V
LB
−1
⎜
⎟
V
⎝
⎠
LBITH
When resistors are used to set V , the threshold at LBI
LB
is 1.00V. When resistors are used to set V , the
DB
threshold at DBI is 1.232V. A resistor-set threshold can
also be used for only one of DBI or LBI. The other
threshold can then be factory set by connecting the
appropriate input to IN.
Serial Interface
An I2C-compatible, two-wire serial interface controls
REG3 on the MAX1587, and REG3 and REG6 on the
MAX1586. The serial interface operates when V
IN
If BKBT is not powered, DBO does not function and is
high impedance. DBO is expected to connect to
nBATT_FAULT on Intel CPUs. If BKBT is not powered,
LBO does not function and is high impedance.
exceeds the 2.40V UVLO threshold and at least one of
ON1–ON6 is asserted. The serial interface is shut down
to minimize off-current drain when no regulators are
enabled.
______________________________________________________________________________________ 21
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
Table 2. V3 and V6 Serial Programming Codes
D5
OUTPUT
0 = PROG V3
1 = PROG V6
D7
D6
D4
D3
D2
D1
D0
DESCRIPTION
(V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
0
V3, CORE
VOLTAGES
X
X
V6, USIM
VOLTAGES
[MAX1586
ONLY]
1.8
2.5
3.0
B6/MAX1587C
22 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
A
B
C
D
E
F
G
H
I
J
K
L
M
t
t
HIGH
LOW
SCL
SDA
t
t
t
t
HD:DAT
HD:STA
SU:STA
SU:DAT
t
t
SU:STO
BUF
A = START CONDITION
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
I = SLAVE PULLS SMB DATA LINE LOW
E = SLAVE PULLS SMB DATA LINE LOW
2
Figure 5. I C-Compatible Serial-Interface Timing Diagram
The serial interface consists of a serial data line (SDA)
and a serial clock line (SCL). Standard I2C-compatible
write-byte commands are used. Figure 5 shows a tim-
ing diagram for the I2C protocol. The MAX1586/
MAX1587 are slave-only devices, relying upon a master
to generate a clock signal. The master (typically a
microprocessor) initiates data transfer on the bus and
generates SCL to permit data transfer. A master device
communicates to the MAX1586/MAX1587 by transmit-
ting the proper address followed by the 8-bit data code
(Table 2). Each transmit sequence is framed by a
START (A) condition and a STOP (L) condition. Each
word transmitted over the bus is 8 bits long and is
always followed by an acknowledge clock pulse.
(see the Acknowledge Bit (ACK) section). The STOP
condition frees the bus.
When a STOP condition or incorrect address is detect-
ed, the MAX1586/MAX1587 internally disconnect SCL
from the serial interface until the next START condition,
minimizing digital noise and feedthrough.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
every 8-bit data word. The receiving device always
generates ACK. The MAX1586/MAX1587 generate an
ACK when receiving an address or data by pulling SDA
low during the ninth clock period. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
Table 2 shows the serial data codes used to program
V3 and V6. The default power-up voltage for V3 is 1.3V
and for V6 is 0V.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). Both SDA and SCL idle
high when the bus is not busy.
Serial Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the
7-bit slave address (Table 3). When idle, the
MAX1586/MAX1587 wait for a START condition fol-
lowed by its slave address. The serial interface com-
pares each address value bit by bit, allowing the
interface to power down immediately if an incorrect
address is detected.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 5). A START condition from the master signals
the beginning of a transmission to the MAX1586/
MAX1587. The master terminates transmission by issu-
ing a not acknowledge followed by a STOP condition
Table 3. Serial Address
A0
RD/W
SRAD A7
A6
A5
A4
A3
A2
A1
0
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
______________________________________________________________________________________ 23
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
R = R [(V /1.25) – 1]
OUT
The LSB of the address word is the read/write (R/W) bit.
R/W indicates whether the master is writing or reading
(RD/W 0 = write, RD/W 1 = read). The MAX1586/
MAX1587 only support the SEND BYTE format; there-
fore, RD/W is required to be 0.
H
L
The V3 (VCC_CORE) output voltage is set from 0.7V to
1.475V in 25mV steps by the I2C serial interface. See
the Serial Interface section for details.
Linear regulator V4 provides a fixed 1.3V output volt-
age. Linear regulator V5 provides a fixed 1.1V output
voltage. V4 and V5 voltages are not adjustable.
After receiving the proper address, the MAX1586/
MAX1587 issue an ACK by pulling SDA low for one
clock cycle. The MAX1586/MAX1587 have two user-
programmed addresses (Table 3). Address bits A7
through A2 are fixed, while A1 is controlled by SRAD.
Connecting SRAD to GND sets A1 = 0. Connecting
SRAD to IN sets A1 = 1.
The output voltage of linear regulator V6 (VCC_USIM) is
set to 0V, 1.8V, 2.5V, or 3.0V by the I2C serial interface.
See the Serial Interface section for details.
Linear regulator V7 (VCC_BATT) tracks the voltage at
V1 as long as ON1 is high and V1 is in regulation. When
ON1 is low or V1 is not in regulation, V7 switches to the
V3 Output Ramp-Rate Control
When V3 is dynamically changed with the serial inter-
face, the output voltage changes at a rate controlled by
backup battery (V ).
BKBT
Inductor Selection
a capacitor (C ) connected from RAMP to ground.
RAMP
The external components required for the step-down
are an inductor, input and output filter capacitors, and a
compensation RC network.
The voltage change is a conventional RC exponential
described by:
Vo(t) = Vo(0) + dV(1 – exp(-t/(100kΩ C
)))
RAMP
The MAX1586/MAX1587 step-down converters provide
best efficiency with continuous inductor current. A rea-
A useful approximation is that it takes approximately 2.2
RC time constants for V3 to move from 10% to 90% of
sonable inductor value (L ) is derived from:
IDEAL
the voltage difference. For C
= 1500pF, this time
RAMP
L
= [2(V ) x D(1 - D)]/(I
x f
)
OSC
is 330µs. For 1V to 1.3V change, this equates to
1mV/µs. See the Typical Operating Characteristics for
examples of different ramp-rate settings.
IDEAL
IN
OUT(MAX)
This sets the peak-to-peak inductor current at 1/2 the
DC inductor current. D is the duty cycle:
The maximum capacitor value that can be used at
RAMP is 2200pF. If larger values are used, the V3 ramp
rate is still controlled according to the above equation,
but when V3 is first activated, POK indicates an “in reg-
ulation” condition before V3 reaches its final voltage.
D = V
/V
OUT IN
Given L
, the peak-to-peak inductor ripple current
IDEAL
is 0.5 x I
. The peak inductor current is 1.25 x
OUT
I
. Make sure the saturation current of the
OUT(MAX)
inductor exceeds the peak inductor current and the
rated maximum DC inductor current exceeds the maxi-
The RAMP pin is effectively the reference for REG3.
FB3 regulates to 1.28 times the voltage on RAMP.
mum output current (I
). Inductance values
OUT(MAX)
larger than L
can be used to optimize efficiency or
IDEAL
Design Procedure
to obtain the maximum possible output current. Larger
inductance values accomplish this by supplying a
given load current with a lower inductor peak current.
Typically, output current and efficiency are improved
Setting the Output Voltages
The outputs V1 and V2 have preset output voltages, but
can also be adjusted using a resistor voltage-divider. To
set V1 to 3.3V, connect FB1 to GND. V2 can be preset to
1.8V or 2.5V on the MAX1586A and MAX1587A. To set
V2 to 1.8V on the MAX1586A and MAX1587A, connect
FB2 to IN. To set to 2.5V, connect FB2 to GND. V2 can
preset to 3.3V or 2.5V on the MAX1587B. To set V2 to
3.3V on the MAX1587B, connect FB2 to IN. To set to
2.5V, connect FB2 to GND.
for inductor values up to about two times L
. If the
IDEAL
inductance is raised too much, however, the inductor
size may become too large, or the increased inductor
resistance may reduce efficiency more than the gain
derived from lower peak current.
Smaller inductance values allow smaller inductor sizes,
but also result in larger peak inductor current for a
given load. Larger output capacitance may then be
needed to suppress the increase in output ripple
caused by larger peak current.
To set V1 or V2 to other than the preset output voltages,
connect a resistor voltage-divider from the output volt-
age to the corresponding FB input. The FB_ input bias
current is less than 100nA, so choose the low-side
Capacitor Selection
The input capacitor in a DC-DC converter reduces cur-
rent peaks drawn from the battery or other input power
(FB_-to-GND) resistor (R ) to be 100kΩ or less. Then cal-
L
culate the high-side (output-to-FB_) resistor (R ) using:
H
B6/MAX1587C
24 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
source and reduces switching noise in the controller.
Table 4. Compensation Parameters
The impedance of the input capacitor at the switching
frequency should be less than that of the input source
so high-frequency switching currents do not pass
through the input source.
PARAMETER
REG1
REG2
REG3
Error-Amplifier
Transconductance, gm
87µS
87µS
68µS
EA
The output capacitor keeps output ripple small and
ensures control-loop stability. The output capacitor
must also have low impedance at the switching fre-
quency. Ceramic, polymer, and tantalum capacitors
are suitable, with ceramic exhibiting the lowest ESR
and lowest high-frequency impedance.
Current-Sense Amp
0.5V/A
0.75V/A 1.25V/A
Transresistance, R
CS
Table 5. Typical Compensation Values
COMPONENT OR
PARAMETER
REG1
REG2
REG3
Output ripple with a ceramic output capacitor is
approximately:
V
3.3V
1300mA
3.3µH
3%
2.5V
900mA
6.8µH
3%
1.3V
500mA
10µH
OUT
V
= I
[1/(2π x f
x C
)]
RIPPLE
L(PEAK)
OSC
OUT
Output Current
Inductor
If the capacitor has significant ESR, the output ripple
component due to capacitor ESR is:
Load-Step Droop
3%
V
= I
x ESR
RIPPLE(ESR)
L(PEAK)
Loop Crossover Freq (f )
100kHz
330pF
240kΩ
22µF
100kHz
270pF
240kΩ
22µF
100kHz
330pF
240kΩ
22µF
C
Output capacitor specifics are also discussed in the
Compensation and Stability section.
C
C
R
C
Compensation and Stability
The relevant characteristics for REG1, REG2, and
REG3 compensation are:
C
OUT
input to the error amplifier moves 0.03 x 1.25V, or
37.5mV. The error-amplifier output drives 37.5mV x
1) Transconductance (from FB_ to CC_), gm
EA
gm , or I
= 37.5mV x 87µS = 3.26µA across R to
C
EA
EAO
2) Current-sense amplifier transresistance, R
CS
provide transient gain. Find the value of R that allows
C
3) Feedback regulation voltage, V (1.25V)
FB
the required load-step swing from:
4) Step-down output voltage, V
, in V
OUT
R = R x I /I
IND(PK) EAO
C
CS
5) Output load equivalent resistance, R
= V
/
OUT
LOAD
where I
is the peak inductor current. In a step-
IND(PK)
I
LOAD
down DC-DC converter, if L
is used, output cur-
IDEAL
rent relates to inductor current by:
The key steps for step-down compensation are:
1) Set the compensation RC zero to cancel the R
I
= 1.25 x I
IND(PK)
OUT
LOAD
C
OUT
pole.
So for an 800mA output load step with V = 3.6V and
IN
V
OUT
= 2.5V:
2) Set the loop crossover at or below approximately
1/10th the switching frequency.
R = R x I
/I
= (0.75V/A) x
C
CS
IND(PK) EAO
(1.25 x 0.8A)/3.26µA = 230kΩ
We choose 240kΩ. Note that the inductor does not limit
the response in this case since it can ramp at (V
For example, with V
= 5V, V
= 2.5V for
OUT
IN(MAX)
= 800mA, then R
REG2, and I
= 3.125Ω. For
OUT
LOAD
REG2, R = 0.75V/A and gm = 87µS.
CS
EA
-
IN
V
)/L, or (3.6V - 2.5V)/3.3µH = 242mA/µs.
OUT
Choose the crossover frequency, f ≤ f
/10. Choose
C
OSC
100kHz. Then calculate the value of the compensation
capacitor, C :
The output filter capacitor is then selected so that the
pole cancels the R C zero:
C
C
R
OUT LOAD
C
C
C = (V /V
) x (R
/R ) x (gm /(2π x f ))
LOAD CS EA C
C
FB OUT
C
x R
= R x C
LOAD C C
OUT
= (1.25/2.5) x (3.125/0.75) x (87 x 10-6/(6.28
x 100,000)) = 289pF
For the example:
R
= V
x I = 2.5V/0.8A =
LOAD
OUT LOAD
Choose 330pF, the next highest standard value.
3.125Ω
= R x C /R = 240kΩ x 330pF/
LOAD
Now select the compensation resistor, R , so transient-
C
droop requirements are met. As an example, if 3% tran-
sient droop is allowed for the desired load step, the
C
OUT
C
C
3.125Ω = 25µF
______________________________________________________________________________________ 25
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
BATT
C11
10μF
MAIN
BATT
IN SLPIN
DBI (3.2V OR ADJ)
UVLO
MAX1586
AND
BATT
MON
LBI (3.6V OR ADJ)
REF
PV1
LX1
PG1
C12
4.7μF
TO
BATT
STEP-DOWN
PWM
REG1
TO V1
C19
0.1μF
R19
1MΩ
R20
1MΩ
REF
1.25V
V1
VCC_IO
ON
L1
3.3μH
C15
LOW-BATT
WARNING
LBO
DBO
22μF 3.3V
1300mA
TO CPU
nBATT_FAULT
V1
SLEEP
LDO
FB1
ON1
ON2
FROM CPU
SYS_EN
PV2
LX2
PG2
TO BATT
C13
4.7μF
ON
STEP-DOWN
PWM
REG2
SLP
RUN
SLEEP
TO V1
BKBT
V2
L2
6.8μH
C16
22μF
VCC_MEM
2.5V
Li+
BACKUP
BATTERY
C25
1μF
REG1 OK
900mA
V7
V7, VCC_BATT
(ALWAYS ON)
C24
1μF
V2
SLEEP
LDO
FB2
TO CPU
nRESET
RSO
V7
RESET
2.3V
PV3
LX3
TO BATT
65ms
C14
4.7μF
STEP-DOWN
PWM
REG3
MR
RESET INPUT
PWM3
V3
PWM
L3
10μH
VCC_CORE
0.7V TO 1.475V
C17
22μF
R18
1MΩ
500mA (MAX1586A, MAX1586B, MAX1587A)
900mA (MAX1586C, MAX1587C)
PG3
FB3
TO V1
ADJ
ON
POK
TO CPU
nVCC-FAULT
ON3
IN45
FROM CPU
V1–V6
POWER-
OK
PWR_EN
TO V2
V4
V4, VCC_PLL
1.3V, 35mA
C23
1μF
RAMP
BYP
C18
1500pF
LDO
REG
4
C20
0.01μF
100kΩ
ON4
ON5
V3
DAC
LDO
REG
5
V5
C22
1μF
VCC_SRAM
1.1V, 35mA
V5
CC1
CC2
CC3
IN6
V6
TO V2
R21
240kΩ
R22
240kΩ
V6
R23
240kΩ
C21
1μF
VCC_USIM
0V, 1.8V, 3.0V (DEF = 0V)
35mA
C26
330pF
2
I C
C27
270pF
LDO
REG
6
C28
330pF
SERIAL
ON6
FROM CPU
SYS_EN
GND
SRAD SCL SDA
Figure 6. MAX1586 Typical Applications Circuit (The MAX1587 omits some features. See the Pin Description section.)
B6/MAX1587C
26 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
We choose 22µF.
Recalculate R using the selected C
.
OUT
C
MAX1586
MAX1587
R = C
C
x R
/C = 208kΩ
LOAD C
OUT
PV3
LX3
TO BATT
Note that the pole cancellation does not have to be
V3
exact. R x C need only be within 0.75 to 1.25 times
C
x C
selection.
C
VCC_CORE
1.55V MAX
R
. This provides flexibility in component
LOAD
OUT
STEP-DOWN
PWM
REG3
R24**
3.3kΩ
If the output filter capacitor has significant ESR, a zero
occurs at:
PG3
FB3
Z
= 1/(2π x C
x R
)
ESR
ESR
OUT
If Z
> f , it can be ignored, as is typically the case
C
ESR
with ceramic or polymer output capacitors. If Z
is
ESR
R25
100kΩ
185.5kΩ
less than f , it should be cancelled with a pole set by
C
P
capacitor C connected from CC_ to GND:
C = C
P
R
/R
OUT ESR C
**OTHER R24 VALUES:
R24 = 5.5kΩ, V3: 0.759V TO 1.60V
R24 = 7.7kΩ, V3: 0.783V TO 1.65V
If C is calculated to be < 10pF, it can be omitted.
P
Optimizing Transient Response
In applications that require load-transient response to
be optimized in favor of minimum component values,
increase the output filter capacitor to increase the R in
the compensation RC. From the equations in the previ-
ous section, doubling the output cap allows a doubling
of the compensation R, which then doubles the tran-
sient gain.
Figure 7. Addition of R24 and R25 increases maximum core
voltage. The values shown raise the maximum core from
1.475V to 1.55V.
column in Table 2, and 185,500 is the internal resis-
tance of the FB3 pin.
Applications Information
Extending the Maximum Core
Voltage Range
Backup-Battery and V7 Configurations
The MAX1586/MAX1587 include a backup-battery con-
nection, BKBT, and an output, V7. These can be utilized
in different ways for various system configurations.
The V3 output can be serially programmed to supply
from 0.7V to 1.475V in 25mV steps. In some cases, a
higher CPU core voltage may be desired. The V3 volt-
age range can be increased by adding two resistors as
shown in Figure 7.
Primary Backup Battery
A connection with a primary (nonrechargeable) lithium
coin cell is shown in Figure 6. The lithium cell connects to
BKBT directly. V7 powers the CPU VCC_BATT from either
V1 (if enabled) or the backup battery. It is assumed
whenever the main battery is good, V1 is on (either with
its DC-DC converter or sleep LDO) to supply V7.
R24 and R25 add a small amount of gain. They are set
so that an internally programmed value of 1.475V
results in a higher actual output at V3. The resistors
shown in Figure 7 set a maximum output of 1.55V, 1.6V,
or 1.65V. All output steps are shifted and the step size
is also slightly increased.
No Backup Battery (or Alternate Backup)
If no backup battery is used, or if an alternate backup
and VCC_BATT scheme is used that does not use the
MAX1586/MAX1587, then BKBT should be biased from
IN with a small silicon diode (1N4148 or similar, as in
Figure 8). BKBT must still be powered when no backup
battery is used because DBO, RSO, and POK require
this supply to function. If BKBT is not powered, these
outputs do not function and are high impedance.
The output voltage for each programmed step of V3 in
Figure 7 is:
V3 = V3
+ (R24[(V3
/R25) +
PROG
PROG
(V3
/185,500)])
PROG
where V3 is the actual output voltage, V3
is the
PROG
original programmed voltage from the "OUTPUT (V)"
______________________________________________________________________________________ 27
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
Rechargeable Li+ Backup Battery
If more backup power is needed and a primary cell has
inadequate capacity, a rechargeable lithium cell can be
accommodated as shown in Figure 9. A series resistor
and diode charge the cell when the 3.3V V1 supply is
active. In addition to biasing V7, the rechargeable bat-
tery may be required to also power other supplies.
MAIN
POWER
IN
4.7μF
D1
1N4148
MAX1586
MAX1587
BKBT
V7
Rechargeable NiMH Backup Battery
In some systems, a NiMH battery may be desired for
backup. Usually this requires multiple cells because
the typical NiMH cell voltage is only 1.2V. By adding a
small DC-DC converter (MAX1724), the low-battery
voltage is boosted to 3V to bias BKBT (Figure 10). The
DC-DC converter’s low operating current (1.5µA typ)
allows it to remain on constantly so the 3V BKBT bias is
always present. A resistor and diode trickle charge the
NiMH cell when the main power is present.
1μF
Figure 8. BKBT connection when no backup battery is used, or
if an alternate backup scheme, not involving the
MAX1586/MAX1587, is used.
PCB Layout and Routing
Good PCB layout is important to achieve optimal perfor-
mance. Conductors carrying discontinuous currents and
any high-current path should be made as short and wide
as possible. A separate low-noise ground plane contain-
ing the reference and signal grounds should connect to
the power-ground plane at only one point to minimize the
effects of power-ground currents. Typically, the ground
planes are best joined right at the IC.
MAIN
IN
POWER
4.7μF
MAX1586
MAX1587
1kΩ
V1
BKBT
V7
4.7μF
1-CELL
Li+ RECHARGEABLE
BACKUP BATTERY
Keep the voltage feedback network very close to the
IC, preferably within 0.2in (5mm) of the FB_ pin. Nodes
with high dV/dt (switching nodes) should be kept as
small as possible and should be routed away from
high-impedance nodes such as FB_. Refer to the
MAX1586 or MAX1587 evaluation kit data sheets for a
full PCB example.
1μF
Figure 9. A 1-cell rechargeable Li+ battery provides more back-
up power when a primary cell is insufficient. The cell is charged
to 3.3V when V1 is active. Alternately, the battery can be
charged from IN if the voltages are appropriate for the cell type.
10kΩ
1N4148
MAIN
POWER
MURATA
LQH32C 10μH
IN
4.7μF
MAX1586
MAX1587
4.7μF
BATT
1-CELL
NiMH
RECHARGEABLE
BACKUP BATTERY
LX
MAX1724
EZK30
3.0V
BKBT
V7
SHDN
OUT
GND
1μF
10μF
Figure 10. A 1-cell NiMH battery can provide backup by boost-
ing with a low-power DC-DC converter. A series resistor-diode
trickle charges the battery when the main power is on.
B6/MAX1587C
28 ______________________________________________________________________________________
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
B6/MAX1587C
Selector Guide
REG2 PRESET VOLTAGE
(ALSO ADJUSTABLE)
REG3 (VCC_CORE)
OUTPUT CURRENT
PART
MAX1586A
OTHER FUNCTIONS
1.8V, 2.5V
3.3V, 2.5V
1.8V, 2.5V
1.8V, 2.5V
1.8V, 2.5V
0.5A
0.5A
0.9A
0.5A
0.9A
VCC_USIM (V6) linear regulator,
LBO and DBO battery monitors
MAX1586B
MAX1586C
MAX1587A
MAX1587C
—
Pin Configurations
TOP VIEW
40
36 35
47 46 45
44 43 42 41
40
39 38 37
48
39 38 37
34
32
33 31
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
RSO
SRAD
ON3
PV3
LX3
PG3
ON5
V5
LB1
CC1
FB1
BKBT
V7
1
2
30
29
RSO
FB1
BKBT
V7
SRAD
3
28 PV3
27 LX3
26 PG3
25 V5
V1
4
SLPIN
V2
5
V1
6
MAX1587AETL
MAX1587CETL
MAX1586AETM
MAX1586BETM
MAX1586CETM
SLPIN
V2
FB2
CC2
POK
SCL
7
24 IN45
V4
23
8
FB2
IN45
V4
9
22 ON45
21 ON2
CC2 10
10
11
ON4
ON2
POK
12
SCL
11
15 16
18
12 13 14
17
19
20
14 15 16
17 18 19 20
21
22 23 24
13
THIN QFN
6mm × 6mm
THIN QFN
7mm × 7mm
Chip Information
Package Information
(For the latest package outline information and land patterns,
PROCESS: BiCMOS
go to www.maxim-ic.com/packages.)
PACKAGE TYPE
40 Thin QFN
PACKAGE CODE
T4066-5
DOCUMENT NO.
21-0141
48 Thin QFN
T4877-6
21-0144
______________________________________________________________________________________ 29
High-Efficiency, Low-I PMICs with
Q
Dynamic Core for PDAs and Smart Phones
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
Corrected equations to calculate resistors in the Dead-Battery and Low-Battery
Comparators—DBI, LBI (MAX1586 only) section.
3
4
12/08
4/09
20, 21
20, 21, 23,
25, 27
Corrected typos
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
B6/MAX1587C
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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