MAX16016LTBM+T [MAXIM]
Power Supply Management Circuit, Fixed, 1 Channel, BICMOS, PDSO10, ROHS COMPLIANT, TDFN-10;
| 型号： | MAX16016LTBM+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Management Circuit, Fixed, 1 Channel, BICMOS, PDSO10, ROHS COMPLIANT, TDFN-10 信息通信管理 光电二极管 |
| 文件： | 总21页 (文件大小：459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4145; Rev 6; 11/11
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
General Description
Features
o System Monitoring for 5V, 3.3V, 3V, 2.5V, or 1.8V
The MAX16016/MAX16020/MAX16021 supervisory cir-
cuits monitor power supplies, provide battery-backup
control, and chip-enable (CE) gating to write protect
memory in microprocessor (µP)-based systems. These
low-power devices improve system reliability by providing
several supervisory functions in a small, single integrated
solution.
Power-Supply Voltages
o 1.53V to 5.5V Operating Voltage Range
o Low 1.2µA Supply Current (0.25µA in Battery-
Backup Mode)
o 145ms (min) Reset Timeout Period
o Battery Freshness Seal
The MAX16016/MAX16020/MAX16021 perform four
basic system functions:
o On-Board Gating of CE Signals, 1.5ns
Propagation Delay (MAX16020/MAX16021)
1) Provide a µP reset output during V
supply power-
CC
o Debounced Manual Reset Input
o Watchdog Timer, 1.2s (typ) Timeout
up, power-down, and brownout conditions.
2) Control V to battery-backup switching internally
CC
o Power-Fail Comparator and Low-Line Indicator for
to maintain data or low-power operation for memo-
ries, real-time clocks (RTCs), and other digital logic
when the main power is removed.
Monitoring Voltages Down to 0.6V
o Battery-On, Battery-OK, and Battery Test
Indicators
3) Provide memory write protection through internal
chip-enable gating during brownout.
o Small 10-Pin TDFN or 16-Pin TQFN Packages
o UL -Certified to Conform to IEC 60950-1
®
4) Provide a combination of additional supervisory
functions listed in the Features section.
Ordering Information
The MAX16016/MAX16020/MAX16021 operate from a
1.53V to 5.5V supply voltage and offer fixed reset
thresholds for monitoring 5V, 3.3V, 3V, 2.5V, and 1.8V
systems. Each device is available with either a push-
pull or open-drain reset output.
PART
TEMP RANGE
PIN-PACKAGE
MAX16016_TB_+T
-40°C to +85°C
10 TDFN-EP*
The first placeholder “_” designates all output options. Letter
“L” indicates push-pull outputs and letter “P” indicates open-
drain outputs. The last placeholder “_” designates the reset
threshold (see Table 1).
T = Tape and reel.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
The MAX16016/MAX16020/MAX16021 are available in
small TDFN/TQFN packages and are fully specified for
an operating temperature range of -40°C to +85°C.
Applications
Main/Backup Power for RTCs, CMOS Memories
Ordering Information continued at end of data sheet.
Selector Guide located at end of data sheet.
Industrial Control
Pin Configurations
GPS Systems
TOP VIEW
Set-Top Boxes
Point-of-Sale Equipment
Portable/Battery Equipment
16
15
14
13
BATT
MR
1
2
3
4
12 RESET
11 GND
10 PFO
+
MAX16020
PFI
EP
WDI
9
WDO
5
6
7
8
TQFN
Pin Configurations continued at end of data sheet.
UL is a registered trademark of Underwriters Laboratories, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
ABSOLUTE MAXIMUM RATINGS
CC
V
, BATT, OUT, BATT_TEST to GND.....................-0.3V to +6V
Output Current
OUT Short Circuit to GND Duration....................................10s
RESET, RESET, BATTON....................................................20mA
RESET, RESET, PFO, BATTOK, WDO, BATTON,
BATT_TEST, LL, (all open-drain) to GND.................-0.3V to +6V
RESET, RESET, BATTOK, WDO, BATTON,
Continuous Power Dissipation (T = +70°C)
A
10-Pin TDFN (derate 24.4mW/°C above +70°C) .......1951mW
16-Pin TQFN (derate 25mW/°C above +70°C) ..........2000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
LL (all push-pull) to GND......................-0.3V to (V
WDI, PFI to GND.......................................-0.3V to (V
CEIN, CEOUT to GND..............................-0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
OUT
OUT
OUT
MR to GND .................................................-0.3V to (V + 0.3V)
CC
Input Current
V
V
Peak Current.................................................................1A
Continuous Current ...............................................250mA
CC
CC
TDFN............................................................................+260°C
TQFN............................................................................+240°C
BATT Peak Current .......................................................500mA
BATT Continuous Current ...............................................70mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN
Junction-to Ambient Thermal Resistance (θ ) ...........41°C/W
TQFN
Junction-to Ambient Thermal Resistance (θ ) ...........40°C/W
JA
JA
Junction-to Case Thermal Resistance (θ ) ..................9°C/W
Junction-to Case Thermal Resistance (θ ) ..................6°C/W
JC
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
= 1.53V to 5.5V, V
= 3V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
CC
BATT
A
A
PARAMETER
SYMBOL
CONDITIONS
> V
MIN
TYP
MAX
5.5
2
UNITS
Operating Voltage Range (Note 3)
Supply Current
V
V
V
V
or V
0
V
CC, BATT
CC
CC
BATT
TH
V
V
V
V
= 1.62V
= 2.8V
= 3.6V
= 5.5V
1.2
1.9
2.3
3.4
CC
CC
CC
CC
/MAX6021
3
I
> V
µA
CC
TH
3.5
5
Supply Current in
Battery-Backup Mode
I
V
V
V
= 0V
0.25
0.5
µA
V
BATT
CC
CC
CC
0.1
V
Switchover Threshold Voltage
rising, V
- V
CC BATT
CC
x V
CC
BATT Switchover Threshold
Voltage
falling, V
< V , V
- V
BATT
0
mV
CC
TH CC
BATT Standby Current
V
V
V
V
V
V
V
V
> V
+ 0.2V
BATT
-10
+10
20
nA
nA
CC
BATT Freshness Leakage Current
= 5.5V
BATT
= 4.75V, I
= 3.15V, I
= 2.35V, I
= 1.91V, I
= 150mA
= 65mA
= 25mA
= 10mA
= 20mA
= 20mA
1.4
1.7
2.1
2.6
4.5
4.5
5.0
5.5
CC
OUT
OUT
OUT
OUT
CC
V
to OUT On-Resistance
R
Ω
CC
ON
CC
CC
= 4.5V, I
V
V
- 0.1
BATT
BATT
OUT
OUT
BATT
BATT
Output Voltage in
Battery-Backup Mode
V
V
OUT
= 2.5V, I
- 0.15
2
_______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
ELECTRICAL CHARACTERISTICS (continued)
(V
= 1.53V to 5.5V, V = 3V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
BATT A A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RESET OUTPUT (RESET, RESET)
Reset Threshold
V
(see Table 1)
V
TH
V
Falling to Reset Delay
t
V
falling at 10V/ms
20
µs
ms
CC
RD
CC
Reset Timeout Period
t
145
215
285
0.3
0.3
0.3
RP
V
V
V
≥ 3.3V, I
≥ 1.6V, I
≥ 1.2V, I
= 3.2mA, RESET asserted
= 1mA, RESET asserted
= 100µA, RESET asserted
CC
CC
CC
SINK
SINK
SINK
RESET Output Low Voltage
V
V
OL
RESET Output High Voltage
(Push-Pull Output)
V
= 1.1 x V , I
= 100µA,
V
OUT
- 0.3
CC
TH SOURCE
V
V
OH
RESET deasserted
RESET Output Leakage Current
(Open-Drain Output)
V
V
= 5.5V, RESET deasserted
1
µA
RESET
≥ 3.3V, I
= 3.2mA, RESET
= 1.0mA, RESET
CC
SINK
0.3
0.3
deasserted
RESET Output Low Voltage
V
V
OL
V
≥ 1.8V, I
CC
SINK
deasserted
RESET Output High Voltage
(Push-Pull Output)
V
= 0.9 x V , I
= 100µA,
V
OUT
- 0.3
CC
TH SOURCE
V
V
OH
RESET asserted
RESET Output Leakage Current
(Open-Drain Output)
V
V
= 5.5V, RESET asserted
1
µA
RESET
POWER-FAIL COMPARATOR
PFI, Input Threshold
PFI, Hysteresis
V
falling, 1.6V ≤ V ≤ 5.5V
CC
0.572
-1
0.590
30
0.611
V
PFT
IN
V
mV
µA
PFT-HYS
PFI Input Current
V
V
= 5.5V
+1
CC
CC
≥ 1.6V, I
= 1mA, output asserted
= 100µA, output asserted
0.3
SINK
PFO Output Low Voltage
V
V
OL
V
≥ 1.2V, I
0.3
CC
SINK
PFO Output Voltage
High (Push-Pull Output)
V
= 1.1 x V , I
= 100µA, output
V
OUT
- 0.3
CC
TH SOURCE
V
V
OH
asserted
PFO, Leakage Current
(Open-Drain Output)
V
V
= 5.5V, output deasserted
1
µA
µs
PFO
PFO, Delay Time
+ 100mV to V
- 100mV
20
PFT
PFT
MANUAL RESET (MR)
Input Low Voltage
Input High Voltage
Pullup Resistance
Glitch Immunity
V
0.3 x V
V
V
IL
CC
V
0.7 x V
20
IH
CC
30
kΩ
ns
ns
V
= 3.3V
100
120
CC
MR to Reset Delay
_______________________________________________________________________________________
3
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
ELECTRICAL CHARACTERISTICS (continued)
(V
= 1.53V to 5.5V, V = 3V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
BATT A A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
WATCHDOG TIMER (WDI, WDO)
Watchdog Timeout Period
t
0.83
320
1.235
1.64
s
WD
Minimum WDI Input Pulse Width
t
ns
WDI
0.3 x
WDI Input Low Voltage
WDI Input High Voltage
V
(Note 6)
(Note 6)
V
V
IL
V
CC
0.7 x
V
IH
V
CC
WDI Input Current (Note 7)
V
V
= 0V or 5.5V, time average
-1
+1
µA
V
WDI
WDO Output Low Voltage
V
= 5.0V, I = 1mA, WDO asserted
SINK
0.3
OL
CC
WDO Output High Voltage
(Push-Pull Output)
V
= 1.1 x V , I
= 100µA, WDO
V
OUT
- 0.3
CC
TH SOURCE
V
V
OH
deasserted
WDO Leakage Current
(Open-Drain Output)
V
= 5.5V, WDO deasserted
1
µA
WDO
BATTERY-ON INDICATOR (BATTON)
Output Low Voltage
V
I
= 3.2mA, V = 2.1V
BATT
0.3
1
V
OL
SINK
BATTON Leakage Current
V
= 5.5V
µA
BATTON
V
= 0.9 x V , I
= 100µA,
V
OUT
- 0.3
CC
TH SOURCE
BATTON Output High Voltage
V
V
OH
BATTON asserted
Output Short-Circuit Current
(Note 4)
Sink current, V = 5V
60
mA
CC
CE GATING (CEIN, CEOUT)
CEIN Leakage Current
Reset asserted, V
= 0.9 x V or 0V
-1
+1
50
µA
CC
TH
CEIN to CEOUT Resistance
Reset not asserted (Note 5)
8
Ω
/MAX6021
Reset asserted, CEOUT = 0,
CEOUT Short-Circuit Current
0.75
2
7
mA
ns
V
= 0.9 x V
TH
CC
CEIN to CEOUT Propagation
Delay
50Ω source, C
= 50pF, V
= 4.75V
= 100µA
= 1µA
1.5
LOAD
CC
0.8 x
V
V
= 5V, V
= 0V, V
≥ V , I
BATT SOURCE
CC
CC
CC
V
CC
Output High Voltage
V
V
-
BATT
0.1
≥ 2.2V, I
BATT
SOURCE
Reset to CEOUT Delay
12
µs
4
_______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
ELECTRICAL CHARACTERISTICS (continued)
(V
= 1.53V to 5.5V, V = 3V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
BATT A A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOW LINE (LL)
Low Line to Reset Threshold
Voltage
V
falling
(see Table 2)
20
mV
µs
V
CC
V
Falling to LL Delay
V
V
V
V
falling at 10V/ms
CC
CC
CC
CC
≥ 1.6V, I
≥ 1.2V, I
= 1mA, LL asserted
= 100µA, LL asserted
0.3
0.3
SINK
SINK
LL Output Low Voltage
V
OL
LL Output High Voltage (Push-
Pull Output)
= 0.9 x V
, I
= 100µA,
V
-
CC
TH_LL SOURCE
OUT
0.3
V
V
OH
LL deasserted
Output Leakage Current
V
= 5.5V, LL deasserted
1
µA
LL
BATTERY-OK INDICATOR (BATTOK, BATT_TEST)
BATTOK Threshold
Inferred internally from BATT
= 1.1 x V , I = 1mA, reset
asserted
2.508
2.6
2.673
0.3
V
V
V
CC
TH SINK
BATTOK Output Voltage Low
V
OL
V
= 1.1 x V , I
= 100µA,
V
-
CC
TH SOURCE
OUT
0.3
BATTOK Output High Voltage
V
V
OH
BATTOK asserted
BATTOK Output Leakage
Current
V
V
= 5.5V, deasserted
1
µA
V
BATTOK
BATT_TEST Output Low Voltage
= 1.1 x V , I
= 1mA
0.3
CC
TH SINK
Note 2: All devices are 100% production tested at T = +25°C and T = +85°C. Limits to -40°C are guaranteed by design.
A
A
Note 3: V
can be 0V anytime, or V
can go down to 0V if V
is active (except at startup).
BATT
CC
BATT
Note 4: Use external current-limit resistor to limit current to 20mA (max).
Note 5: CEIN/CEOUT resistance is tested with V = 5V and V = 0V or 5V.
CEIN
CC
Note 6: WDI is internally serviced within the watchdog period if WDI is left unconnected.
Note 7: The WDI input current is specified as the average input current when the WDI input is driven high or low. The WDI input is
designed for a three-stated output device with a 10µA maximum leakage current and capable of driving a maximum capaci-
tive load of 200pF. The three-state device must be able to source and sink at least 200µA when active.
Table 1b. Reset Threshold Ranges
(MAX16020/MAX16021)
Table 1a. Reset Threshold Ranges
(MAX16016)
RESET THRESHOLD RANGES (V)
SUFFIX
RESET THRESHOLD RANGES (V)
SUFFIX
MIN
TYP
MAX
4.852
4.585
3.190
3.034
2.716
2.390
2.255
1.710
1.618
MIN
TYP
4.63
4.38
3.08
2.93
2.63
2.32
2.19
1.67
1.575
MAX
4.906
4.635
3.239
3.080
2.755
2.425
2.288
1.733
1.639
L
M
T
4.520
4.275
3.010
2.862
2.568
2.260
2.133
1.616
1.528
4.684
4.428
3.100
2.946
2.640
2.323
2.192
1.661
1.571
L
M
T
4.508
4.264
2.991
2.845
2.549
2.243
2.117
1.603
1.514
S
S
R
Z
R
Z
Y
Y
W
V
W
V
_______________________________________________________________________________________
5
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
Table 2. Low-Line Threshold Ranges
LOW-LINE THRESHOLD RANGES (V)
SUFFIX
MIN
TYP
MAX
4.955
4.683
L
M
T
4.627
4.806
4.543
3.181
3.023
2.409
2.383
2.246
1.704
1.612
4.378
3.075
2.922
2.620
3.274
3.111
2.787
S
R
Z
2.309
2.180
1.653
1.563
2.450
2.311
1.752
1.657
Y
W
V
Typical Operating Characteristics
(V = 5V, V
CC
= 0V, T = +25°C, unless otherwise noted.)
A
BATT
V
SUPPLY CURRENT
V
SUPPLY CURRENT
BATT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
CC
CC
vs. SUPPLY VOLTAGE
vs. TEMPERATURE (I
= 0mA)
OUT
6
5
4
3
2
1
0
0.7
0.6
0.5
0.4
5
MAX16020PTEZ+
MAX16020PTEZ+
= 2.5V
MAX16020PTEZ+
V
BATT
4
3
2
1
0
0.3
0.2
0.1
/MAX6021
0
-40
-15
10
35
60
85
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
BATTERY SUPPLY CURRENT
BATT STANDBY CURRENT
vs. TEMPERATURE
V
CC
TO OUT ON-RESISTANCE
vs. SUPPLY VOLTAGE
vs. TEMPERATURE (V = 0V)
CC
0.5
0.4
0.3
0.2
0.1
0
5
4
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 3.0V
V
V
= 3.2V
MAX16020PTEZ+
BATT
CC
= 3.0V
BATT
3
I
= 25mA
OUT
2
1
0
-1
-2
-3
-4
-5
I
= 10mA
OUT
-40
-15
10
35
60
85
-40
-15
10
35
60
85
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
Typical Operating Characteristics (continued)
(V = 5V, V
CC
= 0V, T = +25°C, unless otherwise noted.)
A
BATT
V
CC
TO OUT ON-RESISTANCE
vs. TEMPERATURE
BATT TO OUT ON-RESISTANCE
RESET OUTPUT VOLTAGE LOW
vs. SINK CURRENT
vs. TEMPERATURE (V = 0V, I
= 20mA)
CC
OUT
0.5
0.4
0.3
0.2
0.1
0
5
5
4
3
2
1
0
V
= 3.15V, I
= 65mA
CC
OUT
V
= 2.5V
BATT
4
3
2
1
0
V
= 3V
BATT
V
= 3.3V
CC
V
= 5V
CC
V
= 4.5V
BATT
0
2
4
6
8
10 12 14 16 18 20
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SINK CURRENT (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET TIMEOUT PERIOD
vs. TEMPERATURE
NORMALIZED RESET THRESHOLD
vs. TEMPERATURE
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
210
208
206
204
202
200
198
196
194
192
190
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.996
500
450
400
350
300
MAX16020PTEZ+
MAX16020PTEZ+
250
200
150
100
50
RESET OCCURS ABOVE THE CURVE
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
50 100 150 200 250 300 350 400
RESET THRESHOLD OVERDRIVE (mV)
TEMPERATURE (°C)
TEMPERATURE (°C)
NORMALIZED LL THRESHOLD
vs. TEMPERATURE
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
PFI THRESHOLD
vs. TEMPERATURE
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.65
0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
0.56
0.55
V
PFI+
V
PFI-
35
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
Typical Operating Characteristics (continued)
(V = 5V, V
CC
= 0V, T = +25°C, unless otherwise noted.)
A
BATT
V
SUPPLY CURRENT
BATTON OUTPUT VOLTAGE LOW
vs. SINK CURRENT
WDO OUTPUT VOLTAGE LOW
vs. SINK CURRENT
CC
vs. WDI FREQUENCY
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
70
60
50
40
30
20
10
0
V
= 3.3V
V
= 3.3V
CC
CC
V
= 5V
V
= 5V
CC
CC
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
10
100
1000
SINK CURRENT (mA)
SINK CURRENT (mA)
WDI FREQUENCY (kHz)
BATTOK OUTPUT VOLTAGE LOW
vs. SINK CURRENT
MR FALLING TO RESET DELAY
MAX16016 toc20
0.5
0.4
0.3
0.2
0.1
0
MR
5V/div
V
= 3.3V
CC
V
= 5V
CC
RESET
5V/div
/MAX6021
0
2
4
6
8
10 12 14 16 18 20
200ns/div
SINK CURRENT (mA)
RESET PROPAGATION DELAY
vs. THRESHOLD OVERDRIVE
CHIP-ENABLE GATING LOCKING OUT
SIGNAL DURING RESET CONDITION
MAX16016 toc22
70
60
50
40
30
20
10
0
MAX16020PTEZ+
RESET
5V/div
CEIN
5V/div
CEOUT
5V/div
0
50 100 150 200 250 300 350 400
THRESHOLD OVERDRIVE (mV)
10µs/div
8
_______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
Pin Description—MAX16016
PIN
NAME
FUNCTION
1
V
Supply Voltage Input. Bypass V
to GND with a 0.1µF capacitor.
CC
CC
Backup Battery Input. If V
falls below its reset threshold, and if V
> V , OUT connects to
BATT CC
CC
BATT. If V
capacitor.
rises above 1.01 x V
, OUT connects to V . Bypass BATT to GND with a 0.1µF
2
3
4
BATT
MR
CC
BATT CC
Active-Low Manual Reset Input. RESET asserts when MR is pulled low. RESET remains low for the
duration of reset timeout period after MR transitions from low to high. Connect MR to V or leave
unconnected if not used. MR is internally connected to V
CC
through a 30kΩ pullup resistor.
CC
Power-Fail Comparator Input. Connect PFI to a resistive divider to set the desired PFI threshold. The
PFI input is referenced to an internal V threshold. A V internal hysteresis provides noise
PFI
PFT
PFT-HYS
immunity. The power-fail comparator is powered from OUT.
Watchdog Timer Input. If WDI remains high or low for longer than the watchdog timeout period (t ),
WD
the internal watchdog timer runs out and a reset pulse is triggered for the reset timeout period. The
internal watchdog clears when reset asserts or whenever WDI sees a rising or falling edge. To
disable the watchdog feature, leave WDI unconnected or three-state the driver connected to WDI.
5
WDI
6
7
8
BATTON Active-High Battery-On Output. BATTON goes high when in battery-backup mode.
Active-Low Power-Fail Comparator Output. PFO goes low when V
falls below the internal V
PFT
PFI
PFO
threshold and goes high when V
rises above V
+ V
hysteresis.
PFI
PFT
PFT-HYS
GND
Ground
Active-Low Reset Output. RESET asserts when V falls below the reset threshold or M R is pulled low.
CC
9
RESET
RESET remains low for the duration of the reset timeout period after V rises above the reset threshold
CC
and M R goes high. RESET also asserts low when the internal watchdog timer runs out.
Switched Output. OUT is connected to V
when the reset output is not asserted or when V
is
CC
CC
10
OUT
greater than V
. OUT connects to BATT when RESET is asserted and V
is greater than V
.
BATT
BATT
CC
Bypass OUT to GND with a 0.1µF (min) capacitor.
_______________________________________________________________________________________
9
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
Pin Description—MAX16020/MAX16021
PIN
NAME
FUNCTION
MAX16020 MAX16021
Backup Battery Input. If V
falls below its reset threshold, and if V
> V , OUT
BATT CC
CC
connects to BATT. If V
CC
GND with a 0.1µF capacitor.
rises above 1.01 x V
, OUT connects to V . Bypass BATT to
1
2
3
1
2
3
BATT
BATT CC
Active-Low Manual Reset Input. RESET asserts when MR is pulled low. RESET remains low
for the duration of reset timeout period after MR transitions from low to high. Connect MR to
MR
V
or leave unconnected if not used. MR is internally connected to V
through a 30kΩ
CC
CC
pullup resistor.
Power-Fail Comparator Input. Connect PFI to a resistive divider to set the desired PFI
threshold. The PFI input is referenced to an internal threshold V , V internal
PFI
PFT PFT-HYS
hysteresis provides noise immunity. The power-fail comparator is powered from OUT.
Watchdog Timer Input. If WDI remains high or low for longer than the watchdog timeout
period (t ), the internal watchdog timer runs out and asserts WDO. The internal watchdog
clears when reset asserts or whenever WDI sees a rising or falling edge. To disable the
watchdog feature, leave WDI unconnected or three-state the driver connected to WDI.
WD
4
5
4
5
WDI
Active-Low Low-Line Output. LL goes low when V
falls to 2.5% above the reset threshold
CC
(Table 2). LL provides an early warning of V
failure before reset asserts. Use this output
CC
LL
to generate a nonmaskable interrupt (NMI) to initiate an orderly shutdown routine when
is falling.
V
CC
Open-Drain Battery-Test Output. Pulses low for 1.3s every 24 hours during the battery
BATT_TEST voltage test. If V < 2.6V, BATTOK deasserts low. See Figure 6 for providing additional
6
—
6
BATT
load during the battery test.
Active-High Reset Output. RESET asserts when V falls below the reset threshold or when
CC
/MAX6021
MR asserts and stays asserted for the reset timeout period after V
threshold and MR deasserts.
rises above the reset
—
RESET
CC
Battery-OK Output. BATTOK goes low when the battery voltage falls below the BATTOK
threshold (BATTOK is low when in battery-backup mode).
7
8
7
8
BATTOK
BATTON
Active-High Battery-On Output. BATTON goes high when in battery-backup mode.
10 ______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
Pin Description—MAX16020/MAX16021 (continued)
PIN
NAME
FUNCTION
MAX16020 MAX16021
Active-Low Watchdog Output. WDO asserts when WDI remains high or low longer than the
watchdog timeout period. WDO returns high on the next WDI transition or when a reset is
asserted.
9
9
WDO
Active-Low Power-Fail Comparator Output. PFO goes low when V
falls below the internal
hysteresis.
PFT-HYS
PFI
10
11
10
11
PFO
0.6V V
threshold and goes high when V
rises above V
+ V
PFT
PFI
PFT
GND
Ground
Active-Low Reset Output. RESET asserts when V falls below the reset threshold or MR is
CC
12
13
14
12
13
14
RESET
pulled low. RESET remains low for the duration of the reset timeout period after V rises
above the reset threshold and MR goes high.
CC
Switched Output. OUT is connected to V
when the reset output is not asserted or when
CC
V
is greater than V
. OUT connects to BATT when RESET is asserted and V
is
OUT
CC
BATT
BATT
greater than V . Bypass OUT to GND with a 0.1µF (min) capacitor.
CC
Active-Low Chip-Enable Output. CEOUT goes low only when CEIN is low and reset is not
asserted. If CEIN is low when reset is asserted, CEOUT stays low for 12µs (typ) or until
CEIN goes high, whichever occurs first.
CEOUT
CEIN
15
16
15
16
Chip-Enable Input. The input to CE gating circuitry. Connect to GND or OUT if not used.
V
Supply Voltage Input. Bypass V to GND with a 0.1µF capacitor.
CC
CC
Exposed Pad. Internally connected to GND. Connect EP to a large ground plane to aid
heat dissipation. Do not use EP as the only ground connection for the device.
—
—
EP
______________________________________________________________________________________ 11
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
Functional Diagrams
BATT
BATTERY
FRESHNESS SEAL
OUT
V
CC
BATTON
RESET
MR
DELAY
RESET
OUT
REF
PFO
/MAX6021
PFI
CLEAR
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
WDI
MAX16016
100nA
25kΩ
GND
12 ______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
Functional Diagrams (continued)
BATT
BATTERY TEST
CIRCUIT
BATT_TEST
(MAX16020 ONLY)
BATTERY
FRESHNESS SEAL
DISABLE
OUT
V
CC
LATCH
BATTOK
BATTON
MR
RESET
(RESET)
(MAX16021
ONLY)
DELAY
RESET
LL
OUT
REF
OUT
PF1
WDI
PFO
CE OUTPUT
CONTROL
CLEAR
WATCHDOG
TRANSITION
DETECTOR
WDO
WATCHDOG
TIMER
25kΩ
CEIN
CEOUT
100nA
MAX16020
MAX16021
GND
______________________________________________________________________________________ 13
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
brownout. During normal operation, the CE gate is
Detailed Description
enabled and passes all CE transitions. When the reset
The Typical Application Circuit shows a typical connec-
output asserts, this path becomes disabled, preventing
erroneous data from corrupting the CMOS RAM.
CEOUT is pulled up to OUT through an internal current
source. The 1.5ns propagation delay from CEIN to
CEOUT allows the devices to be used with most µPs
and high-speed DSPs.
tion using the MAX16020. OUT powers the static ran-
dom-access memory (SRAM). If V
is greater than the
CC
reset threshold (V ), or if V
is lower than V , but
TH
, V
CC
TH
higher than V
connects to OUT. If V
is lower
BATT CC
CC
than V and V
is less than V
, BATT connects to
TH
CC
BATT
OUT (see the Functional Diagrams). In battery-backup
mode, an internal MOSFET connects the backup battery
to OUT. The on-resistance of the MOSFET is a function of
backup-battery voltage and temperature.
During normal operation (reset not asserted), CEIN is
connected to CEOUT through a low on-resistance
transmission gate. If CEIN is high when a reset asserts,
CEOUT remains high regardless of any subsequent
transition on CEIN during the reset event.
Backup-Battery Switchover
In a brownout or power failure, it may be necessary to
preserve the contents of the RAM. With a backup battery
installed at BATT, the MAX16016/MAX16020/MAX16021
automatically switch the RAM to the backup power when
If CEIN is low when reset asserts, CEOUT is held low
for 12µs to allow completion of the read/write operation.
After the 12µs delay expires, CEOUT goes high and
stays high regardless of any subsequent transitions on
CEIN during the reset event. When CEOUT is disconnect-
ed from CEIN, CEOUT is actively pulled up to OUT.
V
CC
falls. The MAX16016/MAX16020/MAX16021 have a
BATTON output that goes high when in battery-backup
mode. These devices require two conditions before
switching to battery-backup mode:
The propagation delay through the CE circuitry
depends on both the source impedance of the drive to
CEIN and the capacitive loading at CEOUT. Minimize
the capacitive load at CEOUT to minimize the propaga-
tion delay, and use a low output-impedance driver.
1) V
2) V
must be below the reset threshold.
CC
CC
must be below V
.
BATT
Table 3 lists the status of the inputs and outputs in bat-
tery-backup mode. The device does not power up if the
only voltage source is on BATT. OUT only powers up
Low-Line Output (LL)
The low-line comparator monitors V
with a threshold
CC
from V
at startup.
CC
voltage typically 2.5% higher than the reset threshold
(see Table 2). LL asserts prior to a reset condition during
a brownout condition. On power-up, LL deasserts after
the reset output. LL can be used to provide a nonmask-
able interrupt (NMI) to the µP when the voltage begins to
fall to initiate an orderly software shutdown routine.
CE Signal Gating
The MAX16020/MAX16021 provide internal gating of
CE signals to prevent erroneous data from being written
to CMOS RAM in the event of a power failure or
/MAX6021
Table 3. Input and Output Status in
Battery-Backup Mode
Manual Reset Input
Many µP-based products require manual reset capability,
allowing the operator, a test technician, or external logic
circuitry to initiate a reset. For the MAX16016/MAX16020/
MAX16021, a logic-low on MR asserts RESET/RESET.
RESET/RESET remains asserted while MR is low. When
MR goes high RESET/RESET deasserts after a minimum
PIN
STATUS
V
Disconnected from OUT
CC
OUT
Connected to BATT
Connected to OUT. Current drawn from the
of 145ms (t ). MR has an internal 30kΩ pullup resistor to
RP
BATT
battery is less than 0.55µA (at V
= 3V,
BATT
V
. MR can be driven with TTL/CMOS logic levels or
CC
excluding I
) when V
= 0V.
OUT
CC
with open-drain/collector outputs. Connect a normally
open momentary switch from MR to GND to create a
manual reset function; external debounce circuitry is not
required. If MR is driven from a long cable or the device is
used in a noisy environment, connect a 0.1µF capacitor
from MR to GND to provide additional noise immunity.
RESET/RESET Asserted
High state (push-pull), high impedance
(open-drain)
BATTON, WDO
BATTOK, LL
CEIN
Low state
Disconnected from CEOUT
CEOUT
PFO
Pulled up to V
Not affected
OUT
14 ______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
Watchdog Timer
watchdog fault occurs in this mode, WDO goes low,
which pulls MR low, causing a reset pulse to be issued.
As soon as the reset output is asserted, the watchdog
timer clears and WDO returns high. With WDO connect-
ed to MR, a continuous high or low on WDI causes
145ms (min) reset pulses to be issued every 1.235s.
Watchdog Input
The watchdog monitors µP activity through the input
WDI. If the µP becomes inactive, either the reset output is
asserted in pulses (MAX16016) or the watchdog output
goes low (MAX16020/MAX16021). To use the watchdog
function, connect WDI to a bus line or µP I/O line. If WDI
remains high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and RESET
asserts for the reset timeout period (MAX16016) or WDO
goes low (MAX16020/MAX16021). The internal watchdog
timer clears whenever the reset output asserts or the
WDI sees a rising or falling edge within the watchdog
timeout period. The WDI input is designed for a three-
stated output device with a 10µA maximum leakage cur-
rent and the capability of driving a maximum capacitive
load of 200pF. The three-state device must be able to
source and sink at least 200µA when active. Disable the
watchdog timer by leaving WDI unconnected or by
three-stating the driver connected to WDI. The watchdog
timer periodically attempts to pulse WDI to the opposite
logic-level through a 25kΩ resistor for 40µs to determine
whether WDI is either unconnected or latched to a logic
state. The watchdog function is also disabled when in
battery-backup mode.
Battery Testing Function/BATTOK
Indicator (MAX16020/MAX16021)
The MAX16020/MAX16021 feature a battery testing
function that works in conjunction with the BATTOK out-
put. The battery voltage is tested for 1.235s after V
is
CC
applied and once every 24 hours thereafter. During this
test, an internal 100kΩ resistor is connected from BATT
to ground and the battery is monitored to ensure that
the battery voltage is above 2.6V. If the battery voltage
is below 2.6V, the BATTOK output deasserts low to indi-
cate a weak battery condition. The MAX16020 has a
BATT_TEST output that pulses high during the battery
voltage test. Connect a resistor and FET as shown in
Figure 6 to provide an additional load during the battery
test. In battery-backup mode, the battery testing function
is disabled and BATTOK goes low.
Battery Freshness Seal Mode
The MAX16016/MAX16020/MAX16021 battery fresh-
ness seal disconnects the backup battery from internal
Watchdog Output
WDO remains high if there is a transition or pulse at WDI
during the watchdog-timeout period. WDO goes low if no
transition occurs at WDI during the watchdog timeout
period and remains low until the next transition at WDI or
when a reset is asserted. Connect WDO to MR to gener-
ate a system reset on every watchdog fault. When a
circuitry and OUT until V
is applied. This ensures the
CC
backup battery connected to BATT is fresh when the
final product is used for the first time.
The internal freshness seal latch prevents BATT from
powering OUT until V
has come up for the first time,
CC
CC
setting the latch. When V
subsequently turns off,
BATT begins to power OUT.
t
t
t
WD
WD
WD
WDI
WDO
Figure 1. Watchdog Timing (MAX16016/MAX16020)
______________________________________________________________________________________ 15
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
To reenable the freshness seal:
1) Connect a battery to BATT.
Power-Fail Comparator
The MAX16016/MAX16020/MAX16021 offer an under-
voltage comparator that the output PFO goes low when
2) Bring V
to 0V.
CC
the voltage at PFI falls below its V
threshold.
PFT
3) Drive MR higher than V
+ 1.2V for at least 3µs.
BATT
Common uses for the power-fail comparator include
monitoring the power supply (such as a battery) before
any voltage regulation to provide an early power-fail
warning, so software can conduct an orderly system
shutdown. The power-fail comparator has a typical
4) Pull OUT to 0V.
Reset Output
A µP’s reset input starts the µP in a known state. The
µP supervisory circuits assert a reset to prevent code-
execution errors during power-up, power-down, and
brownout conditions. Reset output is guaranteed to be
a logic-low or logic-high depending on the device cho-
input hysteresis of V
and is powered from OUT,
PFT-HYS
making it independent of the reset circuit. Connect the
PFI input to GND if not used.
sen. RESET or RESET asserts when V
is below the
Applications Information
CC
reset threshold and remains asserted for at least 145ms
(t ) after V rises above the reset threshold. RESET
Monitoring an Additional Supply
The MAX16016/MAX16020/MAX16021 µP supervisors
can monitor either positive or negative supplies using a
resistive voltage-divider to PFI. PFO can be used to
generate an interrupt to the µP or to trigger a reset
(Figures 2 and 3). To monitor a negative supply, con-
RP
CC
or RESET also asserts when MR is low. The MAX16016
watchdog function causes RESET to assert in pulses
following a watchdog timeout. The reset output is avail-
able in both push-pull and open-drain configurations.
nect the top of the resistive divider to V . Connect the
CC
bottom of the resistive divider to the negative voltage to
be monitored.
5V
V
1
0.1µF
R1
0.1µF
V
V
2
CC
/MAX6021
V
CC
PFI
PFO
R1
R2
RESET
RESET
PFI
µP
MAX16016
MAX16020
MAX16021
R2
MAX16016L
MAX16020L
MAX16021L
V-
PFO
MR
GND
R2
R1
GND
V
TRIP
= V
PFT
-
(5 - V
)
—
PFT
ADDITIONAL SUPPLY RESET VOLTAGE
R1+R2
V
IS NEGATIVE
TRIP
+5V
V
= V
x
2(RESET) PFT (—)
R2
PFO
0
V
TRIP
V-
0V
Figure 3. Monitoring a Negative Supply
Figure 2. Monitoring an Additional Supply by Connecting PFO
to MR
16 ______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
Adding Hysteresis to PFI
Battery-On Indicator (Push-Pull Version)
BATTON goes high when in battery-backup mode. Use
BATTON to indicate battery-switchover status or to sup-
ply base drive to an external pass transistor for higher
current applications (Figure 5).
The power-fail comparators have a typical input hys-
teresis of V
. This is sufficient for most applica-
PFT-HYS
tions where a power-supply line is being monitored
through an external voltage-divider (see the Monitoring
an Additional Supply section). Figure 4 shows how to
add hysteresis to the power-fail comparator. Select the
Operation Without a Backup Power Source
The MAX16016/MAX16020/MAX16021 provide a bat-
tery-backup function. If a backup power source is not
ratio of R1 and R2 so that PFI sees V
when V falls
IN
PFT
to the desired trip point (V
). Resistor R3 adds hys-
TRIP
used, connect BATT to GND and OUT to V
.
CC
teresis. R3 is typically an order of magnitude greater
than R1 or R2. R3 should be larger than 50kΩ to pre-
vent it from loading down PFO. Capacitor C1 adds
additional noise rejection.
+5V
V
CC
V
IN
0.1µF
1µF
0.1µF
R1
R2
V
CC
V
BATTON
CC
OUT
PFI
BATT
CEOUT
CE
C1*
R3
MAX16016L
MAX16020L
MAX16021L
CMOS RAM
MAX16020L
ADDRESS
DECODE
PFO
CEIN
MR
A0–A15
TO µP
µP
RESET
RESET
GND
*OPTIONAL
R1+R2
R2
GND
V
= V
x
TRIP PFT (—)
R1 R1
+
+
1
V
= (V + V
) x
H
PFT PFT-HYS (– – )
R2 R3
Figure 5. BATTON Driving an External Pass Transistor
V
V
- V
R3
PFT
CC PFT
+
V = R1 x
+ V
L
(
—
—
WHERE V IS THE POWER-FAIL THRESHOLD VOLTAGE
)
PFT
R2
PFT
+5V
PFO
0
V
L
V
H
V
IN
V
TRIP
Figure 4. Adding Hysteresis to the Power-Fail Comparator
______________________________________________________________________________________ 17
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
Replacing the Backup Battery
is above V , the backup power source can
TH
When V
CC
be removed without danger of triggering a reset pulse.
The device does not enter battery-backup mode when
CC
BATT
V
stays above the reset threshold voltage.
V
CC
Negative-Going V
Transients
CC
R
LOAD
The MAX16016/MAX16020/MAX16021 are relatively
immune to short duration, negative going V tran-
MAX16020L
CC
sients. Resetting the µP when V
experiences only
CC
small glitches is usually not desirable. A 0.1µF bypass
BATT_TEST
capacitor mounted close to V
transient immunity.
provides additional
CC
Figure 6. Adjustable BATT_TEST Load
/MAX6021
18 ______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
Pin Configurations (continued)
TOP VIEW
16
15
14
13
+
BATT
MR
1
2
3
4
12 RESET
11 GND
10 PFO
10
9
2
8
7
4
6
5
MAX16021
MAX16016
3
PFI
EP
+
EP
1
WDI
9
WDO
5
6
7
8
TDFN
TQFN
Typical Application Circuit
3.3V
0.1µF
SECONDARY
DC VOLTAGE
0.1µF
V
CC
R1
R2
V
CC
RESET
LL
RST
NMI
I/O
PFI
µP
WDI
WDO
I/O
A0–A15
MAX16020L
OUT
0.1µF
(MIN)
PFO
MR
RAM
CE
CEOUT
CEIN
RTC
BATT
ADDRESS
DECODE
GND
0.1µF
______________________________________________________________________________________ 19
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
Selector Guide
ALL LOGIC
OUTPUTS (EXCEPT
BATT_TEST)
LOW-
LINE
OUTPUT
BATTOK/
BATT_TEST/
RESET
POWER-FAIL
COMPARATOR
WATCHDOG
TIMER
CHIP-
ENABLE
PART
MR
BATTON
MAX16016LTB_
MAX16016PTB_
Push-pull
√
√
√
√
WDI
WDI
√
√
—
—
—
—
—
—
Open-drain
BATTOK/
BATT_TEST
MAX16020LTE_
MAX16020PTE_
MAX16021LTE_
MAX16021PTE_
Push-pull
Open-drain
Push-pull
√
√
√
√
√
√
√
√
WDI/WDO
WDI/WDO
WDI/WDO
WDI/WDO
√
√
√
√
√
√
√
√
√
√
√
√
BATTOK/
BATT_TEST
BATTOK/
RESET
BATTOK/
RESET
Open-drain
Ordering Information (continued)
Chip Information
PROCESS: BiCMOS
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TQFN-EP*
16 TQFN-EP*
MAX16020_TE_+T
MAX16021_TE_+T
The first placeholder “_” designates all output options. Letter
“L” indicates push-pull outputs and letter “P” indicates open-
drain outputs. The last placeholder “_” designates the reset
threshold (see Table 1).
T = Tape and reel.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
/MAX6021
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN-EP
16 TQFN-EP
T1033+1
T1644+4
21-0137
21-0139
90-0093
90-0070
20 ______________________________________________________________________________________
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
/MAX6021
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
3
5/08
7/08
Initial release
—
Released the MAX16016. Updated Ordering Information, Electrical
Characteristics, Tables 1 and 2, Pin Description, and Detailed Description.
1, 3, 4, 5, 9, 10, 12,
13, 15, 16, 19, 20
10/08
12/08
Released the MAX16021.
20
Updated Electrical Characteristics, Pin Description, Table 3, and the Power-
Fail Comparator section.
3, 9, 10, 11, 14, 16
4
5
6
1/10
4/11
Updated Electrical Characteristics.
Updated Pin Description.
4
9, 10
9, 10
11/11
Updated Pin Description.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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