MAX16046A [MAXIM]
12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers; 12通道/ 8通道EEPROM可编程系统管理器，提供非易失故障寄存器
| 型号： | MAX16046A |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers |
| 文件： | 总71页 (文件大小：1016K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5251; Rev 0; 4/10
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
General Description
Features
o Operates from 3V to 14V
The MAX16046A/MAX16048A EEPROM-configurable sys-
tem managers monitor, sequence, track, and margin mul-
tiple system voltages. The MAX16046A manages up to
twelve system voltages simultaneously, and the
MAX16048A manages up to eight supply voltages. These
devices integrate an analog-to-digital converter (ADC) for
monitoring supply voltages, digital-to-analog converters
(DAC) for adjusting supply voltages, and configurable out-
puts for sequencing and tracking supplies (during power-
up and power-down). Nonvolatile EEPROM registers are
configurable for storing upper and lower voltage limits,
setting timing and sequencing requirements, and for
storing critical fault data for readback following failures.
o 1% Accurate 10-Bit ADC Monitors 12/8 Inputs
o 12/8 Monitored Inputs with 1 Overvoltage/
1 Undervoltage/1 Selectable Limit
o 12/8 8-Bit DAC Outputs for Margining or Voltage
Adjustments
o Nonvolatile Fault Event Logger
o Power-Up and Power-Down Sequencing
Capability
o 12/8 Outputs for Sequencing/Power-Good
Indicators
o Closed-Loop Tracking for Up to Four Channels
An internal 1% accurate 10-bit ADC measures each input
and compares the result to one upper, one lower, and
one selectable upper or lower limit. A fault signal asserts
when a monitored voltage falls outside the set limits. Up
to three independent fault output signals are configurable
to assert under various fault conditions.
o Two Programmable Fault Outputs and One Reset
Output
o Six General-Purpose Input/Outputs Configurable as:
Dedicated Fault Output
Watchdog Timer Function
Manual Reset
Margin Enable Input
The integrated sequencer/tracker allows precise control
over the power-up and power-down order of up to twelve
(MAX16046A) or up to eight (MAX16048A) power sup-
plies. Four channels (EN_OUT1–EN_OUT4) support
closed-loop tracking using external series MOSFETs. Six
outputs (EN_OUT1–EN_OUT6) are configurable with
charge-pump outputs to directly drive MOSFETs without
closed-loop tracking.
2
o I C/SMBus-Compatible and JTAG Interface
o EEPROM-Configurable Time Delays, Thresholds,
and DAC Outputs
o 100 Bytes of Internal User EEPROM
o -40°C to +125°C Operating Temperature Range
The MAX16046A/MAX16048A include twelve/eight inte-
grated 8-bit DAC outputs for margining power supplies
when connected to the trim input of a point-of-load
(POL) module.
Applications
Servers
The MAX16046A/MAX16048A include six programmable
general-purpose inputs/outputs (GPIOs). GPIOs are
EEPROM configurable as dedicated fault outputs, as a
watchdog input or output (WDI/WDO), as a manual reset
(MR), or for margin control inputs.
Workstations
Storage Systems
Networking/Telecom
The MAX16046A/MAX16048A feature two methods of
fault management for recording information during sys-
tem shutdown events. The fault logger records a failure
in the internal EEPROM and sets a lock bit protecting
the stored fault data from accidental erasure.
Ordering Information
PART
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
64 TQFP-EP*
56 TQFN-EP*
64 TQFP-EP*
56 TQFN-EP*
MAX16046ACB+
MAX16046ATN+
MAX16048ACB+
MAX16048ATN+
2
An I C/SMBus™-compatible or a JTAG serial interface
configures the MAX16046A/MAX16048A. These devices
are offered in a 56-pin, 8mm x 8mm TQFN package or a
64-pin, 10mm x 10mm TQFP package and are fully speci-
fied from -40°C to +125°C.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Typical Operating Circuit
V
SUPPLY
OUT
FB
10μF
IN
IN
IN
DC-DC
GND
+3.3V
MON1
V
CC
EN
EN
EN
DACOUT1
EN_OUT1
V
CC
SCL
SDA
OUT
FB
MON2–MON11
DC-DC
GND
MAX16046A
RESET
INT
RESET
FAULT
WDI
μC
DACOUT2–
DACOUT11
I/O
EN_OUT1–
EN_OUT11
/MX16048A
WDO
INT
OUT
FB
MON12
ABP
DBP
A0
DC-DC
GND
1μF
1μF
DACOUT12
EN_OUT12
EN
GND
Selector Guide
VOLTAGE-DETECTOR
INPUTS
GENERAL-PURPOSE
INPUTS/OUTPUTS
SEQUENCING
OUTPUTS
PART
DAC OUTPUTS
MAX16046A
MAX16048A
12
8
12
8
6
6
12
8
2
_______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
ABSOLUTE MAXIMUM RATINGS
CC
V
to GND ....................……………………………-0.3V to +15V
EN_OUT1–EN_OUT6
EN, MON_, SCL, SDA, A0 ........................................-0.3V to +6V
GPIO_, RESET (configured as open drain) to GND.....-0.3V to +6V
EN_OUT1–EN_OUT6 (configured as open drain)
to GND.................................................................-0.3V to +12V
EN_OUT7–EN_OUT12 (configured as open drain)
to GND...................................................................-0.3V to +6V
GPIO_, EN_OUT_, RESET
(configured as charge pump) ............-0.3V to (V
+ 6V)
MON1–6
Continuous Current (all pins)............................................ 20mA
56-Pin TQFN (derate 47.6mW/°C above +70°C).........3810mW*
Thermal Resistance:
θ
θ
....................................................................................21°C/W
...................................................................................0.6°C/W
JA
JC
64-Pin TQFP (derate 43.5mW/°C above +70°C) ....3478.3mW*
Thermal Resistance:
(configured as push-pull) to GND .........-0.3V to (V
DBP, ABP to GND .........-0.3V to the lower of 3V or (V
+ 0.3V)
+ 0.3V)
DBP
CC
θ
θ
....................................................................................23°C/W
......................................................................................1°C/W
JA
JC
TCK, TMS, TDI.......................................................-0.3V to +3.6V
TDO ..........................................................-0.3V to (V
DACOUT_.................………………………-0.3V to (V
+ 0.3V)
+ 0.3V)
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
DBP
ABP
*As per JEDEC 51 Standard, Multilayer Board (PCB).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3V to 14V, T = -40°C to +125°C, unless otherwise specified. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
1.4
3
TYP
MAX
UNITS
RESET output asserted low
Operating Voltage Range
V
CC
V
V
14
Undervoltage Lockout
V
UVLO
2.85
Undervoltage-Lockout
Hysteresis
UVLO
(Note 2)
50
mV
HYS
V
= 14V, V = 3.3V, no load on any
EN
CC
Supply Current
I
4.8
6.5
mA
CC
output
DBP Regulator Voltage
ABP Regulator Voltage
Boot Time
V
V
C
C
= 1μF, no load on any output
2.6
2.7
2.88
0.8
2.8
2.96
1.5
V
V
DBP
DBP
ABP
CC
= 1μF, no load on any DACOUT_
2.78
ABP
t
V
> V
ms
%
BOOT
UVLO
Internal Timing Accuracy
ADC
(Note 3)
-10
+10
ADC Resolution
10
Bits
MON_ range set to ‘00’
0.65
0.75
0.95
0.85
0.95
1.15
0.8
T
-40°C to
A =
MON_ range set to ‘01’
MON_ range set to ‘10’
MON_ range set to ‘00’
MON_ range set to ‘01’
MON_ range set to ‘10’
+85°C
ADC Total Unadjusted Error
(Note 4)
ADC
%FSR
ERR
T
A =
-40°C to
+125°C
ADC Integral Nonlinearity
ADC
LSB
LSB
INL
ADC Differential Nonlinearity
ADC
0.8
DNL
ADC Total Monitoring Cycle
Time
MAX16046A, all channels monitored,
no MON_ fault detected (Note 5)
t
120
150
μs
CYCLE
MON1–MON4
MON5–MON12
46
65
100
140
MON_ Input Impedance
R
kꢀ
IN
_______________________________________________________________________________________
3
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V to 14V, T = -40°C to +125°C, unless otherwise specified. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
5.6
MAX
UNITS
MON_ range set to ‘00’ in r0Fh–r11h
MON_ range set to ‘01’ in r0Fh–r11h
MON_ range set to ‘10’ in r0Fh–r11h
MON_ range set to ‘00’ in r0Fh–r11h
MON_ range set to ‘01’ in r0Fh–r11h
MON_ range set to ‘10’ in r0Fh–r11h
EN voltage rising
ADC MON_ Ranges
ADC
RNG
V
2.8
1.4
5.46
2.73
1.36
0.525
0.500
ADC LSB Step Size
ADC
LSB
mV
V
V
TH_EN_R
EN Input-Voltage Threshold
V
EN voltage falling
0.486
-0.5
0
0.517
+0.5
5.5
TH_EN_F
EN Input Current
I
μA
V
EN
EN Input Voltage Range
CLOSED-LOOP TRACKING
Tracking Differential Voltage
Stop Ramp
V
V
V
> V
> V
V
< V
< V
150
20
mV
TRK
INS_
INS_
TH_PL, INS_
TH_PG
Tracking Differential Voltage
Hysteresis
%V
TRK
Tracking Differential Fault
Voltage
V
, V
TH_PL INS_
280
325
370
mV
TRK_F
TH_PG
/MX16048A
Slew-rate register set to ‘00’
Slew-rate register set to ‘01’
Slew-rate register set to ‘10’
Slew-rate register set to ‘11’
Power-good register set to ‘00’,
640
320
150
70
800
400
200
100
960
480
250
115
Track/Sequence Slew-Rate
Rising or Falling
TRK
V/s
SLEW
94
91.5
89
95
92.5
90
96
93.5
91
V
MON
_ = 3.5V
Power-good register set to ‘01’,
_ = 3.5V
V
MON
INS_ Power-Good Threshold
V
%V
MON_
TH_PG
Power-good register set to ‘10’,
_ = 3.5V
V
MON
Power-good register set to ‘11’,
_ = 3.5V
86.5
87.5
0.5
88.5
V
MON
Power-Good Threshold
Hysteresis
V
%V
TH_PG
PG_HYS
Power-Low Threshold
Power-Low Hysteresis
GPIO_ Input Impedance
V
INS_ falling
125
75
142
10
160
145
mV
mV
kꢀ
TH_PL
V
TH_PL_HYS
GPIO
GPIO_ configured as INS_
100
INR
INS_ to GND Pulldown
Impedance when Enabled
INS
V
= 2V
INS_
100
ꢀ
RPD
4
_______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V to 14V, T = -40°C to +125°C, unless otherwise specified. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
V
DAC
DAC Resolution
8
DACOUT_ range set to ‘11’
DACOUT_ range set to ‘10’
DACOUT_ range set to ‘01’
DACOUT_ range set to ‘11’
DACOUT_ range set to ‘10’
DACOUT_ range set to ‘01’
0.8
DAC Output Voltage Range
DAC
RNG
0.6
0.4
3.137
2.353
1.568
1.202
DAC LSB Step Size
mV
T
A
= +25°C
= -5°C to
1.195
1.190
1.208
1.215
T
A
I
=
50μA,
DACOUT
+85°C
mid code, DACOUT_
range set to ‘11’
T
A
= -40°C to
1.187
0.896
0.890
1.218
0.907
0.912
+125°C
T
T
= +25°C
= -5°C to
0.901
0.601
A
I
=
50μA,
A
DACOUT
DAC Center Code Absolute
Accuracy
+85°C
DAC
mid code, DACOUT_
range set to ‘10’
V
ACC
T
A
= -40°C to
0.888
0.597
0.592
0.915
0.606
0.612
+125°C
T
A
= +25°C
T
A
= -5°C to
I
=
50μA,
DACOUT
+85°C
= -40°C to
mid code, DACOUT_
range set to ‘01’
T
A
0.590
0.615
+125°C
Any range, T
Any range, T
-40°C to +85°C
-40°C to +125°C
-0.8
-1.0
+0.8
+1.0
+8
A =
Gain Error
%
A =
DAC Output Sink Capability
DAC Output Source Capability
DAC Output Switch Leakage
DAC Output Capacitive Load
DAC Output Settling Time
DAC
Sinking current, I
= 0.5mA
mV
mV
nA
pF
μs
SINK
DACOUTMAX
DAC
Sourcing current, I
= -0.5mA
-8
SOURCE
DACOUTMAX
DACOUT_ switch off
(Note 5)
-150
+150
50
50
60
40
DC
DAC Power-Supply Rejection
Ratio
DAC
dB
PSRR
100mV step in 20ns with 50pF load
DACOUT_ code from 07h to F8h,
any range
DAC Differential Nonlinearity
DAC Integral Nonlinearity
DAC
-0.6
-0.9
+0.6
+0.9
LSB
LSB
DNL
DACOUT_ code from 07h to F8h,
any range
DAC
INL
_______________________________________________________________________________________
5
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V to 14V, T = -40°C to +125°C, unless otherwise specified. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.4
1
UNITS
OUTPUTS (EN_OUT_, RESET, GPIO_)
Output-Voltage Low
V
I
I
= 2mA
V
V
OL
SINK
Output-Voltage High (Push-Pull)
=100μA
2.4
SOURCE
Output Leakage (Open Drain)
I
μA
V
GPIO1–GPIO4, V
GPIO1–GPIO4, V
= 3.3V
= 5.0V
1
OUT_LKG
GPIO_
GPIO_
23
EN_OUT_ Overdrive (Charge
Pump) (EN_OUT1 to EN_OUT6
V
I
= 0.5μA
GATE_
4.6
4.5
5.1
5.6
OV
Only) Volts above V
MON_
EN_OUT_ Pullup Current (Charge
Pump)
During power-up/power-down,
= 1V
I
6
μA
μA
CHG_UP
V
GATE_
EN_OUT_ Pulldown Current
(Charge Pump)
During power-up/power-down,
= 5V
I
10
CHG_DOWN
V
GATE_
INPUTS (A0, GPIO_)
Logic-Input Low Voltage
Logic-Input High Voltage
SMBUS INTERFACE
Logic-Input Low Voltage
Logic-Input High Voltage
V
0.8
V
V
IL
V
2.0
IH
/MX16048A
V
Input voltage falling
Input voltage rising
0.8
+1
V
V
IL
V
2.0
-1
IH
V
CC
shorted to GND, SCL/SDA at 0V or
3.3V
Input Leakage Current
μA
-1
+1
Output-Voltage Low
Input Capacitance
SMBUS TIMING
V
I
= 3mA
SINK
0.4
V
OL
C
5
pF
IN
Serial Clock Frequency
f
400
kHz
μs
SCL
Bus Free Time Between STOP
and START Condition
t
1.3
BUF
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
t
0.6
0.6
0.6
1.3
0.6
200
μs
μs
μs
μs
μs
ns
SU:STA
HD:STA
SU:STO
t
t
t
LOW
Clock High Period
t
HIGH
Data Setup Time
t
t
SU:DAT
T
T
-40°C to +85°C
250
500
10pF ꢀ C
400pF
ꢀ
A =
BUS
Output Fall Time
t
ns
OF
-40°C to +125°C
A =
Receive
Transmit
0
Data Hold Time
μs
ns
HD:DAT
0.3
0.9
Pulse Width of Spike Suppressed
t
30
SP
6
_______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V to 14V, T = -40°C to +125°C, unless otherwise specified. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
JTAG INTERFACE
TDI, TMS, TCK Logic-Low Input
Voltage
V
Input voltage falling
Input voltage rising
0.55
V
V
IL
TDI, TMS, TCK Logic-High Input
Voltage
V
2
IH
TDO Logic-Output Low Voltage
TDO Logic-Output High Voltage
TDO Leakage Current
V
V
V
ꢀ 2.5V, I
ꢀ 2.5V, I
= 2mA
0.4
V
OL_TDO
DBP
SINK
V
= 200mA
2.4
-1
7
V
OH_TDO
DBP
SOURCE
TDO high impedance
Pullup to V
+1
13
μA
kꢁ
pF
TDI, TMS Pullup Resistors
Input/Output Capacitance
JTAG TIMING
R
JPU
10
5
DBP
C
I/O
TCK Clock Period
t
1000
ns
ns
ns
ns
ns
1
TCK High/Low Time
t
t
50
15
15
500
2, 3
TCK to TMS, TDI Setup Time
TCK to TMS, TDI Hold Time
TCK to TDO Delay
t
t
t
4
5
6
500
500
TCK to TDO High-Impedance
Delay
t
ns
7
EEPROM TIMING
EEPROM Byte Write Cycle Time
t
(Note 6)
16
20
ms
WR
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at T = +25°C
A
and T = +125°C. Specifications at T = -40°C are guaranteed by design.
A
A
Note 2: V
is the minimum voltage on V
to ensure the device is EEPROM configured.
UVLO
CC
Note 3: Applies to RESET, fault, delay, and watchdog timeouts.
Note 4: Total unadjusted error is a combination of gain, offset, and quantization error.
Note 5: Guaranteed by design.
Note 6: An additional cycle is required when writing to configuration memory for the first time.
_______________________________________________________________________________________
7
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
SDA
t
BUF
t
SU:DAT
t
SU:STA
t
t
SU:STO
HD:DAT
t
t
LOW
HD:STA
SCL
t
HIGH
t
HD:STA
t
t
R
F
START
STOP
START
REPEATED START
CONDITION
CONDITION
CONDITION
CONDITION
2
Figure 1. I C/SMBus Timing Diagram
/MX16048A
t
1
t
t
2
3
TCK
t
t
4
5
TDI, TMS
t
6
t
7
TDO
Figure 2. JTAG Timing Diagram
8
_______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Typical Operating Characteristics
(V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
V
SUPPLY CURRENT
CC
NORMALIZED MON_ THRESHOLD
vs. TEMPERATURE
NORMALIZED EN THRESHOLD
vs. TEMPERATURE
CC
vs. V SUPPLY VOLTAGE
4.0
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
T
= +125°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
A
T
= +85°C
A
RISING
FALLING
T
=+25°C
A
T
= -40°C
A
2.8V RANGE, HALF-SCALE
PRIMARY UNDERVOLTAGE
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
-45 -25 -5 15 35 55 75 95 115 135
TEMPERATURE (°C)
-45 -25 -5 15 35 55 75 95 115 135
TEMPERATURE (°C)
V
(V)
CC
TRANSIENT DURATION
vs. THRESHOLD OVERDRIVE (EN)
NORMALIZED RESET TIMEOUT PERIOD
vs. TEMPERATURE
160
140
120
100
80
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
60
40
20
0
1
10
100
-45 -25 -5 15 35 55 75 95 115 135
TEMPERATURE (°C)
EN OVERDRIVE (mV)
MINIMUM TRANSIENT DURATION
vs. MON_ PUV THRESHOLD OVERDRIVE
OUTPUT-VOLTAGE LOW
vs. SINK CURRENT
250
200
150
100
50
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
DEGLITCH = 16
EN_OUT_
GPIO_
DEGLITCH = 8
DEGLITCH = 4
DEGLITCH = 2
0
10
175
340
505
670
835 1000
0
1
2
3
4
5
6
THRESHOLD OVERDRIVE (mV)
SINK CURRENT (mA)
_______________________________________________________________________________________
9
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Typical Operating Characteristics (continued)
(V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
ADC ACCURACY
vs. TEMPERATURE
OUTPUT-VOLTAGE HIGH vs. SOURCE
CURRENT (PUSH-PULL OUTPUT)
OUTPUT-VOLTAGE HIGH vs. SOURCE
CURRENT (CHARGE-PUMP OUTPUT)
6
5
4
3
2
1
0
2.70
2.65
2.60
2.55
2.50
2.45
2.40
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
5.6V RANGE, INPUT = 2.5V
0
1
2
3
4
5
6
7
0
100
200
300
400
-45 -25 -5 15 35 55 75 95 115 135
TEMPERATURE (°C)
SOURCE CURRENT (μA)
SOURCE CURRENT (μA)
FET TURN-ON WITH CHARGE PUMP
TRACKING MODE
MAX16046A toc11
MAX16046A toc12
/MX16048A
V
EN_OUT_
10V/div
INS4
INS3
INS2
0V
V
SOURCE
1V/div
0V
2V/div
INS1
0V
I
DRAIN
1A/div
0V
20ms/div
20ms/div
TRACKING MODE WITH
FAST SHUTDOWN
SEQUENCING MODE
MAX16046A toc13
MAX16046A toc14
INS4
INS3
INS2
INS4
INS3
1V/div
0V
1V/div
0V
INS2
INS1
INS1
20ms/div
40ms/div
10 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Typical Operating Characteristics (continued)
(V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
DACOUT_ VOLTAGE
vs. TEMPERATURE
ADC DNL
MIXED MODE
MAX16046A toc15
1.0
0.8
1.30
0.8V TO 1.6V RANGE,
HALF SCALE
1.28
1.26
0.6
0.4
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
INS4
0.2
INS3
INS2
INS1
1V/div
0V
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
128 256 384 512 640 768 896 1024
INPUT VOLTAGE (DIGITAL CODE)
-45 -25 -5 15 35 55 75 95 115 135
TEMPERATURE (°C)
20ms/div
INTERNAL TIMING ACCURACY
vs. TEMPERATURE
ADC INL
1.0
0.8
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
128 256 384 512 640 768 896 1024
INPUT VOLTAGE (DIGITAL CODE)
-45 -25 -5 15 35 55 75 95 115 135
TEMPERATURE (°C)
______________________________________________________________________________________ 11
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Pin Descriptions
PIN
NAME
FUNCTION
THIN QFN
MAX16046A MAX16048A
ADC Monitored Voltage Inputs. Set ADC input range for each MON_ through
configuration registers. Measured values are written to ADC registers and can be
read back through the I C or JTAG interface.
MON1–
MON8
1–8
1–8
—
2
ADC Monitored Voltage Inputs. Set ADC input range through configuration registers.
Measured values are written to ADC registers and can be read back through the I C
or JTAG interface.
MON9–
MON12
2
9–12
9–12, 33–36,
53–56
—
N.C.
No Connection. Must be left unconnected.
Configurable Reset Output
13
13
RESET
Four-State SMBus Address. Address sampled upon POR. Connect A0 to ground,
DBP, SCL, or SDA to program an individual address when connecting multiple
devices. See the I C/SMBus-Compatible Serial Interface section.
14
14
A0
2
15
16
15
16
SCL
SDA
TMS
TDI
SMBus Serial Clock Input
SMBus Serial Data Open-Drain Input/Output
JTAG Test Mode Select
17
17
/MX16048A
18
18
JTAG Test Data In
19
19
TCK
TDO
GND
JTAG Test Clock
20
20
JTAG Test Data Out
21, 40
21, 40
Ground. Connect all GND connections together.
General-Purpose Input/Output. GPIO6 and GPIO5 are configurable as open-drain or
push-pull outputs, dedicated fault outputs, or for watchdog functionality. GPIO5 is
configurable as a watchdog input (WDI). GPIO6 is configurable as a watchdog
output (WDO). These inputs/outputs are also configurable for margining. Use the
EEPROM to configure GPIO5 and GPIO6. See the General-Purpose Inputs/Outputs
section.
22
23
22
23
GPIO6
GPIO5
Analog Enable Input. Apply a voltage greater than the 0.525V (typ) threshold to
enable all outputs. The power-down sequence is triggered when EN falls below 0.5V
(typ) and all outputs are deasserted.
24
24
EN
DAC Outputs. DACOUT1–DACOUT8 are the outputs of an internal 8-bit DAC. Set
DACOUT1–DACOUT8 ranges through configuration registers. Connect a DACOUT_
DACOUT8 to an external DC-DC converter for margining. Leave DACOUT_ outputs
unconnected, if unused.
DACOUT1–
25–32
25–32
DAC Outputs. DACOUT9–DACOUT12 are the outputs of an internal 8-bit DAC. Set
DACOUT9–
DACOUT9–DACOUT12 ranges through configuration registers. Connect a
33–36
—
DACOUT12 DACOUT_ to an external DC-DC converter for margining. Leave DACOUT_ outputs
unconnected, if unused.
12 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Pin Descriptions (continued)
PIN
NAME
FUNCTION
THIN QFN
MAX16046A MAX16048A
Internal Analog Voltage Bypass. Bypass ABP to GND with a 1μF ceramic capacitor.
ABP powers the internal circuitry of the MAX16046A/MAX16048A. Do not use ABP
to power any external circuitry.
37
38
37
38
ABP
V
CC
Power-Supply Input. Bypass V to GND with a 10μF ceramic capacitor.
CC
Internal Digital Voltage Bypass. Bypass DBP to GND with a 1μF ceramic capacitor.
DBP supplies power to the EEPROM memory, to the internal logic circuitry, and to
the internal charge pumps when the programmable outputs are configured as
charge pumps. All push-pull outputs are referenced to DBP. Do not use DBP to
power any external circuitry.
39
41
42
39
41
42
DBP
General-Purpose Input/Output 1. Configure GPIO1 as a logic input, a return sense
line for closed-loop tracking, an open-drain/push-pull fault output, or an open-
drain/push-pull output port. Use the EEPROM to configure GPIO1. See the General-
Purpose Inputs/Outputs section.
GPIO1
GPIO2
General-Purpose Input/Output 2. GPIO2 is configurable as a logic input, a return
sense line for closed-loop tracking, an open-drain/push-pull fault output, or an
open-drain/push-pull output port. GPIO2 is also configurable as a dedicated
MARGINUP input. Use the EEPROM to configure GPIO2. See the General-Purpose
Inputs/Outputs section.
General-Purpose Input/Output 3. GPIO3 is configurable as a logic input, a return
sense line for closed-loop tracking, an open-drain/push-pull fault output, or an
open-drain/push-pull output port. GPIO3 is also configurable as a dedicated
MARGINDN input. Use the EEPROM to configure GPIO3. See the General-Purpose
Inputs/Outputs section.
43
44
43
44
GPIO3
GPIO4
General-Purpose Input/Output 4. GPIO4 is configurable as a logic input, a return
sense line for closed-loop tracking, an open-drain/push-pull fault output, or an
open-drain/push-pull output port. GPIO4 is also configurable as an active-low
manual reset, MR. Use the EEPROM to configure GPIO4. See the General-Purpose
Inputs/Outputs section.
Output. EN_OUT1–EN_OUT6 are configurable with active-high/active-low logic and
with an open-drain or push-pull configuration. Program the EEPROM to configure
EN_OUT1–EN_OUT6 as a charge-pump output 5V greater than the monitored input
EN_OUT1–
EN_OUT6
45–50
45–50
voltage (V
tracking.
+ 5V). EN_OUT1–EN_OUT4 can also be used for closed-loop
MON_
EN_OUT7– Output. Configure EN_OUT_ with active-low/active-high logic and with an open-
EN_OUT8 drain or push-pull configuration.
51, 52
53–56
51, 52
—
EN_OUT9– Output. Configure EN_OUT_ with active-low/active-high logic and with an open-
EN_OUT12 drain or push-pull configuration.
Exposed Pad. Internally connected to GND. Connect to GND. EP also functions as a
—
—
EP
heatsink to maximize thermal dissipation. Do not use as the main ground
connection.
______________________________________________________________________________________ 13
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Pin Descriptions (continued)
PIN
NAME
FUNCTION
TQFP
MAX16046A MAX16048A
ADC Monitored Voltage Inputs. Set ADC input range for each IN_ through
MON1–
MON8
1–7, 10
11–14
1–7, 10
—
configuration registers. Measured values are written to ADC registers and can be
2
read back through the I C or JTAG interface.
ADC Monitored Voltage Inputs. Set ADC input range through configuration
registers. Measured values are written to ADC registers and can be read back
through the I C or JTAG interface.
MON9–
MON12
2
8, 9, 11–15,
25, 33, 38–
41, 48, 49,
60–64
8, 9, 15, 25,
33, 48,
N.C.
No Connection. Must leave unconnected.
Configurable Reset Output
49, 64
16
17
16
RESET
Four-State SMBus Address. Address sampled upon POR. Connect A0 to ground,
DBP, SCL, or SDA to program an individual address when connecting multiple
17
A0
2
devices. See the I C/SMBus-Compatible Serial Interface section.
18
19
18
19
SCL
SDA
TMS
TDI
SMBus Serial Clock Input
SMBus Serial Data Open-Drain Input/Output
JTAG Test Mode Select
JTAG Test Data In
/MX16048A
20
20
21
21
22
22
TCK
TDO
GND
JTAG Test Clock
23
23
JTAG Test Data Out
24, 45
24, 45
Ground
General-Purpose Input/Output. GPIO6 and GPIO5 are configurable as open-drain or
push-pull outputs, dedicated fault outputs, or for watchdog functionality. GPIO5 is
configurable as a watchdog input (WDI). GPIO6 is configurable as a watchdog
output (WDO). These inputs/outputs are also configurable for margining. Use the
EEPROM to GPIO5 and GPIO6. See the General-Purpose Inputs/Outputs section.
GPIO6,
GPIO5
26, 27
28
26, 27
28
Analog Enable Input. Apply a voltage greater than the 0.525V (typ) threshold to
enable all outputs. Power-down sequence triggered when EN falls below 0.5V (typ)
and all outputs are deasserted.
EN
DAC Outputs. DACOUT1–DACOUT8 are the outputs of an internal 8-bit DAC. Set
DACOUT_ ranges through configuration registers. Connect a DACOUT_ to an
external DC-DC converter for margining. Leave DACOUT_ outputs unconnected, if
unused.
29–32,
34–37
29–32,
34–37
DACOUT1–
DACOUT8
DAC Outputs. DACOUT9–DACOUT12 are the outputs of an internal 8-bit DAC. Set
DACOUT9– DACOUT_ ranges range through configuration registers. Connect a DACOUT_ to
38–41
—
an external DC-DC converter for margining. Leave DACOUT_ outputs
unconnected, if unused.
DACOUT12
14 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Pin Descriptions (continued)
PIN
NAME
FUNCTION
TQFP
MAX16046A MAX16048A
Internal Analog Voltage Regulator Output. Bypass ABP to GND with a 1μF ceramic
capacitor. ABP powers the internal circuitry of the MAX16046A/MAX16048A and
supplies power to the internal charge pumps when the programmable outputs are
configured as charge pumps. Do not use ABP to power any external circuitry.
42
43
44
42
43
44
ABP
V
CC
Power-Supply Input. Bypass V to GND with a 10μF ceramic capacitor.
CC
Internal Digital Voltage Regulator Output. Bypass DBP to GND with a 1μF ceramic
capacitor. DBP supplies power to the EEPROM memory and the internal logic
circuitry. All push-pull outputs are referenced to DBP. Do not use DBP to power
any external circuitry.
DBP
General-Purpose Input/Output 1. Configure GPIO1 as a TTL input, a return sense
line for closed-loop tracking, an open-drain/push-pull fault output, or an open-
drain/push-pull output port. Use the EEPROM to configure GPIO1. See the General-
Purpose Inputs/Outputs section.
46
47
46
47
GPIO1
General-Purpose Input/Output 2. GPIO2 is configurable as a TTL input, a return
sense line for closed-loop tracking, an open-drain/push-pull fault output, or an
open-drain/push-pull output port. GPIO2 is also configurable as a dedicated
MARGINUP input. Use the EEPROM to configure GPIO2. See the General-Purpose
Inputs/Outputs section.
GPIO2
GPIO3
GPIO4
General-Purpose Input/Output 3. GPIO3 is configurable as a TTL input, a return
sense line for closed-loop tracking, an open-drain/push-pull fault output, or an
open-drain/push-pull output port. GPIO3 is also configurable as a dedicated
MARGINDN input. Use the EEPROM to configure GPIO3. See the General-Purpose
Inputs/Outputs section.
50
50
General-Purpose Input/Output 4. GPIO4 is configurable as a TTL input, a return
sense line for closed loop tracking, an open-drain/push-pull fault output, or an
open-drain/push-pull output port. GPIO4 is also configurable as an active-low
manual reset, MR. Use the EEPROM to configure GPIO4. See the General-Purpose
Inputs/Outputs section.
51
51
Output. EN_OUT1–EN_OUT6 are configurable with active-high/active-low logic
and with open-drain or push-pull configurations. Program the EEPROM to configure
EN_OUT_ with a charge-pump output 5V greater than the monitored input voltage
EN_OUT1–
EN_OUT6
52–57
52–57
(V
+ 5V). EN_OUT1–EN_OUT4 can also be used for closed-loop tracking.
IN_
EN_OUT7,
EN_OUT8
Output. Configure EN_OUT_ with active-low/active-high logic and with an open-
drain or push-pull configuration.
58, 59
60–63
58, 59
—
EN_OUT9– Output. Configure EN_OUT_ with active-low/active-high logic and with an open-
EN_OUT12 drain or push-pull configuration.
Exposed Pad. Internally connected to GND. Connect to GND. EP also functions as
EP
EP
EP
a heatsink to maximize thermal dissipation. Do not use as the main ground
connection.
______________________________________________________________________________________ 15
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Functional Diagram
V
CC
MAX16046A
MAX16048A
FAULT1
FAULT2
EN
MR
LOGIC
MARGIN
MARGINUP
MARGINDN
V
TH_EN
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
DIGITAL COMPARATORS
NONVOLATILE
FAULT EVENT
LOGGER
WDI
WATCHDOG
TIMER
WDO
FAULTPU
MON1–
MON12
(MON1–
MON8)
VOLTAGE
SCALING
AND MUX
INS1
INS2
INS3
10-BIT
ADC (SAR)
ADC
REGISTERS
THRESHOLD
REGISTERS
CLOSED-LOOP
TRACKER
INS4
DACOUT1–
DACOUT12
(DACOUT1–
DACOUT8)
RAM
REGISTERS
DAC
REGISTERS
TRACK AND
HOLD
8-BIT DAC
/MX16048A
EN_OUT1–
EN_OUT12
(EN_OUT1–
EN_OUT8)
EN_OUT1–
EN_OUT4
SEQUENCER
EEPROM
REGISTERS
RESET
2
I C SLAVE
JTAG INTERFACE
INTERFACE
GND
A0 SDA SCL
TMS TCK TDI TDO
( ) MAX16048A ONLY.
16 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Register Summary (All Registers 8-Bits Wide)
Note: This data sheet uses a specific convention for referring to bits within a particular address location. As an example, r0Fh[3:0]
refers to bit 3 to bit 0 in register with address 15 decimal.
PAGE
REGISTER
DESCRIPTION
ADC Conversion Results
(Registers r00h to r17h)
Input ADC conversion results. ADC writes directly to these registers during normal
operation. ADC input ranges (MON1–MON12) are selected with registers r0Fh to r11h.
Failed Line Flags
(Registers r18h to r19h)
Voltage fault flag bits. Flags for each input signal when undervoltage or overvoltage
threshold is exceeded.
Extended
GPIO Data
GPIO state data. Used to read back and control the state of each GPIO.
(Registers r1Ah to r1Bh)
DAC Enables
(Registers r1Ch to r1Dh)
DAC output control. Controls whether DAC outputs are high impedance or connected
to the DAC.
DAC Registers
(Registers r00h to r0Bh)
Default
DAC code registers. Sets the output voltage of each DAC output.
ADC input voltage range. Selects the voltage range of the monitored inputs.
DAC range registers. Sets the voltage output range of each DAC output.
ADC Range Selections
(Registers r0Fh to r11h)
DAC Range
(Registers r12h to r14h)
RESET and Fault Outputs
(Registers r15h to r1Bh)
RESET and FAULT1–FAULT2 output configuration. Programs the functionality of the
RESET, FAULT1, and FAULT2 outputs, as well as which inputs they depend on.
General-purpose input/output configuration registers. GPIOs are configurable as a
manual-reset input, a margin disable input, margin-up/margin-down control inputs, a
watchdog timer input and output, logic inputs/outputs, fault-dependent outputs, or as
the feedback/pulldown inputs (INS_) for closed-loop tracking.
GPIO Configuration
(Registers r1Ch to r1Eh)
Programmable output configurations. Selectable output configurations include: active-
low or active-high, open-drain or push-pull outputs. EN_OUT1–EN_OUT6 are
configurable as charge-pump outputs and EN_OUT1–EN_OUT4 can be configured for
closed-loop tracking.
Programmable Output
Configuration
(Registers r1Fh to r22h)
Overvoltage and
Undervoltage Thresholds
(Registers r23h to r46h)
Input overvoltage and undervoltage thresholds. ADC conversion results are compared
to overvoltage and undervoltage threshold values stored here. MON_ voltages
exceeding threshold values trigger a fault event.
Default and
EEPROM
Selects how the device should operate during faults. Options include latch-off or
autoretry after fault. The autoretry delay is selectable (r4Fh). Use registers r48h
through r4Ch to select fault conditions that trigger a critical fault event.
Fault Behavior
(Registers r47h to r4Ch)
Use register r4Dh to set the Software Enable bit, to select early warning thresholds
and undervoltage/overvoltage, to enable/disable margining, and to enable/disable the
watchdog for independent/dependent mode.
Software Enable and Margin
(Register r4Dh)
Sequencing-Mode
Assign inputs and outputs for sequencing. Select sequence delays (20μs to 1.6s) with
Configuration (Registers r50h registers r50h through r54h. Use register r54h to enable/disable the reverse sequence
to r5Bh and r5Eh to r63h)
bit for power-down operation.
Watchdog Functionality
(Register r55h)
Configure watchdog functionality for GPIO5 and GPIO6.
DAC output levels depend on GPIO2 and GPIO3 when configured for margining
functionality. Set registers r66h to r71h for margin up. Set registers r72h to r7Dh for
margin down.
DAC Output Margin Levels
(Registers r66h to r7Dh)
Fault Log Results
(Registers r00h to r0Eh)
ADC conversion results and failed-line flags at the time of a fault. These values are
recorded by the fault event logger at the time of a critical fault.
EEPROM
User EEPROM (Registers
r9Ch to rFFh)
User-available EEPROM
______________________________________________________________________________________ 17
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Accessing the EEPROM
The MAX16046A/MAX16048A memory is divided into
Detailed Description
Getting Started
The MAX16046A is capable of managing up to twelve
system voltages simultaneously, and the MAX16048A
can manage up to eight system voltages. After boot-
up, if EN is high and the Software Enable bit is set to
‘0,’ an internal multiplexer cycles through each input. At
each multiplexer stop, the 10-bit ADC converts the
monitored analog voltage to a digital result and stores
the result in a register. Each time the multiplexer finish-
es a conversion (12.45μs max), internal logic circuitry
compares the conversion results to the overvoltage and
undervoltage thresholds stored in memory. When a
conversion violates a programmed threshold, the con-
version can be configured to generate a fault. Logic
outputs can be programmed to depend on many com-
binations of faults. Additionally, faults are programma-
ble to trigger the nonvolatile fault logger, which writes
all fault information automatically to the EEPROM and
write-protects the data to prevent accidental erasure.
three separate pages. The default page, selected by
default at POR, contains configuration bits for all func-
tions of the part. The extended page contains the ADC
conversion results, GPIO input and output registers,
and DAC enable bits. Finally, the EEPROM page con-
tains all stored configuration information as well as
saved fault data and user-defined data. See the
Register Map table for more information on the function
of each register.
During the boot-up sequence, the contents of the
EEPROM (r0Fh to r7Dh) are copied into the default
page (r0Fh to r7Dh). Registers r00h to r0Bh of the
default page contain the DAC output voltage registers,
and are reset to ‘0’s at POR. Registers r00h to r0Eh of
the EEPROM page contain saved fault data.
2
The JTAG and I C interfaces provide access to all
three pages. Each interface provides commands to
select and deselect a particular page:
2
2
• 98h(I C)/09h(JTAG)—Switches to the extended
The MAX16046A/MAX16048A contain both I C/SMBus
page. Switch back to the default page with
and JTAG serial interfaces for accessing registers and
EEPROM. Use only one interface at any given time. For
more information on how to access the internal memory
2
99h(I C)/0Ah(JTAG).
/MX16048A
2
• 9Ah(I C)/0Bh(JTAG)—Switches to the EEPROM
2
through these interfaces, see the I C/SMBus-Compatible
page. Switch back to the default page with
2
Serial Interface and JTAG Serial Interface sections.
Registers are divided into three pages with access con-
9Bh(I C)/0Ch(JTAG).
2
See the I C/SMBus-Compatible Serial Interface or the
2
trolled by special I C and JTAG commands.
JTAG Serial Interface section.
The factory-default values at POR (power-on reset) for
Power
to power the MAX16046A/
to ground with a 10μF capaci-
all RAM registers are ‘0’s. POR occurs when V
reach-
CC
Apply 3V to 14V to V
CC
CC
es the undervoltage-lockout threshold (UVLO) of 2.85V
(max). At POR, the device begins a boot-up sequence.
During the boot-up sequence, all monitored inputs are
masked from initiating faults and EEPROM contents are
copied to the respective register locations. During boot-
up, the MAX16046A/MAX16048A are not accessible
through the serial interface. The boot-up sequence can
take up to 1.5ms, after which the device is ready for
normal operation. RESET is low during boot-up and
asserts after boot-up for its programmed timeout period
once all monitored channels are within their respective
thresholds. During boot-up, the GPIOs, DACOUTs, and
EN_OUTs are high impedance.
MAX16048A. Bypass V
tor. Two internal voltage regulators, ABP and DBP, supply
power to the analog and digital circuitry within the device.
Do not use ABP or DBP to power external circuitry.
ABP is a 2.85V (typ) voltage regulator that powers the
internal analog circuitry and supplies power to the DAC
outputs. Bypass the ABP output to GND with a 1μF
ceramic capacitor installed as close to the device as
possible.
DBP is an internal 2.7V (typ) voltage regulator.
EEPROM and digital circuitry are powered by DBP. All
push-pull outputs are referenced to DBP. DBP supplies
the input voltage to the internal charge pumps when
the programmable outputs are configured as charge-
pump outputs. Bypass the DBP output to GND with a
1μF ceramic capacitor installed as close as possible to
the device.
18 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
If a fault condition occurs during the power-up cycle,
the EN_OUT_ outputs are powered down immediately,
independent of the state of EN. If operating in latch-on
fault mode, toggle EN or toggle the Software Enable bit
to clear the latch condition and restart the device once
the fault condition has been removed.
Enable
To initiate sequencing/tracking and enable monitoring,
the voltage at EN must be above 0.525V and the
Software Enable bit in r4Dh[0] must be set to ‘0.’ To
power down and disable monitoring, either pull EN
below 0.5V or set the Software Enable bit to ‘1.’ See
Table 1 for the software enable bit configurations.
Connect EN to ABP if not used.
Table 1. EEPROM Software Enable Configurations
REGISTER/
BIT RANGE
DESCRIPTION
EEPROM ADDRESS
SoftwareEnable bit
0 = Enabled. EN must also be high to begin sequencing.
1 = Disabled (factory default)
0
1
2
Margin bit
1 = Margin functionality is enabled
0 = Margin disabled
4Dh
Early Warning Selection bit
0 = Early warning thresholds are undervoltage thresholds
1 = Early warning thresholds are overvoltage thresholds
Watchdog Mode Selection bit
3
0 = Watchdog timer is in dependent mode
1 = Watchdog timer is in independent mode
[7:4]
Not used
figuration registers are set to ‘11,’ MON_ voltages are
not monitored or converted, and the multiplexer does
not stop at these inputs, decreasing the total cycle
time. These inputs cannot be configured to trigger fault
conditions.
Voltage Monitoring
The MAX16046A/MAX16048A feature an internal 10-bit
ADC that monitors the MON_ voltage inputs. An internal
multiplexer cycles through each of the twelve inputs,
taking 150μs (typ) for a complete monitoring cycle.
Each acquisition takes approximately 12.45μs. At each
multiplexer stop, the 10-bit ADC converts the analog
input to a digital result and stores the result in a regis-
ter. ADC conversion results are stored in registers r00h
The three programmable thresholds for each monitored
voltage include an overvoltage, an undervoltage, and
an early warning threshold that can be set in r4Dh[2] to
be either an undervoltage or overvoltage threshold. See
the Faults section for more information on setting over-
voltage and undervoltage thresholds. All voltage
thresholds are 8 bits wide. The 8 MSBs of the 10-bit
ADC conversion result are compared to these overvolt-
age and undervoltage thresholds.
2
to r17h in the extended page. Use the I C or JTAG seri-
al interface to read ADC conversion results. See the
2
I C/SMBus-Compatible Serial Interface or the JTAG
Serial Interface section for more information on access-
ing the extended page.
The MAX16046A provides twelve inputs, MON1–
MON12, for voltage monitoring. The MAX16048A pro-
vides eight inputs, MON1–MON8, for voltage monitor-
ing. Each input voltage range is programmable in
registers r0Fh to r11h (see Table 2). When MON_ con-
For any undervoltage or overvoltage condition to be
monitored and any faults detected, the MON_ input
must be assigned to a particular sequence order. See
the Sequencing section for more details on assigning
MON_ inputs.
______________________________________________________________________________________ 19
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 2. Input Monitor Ranges and Enables
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
MON1 Voltage Range Selection:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
[1:0]
11 = MON1 is not converted or monitored
MON2 Voltage Range Selection:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON2 is not converted or monitored
[3:2]
[5:4]
[7:6]
[1:0]
[3:2]
[5:4]
[7:6]
0Fh
MON3 Voltage Range Selection:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON3 is not converted or monitored
MON4 Voltage Range Selection:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON4 is not converted or monitored
/MX16048A
MON5 Voltage Range Selection:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON5 is not converted or monitored
MON6 Voltage Range Selection:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON6 is not converted or monitored
10h
MON7 Voltage Range Selection:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON7 is not converted or monitored
MON8 Voltage Range Selection:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON8 is not converted or monitored
20 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Table 2. Input Monitor Ranges and Enables (continued)
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
MON9 Voltage Range Selection*:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
[1:0]
11 = MON9 is not converted or monitored
MON10 Voltage Range Selection*:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON10 is not converted or monitored
[3:2]
[5:4]
[7:6]
11h
MON11 Voltage Range Selection*:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON11 is not converted or monitored
MON12 Voltage Range Selection*:
00 = From 0 to 5.6V in 5.46mV steps
01 = From 0 to 2.8V in 2.73mV steps
10 = From 0 to 1.4V in 1.36mV steps
11 = MON12 is not converted or monitored
*MAX16046A only
______________________________________________________________________________________ 21
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
The extended memory page contains the ADC conver-
sion result registers (see Table 3). These registers are
also used internally for fault threshold comparison.
Voltage-monitoring thresholds are compared with the 8
MSBs of the conversion results. Inputs that are not
enabled are not converted by the ADC; they contain the
last value acquired before that channel was disabled.
The ADC conversion result registers are reset to 00h at
boot-up. These registers are not reset when a reboot
command is executed.
Table 3. ADC Conversion Registers
EXTENDED PAGE
BIT RANGE
DESCRIPTION
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
[7:0]
[7:6]
[5:0]
MON1 ADC Conversion Result (MSB)
MON1 ADC Conversion Result (LSB)
Reserved
MON2 ADC Conversion Result (MSB)
MON2 ADC Conversion Result (LSB)
Reserved
MON3 ADC Conversion Result (MSB)
MON3 ADC Conversion Result (LSB)
Reserved
MON4 ADC Conversion Result (MSB)
MON4 ADC Conversion Result (LSB)
Reserved
MON5 ADC Conversion Result (MSB)
MON5 ADC Conversion Result (LSB)
Reserved
MON6 ADC Conversion Result (MSB)
MON6 ADC Conversion Result (LSB)
Reserved
MON7 ADC Conversion Result (MSB)
MON7 ADC Conversion Result (LSB)
Reserved
MON8 ADC Conversion Result (MSB)
MON8 ADC Conversion Result (LSB)
Reserved
MON9 ADC Conversion Result (MSB)*
MON9 ADC Conversion Result (LSB)*
Reserved
MON10 ADC Conversion Result (MSB)*
MON10 ADC Conversion Result (LSB)*
Reserved
MON11 ADC Conversion Result (MSB)*
MON11 ADC Conversion Result (LSB)*
Reserved
MON12 ADC Conversion Result (MSB)*
MON12 ADC Conversion Result (LSB)*
Reserved
/MX16048A
*MAX16046A only
22 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
and output, logic inputs/outputs, fault-dependent out-
puts, or as the feedback inputs (INS_) for closed-loop
tracking. When programmed as outputs, GPIOs are
open drain or push-pull. See registers r1Ch to r1Eh in
Tables 4 and 5 for more detailed information on config-
uring GPIO1–GPIO6.
General-Purpose Inputs/Outputs
GPIO1–GPIO6 are programmable general-purpose
inputs/outputs. GPIO1–GPIO6 are configurable as a
manual reset input, a margin disable input, margin-
up/margin-down control inputs, a watchdog timer input
Table 4. General-Purpose IO Configuration Registers
REGISTER/
BIT RANGE
DESCRIPTION
EEPROM ADDRESS
[2:0]
[5:3]
[7:6]
[0]
GPIO1 Configuration Register
GPIO2 Configuration Register
1Ch
GPIO3 Configuration Register (LSB)
GPIO3 Configuration Register (MSB)
GPIO4 Configuration Register
GPIO5 Configuration Register
GPIO6 Configuration Register (LSB)
GPIO6 Configuration Register (MSB)
Reserved
[3:1]
[6:4]
[7]
1Dh
1Eh
[1:0]
[7:2]
Table 5. GPIO Mode Selection
CONFIGURATION
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
BITS
000
INS1
INS2
INS3
INS4
—
MARGIN input
Push-pull logic
input/output
Push-pull logic
input/output
Push-pull logic
input/ output
Push-pull logic
input/output
Push-pull logic
input/output
Push-pull logic
input/output
001
Open-drain
logic
input/output
Open-drain
logic
input/output
Open-drain
logic input/
output
Open-drain
logic
input/output
Open-drain
logic input/
output
Open-drain
logic input/
output
010
011
Push-pull
Push-pull
Push-pull
Push-pull
Push-pull
Push-pull
FAULT2 output
Any_Fault output Any_Fault output Any_Fault output Any_Fault output FAULT1 output
Open-drain Open-drain Open-drain Open-drain Open-drain
Any_Fault output Any_Fault output Any_Fault output Any_Fault output FAULT1 output
Open-drain
FAULT2 output
100
101
110
Logic input
Logic input
Logic input
Logic input
Logic input
Logic input
Open-drain,
WDO output
—
—
—
—
—
MARGINUP
MARGINDN
Open-drain,
FAULTPU output
111
—
MR input
WDI input
input
input
Note: The dash “—” represents a reserved GPIO configuration. Do not set any GPIO to these values.
______________________________________________________________________________________ 23
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Voltage Tracking Sense (INS_) Inputs
GPIO1–GPIO4 are configurable as feedback sense
return inputs (INS_) for closed-loop tracking. Connect the
gate of an external n-channel MOSFET to each EN_OUT_
configured for closed-loop tracking. Connect INS_ inputs
to the source of the MOSFETs for tracking feedback.
INS_ connections can also act as 100Ω pulldowns for
closed-loop tracking channels or for other power sup-
plies, if INS_ are connected to the outputs of the sup-
plies. Set the appropriate bits in r4Eh[7:4] to enable
pulldown functionality. See Table 13.
General-Purpose Logic Inputs/Outputs
Configure GPIO1–GPIO6 be used as general-purpose
inputs/outputs. Write values to GPIOs through r1Ah
when operating as outputs, and read values from r1Bh
when operating as inputs. Register r1Bh is read-only.
See Table 6 for more information on reading and writing
to the GPIOs as logic inputs/outputs. Both registers
r1Ah and r1Bh are located in the extended page and
are therefore not loaded from EEPROM on boot-up.
Internal comparators monitor INS_ with respect to a
control tracking ramp voltage for power-up/power-down
and control each EN_OUT_ voltage. Under normal con-
ditions each INS_ voltage tracks the ramp voltage until
the power-good voltage threshold has been reached.
The slew rate for the ramp voltage and the INS_ to
MON_ power-good threshold are programmable. See
the Closed-Loop Tracking section.
Table 6. GPIO Data-In/Data-Out Data
EXTENDED PAGE
BIT RANGE
DESCRIPTION
ADDRESS
GPIO Logic Output Data
0 = GPIO1 is a logic-low output
1 = GPIO1 is a logic-high output
[0]
/MX16048A
0 = GPIO2 is a logic-low output
1 = GPIO2 is a logic-high output
[1]
[2]
[3]
[4]
0 = GPIO3 is a logic-low output
1 = GPIO3 is a logic-high output
1Ah
0 = GPIO4 is a logic-low output
1 = GPIO4 is a logic-high output
0 = GPIO5 is a logic-low output
1 = GPIO5 is a logic-high output
0 = GPIO6 is a logic-low output
1 = GPIO6 is a logic-high output
[5]
[7:6]
[0]
Not used
GPIO Logic Input Data
GPIO1 logic-input state
[1]
[2]
GPIO2 logic-input state
GPIO3 logic-input state
GPIO4 logic-input state
GPIO5 logic-input state
GPIO6 logic-input state
Not used
1Bh
[3]
[4]
[5]
[7:6]
24 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Any_Fault Outputs
GPIO1–GPIO4 are configurable as active-low push-pull
or open-drain fault-dependent outputs. These outputs
assert when any monitored input exceeds an overvolt-
age, undervoltage, or early warning threshold.
outputs can assert on one or more overvoltage, under-
voltage, or early warning conditions for selected inputs.
FAULT1 and FAULT2 dependencies are set using reg-
isters r15h to r18h. See Table 7.
If a fault output depends on more than one MON_, the
fault output will assert if one or more MON_ exceeds a
programmed threshold voltage.
FAULT1 and FAULT2
GPIO5 and GPIO6 are configurable as dedicated fault
outputs, FAULT1 and FAULT2, respectively. Fault
Table 7. FAULT1 and FAULT2 Output Configuration and Dependencies
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
1 = FAULT1 is a digital output dependent on MON1
1 = FAULT1 is a digital output dependent on MON2
1 = FAULT1 is a digital output dependent on MON3
1 = FAULT1 is a digital output dependent on MON4
1 = FAULT1 is a digital output dependent on MON5
1 = FAULT1 is a digital output dependent on MON6
1 = FAULT1 is a digital output dependent on MON7
1 = FAULT1 is a digital output dependent on MON8
1 = FAULT1 is a digital output dependent on MON9*
1 = FAULT1 is a digital output dependent on MON10*
1 = FAULT1 is a digital output dependent on MON11*
1 = FAULT1 is a digital output dependent on MON12*
15h
16h
17h
1 = FAULT1 is a digital output that depends on the overvoltage thresholds at the input
selected by r15h and r16h[3:0]
[4]
[5]
[6]
[7]
1 = FAULT1 is a digital output that depends on the undervoltage thresholds at the
input selected by r15h and r16h[3:0]
1 = FAULT1 is a digital output that depends on the early warning thresholds at the
input selected by r15h and r16h[3:0]
0 = FAULT1 is an active-low digital output
1 = FAULT1 is an active-high digital output
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1 = FAULT2 is a digital output dependent on MON1
1 = FAULT2 is a digital output dependent on MON2
1 = FAULT2 is a digital output dependent on MON3
1 = FAULT2 is a digital output dependent on MON4
1 = FAULT2 is a digital output dependent on MON5
1 = FAULT2 is a digital output dependent on MON6
1 = FAULT2 is a digital output dependent on MON7
1 = FAULT2 is a digital output dependent on MON8
______________________________________________________________________________________ 25
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 7. FAULT1 and FAULT2 Output Configuration and Dependencies (continued)
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
[0]
[1]
[2]
[3]
1 = FAULT2 is a digital output dependent on MON9*
1 = FAULT2 is a digital output dependent on MON10*
1 = FAULT2 is a digital output dependent on MON11*
1 = FAULT2 is a digital output dependent on MON12*
1 = FAULT2 is a digital output that depends on the overvoltage thresholds at the input
selected by r17h and r18h[3:0]
[4]
[5]
[6]
[7]
18h
1 = FAULT2 is a digital output that depends on the undervoltage thresholds at the
input selected by r17h and 18h[3:0]
1 = FAULT2 is a digital output that depends on the early warning thresholds at the
input selected by r17h and r18h[3:0]
0 = FAULT2 is an active-low digital output
1 = FAULT2 is an active-high digital output
*MAX16046A only
DACOUT_ values set in registers r72h to r7Dh. Pull
both MARGINUP and MARGINDN high or low to select
DACOUT_ values set in registers r00h to r0Bh. See the
Voltage Margining section for more information on set-
ting DACOUT_ outputs for margining.
4
Fault-On Power-Up (FAULTPU)
GPIO6 indicates a fault during power-up or power-
down when configured as a “fault-on power-up” output.
Under these conditions, all EN_OUT_ voltages are
pulled low and fault data is saved to nonvolatile
EEPROM. See the Faults section.
Margin-up and margin-down functionality is controlled
by GPIO2 and GPIO3 when configured for margining
(see Table 8). When MARGINUP or MARGINDN are
asserted, the DAC output switches are automatically
closed and the margin function is enabled. Writing to
the DAC-enabled registers (r1Ch and r1Dh) is not
required to close the DAC switches. See the MARGIN
section for an explanation of the margin function.
MARGINUP and MARGINDN
Configure GPIO2 and GPIO3 as margin-up
(MARGINUP) and margin-down (MARGINDN) inputs,
respectively, for margining functionality. Pull
MARGINUP low and pull MARGINDN high to select
DACOUT_ voltage values set in registers r66h to r71h.
Pull MARGINDN low and pull MARGINUP high to select
Table 8. MARGINUP and MARGINDN FUNCTION
MARGINUP
(GPIO2)
MARGINDN
(GPIO3)
DACOUT
SWITCH STATE
DACOUT REGISTER USED
1
1
0
0
1
0
1
0
DACOUT registers r00h to r0Bh
MARGINDN registers r72h to r7Dh
MARGINUP registers r66h to r71h
DACOUT registers r00h to r0Bh
Depends on r1Ch, r1Dh*
Closed
Closed
Depends on r1Ch, r1Dh*
*Note: r1Ch and r1Dh are located in the extended page.
26 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
GPIO5 as WDI. WDO is an open-drain active-low output.
See the Watchdog Timer section for more information
about the operation of the watchdog timer.
MARGIN
GPIO6 is configurable as an active-low MARGIN input.
Drive MARGIN low before varying system voltages above
or below the thresholds to avoid signaling an error. Drive
MARGIN high for normal operation.
Programmable Outputs
(EN_OUT1–EN_OUT12)
When MARGIN is pulled low or r4Dh[1] is a ‘1,’ the mar-
gin function is enabled. FAULT1, FAULT2, Any_Fault,
and RESET are latched in their current state. Threshold
violations will be ignored, and faults will not be logged.
The MAX16046A includes twelve programmable out-
puts, and the MAX16048A includes eight programma-
ble outputs. These outputs are capable of connecting
to either the enable (EN) inputs of a DC-DC or LDO
power supply or to the gates of series-pass MOSFETs
for closed-loop tracking mode, or for charge-pump
mode. Selectable output configurations include: active-
low or active-high, open-drain or push-pull.
EN_OUT1–EN_OUT4 are also configurable for closed-
loop tracking, and EN_OUT1–EN_OUT6 can act as
charge-pump outputs with no closed-loop tracking.
Use the registers r1Fh to r22h to configure outputs. See
Table 9 for detailed information on configuring
EN_OUT1–EN_OUT12.
Manual Reset (MR)
GPIO4 is configurable to act as an active-low manual
reset input, MR. Drive MR low to assert RESET. RESET
remains low for the selected reset timeout period after
MR transitions from low to high. See the RESET section
for more information on selecting a reset timeout period.
Watchdog Input (WDI) and Output (WDO)
Set r1Eh[1:0] and register r1Dh[7] to ‘110’ to configure
GPIO6 as WDO. Set r1Dh[6:4] to ‘111’ to configure
Table 9. EN_OUT1–EN_OUT12 Configuration
REGISTER/
EEPROM ADDRESS
BIT
RANGE
DESCRIPTION
EN_OUT1 Configuration:
000 = EN_OUT1 is an open-drain active-low output
001 = EN_OUT1 is an open-drain active-high output
010 = EN_OUT1 is a push-pull active-low output
011 = EN_OUT1 is a push-pull active-high output
100 = EN_OUT1 is used in closed-loop tracking
101 = EN_OUT1 is configured with a charge-pump output (MON1 + 5V) capable of
driving an external n-channel MOSFET
110 = Reserved
111 = Reserved
EN_OUT2 Configuration:
000 = EN_OUT2 is an open-drain active-low output
001 = EN_OUT2 is an open-drain active-high output
010 = EN_OUT2 is a push-pull active-low output
011 = EN_OUT2 is a push-pull active-high output
100 = EN_OUT2 is used in closed-loop tracking
101 = EN_OUT2 is configured with a charge-pump output (MON2 + 5V) capable of
driving an external n-channel MOSFET
110 = Reserved
111 = Reserved
EN_OUT3 Configuration (LSBs):
[2:0]
[5:3]
[7:6]
1Fh
000 = EN_OUT3 is an open-drain active-low output
001 = EN_OUT3 is an open-drain active-high output
010 = EN_OUT3 is a push-pull active-low output
011 = EN_OUT3 is a push-pull active-high output
100 = EN_OUT3 is used in closed-loop tracking
101 = EN_OUT3 is configured with a charge-pump output (MON3 + 5V) capable of
driving an external n-channel MOSFET
110 = Reserved
111 = Reserved
______________________________________________________________________________________ 27
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 9. EN_OUT1–EN_OUT12 Configuration (continued)
REGISTER/EEPROM
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
EN_OUT3 Configuration (MSB)—see r1Fh[7:6]
EN_OUT4 Configuration:
000 = EN_OUT4 is an open-drain active-low output
001 = EN_OUT4 is an open-drain active-high output
010 = EN_OUT4 is a push-pull active-low output
011 = EN_OUT4 is a push-pull active-high output
100 = EN_OUT4 is used in closed-loop tracking
101 = EN_OUT4 is configured with a charge-pump output (MON4 + 5V) capable of
driving an external n-channel MOSFET
[3:1]
110 = Reserved
111 = Reserved
20h
EN_OUT5 Configuration:
000 = EN_OUT5 is an open-drain active-low output
001 = EN_OUT5 is an open-drain active-high output
010 = EN_OUT5 is a push-pull active low output
011 = EN_OUT5 is a push-pull active-high output
100 = Reserved. EN_OUT5 is not usable for closed-loop tracking.
101 = EN_OUT5 is configured with a charge-pump output (MON5 + 5V) capable of
driving an external n-channel MOSFET
[6:4]
[7]
/MX16048A
110 = Reserved
111 = Reserved
EN_OUT6 Configuration (LSB)—see r21h[1:0]
EN_OUT6 Configuration (MSBs):
000 = EN_OUT6 is an open-drain active-low output
001 = EN_OUT6 is an open-drain active-high output
010 = EN_OUT6 is a push-pull active-low output
011 = EN_OUT6 is a push-pull active-high output
100 = Reserved. EN_OUT6 is not useable for closed-loop tracking.
101 = EN_OUT6 is configured with a charge-pump output (MON6 + 5V) capable of
driving an external n-channel MOSFET
[1:0]
110 = Reserved
111 = Reserved
EN_OUT7 Configuration:
00 = EN_OUT7 is an open-drain active-low output
01 = EN_OUT7 is an open-drain active-high output
10 = EN_OUT7 is a push-pull active-low output
11 = EN_OUT7 is a push-pull active-high output
21h
[3:2]
[5:4]
[7:6]
EN_OUT8 Configuration:
00 = EN_OUT8 is an open-drain active-low output
01 = EN_OUT8 is an open-drain active-high output
10 = EN_OUT8 is a push-pull active-low output
11 = EN_OUT8 is a push-pull active-high output
EN_OUT9 Configuration*:
00 = EN_OUT9 is an open-drain active-low output
01 = EN_OUT9 is an open-drain active-high output
10 = EN_OUT9 is a push-pull active-low output
11 = EN_OUT9 is a push-pull active-high output
28 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Table 9. EN_OUT1–EN_OUT12 Configuration (continued)
REGISTER/EEPROM
ADDRESS
BIT
RANGE
DESCRIPTION
EN_OUT10 Configuration*:
00 = EN_OUT10 is an open-drain active-low output
01 = EN_OUT10 is an open-drain active-high output
10 = EN_OUT10 is a push-pull active-low output
11 = EN_OUT10 is a push-pull active-high output
[1:0]
[3:2]
EN_OUT11 Configuration*:
00 = EN_OUT11 is an open-drain active-low output
01 = EN_OUT11 is an open-drain active-high output
10 = EN_OUT11 is a push-pull active-low output
11 = EN_OUT11 is a push-pull active-high output
22h
EN_OUT12 Configuration*:
00 = EN_OUT12 is an open-drain active-low output
01 = EN_OUT12 is an open-drain active high output
10 = EN_OUT12 is a push-pull active-low output
11 = EN_OUT12 is a push-pull active-high output
[5:4]
[7:6]
Reserved
*MAX16046A only
Charge-Pump Configuration
Open-Drain Output Configuration
Connect an external pullup resistor from the output to
an external voltage up to 6V (abs max, EN_OUT7 to
EN_OUT12) or 12V (abs max, EN_OUT1 to EN_OUT6)
when configured as an open-drain output. Choose the
pullup resistor depending on the number of devices
connected to the open-drain output and the allowable
current consumption. The open-drain output configura-
tion allows wire-ORed connection.
EN_OUT1–EN_OUT6 can act as high-voltage charge-
pump outputs to drive up to six external n-channel
MOSFETs. During sequencing, an EN_OUT_ output
configured this way drives 6μA until the voltage reach-
es 5V above the corresponding MON_ to fully enhance
the external n-channel MOSFET. For example,
EN_OUT2 will rise to 5V above MON2. See the
Sequencing section for more detailed information on
power-supply sequencing.
Push-Pull Output Configuration
The MAX16046A/MAX16048As’ programmable outputs
sink 2mA and source 100μA when configured as push-
pull outputs.
Closed-Loop Tracking Operation
EN_OUT1–EN_OUT4 can operate in closed-loop track-
ing mode. When configured for closed-loop tracking,
EN_OUT1–EN_OUT4 are capable of driving the gates
of up to four external n-channel MOSFETs. For closed-
loop tracking, configure GPIO1–GPIO4 as return-sense
line inputs (INS_) to be used in conjunction with
EN_OUT1–EN_OUT4 and MON1–MON4. See the
Closed-Loop Tracking section.
EN_OUT_ State During Power-Up
When V
is ramped from 0V to the operating supply
CC
voltage, the EN_OUT_ output is high impedance until
V
CC
is approximately 2.4V and then EN_OUT_ will be in
its configured deasserted state. See Figures 3 and 4.
RESET is configured as an active-low open-drain output
pulled up to V
and 4.
through a 10kΩ resistor for Figures 3
CC
______________________________________________________________________________________ 29
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
MAX16046A fig03
MAX16046A fig04
V
CC
UVLO
2V/div
V
CC
2V/div
0V
0V
RESET
2V/div
RESET
2V/div
0V
0V
ASSERTED
LOW
EN_OUT_
2V/div
EN_OUT_
2V/div
0V
0V
HIGH-Z
20ms/div
10ms/div
Figure 3. RESET and EN_OUT_ During Power-Up, EN_OUT_ Is
in Open-Drain Active-Low Configuration
Figure 4. RESET and EN_OUT_ During Power-Up, EN_OUT_ Is
in Push-Pull Active-High Configuration
the programmed undervoltage limit; otherwise a fault
condition will occur. The fault occurs regardless of the
critical fault enable bits. This undervoltage limit cannot
be disabled during power-up and power-down.
EN_OUT_s configured for open-drain, push-pull, or
charge-pump operation are always asserted at the end
of a slot, following the sequence delay. See Tables 10,
11, and 12 for the MON_ slot assignment bits.
Sequencing
Each EN_OUT_ has one or more associated MON_
inputs, facilitating the voltage monitoring of multiple
power supplies. To sequence a system of power sup-
plies safely, the output voltage of a power supply must
be good before the next power supply may turn on.
Connect EN_OUT_ outputs to the enable input of an
external power supply and connect MON_ inputs to the
output of the power supply for voltage monitoring. More
than one MON_ may be used if the power supply has
multiple outputs.
/MX16048A
Slot 0 does not monitor any MON_ input. Instead, Slot 0
waits for the Software Enable bit r4Dh[0] to be a logic
‘0’ and for the voltage on EN to rise above 0.525V
before asserting any assigned outputs. Outputs
assigned to Slot 0 are asserted before the Slot 0
sequence delay. Generally, Slot 0 controls the enable
inputs of power supplies that are first in the sequence.
Sequence Order
The MAX16046A/MAX16048A utilize a system of
ordered slots to sequence multiple power supplies. To
determine the sequence order, assign each EN_OUT_
to a slot ranging from Slot 0 to Slot 11. EN_OUT_(s)
assigned to Slot 0 are turned on first, followed by out-
puts assigned to Slot 1, and so on through Slot 11.
Multiple EN_OUT_s assigned to the same slot turn on at
the same time.
Similarly, Slot 12 does not control any EN_OUT_ outputs.
Rather, Slot 12 monitors assigned MON_ inputs and then
enters the power-on state. Generally, Slot 12 monitors
the last power supplies in the sequence. The power-up
sequence is complete when any MON_ inputs assigned
to Slot 12 exceed their undervoltage thresholds and the
sequence delay is expired. If no MON_ inputs are
assigned to Slot 12, the power-up sequence is complete
after the slot sequence delay is expired.
Each slot has a built-in configurable sequence delay
(registers r50h to r54h) ranging from 20μs to 2.4s.
During a reverse sequence, slots are turned off in
reverse order starting from Slot 11. The MAX16046A/
MAX16048A may be configured to power-down in
simultaneous mode or in reverse sequence mode as
set in r54h[4]. See Tables 10, 11, and 12 for the
EN_OUT_ slot assignment bits, and Tables 13 and 14
for the sequence delays.
The output rail(s) of a power supply should be monitored
by one or more MON_ inputs placed in the succeeding
slot, ensuring that the output of the supply is not checked
until it has first been turned on. For example, if a power
supply uses EN_OUT1 located in Slot 3 and has two
monitoring inputs, MON1 and MON2, they must both be
assigned to Slot 4. In this example, EN_OUT1 turns on at
the end of Slot 3. At the start of Slot 4, MON1 and MON2
must exceed the undervoltage threshold before the pro-
grammed power-up fault delay; otherwise a fault triggers.
Monitoring Inputs While Sequencing
An enabled MON_ input may be assigned to a slot rang-
ing from Slot 1 to Slot 12. Monitoring inputs are always
checked at the beginning of a slot. The inputs are given
the power-up fault delay within which they must satisfy
30 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
dependencies. Power down EN_OUT_s simultaneously
or in reverse sequence mode by setting the Reverse
Sequence bit (r54h[4]) appropriately. In reverse
sequence mode (r54h[4] set to ‘1’), the EN_OUT_s
assigned to Slot 11 deassert, the MAX16046A/
MAX16048A wait for the Slot 11 sequence delay and
then proceed to Slot 10, and so on until the EN_OUT_s
assigned to Slot 0 turn off. When simultaneous power-
down is selected (r54h[4] set to ‘0’), all EN_OUT_s turn
off at the same time.
RESET Deassertion
After any MON_ inputs assigned to Slot 12 exceed their
undervoltage thresholds, the reset timeouts begin. When
the reset timeout completes, RESET deasserts. The reset
timeout period is set in r19h[6:4] (see Table 27).
Power-Down
Power-down starts when EN is pulled low or the
Software Enable bit is set to ‘1.’ RESET asserts as soon
as power-down begins regardless of the reset output
Table 10. MON_ and EN_OUT_ Slot Assignment Registers
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
MON1 Slot Assignment Register
MON2 Slot Assignment Register
MON3 Slot Assignment Register
MON4 Slot Assignment Register
MON5 Slot Assignment Register
MON6 Slot Assignment Register
MON7 Slot Assignment Register
MON8 Slot Assignment Register
MON9 Slot Assignment Register*
MON10 Slot Assignment Register*
MON11 Slot Assignment Register*
MON12 Slot Assignment Register*
EN_OUT1 Slot Assignment Register
EN_OUT2 Slot Assignment Register
EN_OUT3 Slot Assignment Register
EN_OUT4 Slot Assignment Register
EN_OUT5 Slot Assignment Register
EN_OUT6 Slot Assignment Register
EN_OUT7 Slot Assignment Register
EN_OUT8 Slot Assignment Register
EN_OUT9 Slot Assignment Register*
56h
57h
58h
59h
5Ah
5Bh
5Eh
5Fh
60h
61h
62h
EN_OUT10 Slot Assignment Register*
EN_OUT11 Slot Assignment Register*
EN_OUT12 Slot Assignment Register *
63h
*MAX16046A only
______________________________________________________________________________________ 31
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 11. MON_ Slot Assignment
CONFIGURATION BITS
DESCRIPTION
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MON_ is not assigned to a slot
MON_ is assigned to Slot 1
MON_ is assigned to Slot 2
MON_ is assigned to Slot 3
MON_ is assigned to Slot 4
MON_ is assigned to Slot 5
MON_ is assigned to Slot 6
MON_ is assigned to Slot 7
MON_ is assigned to Slot 8
MON_ is assigned to Slot 9
MON_ is assigned to Slot 10
MON_ is assigned to Slot 11
MON_ is assigned to Slot 12
Not used
Not used
Not used
/MX16048A
Table 12. EN_OUT_ Slot Assignment
CONFIGURATION BITS
DESCRIPTION
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
EN_OUT_ is not assigned to a slot
EN_OUT_ is assigned to Slot 0
EN_OUT_ is assigned to Slot 1
EN_OUT_ is assigned to Slot 2
EN_OUT_ is assigned to Slot 3
EN_OUT_ is assigned to Slot 4
EN_OUT_ is assigned to Slot 5
EN_OUT_ is assigned to Slot 6
EN_OUT_ is assigned to Slot 7
EN_OUT_ is assigned to Slot 8
EN_OUT_ is assigned to Slot 9
EN_OUT_ is assigned to Slot 10
EN_OUT_ is assigned to Slot 11
Not used
Not used
Not used
32 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Table 13. Sequence Delays and Fault Recovery
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
Power-Up Fault Timeout
00 = 37.5ms
[1:0]
01 = 75ms
10 = 150ms
11 = 300ms
Power-Down Fault Timeout
00 = 37.5ms
[3:2]
01 = 75ms
10 = 150ms
11 = 300ms
INS1 Pulldown Resistor Enable
0 = Pulldown resistor for INS1 is disabled
1 = Pulldown resistor for INS1 is enabled
4Eh
[4]
[5]
[6]
[7]
INS2 Pulldown Resistor Enable
0 = Pulldown resistor for INS2 is disabled
1 = Pulldown resistor for INS2 is enabled
INS3 Pulldown Resistor Enable
0 = Pulldown resistor for INS3 is disabled
1 = Pulldown resistor for INS3 is enabled
INS4 Pulldown Resistor Enable
0 = Pulldown resistor for INS4 is disabled
1 = Pulldown resistor for INS4 is enabled
Autoretry Timeout
000 = 20μs
001 = 18.75ms
010 = 37.5ms
011 = 75ms
[2:0]
100 = 150ms
101 = 300ms
110 = 600ms
111 = 2.4s
Fault Recovery Mode
[3]
0 = Autoretry procedure is performed following a fault event
1 = Latch-off on fault
4Fh
Slew Rate
00 = 800V/s
01 = 400V/s
10 = 200V/s
11 = 100V/s
[5:4]
Fault Deglitch
00 = 2 conversions
01 = 4 conversions
10 = 8 conversions
11 = 16 conversions
[7:6]
______________________________________________________________________________________ 33
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 13. Sequence Delays and Fault Recovery (continued)
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
[2:0]
[5:3]
[7:6]
[0]
Slot 0 Sequence Delay
50h
51h
Slot 1 Sequence Delay
Slot 2 Sequence Delay (LSBs)
Slot 2 Sequence Delay (MSB)—see r50h[7:6]
Slot 3 Sequence Delay
[3:1]
[6:4]
[7]
Slot 4 Sequence Delay
Slot 5 Sequence Delay (LSB)—see r52h[1:0]
Slot 5 Sequence Delay
[1:0]
[4:2]
[7:5]
[2:0]
[5:3]
[7:6]
[0]
52h
53h
Slot 6 Sequence Delay
Slot 7 Sequence Delay
Slot 8 Sequence Delay
Slot 9 Sequence Delay
Slot 10 Sequence Delay (LSBs)
Slot 10 Sequence Delay (MSB)—see r53h[7:6]
Slot 11 Sequence Delay
[3:1]
/MX16048A
Reverse Sequence
0 = Power down all EN_OUT_s at the same time (simultaneously)
1 = Controlled power-down will be reverse of power-up sequence
54h
[4]
[7:5]
Not used
Table 14. Slot Sequence Delay Selection
CONFIGURATION BITS
SLOT SEQUENCE DELAY
000
001
010
011
100
101
110
111
20μs
18.75ms
37.5ms
75ms
150ms
300ms
600ms
2.4s
34 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Closed-Loop Tracking
The MAX16046A/MAX16048A track up to four voltages
during any time slot except Slot 0 and Slot 12.
Configure GPIO1–GPIO4 as sense line inputs (INS_) to
monitor tracking voltages. Configure GPIO6 as
FAULTPU to indicate tracking faults, if desired. See the
General-Purpose Inputs/Outputs section for information
on configuring GPIOs.
Power-down initiates when EN is forced low or when
the Software Enable bit in r4Dh[0] is set to ‘1.’ If the
Reverse Sequence bit is set (r54h[4]) INS_ voltages fol-
low a falling reference ramp to ground as long as
MON_ voltages remain high enough to supply the
required voltage/current. If a monitored voltage drops
faster than the control ramp voltage or the correspond-
ing MON_ voltage falls too quickly, power-down track-
ing operation is terminated and all EN_OUT_ voltages
are immediately forced to ground. If the Reverse
Sequence bit is set to ‘0,’ all EN_OUT_ voltages are
forced low simultaneously.
For closed-loop tracking, use MON1, EN_OUT1, and
INS1 together to form a complete channel. Use MON2,
EN_OUT2, and INS2 to form a second complete chan-
nel. Use MON3, EN_OUT3, and INS3 together to form a
third channel; and use MON4, EN_OUT4, and INS4 to
form a fourth channel.
The MAX16046A/MAX16048A include selectable internal
100Ω pulldown resistors to ensure that tracked voltages
are not held high by large external capacitors during a
fault event. The pulldowns help to ensure that monitored
INS_ voltages are fully discharged before the next power-
up cycle is initiated. These pulldowns are high imped-
ance during normal operation. Set r4Eh[7:4] to ‘1’ to
enable the pulldown resistors (Table 13). These pulldown
resistors may also be used with EN_OUT1–EN_OUT4
channels not configured for closed-loop tracking, which
is useful to discharge the output capacitors of a DC-DC
converter during shutdown. For this case, configure the
GPIO as an INS_ input and set the 100Ω pulldown bit,
but do not enable closed-loop tracking. Connect the
INS_ input to the output of the power supply.
When configured for closed-loop tracking, assign each
EN_OUT_ to the same slot as its associated single
monitoring input (MON_). For example, if EN_OUT2 is
assigned to Slot 3, the monitoring input is MON2 and
must be assigned to Slot 3. This is because the MON_
input, checked at the start of the slot, must be valid
before tracking can begin. Tracking begins immediate-
ly and must finish before the power-up fault timeout
expires, or a fault will trigger. EN_OUT_ configured for
closed-loop tracking cannot be assigned to Slot 0.
The tracking control circuitry includes a ramp generator
and a comparator control block for each tracked volt-
age (see the Functional Diagram and Figure 5). The
comparator control block compares each INS_ voltage
with a control voltage ramp. If INS_ voltages vary from
the control ramp by more than 150mV (typ), the com-
parator control block signals an alert that dynamically
stops the ramp until the slow INS_ voltage rises to with-
in the allowed voltage window. The total tracking time is
extended under these conditions, but must still com-
plete within the selected power-up/power-down fault
timeout. The power-up/power-down tracking fault time-
out period is adjustable through r4Eh[3:0].
V
IN
V
OUT
MON_
EN_OUT_
INS_
GATE
DRIVE
ADC MUX
LOGIC
A voltage difference between any two tracking INS_
voltages exceeding 330mV generates a tracking fault,
forcing all EN_OUT_ voltages low and generating a
fault log. If configured as FAULTPU, GPIO6 asserts
when a tracking fault occurs.
V
TH_PG
REFERENCE
RAMP
100Ω
The comparator control blocks also monitor INS_ voltages
with respect to input (MON_) voltages. Under normal con-
ditions each INS_ tracks the control ramp until the INS_
voltages reach the configured power-good (PG) thresh-
olds, set as a programmable percentage of the MON_
voltage. Use register r64h to set the PG thresholds (Table
15). Once PG is detected, the external n-channel FET sat-
urates with 5V (typ) applied between gate and source.
The slew rate for the control ramp is programmable from
100V/s to 800V/s in r4Fh[5:4] (see Table 13).
Figure 5. Closed-Loop Tracking
______________________________________________________________________________________ 35
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 15. Power-Good (PG) Thresholds
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
00 = PG is asserted when monitored V
is 95% of V
INS1
MON1
MON1
MON1
MON1
01 = PG is asserted when monitored V
10 = PG is asserted when monitored V
11 = PG is asserted when monitored V
is 92.5% of V
INS1
[1:0]
is 90% of V
INS1
is 87.5% of V
INS1
00 = PG is asserted when monitored V
01 = PG is asserted when monitored V
10 = PG is asserted when monitored V
11 = PG is asserted when monitored V
is 95% of V
is 92.5% of V
is 90% of V
is 87.5% of V
MON2
MON2
MON2
MON2
INS2
INS2
[3:2]
[5:4]
[7:6]
INS2
INS2
64h
00 = PG is asserted when monitored V
01 = PG is asserted when monitored V
10 = PG is asserted when monitored V
11 = PG is asserted when monitored V
is 95% of V
is 92.5% of V
is 90% of V
is 87.5% of V
MON3
MON3
MON3
MON3
INS3
INS3
INS3
INS3
00 = PG is asserted when monitored V
01 = PG is asserted when monitored V
10 = PG is asserted when monitored V
11 = PG is asserted when monitored V
is 95% of V
is 92.5% of V
is 90% of V
is 87.5% of V
MON4
MON4
MON4
MON4
INS4
INS4
INS4
INS4
/MX16048A
Set any DACOUT_ range configuration register to 00h
to switch off the DACOUT buffer. Set the DACOUT_
enable bit to ‘0’ to leave the DAC output as high imped-
ance. See Table 16 for the registers associated with the
DAC output ranges.
DAC Outputs
The MAX16046A/MAX16048A feature an 8-bit DAC with
12 outputs (MAX16046A) or 8 outputs (MAX16048A) for
voltage margining. Program the voltage on the DAC
outputs (DACOUT1–DACOUT12) to trim external
power-supply voltages, either by connecting through a
series resistor to the feedback node or to the trim input.
DAC outputs are high impedance during power-up to
prevent improper operation of the external power sup-
plies, and must be explicitly enabled by setting the
appropriate DACOUT_ enable bits.
The DAC enable bits are not copied from EEPROM dur-
ing the boot phase; therefore each DACOUT_ output
must be enabled in the r1Ch and r1Dh registers, locat-
ed in the extended page, following power-up. See
Table 17 for the DAC enable bits.
To control the voltage on a particular DAC output, write
the 8-bit binary value to the appropriate output regis-
ter; see Table 18 for the register locations. Although
these registers are located in the default page, they
are not stored in nonvolatile EEPROM and are set to ‘0’
after a POR.
Each DACOUT output has three voltage ranges: 0.4V to
0.8V, 0.6V to 1.2V, and 0.8V to 1.6V. Configure DAC
outputs using registers r12h to r14h (see Table 16).
Calculate DACOUT_ voltages, V
lowing equation:
, using the fol-
DACOUT_
V
= DAC
(DAC
(V) + ((DAC - 80h) x
n
)/255) (V)
DACOUT_
ACC
RNG
where DAC
is the DAC center code absolute accu-
RNG
ACC
racy and DAC
is the DAC output voltage range as
listed in the Electrical Characteristics table and 07h <
DAC < F8h.
n
36 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Table 16. DACOUT Ranges
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
DACOUT1 Range Selection:
00 = DACOUT1 is OFF
[1:0]
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
DACOUT2 Range Selection:
00 = DACOUT2 is OFF
[3:2]
[5:4]
[7:6]
[1:0]
[3:2]
[5:4]
[7:6]
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
12h
DACOUT3 Range Selection:
00 = DACOUT3 is OFF
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
DACOUT4 Range Selection:
00 = DACOUT4 is OFF
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
DACOUT5 Range Selection:
00 = DACOUT5 is OFF
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
DACOUT6 Range Selection:
00 = DACOUT6 is OFF
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
13h
DACOUT7 Range Selection:
00 = DACOUT7 is OFF
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
DACOUT8 Range Selection:
00 = DACOUT8 is OFF
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
______________________________________________________________________________________ 37
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 16. DACOUT Ranges (continued)
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
DACOUT9 Range Selection*:
00 = DACOUT9 is OFF
[1:0]
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
DACOUT10 Range Selection*:
00 = DACOUT10 is OFF
[3:2]
[5:4]
[7:6]
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
14h
DACOUT11 Range Selection*:
00 = DACOUT11 is OFF
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
DACOUT12 Range Selection*:
00 = DACOUT12 is OFF
01 = 0.4V (min) to 0.8V (max)
10 = 0.6V (min) to 1.2V (max)
11 = 0.8V (min) to 1.6V (max)
/MX16048A
*MAX16046A only
Table 18. DACOUT Voltages
Table 17. DACOUT Enables
REGISTER
BIT RANGE
ADDRESS
EXTENDED PAGE
DESCRIPTION
DACOUT ENABLES
ADDRESS
00h
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
DACOUT1 Data
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
1 = DACOUT1 is enabled
1 = DACOUT2 is enabled
1 = DACOUT3 is enabled
1 = DACOUT4 is enabled
1 = DACOUT5 is enabled
1 = DACOUT6 is enabled
1 = DACOUT7 is enabled
1 = DACOUT8 is enabled
1 = DACOUT9 is enabled*
1 = DACOUT10 is enabled*
1 = DACOUT11 is enabled*
1 = DACOUT12 is enabled*
Reserved
01h
DACOUT2 Data
DACOUT3 Data
DACOUT4 Data
DACOUT5 Data
DACOUT6 Data
DACOUT7 Data
DACOUT8 Data
DACOUT9 Data*
DACOUT10 Data*
DACOUT11 Data*
DACOUT12 Data*
02h
03h
1Ch
04h
05h
06h
07h
08h
09h
0Ah
1Dh
0Bh
*MAX16046A only
*MAX16046A only
38 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
and 5). Set DACOUT_ voltages to the appropriate values
and then enable the appropriate DAC outputs.
Voltage Margining
Margining is commonly performed while a system is
under development, but margining can also be per-
formed during the manufacturing process. The supply
voltages of external DC-DC regulators can be adjusted
by trimming the regulator’s reference input (for voltage-
regulator modules), altering the voltage regulator’s
feedback node, or adjusting a “brick” power supply’s
trim input. See the Applications Information section for
sample circuits.
To control margining with external circuitry, configure
GPIO2 and GPIO3 as MARGINUP and MARGINDN
inputs, respectively. Pull MARGINUP low and pull
MARGINDN high to select DACOUT_ voltage values
set in registers r66h to r71h. Pull MARGINDN low and
pull MARGINUP high to select DACOUT_ values set in
registers r72h to r7Dh (see Tables 19 and 20). Pull both
MARGINUP and MARGINDN high or low to select
DACOUT_ values set in registers r00h to r0Bh.
Margining can be controlled over the serial interface or by
using GPIO2 and GPIO3. Before adjusting the voltages
using the DAC outputs, enable voltage margining func-
tionality by setting the Margin bit at r4Dh[1] to ‘1’ (see
Table 1) or configure GPIO6 as MARGIN (see Tables 4
See Table 16 for more information on setting the volt-
age ranges for the DACOUT_ outputs. Table 20 shows
which register values are used for the DAC outputs for
each state of MARGINUP and MARGINDN.
Table 19. DACOUT1–DACOUT12 Margin Data
REGISTER/
BIT
REGISTER/
BIT
EEPROM
DESCRIPTION
EEPROM
DESCRIPTION
RANGE
RANGE
ADDRESS
ADDRESS
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
DACOUT1 Margin-Down Data
DACOUT2 Margin-Down Data
DACOUT3 Margin-Down Data
DACOUT4 Margin-Down Data
DACOUT5 Margin-Down Data
DACOUT6 Margin-Down Data
DACOUT7 Margin-Down Data
DACOUT8 Margin-Down Data
DACOUT9 Margin-Down Data*
DACOUT10 Margin-Down Data*
DACOUT11 Margin-Down Data*
DACOUT12 Margin-Down Data*
66h
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
DACOUT1 Margin-Up Data
DACOUT2 Margin-Up Data
DACOUT3 Margin-Up Data
DACOUT4 Margin-Up Data
DACOUT5 Margin-Up Data
DACOUT6 Margin-Up Data
DACOUT7 Margin-Up Data
DACOUT8 Margin-Up Data
DACOUT9 Margin-Up Data*
DACOUT10 Margin-Up Data*
DACOUT11 Margin-Up Data*
DACOUT12 Margin-Up Data*
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
*MAX16046A only
Table 20. DACOUT Margining Output Dependencies
MARGINUP
(GPIO2)
MARGINDN
(GPIO3)
DACOUT REGISTER USED
DACOUT SWITCH STATE
1
1
0
0
1
0
1
0
DACOUT registers r00h to r0Bh
MARGIN DN registers r72h to r7Dh
MARGIN UP registers r66h to r71h
DACOUT registers r00h to r0Bh
Depends on r1Ch, r1Dh
Closed
Closed
Depends on r1Ch, r1Dh
______________________________________________________________________________________ 39
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
at a monitored input exceeds the overvoltage threshold
for that input. An undervoltage fault occurs when the
voltage at a monitored input falls below the undervolt-
age threshold. Fault thresholds are set in registers r23h
to r46h as shown in Table 21. Disabled inputs are not
monitored for fault conditions and are skipped over by
the input multiplexer. Only the upper 8 bits of a conver-
sion result are compared with the programmed fault
thresholds. Inputs not assigned to a sequencing slot
are not monitored for fault conditions but are still
recorded in the ADC results registers.
Faults
The MAX16046A/MAX16048A monitor the input (MON_)
channels and compare the results with an overvoltage
threshold, an undervoltage threshold, and a selectable
overvoltage or undervoltage early warning threshold.
Based on these conditions, the MAX16046A/
MAX16048A can assert various fault outputs and save
specific information about the channel conditions and
voltages into the nonvolatile EEPROM. Once a critical
fault event occurs, the failing channel condition, ADC
conversions at the time of the fault, or both may be
saved by configuring the event logger. The event log-
ger records a single failure in the internal EEPROM and
sets a lock bit which protects the stored fault data from
accidental erasure on a subsequent power-up.
The general-purpose inputs/outputs (GPIO1–GPIO6)
can be configured as Any_Fault outputs or dedicated
FAULT1 and FAULT2 outputs to indicate fault condi-
tions. These fault outputs are not masked by the critical
fault enable bits shown in Table 23. See the General-
Purpose Inputs/Outputs section for more information on
configuring GPIOs as fault outputs.
The MAX16046A/MAX16048A are capable of measur-
ing overvoltage and undervoltage fault events. Fault
conditions are detected at the end of each ADC con-
version. An overvoltage event occurs when the voltage
Table 21. Fault Thresholds
/MX16048A
REGISTER/
DESCRIPTION
REGISTER/
DESCRIPTION
EEPROM ADDRESS
EEPROM ADDRESS
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
MON7 Early Warning Threshold
MON7 Overvoltage Threshold
MON7 Undervoltage Threshold
MON8 Early Warning Threshold
MON8 Overvoltage Threshold
MON8 Undervoltage Threshold
MON9 Early Warning Threshold*
MON9 Overvoltage Threshold*
MON9 Undervoltage Threshold*
MON10 Early Warning Threshold*
MON10 Overvoltage Threshold*
MON10 Undervoltage Threshold*
MON11 Early Warning Threshold*
MON11 Overvoltage Threshold*
MON11 Undervoltage Threshold*
MON12 Early Warning Threshold*
MON12 Overvoltage Threshold*
MON12 Undervoltage Threshold*
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
MON1 Early Warning Threshold
MON1 Overvoltage Threshold
MON1 Undervoltage Threshold
MON2 Early Warning Threshold
MON2 Overvoltage Threshold
MON2 Undervoltage Threshold
MON3 Early Warning Threshold
MON3 Overvoltage Threshold
MON3 Undervoltage Threshold
MON4 Early Warning Threshold
MON4 Overvoltage Threshold
MON4 Undervoltage Threshold
MON5 Early Warning Threshold
MON5 Overvoltage Threshold
MON5 Undervoltage Threshold
MON6 Early Warning Threshold
MON6 Overvoltage Threshold
MON6 Undervoltage Threshold
*MAX16046A only
40 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Deglitch
Fault conditions are detected at the end of each con-
version. If the voltage on an input falls outside a moni-
tored threshold for one acquisition, the input multiplexer
remains on that channel and performs several succes-
sive conversions. To trigger a fault, the input must stay
outside the threshold for a certain number of acquisi-
tions as determined by the deglitch setting in r4Fh[7:6]
(see Table 25).
Critical Faults
If a specific input threshold is critical to the operation of
the system, an automatic fault log can be configured to
shut down all the EN_OUT_s and trigger a transfer of
fault information to EEPROM. For a fault condition to
trigger a critical fault, set the appropriate enable bit in
registers r48h to r4Ch (see Table 23).
Logged fault information is stored in EEPROM registers
r00h to r0Eh (see Table 24). Once a fault log event
occurs, the EEPROM is locked and must be unlocked
to enable a new fault log to be stored. Write a ‘1’ to
r5Dh[1] to unlock the EEPROM. Fault information can
be configured to store ADC conversion results and/or
fault flags in registers r01h and r02h. Select the critical
fault configuration in r47h[1:0]. Set r47h[1:0] to ‘11’ to
turn off the fault logger. All stored ADC results are 8
bits wide.
Fault Flags
Fault flags indicate the fault status of a particular input.
The fault flag of any monitored input in the device can
be read at any time from registers r18h and r19h in the
extended page, as shown in Table 22. Clear a fault flag
by writing a ‘1’ to the appropriate bit in the flag register.
Unlike the fault signals sent to the fault outputs, these
bits are masked by the critical fault enable bits (see
Table 23). The fault flag will only be set if the matching
enable bit in the critical fault enable register is also set.
Table 22. Fault Flags
EXTENDED PAGE
BIT RANGE
DESCRIPTION
ADDRESS
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
1 = MON1 conversion exceeds overvoltage or undervoltage thresholds
1 = MON2 conversion exceeds overvoltage or undervoltage thresholds
1 = MON3 conversion exceeds overvoltage or undervoltage thresholds
1 = MON4 conversion exceeds overvoltage or undervoltage thresholds
1 = MON5 conversion exceeds overvoltage or undervoltage thresholds
1 = MON6 conversion exceeds overvoltage or undervoltage thresholds
1 = MON7 conversion exceeds overvoltage or undervoltage thresholds
1 = MON8 conversion exceeds overvoltage or undervoltage thresholds
1 = MON9 conversion exceeds overvoltage or undervoltage thresholds*
1 = MON10 conversion exceeds overvoltage or undervoltage thresholds*
1 = MON11 conversion exceeds overvoltage or undervoltage thresholds*
1 = MON12 conversion exceeds overvoltage or undervoltage thresholds*
Not used
18h
19h
*MAX16046A only
______________________________________________________________________________________ 41
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 23. Critical Fault Configuration and Enable Bits
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
Critical Fault Log Control
00 = Failed lines and ADC conversion values save to EEPROM upon critical fault
01 = Failed line flags only saved to EEPROM upon critical fault
10 = ADC conversion values only saved to EEPROM upon critical fault
11 = No information saved upon critical fault
[1:0]
47h
[7:2]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Not used
1 = Fault log triggered when MON1 is below its undervoltage threshold
1 = Fault log triggered when MON2 is below its undervoltage threshold
1 = Fault log triggered when MON3 is below its undervoltage threshold
1 = Fault log triggered when MON4 is below its undervoltage threshold
1 = Fault log triggered when MON5 is below its undervoltage threshold
1 = Fault log triggered when MON6 is below its undervoltage threshold
1 = Fault log triggered when MON6 is below its undervoltage threshold
1 = Fault log triggered when MON8 is below its undervoltage threshold
1 = Fault log triggered when MON9 is below its undervoltage threshold*
1 = Fault log triggered when MON10 is below its undervoltage threshold*
1 = Fault log triggered when MON11 is below its undervoltage threshold*
1 = Fault log triggered when MON12 is below its undervoltage threshold*
1 = Fault log triggered when MON1 is above its overvoltage threshold
1 = Fault log triggered when MON2 is above its overvoltage threshold
1 = Fault log triggered when MON3 is above its overvoltage threshold
1 = Fault log triggered when MON3 is above its overvoltage threshold
1 = Fault log triggered when MON5 is above its overvoltage threshold
1 = Fault log triggered when MON6 is above its overvoltage threshold
1 = Fault log triggered when MON7 is above its overvoltage threshold
1 = Fault log triggered when MON8 is above its overvoltage threshold
1 = Fault log triggered when MON9 is above its overvoltage threshold*
1 = Fault log triggered when MON10 is above its overvoltage threshold*
1 = Fault log triggered when MON11 is above its overvoltage threshold*
1 = Fault log triggered when MON12 is above its overvoltage threshold*
1 = Fault log triggered when MON1 is above/below its early earning threshold
1 = Fault log triggered when MON2 is above/below its early warning threshold
1 = Fault log triggered when MON3 is above/below its early warning threshold
1 = Fault log triggered when MON4 is above/below its early warning threshold
1 = Fault log triggered when MON5 is above/below its early warning threshold
1 = Fault log triggered when MON6 is above/below its early warning threshold
1 = Fault log triggered when MON7 is above/below its early warning threshold
1 = Fault log triggered when MON8 is above/below its early warning threshold
48h
/MX16048A
49h
4Ah
4Bh
42 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Table 23. Critical Fault Configuration and Enable Bits (continued)
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
[0]
[1]
1 = Fault log triggered when MON9 is above/below its early warning threshold*
1 = Fault log triggered when MON10 is above/below its early warning threshold*
1 = Fault log triggered when MON11 is above/below its early warning threshold*
1 = Fault log triggered when MON12 is above/below its early warning threshold*
Not used
4Ch
[2]
[3]
[7:4]
*MAX16046A only
Table 24. Fault Log EEPROM
EEPROM
BIT RANGE
ADDRESS
DESCRIPTION
Power-Up/Power-Down Fault Register
Slot where power-up/power-down fault is detected
Tracking Fault Bits
If ‘0,’ tracking fault occurred on MON1/EN_OUT1/INS1
If ‘0,’ tracking fault occurred on MON2/EN_OUT2/INS2
If ‘0,’ tracking fault occurred on MON3/EN_OUT3/INS3
If ‘0,’ tracking fault occurred on MON4/EN_OUT4/INS4
If ‘1,’ fault occurred on MON1
If ‘1,’ fault occurred on MON2
If ‘1,’ fault occurred on MON3
If ‘1,’ fault occurred on MON4
If ‘1,’ fault occurred on MON5
If ‘1,’ fault occurred on MON6
If ‘1,’ fault occurred on MON7
If ‘1,’ fault occurred on MON8
If ‘1,’ fault occurred on MON9*
If ‘1,’ fault occurred on MON10*
If ‘1,’ fault occurred on MON11*
If ‘1,’ fault occurred on MON12*
Not used
[3:0]
[4]
00h
01h
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
02h
03h
MON_ ADC Fault Information (only the 8 MSBs of converted channels are saved following
a fault event)
[7:0]
MON1 conversion result at the time the fault log was triggered
MON2 conversion result at the time the fault log was triggered
MON3 conversion result at the time the fault log was triggered
MON4 conversion result at the time the fault log was triggered
MON5 conversion result at the time the fault log was triggered
MON6 conversion result at the time the fault log was triggered
MON7 conversion result at the time the fault log was triggered
MON8 conversion result at the time the fault log was triggered
MON9 conversion result at the time the fault log was triggered*
MON10 conversion result at the time the fault log was triggered*
MON11 conversion result at the time the fault log was triggered*
MON12 conversion result at the time the fault log was triggered*
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
*MAX16046A only
______________________________________________________________________________________ 43
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Power-Up/Power-Down Faults
All EN_OUTs are deasserted if an overvoltage or under-
voltage fault is detected during power-up/power-down
(regardless of the critical fault enable bits). Under these
conditions, information of the failing slot is stored in
EEPROM r00h[3:0] unless r47h[1:0] is set to ‘11’ (see
Table 23).
Set r4Fh[3] to ‘1’ to select the latch-on-fault mode. In
this configuration EN_OUT_s are deasserted after a
critical fault event. The device does not re-initiate the
power-up sequence until EN is toggled or the Software
Enable bit is reset to ‘0.’ See the Enable section for
more information on setting the Software Enable bit.
If fault information is stored in EEPROM (see the Critical
Faults section) and autoretry mode is selected, set an
autoretry delay greater than the time required for the
storing operation. If fault information is stored in
EEPROM and latch-on-fault mode is chosen, toggle EN
or reset the Software Enable bit only after the comple-
tion of the storing operation. If saving information about
the failed lines only, ensure a delay of at least 90ms
before the restart procedure. Otherwise, ensure a mini-
mum 306ms timeout. This ensures that ADC conver-
sions are completed and values are stored correctly in
EEPROM. See Table 26 for more information about
required fault log operation periods.
If there is a tracking fault on a channel configured for
closed-loop tracking, a fault log operation occurs and
the bits representing the failed tracking channels are
set to ‘0’ unless r47h[1:0] is set to ‘11’ (see Table 24).
Autoretry/Latch Mode
For critical faults, the MAX16046A/MAX16048A can be
configured for one of two fault management methods:
autoretry or latch-on-fault. Set r4Fh[3] to ‘0’ to select
autoretry mode. In this configuration, the device will
shut down after a critical fault event then restart follow-
ing a configurable delay. Use r4Fh[2:0] to select an
autoretry delay from 20μs to 2.4s. See Table 25 for
more information on setting the autoretry delay.
Table 25. Fault Recovery Configuration
/MX16048A
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
Autoretry Delay
000 = 20μs
001 = 18.75ms
010 = 37.5ms
011 = 75ms
[2:0]
100 = 150ms
101 = 300ms
110 = 600ms
111 = 2.4s
Fault Recovery Mode
[3]
0 = Autoretry procedure is performed following a fault event
1 = Latchoff on fault
4Fh
Slew Rate
00 = 800V/s
01 = 400V/s
10 = 200V/s
11 = 100V/s
[5:4]
Fault Deglitch
00 = 2 conversions
01 = 4 conversions
10 = 8 conversions
11 = 16 conversions
[7:6]
44 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Table 26. EEPROM Fault Log Operation Period
FAULT CONTROL
MINIMUM REQUIRED SHUTDOWN PERIOD
REGISTER
r47h[1:0]
DESCRIPTION
(ms)
00
01
10
11
Failed lines and ADC values saved
Failed lines saved
306
90
ADC values saved
252
N/A
No information saved
RESET is a configurable output that monitors selected
MON_ voltages during normal operation. RESET also
depends on any monitoring input that has one or more
critical fault enable bits set. Use r19h[1:0] to configure
RESET to assert on an overvoltage fault, undervoltage
fault, or both. Use r19h[3:2] to configure RESET as an
active-high/active-low push-pull/open-drain output. If
desired, configure GPIO4 as a manual reset input, MR,
and pull MR low to assert RESET. RESET includes a
programmable timeout. See Table 27 for RESET depen-
dencies and configuration registers.
RESET
The reset output, RESET, is asserted during power-
up/power-down and deasserts following the reset time-
out period once the power-up sequence is complete.
The power-up sequence is complete when any MON_
inputs assigned to Slot 12 exceed their undervoltage
thresholds. If no MON_ inputs are assigned to Slot 12,
the power-up sequence is complete after the slot
sequence delay is expired.
Table 27. RESET Configuration and Dependencies
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
RESET OUTPUT CONFIGURATION
00 = RESET is asserted if at least one of the selected inputs exceeds its undervoltage
threshold
01 = RESET is asserted if at least one of the selected inputs exceeds its early warning
[1:0]
threshold
10 = RESET is asserted if at least one of the selected inputs exceeds its overvoltage
threshold
11 = RESET is asserted if any of the selected inputs exceeds undervoltage or overvoltage
thresholds
0 = RESET is an active-low output
1 = RESET is an active-high output
[2]
[3]
0 = RESET is an open-drain output
1 = RESET is a push-pull output
19h
RESET TIMEOUT
000 = 25μs
001 = 3ms
010 = 37.5ms
011 = 150ms
100 = 300ms
101 = 600ms
110 = 1200ms
111 = 2400ms
[6:4]
[7]
Reserved
______________________________________________________________________________________ 45
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 27. RESET Configuration and Dependencies (continued)
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
RESET DEPENDENCIES
1 = RESET is dependent on MON1
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
1 = RESET is dependent on MON2
1 = RESET is dependent on MON3
1 = RESET is dependent on MON4
1 = RESET is dependent on MON5
1 = RESET is dependent on MON6
1 = RESET is dependent on MON7
1 = RESET is dependent on MON8
1 = RESET is dependent on MON9*
1 = RESET is dependent on MON10*
1 = RESET is dependent on MON11*
1 = RESET is dependent on MON12*
Reserved
1Ah
1Bh
*MAX16046A only
/MX16048A
routine watchdog updates. Set r55h[6] to ‘1’ to enable
the watchdog startup delay. Set r55h[6] to ‘0’ to disable
the watchdog startup delay.
Watchdog Timer
The watchdog timer can operate together with or inde-
pendently of the MAX16046A/MAX16048A. When oper-
ating in dependent mode, the watchdog is not
activated until the sequencing is complete and RESET
is de-asserted. When operating in independent mode,
the watchdog timer is independent of the sequencing
The normal watchdog timeout period, t
, begins after
WDI
the first transition on WDI before the conclusion of the
long startup watchdog period, t (Figures 6
WDI_STARTUP
and 7). During the normal operating mode, WDO
asserts if the μP does not toggle WDI with a valid transi-
tion (high-to-low or low-to-high) within the standard
operation and activates immediately after V
exceeds
CC
the UVLO threshold and the boot phase is complete.
Set r4Dh[3] to ‘0’ to configure the watchdog in depen-
dent mode. Set r4Dh[3] to ‘1’ to configure the watchdog
in independent mode. See Table 28 for more informa-
tion on configuring the watchdog timer in dependent or
independent mode.
timeout period, t
. WDO remains asserted until WDI
WDI
is toggled or RESET is asserted (Figure 7).
While EN is low, or r55h[7] is a ‘0,’ the watchdog timer is
in reset. The watchdog timer does not begin counting until
the power-on mode is reached and RESET is deasserted.
The watchdog timer is reset and WDO deasserts any time
RESET is asserted (Figure 8). The watchdog timer will be
held in reset while RESET is asserted.
Dependent Watchdog Timer Operation
The watchdog timer can be used to monitor μP activity
in two modes. Flexible timeout architecture provides an
adjustable watchdog startup delay of up to 192s, allow-
ing complicated systems to complete lengthy boot-up
routines. An adjustable watchdog timeout allows the
supervisor to provide quick alerts when processor
The watchdog can be configured to control the RESET
output as well as the WDO output. RESET is pulsed low
for the reset timeout, t , when the watchdog timer
RP
expires and the Watchdog Reset Output Enable bit
(r55h[7]) is set to ‘1.’ Therefore, WDO pulses low for a
short time (approximately 1μs) when the watchdog timer
expires. RESET is not affected by the watchdog timer
when the Watchdog Reset Output Enable bit (r55h[7]) is
set to ‘0.’
activity fails. After each reset event (V
drops below
CC
UVLO then returns above UVLO, software reboot, man-
ual reset (MR), EN input going low then high, or watch-
dog reset) and once sequencing is complete, the
watchdog startup delay provides an extended time for
the system to power up and fully initialize all μP and
system components before assuming responsibility for
See Table 29 for more information on configuring
watchdog functionality.
46 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
V
TH
LAST MON_
< t
WDI
t
WDI
WDI_STARTUP
< t
WDI
t
RP
RESET
Figure 6. Normal Watchdog Startup Sequence
V
CC
< t
WDI
> t
< t
WDI
WDI
WDI
< t
WDI
< t
WDI
< t
WDI
< t
WDI
0V
CC
t
WDI
V
WDO
0V
Figure 7. Watchdog Timer Operation
V
CC
< t
WDI
< t
WDI
t
t
< t
WDI_STARTUP
WDI
WDI
RP
0V
CC
V
RESET
0V
V
CC
WDO
0V
1μs
Figure 8. Watchdog Startup Sequence with Watchdog Reset Output Enable Bit (r55h[7]) Set to ‘1’
______________________________________________________________________________________ 47
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 28. Watchdog Mode Selection
REGISTER/
EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
SoftwareEnable Bit
0
1
2
0 = Enabled. EN must also be high to begin sequencing.
1 = Disabled (factory default)
Margin Bit
1 = Margin functionality is enabled
0 = Margin disabled
4Dh
Early Warning Selection Bit
0 = Early warning thresholds are undervoltage thresholds
1 = Early warning thresholds are overvoltage thresholds
Watchdog Mode Selection Bit
3
0 = Watchdog timer is in dependent mode
1 = Watchdog timer is in independent mode
[7:4]
Not used
Table 29. Watchdog Enables and Configuration
/MX16048A
REGISTER/ EEPROM
BIT RANGE
DESCRIPTION
ADDRESS
Watchdog Timeout
000 = 1.5ms
001 = 6ms
010 = 18.75ms
[2:0]
[4:3]
011 = 75ms
100 = 300ms
101 = 1200ms
110 = 2400ms
111 = 4800ms
Watchdog Startup Delay
00 = 38.4s
01 = 76.8s
55h
10 = 153.6s
11 = 192s
Watchdog Enable
1 = Watchdog enabled
0 = Watchdog disabled
[5]
[6]
[7]
Watchdog Startup Delay Enable
1 = Watchdog startup delay enabled
0 = Watchdog startup delay disabled
Watchdog Reset Output Enable
1 = Watchdog timeout asserts RESET output
0 = Watchdog timeout does not assert RESET output
48 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Independent Watchdog Timer Operation
When r4Dh[3] is ‘1’ the watchdog timer operates in the
independent mode. In the independent mode, the
watchdog timer operates as if it were a separate chip.
low for 3 system clock cycles or approximately 1μs. If
the Watchdog Reset Output Enable bit (r55h[7]) is set
to ‘0,’ when the WDT expires, WDO will be asserted but
RESET will not be affected.
The watchdog timer is activated immediately upon V
CC
Miscellaneous
Table 30 lists several miscellaneous programmable
items. Register r5Ch provides storage space for a user-
defined configuration or firmware version number. Bit
r5Dh[0] locks and unlocks the configuration registers.
Bit r5Dh[1] locks and unlocks EEPROM addresses 00h
to 11h. Write data to EEPROM r5Dh as normally done;
however, to toggle a bit in register r5Dh, write a ‘1’ to
that bit. The r65h[2:0] bits contain a read-only manufac-
turing revision code.
exceeding UVLO and once the boot-up sequence is
finished. If RESET is asserted by the sequencer state
machine, the watchdog timer and WDO will not be
affected.
There will be a long startup delay if r55h[6] is a ‘1.’ If
r55h[6] is a ‘0,’ there will not be a long startup delay.
In independent mode, if the Watchdog Reset Output
Enable bit r55h[7] is set to ‘1,’ when the watchdog timer
expires, WDO will be asserted then RESET will be
asserted. WDO will then be deasserted. WDO will be
Table 30. Miscellaneous Settings
REGISTER/
EEPROM
ADDRESS
BIT RANGE
[7:0]
DESCRIPTION
5Ch
5Dh
User identification. Eight bits of memory for user-defined identification.
Configuration Lock
0 = Configuration registers and EEPROM writable.
1 = Configuration registers and EEPROM [except r5Dh] locked.
[0]
EEPROM Fault Data Lock Flag (set automatically after fault log is triggered):
0 = EEPROM is not locked. A triggered fault log stores fault information to EEPROM.
1 = EEPROM addresses 00h to 11h are locked. Write a ‘1’ to this bit to toggle the flag.
[1]
[7:2]
[2:0]
[7:3]
Not used
Manufacturing revision code. This register is read only. Not stored in EEPROM.
Not used
65h
______________________________________________________________________________________ 49
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
2
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 9);
otherwise the MAX16046A/MAX16048A registers a
START or STOP condition (Figure 10) from the master.
SDA and SCL idle high when the bus is not busy.
I C/SMBus-Compatible
Serial Interface
2
The MAX16046A/MAX16048A feature an I C/SMBus-
compatible 2-wire serial interface consisting of a serial
data line (SDA) and a serial clock line (SCL). SDA and
SCL facilitate bidirectional communication between the
MAX16046A/MAX16048A and the master device at
clock rates up to 400kHz. Figure 1 shows the 2-wire
interface timing diagram. The MAX16046A/MAX16048A
are transmit/receive slave-only devices, relying upon a
master device to generate a clock signal. The master
device (typically a microcontroller) initiates a data
transfer on the bus and generates SCL to permit that
transfer.
START and STOP Conditions
Both SCL and SDA idle high when the bus is not busy.
A master device signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high. The master device issues
a STOP condition by transitioning SDA from low to high
while SCL is high. A STOP condition frees the bus for
another transmission. The bus remains active if a
REPEATED START condition is generated, such as in
the block read protocol (see Figure 1).
A master device communicates to the MAX16046A/
MAX16048A by transmitting the proper address followed
by command and/or data words. The slave address
input, A0, is capable of detecting four different states,
allowing multiple identical devices to share the same seri-
al bus. The slave address is described further in the
Slave Address section. Each transmit sequence is framed
by a START (S) or REPEATED START (SR) condition and
a STOP (P) condition. Each word transmitted over the bus
is 8 bits long and is always followed by an acknowledge
pulse. SCL is a logic input, while SDA is an open-drain
input/output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7kΩ for
most applications.
Early STOP Conditions
The MAX16046A/MAX16048A recognize a STOP condi-
tion at any point during transmission except if a STOP
condition occurs in the same high pulse as a START
2
condition. This condition is not a legal I C format; at least
one clock pulse must separate any START and STOP
condition.
/MX16048A
REPEATED START Conditions
A REPEATED START may be sent instead of a STOP
condition to maintain control of the bus during a read
operation. The START and REPEATED START condi-
tions are functionally identical.
SDA
SCL
SDA
S
P
SCL
START
CONDITION
STOP
CONDITION
CHANGE OF
DATA ALLOWED
DATA LINE STABLE,
DATA VALID
Figure 9. Bit Transfer
Figure 10. START and STOP Conditions
50 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Acknowledge
The acknowledge bit (ACK) is the 9th bit attached to
any 8-bit data word. The receiving device always gen-
erates an ACK. The MAX16046A/MAX16048A generate
an ACK when receiving an address or data by pulling
SDA low during the 9th clock period (Figure 11). When
transmitting data, such as when the master device
reads data back from the MAX16046A/MAX16048A, the
device waits for the master device to generate an ACK.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
the receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master should reattempt communication at a
later time. The MAX16046A/MAX16048A generate a
NACK after the command byte received during a soft-
ware reboot, while writing to the EEPROM, or when
receiving an illegal memory address.
Slave Address
Use the slave address input, A0, to allow multiple identi-
cal devices to share the same serial bus. Connect A0 to
GND, DBP (or an external supply voltage greater than
2V), SCL, or SDA to set the device address on the bus.
See Table 31 for a listing of all possible 7-bit addresses.
2
Table 31. Setting the I C/SMBus Slave
Address
A0
0
SLAVE ADDRESS
1010 00XR
1
1010 01XR
SCL
SDA
1010 10XR
1010 11XR
X = Don’t care, R = Read/write select bit
CLOCK PULSE FOR ACKNOWLEDGE
8
2
1
9
SCL
SDA BY
TRANSMITTER
S
NACK
ACK
SDA BY
RECEIVER
Figure 11. Acknowledge
______________________________________________________________________________________ 51
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Send Byte
The send byte protocol allows the master device to
send one byte of data to the slave device (see Figure
12). The send byte presets a register pointer address
for a subsequent read or write. The slave sends a
NACK instead of an ACK if the master tries to send a
memory address or command code that is not allowed.
If the master sends 94h or 95h, the data is ACK,
because this could be the start of the write block or
read block. If the master sends a STOP condition
before the slave asserts an ACK, the internal address
pointer does not change. If the master sends 96h, this
signifies a software reboot. The send byte procedure is
the following:
which page is currently selected. The write byte proce-
dure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends an 8-bit data byte.
7) The addressed slave asserts an ACK on SDA.
8) The master sends a STOP condition.
To write a single byte, only the 8-bit memory address
and a single 8-bit data byte are sent. The data byte is
written to the addressed location if the memory address
is valid. The slave will assert a NACK at step 5 if the
memory address is not valid.
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address or com-
mand code.
Read Byte
The read byte protocol (see Figure 12) allows the mas-
ter device to read a single byte located in the default
page, extended page, or EEPROM page depending on
which page is currently selected. The read byte proce-
dure is the following:
5) The addressed slave asserts an ACK (or NACK) on
SDA.
/MX16048A
6) The master sends a STOP condition.
Receive Byte
The receive byte protocol allows the master device to
read the register content of the MAX16046A/
MAX16048A (see Figure 12). The EEPROM or register
address must be preset with a send byte or write word
protocol first. Once the read is complete, the internal
pointer increases by one. Repeating the receive byte
protocol reads the contents of the next address. The
receive byte procedure follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends a REPEATED START condition.
1) The master sends a START condition.
7) The master sends the 7-bit slave address and a
read bit (high).
2) The master sends the 7-bit slave address and a
read bit (high).
8) The addressed slave asserts an ACK on SDA.
9) The slave sends an 8-bit data byte.
10) The master asserts a NACK on SDA.
11) The master sends a STOP condition.
3) The addressed slave asserts an ACK on SDA.
4) The slave sends 8 data bits.
5) The master asserts a NACK on SDA.
6) The master generates a STOP condition.
If the memory address is not valid, it is NACKed by the
slave at step 5 and the address pointer is not modified.
Write Byte
The write byte protocol (see Figure 12) allows the mas-
ter device to write a single byte in the default page,
extended page, or EEPROM page, depending on
52 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Command Codes
The MAX16046A/MAX16048A use eight command
codes for block read, block write, and other com-
mands. See Table 32 for a list of command codes.
remaining bytes of data. The last data byte sent is
stored at register address FFh. The slave generates a
NACK at step 5 if the command code is invalid or if the
device is busy, and the address pointer is not altered.
The block write procedure is the following:
To initiate a software reboot, send 96h using the send
byte format. A software-initiated reboot is functionally the
same as a hardware-initiated power-on reset. During
boot-up, EEPROM configuration data in the range of 0Fh
to 7Dh is copied to the same register addresses in the
default page.
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends the 8-bit command code for
block write (94h).
Send command code 97h to trigger a fault store to
EEPROM. Configure the Critical Fault Log Control register
(r47h) to store ADC conversion results and/or fault flags
in registers once the command code has been sent.
5) The addressed slave asserts an ACK on SDA.
6) The master sends the 8-bit byte count (1 byte to 16
bytes), n.
Using command code 98h allows access to the extend-
ed page, which contains registers for ADC conversion
results, DACOUT enables, and GPIO input/output data.
Use command code 99h to return to the default page.
7) The addressed slave asserts an ACK on SDA.
8) The master sends 8 bits of data.
9) The addressed slave asserts an ACK on SDA.
10) Repeat steps 8 and 9 n - 1 times.
Send command code 9Ah to access the EEPROM
page. Once command code 9Ah has been sent, all
addresses are recognized as EEPROM addresses only.
Send command code 9Bh to return to the default page.
11) The master sends a STOP condition.
Block Read
The block read protocol (see Figure 12) allows the
master device to read a block of up to 16 bytes from
memory. Read fewer than 16 bytes of data by issuing
an early STOP condition from the master, or by gener-
ating a NACK with the master. The destination address
should be preloaded by a previous send byte com-
mand; otherwise the block read command begins to
read at the current address pointer. If the number of
bytes to be read causes the address pointer to exceed
FFh for the configuration register or EEPROM, the
address pointer stays at FFh and the last data byte
read is from register rFFh. The block read procedure is
the following:
Table 32. Command Codes
COMMAND CODE
ACTION
94h
95h
96h
97h
98h
99h
9Ah
9Bh
Write block
Read block
Reboot EEPROM in register file
Trigger fault store to EEPROM
Extended page access on
Extended page access off
EEPROM page access on
EEPROM page access off
1) The master sends a START condition.
Block Write
The block write protocol (see Figure 12) allows the
master device to write a block of data (1 byte to 16
bytes) to memory. The destination address should be
preloaded by a previous send byte command; other-
wise the block write command begins to write at the
current address pointer. After the last byte is written,
the address pointer remains preset to the next valid
address. If the number of bytes to be written causes
the address pointer to exceed FFh for EEPROM or 7Dh
for configuration registers, the address pointer stays at
FFh or 7Dh, overwriting this memory address with the
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends 8 bits of the block read com-
mand (95h).
5) The slave asserts an ACK on SDA, unless busy.
6) The master generates a REPEATED START condition.
7) The master sends the 7-bit slave address and a
read bit (high).
______________________________________________________________________________________ 53
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
8) The slave asserts an ACK on SDA.
9) The slave sends the 8-bit byte count (16).
10) The master asserts an ACK on SDA.
11) The slave sends 8 bits of data.
12) The master asserts an ACK on SDA.
13) Repeat steps 11 and 12 up to fifteen times.
14) The master asserts a NACK on SDA.
15) The master sends a STOP condition.
SEND BYTE FORMAT
RECEIVE BYTE FORMAT
S
ADDRESS WR ACK
DATA
ACK
P
S
ADDRESS WR ACK
DATA
NACK
P
0
1
7 BITS
8 BITS
7 BITS
8 BITS
SLAVE ADDRESS:
DATA BYTE: PRESETS THE
SLAVE ADDRESS:
DATA BYTE: PRESETS THE
EQUIVALENT TO CHIP-
SELECT LINE OF A
3-WIRE INTERFACE.
INTERNAL ADDRESS POINTER
OR REPRESENTS A COMMAND.
EQUIVALENT TO CHIP-
SELECT LINE OF A
3-WIRE INTERFACE.
INTERNAL ADDRESS POINTER
OR REPRESENTS A COMMAND.
WRITE BYTE FORMAT
S
ADDRESS
ACK
COMMAND
ACK
DATA
ACK
P
WR
0
SLAVE TO MASTER
7 BITS
8 BITS
8 BITS
DATA BYTE: DATA GOES INTO THE
REGISTER (OR EEPROM LOCATION)
SET BY THE COMMAND BYTE.
COMMAND BYTE:
SELECTS REGISTER OR
EEPROM LOCATION
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A
YOU ARE WRITING TO.
3-WIRE INTERFACE.
MASTER TO SLAVE
/MX16048A
READ BYTE FORMAT
SLAVE
ADDRESS
SLAVE
ADDRESS
S
ACK COMMAND ACK SR
8 BITS
ACK DATA BYTE NACK
8 BITS
WR
0
WR
1
P
7 BITS
7 BITS
DATA BYTE: DATA COMES
FROM THE REGISTER SET BY
THE COMMAND BYTE.
SLAVE ADDRESS:
COMMAND BYTE:
PREPARES DEVICE
FOR FOLLOWING
READ.
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A
3-WIRE INTERFACE.
EQUIVALENT TO CHIP-
SELECT LINE OF A
3-WIRE INTERFACE.
BLOCK WRITE FORMAT
BYTE
COUNT= N
DATA BYTE
DATA BYTE
DATA BYTE
N
S
ADDRESS
7 BITS
ACK COMMAND ACK
ACK
ACK
ACK
ACK
P
WR
0
1
...
8 BITS
8 BITS
8 BITS
8 BITS
8 BITS
COMMAND BYTE:
DESTINATION
ADDRESS
SLAVE ADDRESS:
DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE
COMMAND
EQUIVALENT TO CHIP-
SELECT LINE OF A
3-WIRE INTERFACE.
BLOCK READ FORMAT
DATA BYTE
...
DATA BYTE
BYTE
COUNT= N
DATA BYTE
1
S
ADDRESS
7 BITS
ACK COMMAND ACK SR ADDRESS
ACK
ACK
ACK
N
P
ACK
NACK
WR
0
WR
1
8 BITS
7 BITS
8 BITS
8 BITS
8 BITS
8 BITS
SLAVE ADDRESS:
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A
DATA BYTE: DATA IS READ FROM THE REGISTER (OR
EEPROM LOCATION) SET BY THE COMMAND CODE
COMMAND BYTE:
PREPARES DEVICE
FOR BLOCK
EQUIVALENT TO CHIP-
SELECT LINE OF A
3-WIRE INTERFACE.
3-WIRE INTERFACE.
OPERATION.
S = START CONDITION
P = STOP CONDITION
ACK = ACKNOWLEDGE, SDA PULLED LOW DURING RISING EDGE OF SCL
NACK = NOT ACKNOWLEGE, SDA LEFT HIGH DURING RISING EDGE OF SCL
SR = REPEATED START CONDITION ALL DATA IS CLOCKED IN/OUT OF THE DEVICE ON RISING EDGES OF SCL
= SDA TRANSISTIONS FROM HIGH TO LOW DURING PERIOD OF SCL
= SDA TRANSISTIONS FROM LOW TO HIGH DURING PERIOD OF SCL
D.C. = DON'T CARE
2
Figure 12: I C/SMBus Protocols
54 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
scan functionality. The MAX16046A/MAX16048A con-
tain extra JTAG instructions and registers not included
in the JTAG specification that provide access to inter-
nal memory. The extra instructions include LOAD
ADDRESS, WRITE, READ, REBOOT, SAVE, and
USERCODE.
JTAG Serial Interface
The MAX16046A/MAX16048A contain a JTAG port
that complies with a subset of the IEEE 1149.1 specifi-
2
cation. Either the I C or the JTAG interface may be
used to access internal memory; however, only one
interface is allowed to run at a time. The MAX16046A/
MAX16048A do not support IEEE 1149.1 boundary-
01100
01011
01010
01001
01000
00111
REGISTERS
AND EEPROM
MEMORY WRITE REGISTER
[LENGTH = 8 BITS]
00110
MUX 1
00101
MEMORY READ REGISTER
[LENGTH = 8 BITS]
MEMORY ADDRESS REGISTER
[LENGTH = 8 BITS]
00100
00011
COMMAND
DECODER
USER CODE REGISTER
[LENGTH = 32 BITS]
01100
01011
01010
01001
01000
00111
RSTEEPADD
SETEEPADD
RSTEXTRAM
SETEXTRAM
SAVE
IDENTIFICATION REGISTER
[LENGTH = 32 BITS]
00000
11111
BYPASS REGISTER
[LENGTH = 1 BIT]
REBOOT
V
DB
INSTRUCTION REGISTER
[LENGTH = 5 BITS]
R
PU
TDI
MUX 2
TDO
TMS
TCK
TEST ACCESS PORT
(TAP) CONTROLLER
Figure 13. JTAG Block Diagram
______________________________________________________________________________________ 55
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Test Access Port (TAP)
Controller State Machine
The TAP controller is a finite state machine that
responds to the logic level at TMS on the rising edge of
TCK. See Figure 14 for a diagram of the finite state
machine. The possible states are described below:
Select-DR-Scan: All test data registers retain their pre-
vious state. With TMS low, a rising edge of TCK moves
the controller into the capture-DR state and initiates a
scan sequence. TMS high during a rising edge on TCK
moves the controller to the select-IR-scan state.
Capture-DR: Data can be parallel-loaded into the test
data registers selected by the current instruction. If the
instruction does not call for a parallel load or the select-
ed test data register does not allow parallel loads, the
test data register remains at its current value. On the
rising edge of TCK, the controller goes to the shift-DR
state if TMS is low or it goes to the exit1-DR state if TMS
is high.
Test-Logic-Reset: At power-up, the TAP controller is in
the test-logic-reset state. The instruction register con-
tains the IDCODE instruction. All system logic of the
device operates normally. This state can be reached
from any state by driving TMS high for five clock cycles.
Run-Test/Idle: The run-test/idle state is used between
scan operations or during specific tests. The instruction
register and test data registers remain idle.
TEST-LOGIC-RESET
1
0
0
1
1
1
SELECT-DR-SCAN
SELECT-IR-SCAN
RUN-TEST/IDLE
/MX16048A
0
CAPTURE-DR
0
0
CAPTURE-IR
0
1
1
0
SHIFT-DR
0
SHIFT-IR
1
1
1
0
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
PAUSE-IR
0
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Figure 14. TAP Controller State Diagram
56 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Shift-DR: The test data register selected by the current
instruction connects between TDI and TDO and shifts
data one stage toward its serial output on each rising
edge of TCK while TMS is low. On the rising edge of TCK,
the controller goes to the exit1-DR state if TMS is high.
of the instruction register as well as all test data regis-
ters remain at their previous states. A rising edge on
TCK with TMS high moves the controller to the exit1-IR
state. A rising edge on TCK with TMS low keeps the
controller in the shift-IR state while moving data one
stage through the instruction shift register.
Exit1-DR: While in this state, a rising edge on TCK puts
the controller in the update-DR state. A rising edge on
TCK with TMS low puts the controller in the pause-DR
state.
Exit1-IR: A rising edge on TCK with TMS low puts the
controller in the pause-IR state. If TMS is high on the
rising edge of TCK, the controller enters the update-IR
state.
Pause-DR: Shifting of the test data registers halts while
in this state. All test data registers retain their previous
state. The controller remains in this state while TMS is
low. A rising edge on TCK with TMS high puts the con-
troller in the exit2-DR state.
Pause-IR: Shifting of the instruction shift register halts
temporarily. With TMS high, a rising edge on TCK puts
the controller in the exit2-IR state. The controller
remains in the pause-IR state if TMS is low during a ris-
ing edge on TCK.
Exit2-DR: A rising edge on TCK with TMS high while in
this state puts the controller in the update-DR state. A
rising edge on TCK with TMS low enters the shift-DR
state.
Exit2-IR: A rising edge on TCK with TMS high puts the
controller in the update-IR state. The controller loops
back to shift-IR if TMS is low during a rising edge of
TCK in this state.
Update-DR: A falling edge on TCK while in the update-
DR state latches the data from the shift register path of
the test data registers into a set of output latches. This
prevents changes at the parallel output because of
changes in the shift register. On the rising edge of TCK,
the controller goes to the run-test/idle state if TMS is
low or goes to the select-DR-scan state if TMS is high.
Update-IR: The instruction code that has been shifted
into the instruction shift register latches to the parallel
outputs of the instruction register on the falling edge of
TCK as the controller enters this state. Once latched,
this instruction becomes the current instruction. A rising
edge on TCK with TMS low puts the controller in the
run-test/idle state. With TMS high, the controller enters
the select-DR-scan state.
Select-IR-Scan: All test data registers retain their previ-
ous states. The instruction register remains unchanged
during this state. With TMS low, a rising edge on TCK
moves the controller into the capture-IR state. TMS high
during a rising edge on TCK puts the controller back
into the test-logic-reset state.
Instruction Register
The instruction register contains a shift register as well
as a latched parallel output and is 5 bits in length. When
the TAP controller enters the shift-IR state, the instruc-
tion shift register connects between TDI and TDO. While
in the shift-IR state, a rising edge on TCK with TMS low
shifts the data one stage toward the serial output at
TDO. A rising edge on TCK in the exit1-IR state or the
exit2-IR state with TMS high moves the controller to the
update-IR state. The falling edge of that same TCK
latches the data in the instruction shift register to the
instruction register parallel output. Instructions support-
ed by the MAX16046A/MAX16048A and the respective
operational binary codes are shown in Table 33.
Capture-IR: Use the capture-IR state to load the shift
register in the instruction register with a fixed value.
This value is loaded on the rising edge of TCK. If TMS
is high on the rising edge of TCK, the controller enters
the exit1-IR state. If TMS is low on the rising edge of
TCK, the controller enters the shift-IR state.
Shift-IR: In this state, the shift register in the instruction
register connects between TDI and TDO and shifts
data one stage for every rising edge of TCK toward the
TDO serial output while TMS is low. The parallel outputs
______________________________________________________________________________________ 57
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 33. JTAG Instruction Set
INSTRUCTION
BYPASS
HEX CODE
1Fh
SELECTED REGISTER/ACTION
Bypass. Mandatory instruction code.
IDCODE
00h
Manufacturer ID code and part number
User code (user-defined ID)
Load address register content
Memory read
USERCODE
LOAD ADDRESS
READ DATA
WRITE DATA
REBOOT
03h
04h
05h
06h
Memory write
07h
Resets the device
SAVE
08h
Stores current fault information in EEPROM
Extended page access on
Extended page access off
EEPROM page access on
EEPROM page access off
SETEXTRAM
RSTEXTRAM
SETEEPADD
RSTEEPADD
09h
0Ah
0Bh
0Ch
BYPASS: When the BYPASS instruction is latched into
the instruction register, TDI connects to TDO through
the 1-bit bypass test data register. This allows data to
pass from TDI to TDO without affecting the device’s
normal operation.
edge of TCK following entry into the capture-DR state.
Shift-DR can be used to shift the identification code out
serially through TDO. During test-logic-reset, the
IDCODE instruction is forced into the instruction regis-
ter. The identification code always has a ‘1’ in the LSB
position. The next 11 bits identify the manufacturer’s
JEDEC number and number of continuation bytes fol-
lowed by 16 bits for the device and 4 bits for the ver-
sion. See Table 34.
/MX16048A
IDCODE: When the IDCODE instruction is latched into
the parallel instruction register, the identification data
register is selected. The device identification code is
loaded into the identification data register on the rising
Table 34. 32-Bit Identification Code
MSB
LSB
Version (4 bits)
0000
Device ID (16 bits)
0000000000000001
Manufacturer ID (11 bits)
00011001011
Fixed value (1 bit)
1
USERCODE: When the USERCODE instruction latches
into the parallel instruction register, the user-code data
register is selected. The device user-code loads into
the user-code data register on the rising edge of TCK
following entry into the capture-DR state. Shift-DR can
be used to shift the user-code out serially through TDO.
See Table 35. This instruction may be used to help
identify multiple MAX16046A/MAX16048A devices con-
nected in a JTAG chain.
Table 35. 32-Bit User-Code Data
MSB
LSB
2
I C/SMBus
D.C. (don’t cares)
User identification (firmware version)
slave address
00000000000000000
See Table 31
r5Ch[7:0] contents
58 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
LOAD ADDRESS: This is an extension to the standard
Applications Information
IEEE 1149.1 instruction set to support access to the
Unprogrammed Device Behavior
memory in the MAX16046A/MAX16048A. When the
LOAD ADDRESS instruction latches into the instruction
register, TDI connects to TDO through the 8-bit memory
address test data register during the shift-DR state.
When the EEPROM has not been programmed using
2
the JTAG or I C interface, the default configuration of
the EN_OUT_ outputs is open-drain active-low. If it is
necessary to hold an EN_OUT_ high or low to prevent
premature startup of a power supply before the
EEPROM is programmed, connect a resistor to ground
or the supply voltage. Avoid connecting a resistor to
ground if the output is to be configured as open-drain
with a separate pullup resistor.
READ DATA: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16046A/MAX16048A. When the READ
instruction latches into the instruction register, TDI con-
nects to TDO through the 8-bit memory read test data
register during the shift-DR state.
Device Behavior at Power-Up
WRITE DATA: This is an extension to the standard
IEEE 1149.1 instruction set to support access to the
memory in the MAX16046A/MAX16048A. When the
WRITE instruction latches into the instruction register,
TDI connects to TDO through the 8-bit memory write
test data register during the shift-DR state.
When V
is ramped from 0V, the RESET output is high
CC
impedance until V
reaches 1.4V, at which point it is
CC
driven low. All other outputs are high impedance until
reaches 2.85V, when the EEPROM contents are
V
CC
copied into register memory, and after which the out-
puts assume their programmed states.
REBOOT: This is an extension to the standard IEEE
1149.1 instruction set to initiate a software controlled
reset to the MAX16046A/MAX16048A. When the
REBOOT instruction latches into the instruction register,
the MAX16046A/MAX16048A resets and immediately
begins the boot-up sequence.
Margining Power Supplies
The MAX16046A/MAX16048A can margin or shift the
voltages on external power supplies to facilitate proto-
typing or manufacturing tests. There are several differ-
ent ways to margin power supplies: One method feeds
a current into the feedback node of a DC-DC converter
or LDO, and another method feeds a current into the
trim input on a DC-DC module.
SAVE: This is an extension to the standard IEEE 1149.1
instruction set that triggers a fault log. The current ADC
conversion results along with fault information are
saved to EEPROM depending on the configuration of
the Critical Fault Log Control register (r47h).
Feedback Method
See Figure 15 for the connections of the MAX16046A/
MAX16048A to a power supply using the feedback
SETEXTRAM: This is an extension to the standard
IEEE 1149.1 instruction set that allows access to the
extended page. Extended registers include ADC con-
version results, DACOUT enables, and GPIO input/out-
put data.
node method. The output voltage, V
lated using the following formula:
, can be calcu-
OUT
⎛
⎜
⎞
⎟
R
R
R
R
R
R
1
3
1
2
1
3
V
= V
1+
+
−
V
DACOUT_
OUT
REF
RSTEXTRAM: This is an extension to the standard IEEE
1149.1 instruction set. Use RSTEXTRAM to return to the
default page and disable access to the extended page.
⎜
⎝
⎟
⎠
where V
is the internal reference voltage of the
REF
SETEEPADD: This is an extension to the standard
IEEE 1149.1 instruction set that allows access to the
EEPROM page. Once the SETEEPADD command has
been sent, all addresses are recognized as EEPROM
addresses only.
power supply and V
is the output voltage of
DACOUT_
the MAX16046A/MAX16048A DACOUT_ output.
Select R and R to obtain the desired output voltage
1
2
with no trim in effect (V
range bits such that V
= V
). Set the DAC
DACOUT_
REF
falls approximately halfway
REF
RSTEEPADD: This is an extension to the standard IEEE
1149.1 instruction set. Use RSTEEPADD to return to the
default page and disable access to the EEPROM.
within the DACOUT_ output range (see the DAC
Outputs section). The resistor, R , varies the amount of
3
control that the DACOUT_ voltage has on the output
voltage of the power supply. Large values of R corre-
3
spond to a higher degree of resolution control over the
output voltage, and small values of R correspond to a
3
lesser degree of resolution control.
______________________________________________________________________________________ 59
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
DC-DC OR LDO
DC-DC OR LDO
OUT
OUT
MAX16046A
MAX16048A
MAX16046A
MAX16048A
R
1
2
R
R
1
R
R
R
3B
3
3A
FB
FB
C
R
2
V
V
DACOUT_
DACOUT_
V
REF
V
REF
Figure 15. Connections for Margining Using Feedback Method
Figure 16. DACOUT Filter
Filtering the DAC Outputs
Some applications require filtering of the DAC outputs.
This is especially necessary in applications that require
a large distance between the power supplies to be
margined and the MAX16046A/MAX16048A, or those
that require immunity to noise. A simple RC filter may
be inserted (see Figure 16).
Calculate the ratio of R and R using the following for-
1
2
mula:
⎛
⎞
V
OUT_NOM
R
R
1
2
1+
=
⎟
⎜
V
⎝
⎠
REF
/MX16048A
Resistors R and R and the reference voltage V
REF
3
4
The calculations change slightly for this configuration.
may be derived from the formulas given in the DC-DC
converter data sheet where trim input functionality is
discussed. DC-DC module data sheets usually include
trim-up and trim-down formulas in the following form:
For DC margining calculations, R = R + R . To cal-
3
3A
3B
culate the lowpass cutoff frequency, use the following
formula:
1
⎛ 1− Δ ⎞
f =
TRIM DOWN:R
TRIM UP:R
kΩ
=
R
kΩ − R kΩ
(
)
(
)
(
)
ADJ_DOWN
3
⎟
4
⎜
2πR
C
⎝
⎠
Δ
3B
⎛ V
⎞
⎛ 1− Δ ⎞
⎠
OUT_NOM
kΩ
=
− 1
⎟ ⎜
R
kΩ − R kΩ
(
)
(
)
(
)
ADJ_UP
3
4
⎜
⎟
Place resistor R
and the capacitor, C, as close as
possible to the feedback node.
3A
⎝
⎠
Δ
V
⎝
REF
where Δ is the fraction of the total correction.
Another form of trim-up and trim-down formulas may
appear as follows:
Trim Input Method
To connect the MAX16046A/MAX16048A to a power
supply using the trim input method, see Figure 17.
Calculate the output voltage, V
, as follows:
OUT
⎛
⎞
R
kΩ ×100
Δ%
(
)
⎛
⎞
⎛
⎞ R V
+ (R + R )V
REF
+ R + R
4 5
3
R
R
3 DACOUT_
4
5
TRIM DOWN:R
kΩ
=
−
R
kΩ + R kΩ
1
2
(
)
(
)
(
)
(
)
⎜
⎟
ADJ_DOWN
4
3
V
= 1+
⎝
⎠
OUT
⎜
⎟ ⎜
⎟
R
⎝
⎠ ⎝
⎠
3
⎛
⎞
⎟
V
R
kΩ × 100 + Δ%
(
)
(
)
(
)
OUT_NOM
3
⎜
TRIM UP:R
kΩ
=
(
)
ADJ_UP
V
Δ%
⎜
⎝
⎟
⎠
REF
where V
is the reference voltage of the power sup-
REF
ply; R , R , R , and R are resistors internal to the
⎛
⎜
⎞
⎟
1
2
3
4
R
kΩ ×100 + R kΩ + R kΩ Δ%
(
)
(
)
(
)
(
)
3
4
3
−
power supply; R is an optional series resistor connect-
5
Δ%
⎜
⎝
⎟
⎠
ing the trim input to the DACOUT_ output; and
V
is the output voltage of the DACOUT_ output.
DACOUT_
60 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Set the DACOUT_ range bits (see the DAC Outputs
DC-DC OR LDO
section) such that V
falls approximately halfway
REF
within the DACOUT range. Set R to vary the amount of
5
OUT
control the DAC has on the output voltage of the power
supply. Large values of R correspond to higher
5
MAX16046A
MAX16048A
R
R
1
2
degree of resolution control over the output voltage,
R
5
and small values of R correspond to lesser degree of
5
resolution control. Be sure to respect the minimum and
maximum output voltages that the DC-DC converter is
capable of generating.
V
DACOUT_
R
3
The following is an example that illustrates the use of
the formulas for calculating the margin up and margin
down values. This example uses a generic 3.3V DC-DC
converter with a trim input. Below are the margin up
and margin down formulas taken from the data sheet
for the power supply:
R
4
TRIM
V
REF
Figure 17. Connections for Margining Using Trim Input Method
⎛ 100
⎞
⎠
TRIM DOWN:R
TRIM UP:R
=
− 2 kΩ
(
)
ADJ_DOWN
⎜
⎟
Table 36. EEPROM Fault Log Operation
Period
⎝
Δ%
⎛ V
(100 + Δ%)
⎞
− 100 + 2Δ%
Δ%
OUT_NOM
=
kΩ
(
)
ADJ_UP
⎜
⎟
1.225Δ%
⎝
⎠
REQUIRED
FAULT CONTROL
PERIOD
REGISTER VALUE
r47h [1:0]
DESCRIPTION
By inspecting these formulas, V
= 1.225V, R =
3
REF
t
FAULT_SAVE
(ms)
1kΩ, and R = 1kΩ. Set the DACOUT_ range from 0.8V
4
to 1.6V to fit the reference voltage. The output voltage
of the DC-DC converter is 3.3V; therefore the ratio (1 +
Failed lines and
ADC values saved
00
306
R /R ) = V /V = 3.3/1.225 = 2.69.
OUT REF
1
2
Set R to zero to use the widest trim range possible
01
10
Failed lines saved
ADC values saved
90
5
(increase R to decrease the trim range). Insert these
5
252
values into the equations for the output voltage:
No information
saved
11
—
V
+1.225
(
)
⎛ 1kΩ × V
+1kΩ ×1.225 ⎞
DACOUT_
2
DACOUT
V
=
2.69
= 2.69
(
(
)
)
OUT
⎜
⎝
⎟
2kΩ
⎠
Maintain power for shutdown during fault conditions in
applications where the always-on power supply cannot
be relied upon by placing a diode and a large capaci-
tor between the voltage source, V , and V
18). The capacitor value depends on V and the time
delay required, t
to calculate the capacitor size:
For V
DACOUT_
= 0.8V, V
= 2.72V, and for
OUT
DACOUT_
V
= 1.6V, V
= 3.80V. These output volt-
OUT
(Figure
CC
IN
ages correspond with a margin down limit of -17.6%
and a margin up limit of 15.2%. Since the reference
voltage is not exactly in the center of the DACOUT_
range, the margin limits are not symmetrical. To
IN
. Use the following formula
FAULT_SAVE
t
× I
decrease the margin limits, increase the value of R .
5
FAULT_SAVE
CC(MAX)
− V
C =
V
− V
DIODE
IN
UVLO
Maintaining Power During a Fault
Condition
where the capacitance is in Farads and t
in seconds. I
drop across the diode, and V
ple, with a V of 14V, a diode drop of 0.7V, and a
FAULT_SAVE
tance is 190μF.
is
Power to the MAX16046A/MAX16048A must be main-
tained for a specific period of time to ensure a success-
ful EEPROM fault log operation during a fault that
removes power to the circuit. The amount of time
required depends on the settings in the fault control
register (r47h[1:0]) according to Table 36.
FAULT_SAVE
is the voltage
is 6.5mA, V
CC(MAX)
DIODE
is 2.85V. For exam-
UVLO
IN
t
of 0.306s, the minimum required capaci-
______________________________________________________________________________________ 61
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
If more than six series-pass MOSFETs are required for
an application, additional series-pass p-channel
MOSFETS may be connected to outputs configured as
V
V
CC
IN
active-low open drain (Figure 20). Connect a pullup
resistor from the gate to the source of the MOSFET, and
ensure the absolute maximum ratings of the
MAX16046A/MAX16048A are not exceeded.
C
MAX16046A
MAX16048A
V
IN
V
OUT
GND
MON_
EN_OUT_
INS_
GATE
DRIVE
ADC MUX
LOGIC
Figure 18. Power Circuit for Shutdown During Fault Conditions
Driving High-Side MOSFET Switches
The MAX16046A/MAX16048A use external n-channel
MOSFET switches for voltage tracking applications. To
configure the part for closed-loop voltage tracking
using series-pass MOSFETs, configure up to four of the
programmable outputs (EN_OUT1–EN_OUT4) of the
MAX16046A/MAX16048A as closed-loop tracking out-
puts and configure up to four of the GPIOs as sense-
return inputs (INS1–INS4). Connect the EN_OUT_
output to the gate of an n-channel MOSFET, connect
the source of the MOSFET to the INS_ feedback input,
and monitor the drain side of the MOSFET with the cor-
responding MON_ input (see Figure 19). Both the input
and the output must be assigned to the same slot (see
the Closed–Loop Tracking section). Configure the
power-up and power-down slew rates in the configura-
tion registers. To provide additional control over power-
down, enable the internal 100Ω pulldown resistors on
the INS_ connections.
V
TH_PG
REFERENCE
RAMP
100Ω
/MX16048A
Figure 19. Closed-Loop Tracking
V
IN
V
OUT
Up to six of the programmable outputs (EN_OUT1–
EN_OUT6) of the MAX16046A/MAX16048A may be con-
figured as charge-pump outputs. In this case, they can
drive the gates of series-pass n-channel MOSFETS with-
out closed-loop tracking functionality. When configured
in this way, these outputs act as simple power switches
to turn on the voltage supply rails. Approximate the slew
rate, SR, using the following formula:
R
MON_
EN_OUT_
MAX16046A
MAX16048A
I
CP
+ C
EXT
SR =
C
(
)
GATE
where I
is the 6μA (typ) charge-pump source cur-
CP
rent, C
is the gate capacitance of the MOSFET,
GATE
EXT
and C
is the capacitance connected from the gate
to ground. Power-down is not well controlled due to the
absence of the 100Ω pulldowns.
Figure 20. Connection for a p-Channel Series-Pass MOSFET
62 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Simple slew-rate control is accomplished by adding a
capacitor from the gate to ground. The slew rate is
approximated by the RC charge curve of the pullup
resistor acting with the capacitor from gate to ground.
Note that the power-off is not well controlled due to the
absence of the 100Ω pulldowns.
Layout and Bypassing
Bypass DBP and ABP each with a 1μF ceramic capacitor
to GND. Bypass V
with a 10μF capacitor to ground.
CC
Avoid routing digital return currents through a sensitive
analog area, such as an analog supply input return path
or ABP’s bypass capacitor ground connection. Use dedi-
cated analog and digital ground planes. Connect the
capacitors as close as possible to the device.
Ensure that MOSFETs have a low gate-to-source
threshold (V
) and R
. See Table 37 for rec-
DS(ON)
GS_TH
ommended n-channel MOSFETs.
Table 37. Recommended MOSFETs
I
AT 50mV
MAX
R
V
AT
4.5V
DS(ON)
MAX V
DS
V
VOLTAGE
DROP
(A)
Q (typ)
g
(nC)
GS_TH
(V)
MANUFACTURER
PART
PACKAGE
GS =
(mΩ)
(V)
FDC633N
30
30
0.67
1.5
42
1.19
11
Super SOT-6
FDP8030L
FDB8030L
TO-220
TO-263AB
4.5
11.11
120
Fairchild
FDD6672A
FDS8876
30
30
20
30
20
1.2
2.5
3
9.5
10.2
4.5
10
5.26
2.94
11.11
5
33
15
TO-252
SO-8
Si7136DP
24.5
27
SO-8
Si4872DY
1
SO-8
Vishay
SUD50N02-09P
3
17
2.94
10.5
TO-252
SOT-363
SC70-6
Si1488DH
IRL3716
20
20
20
20
20
0.95
3
49
4.8
10
1.02
10.4
5
6
TO220AB
2
53
D PAK
TO-262
78
(max)
IRL3402
0.7
2.1
1.2
TO220AB
International
Rectifier
TO220AB
2
D PAK
IRL3715Z
IRLM2502
15.5
45
3.22
1.11
7
8
TO-262
SOT23-3
Micro3
______________________________________________________________________________________ 63
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Register Map
PAGE
Ext
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
READ/WRITE
DESCRIPTION
MON1 ADC Result Register (MSB)
R
R
Ext
MON1 ADC Result Register (LSB)
MON2 ADC Result Register (MSB)
MON2 ADC Result Register (LSB)
MON3 ADC Result Register (MSB)
MON3 ADC Result Register (LSB)
MON4 ADC Result Register (MSB)
MON4 ADC Result Register (LSB)
MON5 ADC Result Register (MSB)
MON5 ADC Result Register (LSB)
MON6 ADC Result Register (MSB)
MON6 ADC Result Register (LSB)
MON7 ADC Result Register (MSB)
MON7 ADC Result Register (LSB)
MON8 ADC Result Register (MSB)
MON8 ADC Result Register (LSB)
MON9 ADC Result Register (MSB)*
MON9 ADC Result Register (LSB)*
MON10 ADC Result Register (MSB)*
MON10 ADC Result Register (LSB)*
MON11 ADC Result Register (MSB)*
MON11 ADC Result Register (LSB)*
MON12 ADC Result Register (MSB)*
MON12 ADC Result Register (LSB)*
Fault Register—Failed Line Flags
Fault Register—Failed Line Flags
GPIO Data Out
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
/MX16048A
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R
Ext
R/W
R/W
R/W
R
Ext
Ext
Ext
GPIO Data In
Ext
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DAC Enables
Ext
DAC Enables
Default
Default
Default
Default
Default
Default
Default
Default
Default
Default
DACOUT1
DACOUT2
DACOUT3
DACOUT4
DACOUT5
DACOUT6
DACOUT7
DACOUT8
DACOUT9*
DACOUT10*
64 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Register Map (continued)
PAGE
Default
Default
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Def/EE
ADDRESS
0Ah
0Bh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
DACOUT11*
DACOUT12*
Power-Up Fault Registers
Failed Line Flags (Fault Registers)
Failed Line Flags (Fault Registers)
MON1 Conversion Result at Time of Fault
MON2 Conversion Result at Time of Fault
MON3 Conversion Result at Time of Fault
MON4 Conversion Result at Time of Fault
MON5 Conversion Result at Time of Fault
MON6 Conversion Result at Time of Fault
MON7 Conversion Result at Time of Fault
MON8 Conversion Result at Time of Fault
MON9 Conversion Result at Time of Fault*
MON10 Conversion Result at Time of Fault*
MON11 Conversion Result at Time of Fault*
MON12 Conversion Result at Time of Fault*
ADC MON4–MON1 Voltage Ranges
ADC MON8–MON5 Voltage Ranges
ADC MON12–MON9 Voltage Ranges*
DACOUT4–DACOUT1 Voltage Ranges
DACOUT8–DACOUT5 Voltage Ranges
DACOUT12–DACOUT9 Voltage Ranges*
FAULT1 Dependencies
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
FAULT1 Dependencies
Def/EE
FAULT2 Dependencies
Def/EE
FAULT2 Dependencies
Def/EE
RESET Output Configuration
Def/EE
RESET Output Dependencies
Def/EE
RESET Output Dependencies
Def/EE
GPIO Configuration
Def/EE
GPIO Configuration
Def/EE
GPIO Configuration
Def/EE
EN_OUT1–EN_OUT3 Output Configuration
EN_OUT3–EN_OUT6 Output Configuration
EN_OUT6–EN_OUT9 Output Configuration*
EN_OUT10–EN_OUT12 Output Configuration*
MON1 Early Warning Threshold
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
MON1 Overvoltage Threshold
Def/EE
MON1 Undervoltage Threshold
______________________________________________________________________________________ 65
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Register Map (continued)
PAGE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
ADDRESS
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
MON2 Early Warning Threshold
MON2 Overvoltage Threshold
MON2 Undervoltage Threshold
MON3 Early Warning Threshold
MON3 Overvoltage Threshold
MON3 Undervoltage Threshold
MON4 Early Warning Threshold
MON4 Overvoltage Threshold
MON4 Undervoltage Threshold
MON5 Early Warning Threshold
MON5 Overvoltage Threshold
MON5 Undervoltage Threshold
MON6 Early Warning Threshold
MON6 Overvoltage Threshold
MON6 Undervoltage Threshold
MON7 Early Warning Threshold
MON7 Overvoltage Threshold
MON7 Undervoltage Threshold
MON8 Early Warning Threshold
MON8 Overvoltage Threshold
MON8 Undervoltage Threshold
MON9 Early Warning Threshold*
MON9 Overvoltage Threshold*
MON9 Undervoltage Threshold*
MON10 Early Warning Threshold*
MON10 Overvoltage Threshold*
MON10 Undervoltage Threshold*
MON11 Early Warning Threshold*
MON11 Overvoltage Threshold*
MON11 Undervoltage Threshold*
MON12 Early Warning Threshold*
MON12 Overvoltage Threshold*
MON12 Undervoltage Threshold*
Fault Control
/MX16048A
Faults Causing Emergency EEPROM Save
Faults Causing Emergency EEPROM Save
Faults Causing Emergency EEPROM Save
Faults Causing Emergency EEPROM Save
Faults Causing Emergency EEPROM Save
Software Enable/MARGIN
66 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Register Map (continued)
PAGE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
ADDRESS
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
DESCRIPTION
Power-Up/Power-Down Pulldown Resistors
Autoretry, Slew Rate, and ADC Fault Deglitch
Sequence Delays
Sequence Delays
Sequence Delays
Sequence Delays
Sequence Delays/Reverse Sequence Bit
Watchdog Timer Setup
MON2–MON1 Slot Assignment from Slot 1 to Slot 12
MON4–MON3 Slot Assignment from Slot 1 to Slot 12
MON6–MON5 Slot Assignment from Slot 1 to Slot 12
MON8–MON7 Slot Assignment from Slot 1 to Slot 12
MON10–MON9 Slot Assignment from Slot 1 to Slot 12*
MON12–MON11 Slot Assignment from Slot 1 to Slot 12*
Customer Firmware Version
EEPROM and Configuration Lock
EN_OUT2–EN_OUT1 Slot Assignment from Slot 0 to Slot 11
EN_OUT4–EN_OUT2 Slot Assignment from Slot 0 to Slot 11
EN_OUT6–EN_OUT5 Slot Assignment from Slot 0 to Slot 11
EN_OUT8–EN_OUT7 Slot Assignment from Slot 0 to Slot 11
EN_OUT10–EN_OUT9 Slot Assignment from Slot 0 to Slot 11*
EN_OUT12–EN_OUT11 Slot Assignment from Slot 0 to Slot 11*
INS Power-Good (PG) Thresholds
Manufacturing Revision Code
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DACOUT1—MARGIN UP
DACOUT2—MARGIN UP
DACOUT3—MARGIN UP
DACOUT4—MARGIN UP
DACOUT5—MARGIN UP
DACOUT6—MARGIN UP
DACOUT7—MARGIN UP
DACOUT8—MARGIN UP
DACOUT9—MARGIN UP*
DACOUT10—MARGIN UP*
DACOUT11—MARGIN UP*
DACOUT12—MARGIN UP*
DACOUT1—MARGIN DN
DACOUT2—MARGIN DN
DACOUT3—MARGIN DN
DACOUT4—MARGIN DN
______________________________________________________________________________________ 67
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Register Map (continued)
PAGE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
Def/EE
EEPROM
ADDRESS
76h
READ/WRITE
R/W
DESCRIPTION
DACOUT5—MARGIN DN
DACOUT6—MARGIN DN
DACOUT7—MARGIN DN
DACOUT8—MARGIN DN
DACOUT9—MARGIN DN*
DACOUT10—MARGIN DN*
DACOUT11—MARGIN DN*
DACOUT12—MARGIN DN*
Reserved
77h
R/W
78h
R/W
79h
R/W
7Ah
R/W
7Bh
R/W
7Ch
R/W
7Dh
R/W
7Eh–93h
9Ch–FFh
—
R/W
User EEPROM
*MAX16046A only
Note: Ext refers to registers contained in the extended page, Default refers to registers contained in the default page, EEPROM
refers to EEPROM memory locations, and Def/EE refers to locations that are stored in EEPROM and loaded into the same addresses
in the default page on boot-up.
/MX16048A
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
56 TQFN
64 TQFP
T5688-3
C64E+6
21-0135
21-0084
68 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Pin Configurations
TOP VIEW
56 55 54 53 52 51 50 49 48 47 46 45 44 43
+
MON1
MON2
MON3
MON4
MON5
MON6
MON7
MON8
MON9
1
2
3
4
5
6
7
8
9
42 GPIO2
41 GPIO1
40 GND
DBP
39
38
V
CC
37 ABP
DACOUT12
36
35
34
DACOUT11
DACOUT10
MAX16046A
MON10 10
MON11 11
MON12 12
RESET 13
A0 14
33 DACOUT9
32 DACOUT8
31 DACOUT7
30 DACOUT6
29 DACOUT5
EP
15 16 17 18 19 20 21 22 23 24 25 26 27 28
TQFN
(8mm x 8mm)
56 55 54 53 52 51 50 49 48 47 46 45 44 43
+
MON1
MON2
MON3
MON4
MON5
MON6
MON7
MON8
N.C.
1
2
3
4
5
6
7
8
9
42 GPIO2
41 GPIO1
40 GND
DBP
39
38
V
CC
37 ABP
N.C.
N.C.
N.C.
36
35
34
MAX16048A
N.C. 10
N.C. 11
N.C. 12
RESET 13
A0 14
33 N.C.
32 DACOUT8
31 DACOUT7
30 DACOUT6
29 DACOUT5
EP
15 16 17 18 19 20 21 22 23 24 25 26 27 28
TQFN
(8mm x 8mm)
______________________________________________________________________________________ 69
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Pin Configurations (continued)
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
MON1
MON2
MON3
MON4
MON5
MON6
MON7
N.C.
1
2
3
4
5
6
7
8
9
48 N.C.
47 GPIO2
46 GPIO1
45 GND
44 DBP
43
V
CC
42 ABP
41 DACOUT12
40 DACOUT11
39 DACOUT10
38 DACOUT9
37 DACOUT8
36 DACOUT7
35 DACOUT6
34 DACOUT5
33 N.C.
MAX16046A
N.C.
MON8 10
MON9 11
MON10 12
MON11 13
MON12 14
N.C. 15
RESET 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
/MX16048A
TQFP
(10mm x 10mm)
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
MON1
MON2
MON3
MON4
MON5
MON6
MON7
N.C.
1
2
3
4
5
6
7
8
9
48 N.C.
47 GPIO2
46 GPIO1
45 GND
44 DBP
43
V
CC
42 ABP
41 N.C.
MAX16048A
N.C.
40 N.C.
MON8 10
N.C. 11
N.C. 12
N.C. 13
N.C. 14
N.C. 15
RESET 16
39 N.C.
38 N.C.
37 DACOUT8
36 DACOUT7
35 DACOUT6
34 DACOUT5
33 N.C.
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP
(10mm x 10mm)
70 ______________________________________________________________________________________
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
/MX16048A
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
4/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 71
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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