MAX16059 [MAXIM]
125nA Supervisory Circuits with Capacitor- Adjustable Reset and Watchdog Timeouts; 125nA监控电路，带有Capacitor-可调复位和看门狗超时
| 型号： | MAX16059 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 125nA Supervisory Circuits with Capacitor- Adjustable Reset and Watchdog Timeouts |
| 文件： | 总17页 (文件大小：749K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
General Description
Features
o Ultra-Low 125nA (typ) Supply Current
The MAX16056–MAX16059 are ultra-low-current 125nA
(typ) microprocessor (µP) supervisory circuits that mon-
itor a single system supply voltage. These devices
o 1.1V to 5.5V Operating Supply Range
o Factory-Set Reset Threshold Options from 1.575V
assert an active-low reset signal whenever the V
CC
to 4.625V in Approximately 100mV Increments
supply voltage drops below the factory-trimmed reset
threshold, manual reset is pulled low, or the watchdog
timer runs out (MAX16056/MAX16058). The reset output
remains asserted for an adjustable reset timeout period
o Capacitor-Adjustable Reset Timeout
o Capacitor-Adjustable Watchdog Timeout
(MAX16056/MAX16058)
o Watchdog Timer Capacitor Open Detect Function
o Optional Watchdog Disable Function
after V
rises above the reset threshold. Factory-
CC
trimmed reset threshold voltages are offered from
1.575V to 4.625V in approximately 100mV increments
(see Table 1).
(MAX16056/MAX16058)
o Manual Reset Input
These devices feature adjustable reset and watchdog
timeout using external capacitors. The MAX16056/
MAX16058 contain a watchdog timer with a watchdog
select input (WDS) that multiplies the watchdog timeout
period by 128. The MAX16057/MAX16059 do not have
the watchdog feature.
o Guaranteed RESET Valid for V
≥ 1.1V
CC
o Push-Pull or Open-Drain RESET Output Options
o Power-Supply Transient Immunity
o Small, 3mm x 3mm TDFN Package
Ordering Information
The MAX16056–MAX16059 are available in either push-
pull or open-drain output-type configurations (see the
Ordering Information). These devices are fully specified
over the -40°C to +125°C automotive temperature range.
The MAX16056/MAX16058 are available in the 8-pin
TDFN package, and the MAX16057/MAX16059 are avail-
able in the 6-pin TDFN package.
WATCH-
DOG
TIMER
PIN-
PACKAGE
RESET
OUTPUT
PART
MAX16056ATA_ _+T 8 TDFN-EP*
MAX16057ATT_ _+T 6 TDFN-EP*
MAX16058ATA_ _+T 8 TDFN-EP*
MAX16059ATT_ _+T 6 TDFN-EP*
Push-Pull
Push-Pull
Yes
No
Open-Drain
Open-Drain
Yes
No
Applications
Portable/Battery-Powered Equipment
PDAs/Cell Phones
MP3 Players/Pagers
Glucose Monitors/Patient Monitors
Metering/HVAC
Note: All devices are specified over the -40°C to +125°C oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
“_ _” represents the two number suffix needed when ordering
the reset threshold voltage value (see Table 1).
Standard versions and their package top marks are shown in
Table 3 at the end of data sheet.
Typical Operating Circuit appears at end of data sheet.
Pin Configurations
V
WDS WDI SRT
V
N.C.
5
SRT
4
CC
8
CC
6
TOP VIEW
7
6
5
MAX16056
MAX16058
MAX16057
MAX16059
EP
EP
1
2
3
4
1
2
3
RESET GND SWT MR
RESET
GND
MR
TDFN
TDFN
*CONNECT EXPOSED PAD TO GND.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-4686; Rev 2; 4/13
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
ABSOLUTE MAXIMUM RATINGS
CC
SRT, SWT, WDS, MR, WDI, to GND ...........-0.3V to (V
RESET (Push-Pull) to GND .........................-0.3V to (V
RESET (Open-Drain) to GND ...................................-0.3V to +6V
Input Current (all pins) .................................................... 20mA
Output Current (RESET) ................................................. 20mA
V
to GND..............................................................-0.3V to +6V
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
+ 0.3V)
+ 0.3V)
6-Pin TDFN...................................................................42°C/W
8-Pin TDFN...................................................................41°C/W
Junction-to-Case Thermal Resistance (θJC) (Note 1)
CC
CC
6-Pin TDFN.....................................................................9°C/W
8-Pin TDFN.....................................................................8°C/W
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Continuous Power Dissipation (T = +70°C)
A
6-Pin TDFN (derate 23.8mW/°C above +70°C) .........1905mW
8-Pin TDFN (derate 24.4mW/°C above +70°C) .........1951mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 1.2V to 5.5V, T = T
A
to T
, unless otherwise noted. Typical values are at V
= 3.3V, T = +25°C.) (Note 2)
CC A
CC
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
= 0°C to +125°C
MIN
1.1
TYP
MAX
5.5
UNITS
T
T
A
A
Supply Voltage
V
V
CC
= -40°C to 0°C
1.2
5.5
V
= 5.0V, T
=
=
=
=
CC
A
142
132
125
142
132
210
185
175
430
415
-40°C to +85°C
V
= 3.3V, T
CC
A
-40°C to +85°C
V
= 1.8V, T
CC
A
V
> V + 150mV,
TH
CC
-40°C to +85°C
no load, reset output
deasserted (Note 3)
nA
Supply Current
I
CC
V
= 5.0V, T
CC
A
-40°C to +125°C
V
= 3.3V, T =
A
CC
-40°C to +125°C
V
= 1.8V, T
=
A
CC
125
7
400
15
-40°C to +125°C
V
V
< V , no load, reset output asserted
µA
V
CC
CC
TH
V
1.5%
-
V
1.5%
+
TH
TH
T
= +25°C
A
V
Reset Threshold
V
falling (see Table 1)
CC
TH
T
= -40°C to
V
-
V
+
TH
A
TH
+125°C
2.5%
2.5%
Hysteresis
to Reset Delay
V
V
V
rising
0.5
80
%
µs
ms
HYST
CC
CC
falling from (V + 100mV) to
TH
V
t
RD
CC
(V - 100mV) at 10mV/µs
TH
Reset Timeout Period
t
C
= 2700pF (Note 4)
SRT
10.5
14.18
17.0
RP
2
Maxim Integrated
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
ELECTRICAL CHARACTERISTICS (continued)
(V
= 1.2V to 5.5V, T = T
A
to T
, unless otherwise noted. Typical values are at V
= 3.3V, T = +25°C.) (Note 2)
CC A
CC
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
= -40°C to
MIN
TYP
MAX
UNITS
T
A
197
240
282
V
V
= 0V to V
,
RAMP1
SRT
CC
+125°C
SRT Ramp Current
I
nA
RAMP1
= 1.6V to 5V
T
A
= +25°C
= 1.6V to 5V (V rising)
RAMP
210
1.173
5
240
1.235
6.4
270
1.297
8
SRT Ramp Threshold
V
V
V
RAMP1
CC
T
T
= +25°C
A
A
Watchdog Timeout Clock Period
t
ms
WDPER
= -40°C to +125°C
3.5
6.4
9.5
T
= -40°C to
A
197
240
282
V
V
= 0V to V
= 1.6V to 5V
,
SWT
RAMP2
+125°C
SWT Ramp Current
I
nA
V
RAMP2
CC
T
= +25°C
= 1.6V to 5V (V rising)
RAMP2
210
240
270
A
SWT Ramp Threshold
V
V
V
V
V
1.173
1.235
1.297
0.3
RAMP2
CC
CC
CC
CC
≥ 1.0V, I
≥ 2.7V, I
≥ 4.5V, I
= 50µA
SINK
SINK
SINK
V
= 1.2mA
= 3.2mA
0.3
OL
0.4
V
≥ 1.8V,
0.8 x
CC
I
= 200µA
V
CC
RESET Output Voltage
SOURCE
V
V
≥ 2.25V,
0.8 x
V
CC
CC
V
MAX16056/MAX16057
OH
I
= 500µA
SOURCE
V
≥ 4.5V,
0.8 x
CC
I
= 800µA
V
CC
SOURCE
RESET Output-Leakage Current,
Open Drain
V
> V , reset not asserted, V
=
RESET
CC
TH
I
1.0
µA
V
LKG
5.5V (MAX16058/MAX16059)
0.7 x
V
IH
V
CC
Input-Logic Levels
0.3 x
V
IL
V
CC
MR Minimum Pulse Width
MR Glitch Rejection
t
1
µs
ns
ns
ns
nA
MPW
200
250
MR to RESET Delay
t
MRD
WDI Minimum Pulse Width
Input Leakage Current
(Note 5)
MR, WDI, WDS is connected to GND or V
150
-100
+100
CC
Note 2: Devices are production tested at T = +25°C. Specifications over temperature limits are guaranteed by design.
A
Note 3: WDI input period is 1s with t
and t
< 50ns.
RISE
FALL
Note 4: Worst case of SRT ramp current and voltage is used to guarantee minimum and maximum limits.
Note 5: Guaranteed by design, not production tested.
Maxim Integrated
3
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Typical Operating Characteristics
(V
CC
= 2.5V, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
RESET TIMEOUT PERIOD
vs. C
SUPPLY CURRENT vs. TEMPERATURE
SRT
10.0
350
300
250
200
150
100
50
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 2.23V
TH
RESET IS NOT ASSERTED
V
= 1.575V
TH
V
V
= 5.5V
CC
V
= 3.3V
= 2.5V
CC
1.0
0.1
T
A
= -40NC
T
A
= +125NC
T
= +85NC
T
A
= +25NC
A
V
CC
5
= 1.8V
CC
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
-40 -25 -10
20 35 50 65 80 95 110 125
0
50
100
150
(nF)
200
250
300
V
TEMPERATURE (NC)
C
CC
SRT
NORMALIZED RESET TIMEOUT PERIOD
vs. TEMPERATURE
NORMALIZED WATCHDOG
TIMEOUT PERIOD vs. TEMPERATURE
MAXIMUM V TRANSIENT DURATION
CC
vs. RESET THRESHOLD OVERDRIVE
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
1000
100
10
RESET OCCURS ABOVE THIS LINE
V
FALLING FROM V + 100mV
TH
CC
1
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
10
100
1000
TEMPERATURE (NC)
TEMPERATURE (NC)
RESET THRESHOLD OVERDRIVE (mV)
NORMALIZED RESET THRESHOLD
VOLTAGE vs. TEMPERATURE
V
TO RESET DELAY
CC
vs. TEMPERATURE
120
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
V
= V + 100mV TO V - 100mV
CC
TH
TH
110
100
90
80
70
60
50
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (NC)
TEMPERATURE (NC)
4
Maxim Integrated
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Typical Operating Characteristics (continued)
(V
CC
= 2.5V, T = +25°C, unless otherwise noted.)
A
RESET OUTPUT-LOW VOLTAGE
vs. SINK CURRENT
RESET OUTPUT-HIGH VOLTAGE
vs. SOURCE CURRENT
SUPPLY CURRENT vs. WATCHDOG
SWITCHING FREQUENCY
0.30
0.50
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
V
V
= 2.5V
CC
V
= 1.8V
CC
V
= 1.8V
CC
V
= 3.3V
CC
= 3.3V
CC
V
= 2.5V
CC
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
(mA)
0.01
0.1
1
10
100 1000 10,000
I
(mA)
SINK
I
SOURCE
WATCHDOG SWITCHING FREQUENCY (kHz)
MANUAL RESET DELAY
vs. TEMPERATURE
MANUAL RESET DELAY
MAX16056 toc13
270
268
266
264
262
260
258
256
254
252
250
MR
1V/div
RESET
1V/div
-40 -25 -10
5
20 35 50 65 80 95 110 125
200ns/div
TEMPERATURE (NC)
RESET SOURCE CAPABILITY
vs. SUPPLY VOLTAGE
RESET SINK CAPABILITY
vs. SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
V
= 0.8 x V
CC
RESET
V
= 0.3V
RESET
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
(V)
V
V
CC
CC
Maxim Integrated
5
5
_______________________________________________________________________________________________________
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Pin Description
PIN
NAME
FUNCTION
MAX16056/ MAX16057/
MAX16058
MAX16059
Push-Pull or Open-Drain Reset Output. RESET asserts whenever V
drops below the
CC
selected reset threshold voltage (V ) or manual reset is pulled low. RESET remains low
TH
1
2
1
2
RESET for the reset timeout period after all reset conditions are deasserted, and then goes high.
The watchdog timer triggers a reset pulse (t ) whenever a watchdog fault occurs
RP
(MAX16056/MAX16058).
GND
SWT
Ground
Watchdog Timeout Input. Connect a capacitor between SWT and GND to set the basic
watchdog timeout period (t ). Determine the period by the formula t
WD
5.15 x 10 /6.4ms] x 6.4ms + 3.2ms (Note 6) with t
use Table 2. Extend the basic watchdog timeout period by using the WDS input. Connect
SWT to ground to disable the watchdog timer function. The value of the capacitor must be
between 2275pF and 0.54µF to have a valid watchdog timeout period.
= Floor[C
in Farads, or
SWT
x
WD
SWT
6
in seconds and C
WD
3
—
Manual-Reset Input. Drive MR low to manually reset the device. RESET remains asserted
for the reset timeout period after MR is released. There is no internal pullup on MR. MR
4
5
3
4
MR
must not be left unconnected. Connect MR to V
if not used.
CC
Reset Timeout Input. Connect a capacitor from SRT to GND to select the reset timeout
6
period. Determine the period as follows: t = 5.15 x 10 x C
with t in seconds and
RP
RP
SRT
SRT
C
in Farads, or use Table 2. The value of the capacitor must be between 39pF and
SRT
4.7µF.
Watchdog Input. A falling transition must occur on WDI within the selected watchdog
timeout period or a reset pulse occurs. The watchdog timer clears when a falling transition
occurs on WDI or whenever RESET is asserted. Connect SWT to ground to disable the
watchdog timer function.
6
—
WDI
Watchdog Select Input. WDS selects the watchdog timeout mode. Connect WDS to
ground to select normal mode. The watchdog timeout period is t . Connect WDS to V
to select extended mode, multiplying the basic timeout period (t ) by a factor of 128. A
WD
change in the state of WDS clears the watchdog timer.
WD
CC
7
8
—
6
WDS
Supply Voltage. V
is the power-supply input and the input for fixed threshold V
CC
CC
V
CC
monitor. For noisy systems, bypass V
with a 0.1µF capacitor to GND.
CC
—
—
5
N.C.
EP
No Connection. Not internally connected.
Exposed Pad. Connect EP to GND or leave unconnected.
—
Note 6: Floor: take the integral value.
6
Maxim Integrated
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Watchdog Timer
Detailed Description
The MAX16056/MAX16058’s watchdog timer circuitry
The MAX16056–MAX16059 are ultra-low-current 125nA
monitors the µP’s activity. If the µP does not toggle
(typ) µP supervisory circuits that monitor a single sys-
(high-to-low) the watchdog input (WDI) within the
tem supply voltage. These devices assert an active-low
capacitor-adjustable watchdog timeout period (t ),
WD
reset signal whenever the V
supply voltage drops
CC
RESET asserts for the reset timeout period (t ). The
RP
below the factory-trimmed reset threshold, manual
reset is pulled low, or the watchdog timer runs out
(MAX16056/MAX16058). The reset output remains
asserted for an adjustable reset timeout period after
internal watchdog timer is cleared by: 1) any event that
asserts RESET, by 2) a falling transition at WDI (that
can detect pulses as short as 150ns) or by 3) a transi-
tion (high-to-low or low-to-high) at WDS. While reset is
asserted, the watchdog timer remains cleared and
does not count. As soon as reset deasserts, the watch-
dog timer resumes counting.
V
rises above the reset threshold. The reset and
watchdog delay periods are adjustable using external
capacitors.
CC
RESET Output
The MAX16056–MAX16059 µP supervisory circuits assert
a reset to prevent code-execution errors during power-
up, power-down, and brownout conditions. The reset
There are two modes of watchdog operation, normal
mode and extended mode. In normal mode (Figure 2),
the watchdog timeout period is determined by the
value of the capacitor connected between SWT and
ground. In extended mode (Figure 3), the watchdog
timeout period is multiplied by 128. For example, in
extended mode, a 0.33µF capacitor gives a watchdog
timeout period of 217s (see Table 2). To disable the
watchdog timer function, connect SWT to ground.
output is guaranteed to be valid for V down to 1.1V.
CC
When V
falls below the reset threshold, the RESET
CC
output asserts low. Once V
exceeds the reset thresh-
CC
old plus the hysteresis, an internal timer keeps the reset
output asserted for the capacitor-adjusted reset timeout
period (t ), then after this interval the reset output
RP
deasserts (see Figure 1). The reset function features
immunity to power-supply voltage transients.
When V
ramps above V + V
, the value of the
CC
TH
HYST
external SWT capacitor is sampled after RESET goes
high. When sampling is finished, the capacitor value is
stored in the device and is used to set watchdog time-
out. If RESET goes low before sampling is finished, the
device interrupts sampling, and sampling is restarted
when RESET goes high again.
Manual-Reset Input (MR)
Many µP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. The MAX16056–
MAX16059 feature an MR input. A logic-low on MR
asserts a reset. RESET remains asserted while MR is
If the external SWT capacitor is less than 470pF, the
sampling result sets the watchdog timeout to zero. This
causes the watchdog to assert RESET continuously
after sampling is finished. If a PCB manufacturing
low and for the timeout period, t , after MR returns
RP
high. Connect MR to V
if unused. MR can be driven
CC
defect caused the connection to C
to be broken,
SWT
with CMOS logic levels or with open-drain/collector out-
puts (with a pullup resistor). Connect a normally open
momentary switch from MR to GND and a resistor from
the capacitance is very low and RESET is continuously
asserted. If the external SWT capacitor is greater than
0.47µF, the sampling result sets the watchdog timeout
to be infinite, disabling the watchdog function.
MR to V
to implement a manual-reset function; exter-
CC
nal debounce circuitry is not required. If MR is driven
by long cables or the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to GND to
provide additional noise immunity.
Maxim Integrated
7
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
V
+ V
HYST
TH
V
TH
V
CC
t
RP
t
RP
t
t
RD
MRD
RESET
t
MPW
MR
Figure 1. RESET Timing Relationship
V
CC
t
t
WDI
RP
WD
0V
V
CC
RESET
0V
NORMAL MODE (WDS = GND)
Figure 2. Watchdog Timing Diagram, Normal Mode, WDS = GND
V
CC
t
x 128
WDI
WD
0V
V
CC
t
RP
RESET
0V
EXTENDED MODE (WDS = V
)
CC
Figure 3. Watchdog Timing Diagram, Extended Mode, WDS = V
8
CC
Maxim Integrated
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
accuracy by substituting the minimum, typical, and
Applications Information
Selecting the Reset Timeout Capacitor
The reset timeout period is adjustable to accommodate
a variety of µP applications. To adjust the reset timeout
maximum values into the equation.
For example, if C
= 100nF.
-9
SWT
-9
t
= Floor[100 x 10 x 1.173/(282 x 10 )/9.5ms] x
WDMIN
3.5ms + 0.5 x 3.2ms = 141.7ms
period (t ), connect a capacitor (C
) between SRT
RP
SRT
-9
-9
and ground. The reset timeout capacitor is calculated
t
= Floor[100 x 10 x 1.235/(240 x 10 )/6.4ms]
WDNOM
as follows:
x 6.4ms + 0.5 x 6.4ms = 515.2ms
6
-9
-9
C
= t /(5.15 x 10 )
t
= Floor[100 x 10 x 1.297/(197 x 10 )/3.5ms]
SRT
RP
WDMAX
x 9.5ms + 0.5 x 9.5ms = 1790.75ms
with t in seconds and C
in Farads.
RP
SRT
C
must be a low-leakage (< 10nA) type capacitor. A
SRT
Transient Immunity
ceramic capacitor with low temperature coefficient
dielectric (i.e., X7R) is recommended.
For applications with higher slew rates on V during
CC
power-up, additional bypass capacitance may be
required.
Selecting Watchdog Timeout Capacitor
The watchdog timeout period is adjustable to accom-
modate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer can determine how often
the watchdog timer should be serviced. Adjust the
The MAX16056–MAX16059 are relatively immune to
short-duration supply voltage transients, or glitches on
V
. The Maximum V
Transient Duration vs. Reset
CC
CC
Threshold Overdrive graph in the Typical Operating
Characteristics shows this transient immunity. The area
below the curve of the graph is the region where these
devices typically do not generate a reset pulse. This
graph was generated using a falling pulse applied to
watchdog timeout period (t ) by connecting a capaci-
tor (C
WD
) between SWT and GND. For normal mode
SWT
operation, calculate the watchdog timeout as follows:
6
V
, starting 100mV above the actual reset threshold
(V ) and ending below this threshold (reset threshold
CC
t
= Floor[C
x 5.15 x 10 /6.4ms] x 6.4ms + 3.2ms
WD
SWT
TH
with t
in seconds and C
in Farads.
overdrive). As the magnitude of the transient increases,
the maximum allowable pulse width decreases.
WD
SWT
(Floor: take the integral value) (Figures 2 and 3)
Typically, a 100mV V
transient duration of 40µs or
CC
The maximum t is 296s. If the capacitor sets t
greater than the 296s, t
timer is disabled.
WD
WD
less does not cause a reset.
= infinite and the watchdog
WD
Using the MAX16056–MAX16059 for
Reducing System Power Consumption
Using the RESET output to control an external p-channel
MOSFET to control the on-time of a power supply can
result in lower system power consumption in systems that
can be regularly put to sleep. By tying the WDI input to
ground, the RESET output becomes a low-frequency
clock output. When RESET is low, the MOSFET is turned
on and power is applied to the system. When RESET is
high, the MOSFET is turned off and no power is con-
sumed by the system. This effectively reduces the shut-
down current of the system to zero (Figure 4).
C
must be a low-leakage (< 10nA) type capacitor.
SWT
A ceramic capacitor with low temperature coefficient
dielectric (i.e., X7R) is recommended.
Watchdog Timeout Accuracy
The watchdog timeout period is affected by the SWT
ramp current (I
old (V
) accuracy, the SWT ramp thresh-
RAMP2
) and the watchdog timeout clock period
RAMP2
(t
). In the equation above, the constant 5.15 x
WDPER
106 is equal to V
/I
, and 6.4ms equals the
RAMP2 RAMP2
watchdog timeout clock period. Calculate the timeout
Maxim Integrated
9
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
BAT
0.1μF
0.1μF
1MΩ
V
CC
V
CC1
RESET
WDI
MAX16056
MR
μP
MANUAL
POWER-ON
SRT
GND
WDS
SWT
C
SWT
C
SRT
V
CC
RESET
V
CC1
t
t
t
RP
RP
WD
Figure 4. Using MAX16056–MAX16059 to Reduce System Power Consumption
10
Maxim Integrated
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Interfacing to Other Voltages
for Logic Compatibility
Ensuring a Valid RESET Down to V
= 0V
CC
(Push-Pull RESET)
The open-drain RESET output can be used to interface
to a µP with other logic levels. The open-drain output is
connected to a voltage from 0V to 5.5V as shown in
Figure 5. Generally, the pullup resistor connected to
RESET connects to the supply voltage that is being
When V
falls below 1.1V, the current-sinking capabil-
CC
ity of RESET decreases drastically. The high-imped-
ance CMOS logic inputs connected to RESET can drift
to undetermined voltages. This presents no problems in
most applications, since most µPs and other circuitry
monitored at the device’s V
input. However, some
do not operate with V
below 1.1V. In those applica-
CC
CC
systems use the open-drain output to level-shift from
the supervisor’s monitored supply to another supply
tions where RESET must be valid down to 0, add a pull-
down resistor between the MAX16056/MAX16057
push-pull RESET output and GND. The resistor sinks
any stray leakage currents, holding RESET low (Figure
6). Choose a pulldown resistor that accommodates
leakages, such that RESET is not significantly loaded
and is capable of pulling to GND. The external pull-
down cannot be used with the open-drain RESET out-
put of the MAX16058/MAX16059.
voltage. As the supervisor’s V
decreases, so does
CC
the device’s ability to sink current at RESET.
3.3V
5V
V
CC
V
CC
V
CC
V
CC
MAX16058
MAX16059
100kΩ
MAX16056
MAX16057
μP
RESET
RESET
RESET
2MΩ
GND
GND
GND
Figure 5. Interfacing with Other Voltage Levels
Figure 6. Ensuring RESET Valid to V
CC
= GND
Maxim Integrated
11
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Table 1. Threshold Suffix Guide
V
THRESHOLD FALLING (V)
TYP
CC
SUFFIX
MIN
MAX
4.741
4.613
4.484
4.408
4.305
4.203
4.100
3.998
3.895
3.793
3.690
3.588
3.485
3.383
3.280
3.152
3.075
2.998
2.870
2.768
2.691
2.563
2.460
2.371
2.290
2.243
2.153
2.050
1.948
1.845
1.707
1.614
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
225
22
21
20
19
18
17
16
4.509
4.388
4.266
4.193
4.095
3.998
3.900
3.802
3.705
3.608
3.510
3.413
3.315
3.218
3.120
2.998
2.925
2.852
2.730
2.633
2.559
2.438
2.340
2.255
2.180
2.133
2.048
1.950
1.853
1.755
1.623
1.536
4.625
4.500
4.375
4.300
4.200
4.100
4.000
3.900
3.800
3.700
3.600
3.500
3.400
3.300
3.200
3.075
3.000
2.925
2.800
2.700
2.625
2.500
2.400
2.313
2.235
2.188
2.100
2.000
1.900
1.800
1.665
1.575
12
Maxim Integrated
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Table 2. Capacitor Selection Guide
CAPACITANCE (pF)
39
t
(ms)
t
(ms)
t x 128 (ms)
WD
RP
WD
47
56
68
82
100
120
0
(no capacitor is connected)
150
180
220
270
Not recommended
330
390
470
560
680
820
1000
1200
1500
1800
2200
2700
3300
3900
4700
5600
6800
8200
10,000
12,000
15,000
18,000
Indeterminate
(0, 9.6, or 16)
Indeterminate
(0, 1228.8, or 1636)
14.18
16.99
20.1
16
1641
1641
2460
2460
3280
4099
4918
6556
7376
9833
11,472
16
22.4
22.4
28.8
35.2
41.6
54.4
60.8
80
24.21
28.84
35.00
42.23
51.5
61.8
77.25
92.7
92.8
Maxim Integrated
13
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Table 2. Capacitor Selection Guide (continued)
CAPACITANCE (pF)
22,000
t
(ms)
t
(ms)
t x 128 (ms)
WD
RP
WD
113.3
112
13,929
17,206
21,302
25,398
30,313
36,867
44,240
53,251
65,539
78,646
98,307
27,000
139.05
169.95
200.85
242.05
288.4
350.2
422.3
515
137.6
169.6
201.6
240
33,000
39,000
47,000
56,000
291.2
348.8
419.2
515.2
617.6
771.2
924.8
1129.6
1392
68,000
82,000
100,000
120,000
150,000
180,000
220,000
270,000
330,000
390,000
470,000
680,000
820,000
1,000,000
1,500,000
2,200,000
3,300,000
4,700,000
618
772.5
927
117,968
144,182
177,769
217,091
256,412
308,841
1133
1390.5
1699.5
2008.5
2420.5
3502
1699.2
2006.4
2416
4223
Indeterminate
5150
(may be infinite and watchdog is disabled)
7725
11,330
16,995
24,205
Infinite
(watchdog is disabled)
14
Maxim Integrated
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Table 3. Standard Versions
PART
TOP MARK
BKZ
BLA
BLB
BLC
BLD
BLE
MAX16056ATA17+
MAX16056ATA23+
MAX16056ATA26+
MAX16056ATA29+
MAX16056ATA31+
MAX16056ATA46+
MAX16057ATT17+
MAX16057ATT23+
MAX16057ATT26+
MAX16057ATT29+
MAX16057ATT31+
MAX16057ATT46+
MAX16058ATA16+
MAX16058ATA22+
MAX16058ATA26+
MAX16058ATA29+
MAX16058ATA31+
MAX16058ATA44+
MAX16059ATT16+
MAX16059ATT22+
MAX16059ATT26+
MAX16059ATT29+
MAX16059ATT31+
MAX16059ATT44+
ATQ
ATR
ATS
ATT
AUC
AUD
BLF
BLG
BLH
BLI
BLJ
BLK
ATW
ATX
ATY
ATZ
AUA
AUB
Maxim Integrated
15
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Typical Operating Circuit
BAT
0.1μF
1MΩ
V
CC
V
CC
RESET
WDI
MAX16056
MR
μP
MANUAL
RESET
SRT
GND
WDS
SWT
C
SWT
C
SRT
Package Information
Chip Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 TDFN-EP
6 TDFN-EP
T833-2
T633-2
21-0137
21-0137
90-0059
90-0058
16
Maxim Integrated
MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
6/09
6/10
4/13
Initial release
—
2, 3, 15
1
Updated Absolute Maximum Ratings, Electrical Characteristics, and Table 3.
Removed Automotive Infotainment from Applications sections
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 17
© 2013 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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